static struct pci_controller pci_hose[MAX_BUSES];
static int pci_num_buses;
-#if !defined(CONFIG_DM_PCI)
-static void pci_init_bus(int bus, struct pci_region *reg)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile pot83xx_t *pot = immr->ios.pot;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
- struct pci_controller *hose = &pci_hose[bus];
- u32 dev;
- u16 reg16;
- int i;
-
- if (bus == 1)
- pot += 3;
-
- /* Setup outbound translation windows */
- for (i = 0; i < 3; i++, reg++, pot++) {
- if (reg->size == 0)
- break;
-
- hose->regions[i] = *reg;
- hose->region_count++;
-
- pot->potar = reg->bus_start >> 12;
- pot->pobar = reg->phys_start >> 12;
- pot->pocmr = ~(reg->size - 1) >> 12;
-
- if (reg->flags & PCI_REGION_IO)
- pot->pocmr |= POCMR_IO;
-#ifdef CONFIG_83XX_PCI_STREAMING
- else if (reg->flags & PCI_REGION_PREFETCH)
- pot->pocmr |= POCMR_SE;
-#endif
-
- if (bus == 1)
- pot->pocmr |= POCMR_DST;
-
- pot->pocmr |= POCMR_EN;
- }
-
- /* Point inbound translation at RAM */
- pci_ctrl->pitar1 = 0;
- pci_ctrl->pibar1 = 0;
- pci_ctrl->piebar1 = 0;
- pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
-
- i = hose->region_count++;
- hose->regions[i].bus_start = 0;
- hose->regions[i].phys_start = 0;
- hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- hose->first_busno = pci_last_busno() + 1;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
- CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
-
- pci_register_hose(hose);
-
- /*
- * Write to Command register
- */
- reg16 = 0xff;
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
-#ifndef CONFIG_PCISLAVE
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-/*
- * The caller must have already set OCCR, and the PCI_LAW BARs
- * must have been set to cover all of the requested regions.
- *
- * If fewer than three regions are requested, then the region
- * list is terminated with a region of size 0.
- */
-void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- int i;
-
- if (num_buses > MAX_BUSES) {
- printf("%d PCI buses requested, %d supported\n",
- num_buses, MAX_BUSES);
-
- num_buses = MAX_BUSES;
- }
-
- pci_num_buses = num_buses;
-
- /*
- * Release PCI RST Output signal.
- * Power on to RST high must be at least 100 ms as per PCI spec.
- * On warm boots only 1 ms is required, but we play it safe.
- */
- udelay(100000);
-
- for (i = 0; i < num_buses; i++)
- immr->pci_ctrl[i].gcr = 1;
-
- /*
- * RST high to first config access must be at least 2^25 cycles
- * as per PCI spec. This could be cut in half if we know we're
- * running at 66MHz. This could be insufficiently long if we're
- * running the PCI bus at significantly less than 33MHz.
- */
- udelay(1020000);
-
- for (i = 0; i < num_buses; i++)
- pci_init_bus(i, reg[i]);
-}
-
-#ifdef CONFIG_PCISLAVE
-
-#define PCI_FUNCTION_CONFIG 0x44
-#define PCI_FUNCTION_CFG_LOCK 0x20
-
-/*
- * Unlock the configuration bit so that the host system can begin booting
- *
- * This should be used after you have:
- * 1) Called mpc83xx_pci_init()
- * 2) Set up your inbound translation windows to the appropriate size
- */
-void mpc83xx_pcislave_unlock(int bus)
-{
- struct pci_controller *hose = &pci_hose[bus];
- u32 dev;
- u16 reg16;
-
- /* Unlock configuration lock in PCI function configuration register */
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
- reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
- pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
-
- /* The configuration bit is now unlocked, so we can scan the bus */
- hose->last_busno = pci_hose_scan(hose);
-}
-#endif
-#endif /* CONFIG_DM_PCI */
-
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, struct bd_info *bd)
{
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- */
-
-/*
- * PCI Configuration space access support for MPC85xx PCI Bridge
- */
-#include <common.h>
-#include <asm/bitops.h>
-#include <asm/cpm_85xx.h>
-#include <pci.h>
-
-#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
-
-#ifndef CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
-#endif
-
-static struct pci_controller *pci_hose;
-
-void
-pci_mpc85xx_init(struct pci_controller *board_hose)
-{
- u16 reg16;
- u32 dev;
-
- volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
-#endif
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct pci_controller * hose;
-
- pci_hose = board_hose;
-
- hose = &pci_hose[0];
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x8000),
- (CONFIG_SYS_IMMR+0x8004));
-
- /*
- * Hose scan.
- */
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- printf("PCI-X will only work at 66 MHz\n");
-
- reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
- }
-
- pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
- pcix->potear1 = 0x00000000;
- pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
- pcix->powbear1 = 0x00000000;
- pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
-
- pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
- pcix->potear2 = 0x00000000;
- pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
- pcix->powbear2 = 0x00000000;
- pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
-
- pcix->pitar1 = 0x00000000;
- pcix->piwbar1 = 0x00000000;
- pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
- pcix->powar3 = 0;
- pcix->powar4 = 0;
- pcix->piwar2 = 0;
- pcix->piwar3 = 0;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC85XX_PCI2
- hose = &pci_hose[1];
-
- hose->first_busno = pci_hose[0].last_busno + 1;
- hose->last_busno = 0xff;
-
- pci_setup_indirect(hose,
- (CONFIG_SYS_IMMR+0x9000),
- (CONFIG_SYS_IMMR+0x9004));
-
- dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
- pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
- pcix2->potear1 = 0x00000000;
- pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
- pcix2->powbear1 = 0x00000000;
- pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
-
- pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
- pcix2->potear2 = 0x00000000;
- pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
- pcix2->powbear2 = 0x00000000;
- pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
-
- pcix2->pitar1 = 0x00000000;
- pcix2->piwbar1 = 0x00000000;
- pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
- pcix2->powar3 = 0;
- pcix2->powar4 = 0;
- pcix2->piwar2 = 0;
- pcix2->piwar3 = 0;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BUS,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_IO_BUS,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-#endif /* !CONFIG_FSL_PCI_INIT */
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