r600/sfn: Update state docu

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7142>

diff --git a/src/gallium/drivers/r600/sfn/sfn_docu.txt b/src/gallium/drivers/r600/sfn/sfn_docu.txt
index dffba5a..148f891 100644 (file)
--- a/src/gallium/drivers/r600/sfn/sfn_docu.txt
+++ b/src/gallium/drivers/r600/sfn/sfn_docu.txt
@@ -4,16 +4,19 @@ This code is an attempt to implement a NIR backend for r600.
 
 ## State
 
-piglits glsl-1.10 - 3.3 and gl-1.* gl-2.* and gl-3.* pass mostly like with TGSI, there are some fixes but
-also a few regressions.
+piglits gpu passes mostly like with TGSI, there are some fixes but also a few regressions.
+
+CTS gles
+ - 2 passes like with TGSI
+ - 3 no regressions, a few fixes compared to TGSI
+ - 31
+    * a few fixes with interpolation specifiers
+    * a few regressiones with seperate_shader.random
+    * syncronization has some unstable tests, this might be because global syncronization is missing (in both)
 
 ## Currently missing features w.r.t. TGSI:
 
- - Tesselation shaders
- - compute shader support
- - image load/store
- - work group shared values
- - SSBO atomics
+ - struct support
 
 ## Needed optimizations:
 
@@ -33,37 +36,13 @@ also a few regressions.
 
 ## Problems
 
-- figure out what is wrong with the textcoord semantics: disabling it results in
-  varyings beyond the supporteed VAR31, and enabling it lets some shaders with
-  VAR0 fail.
-
-- UBOs have a strange behaviour: with
-  glsl-1.50/uniform_buffer/gs-mat4x3.shader_test
-  on TGSI we have
-     ADD TEMP[1].xyz = CONST[1][0].xyzz CONST[1][1].xyzz
-  with NIR we have
-     vec4 ssa_12 = intrinsic load_ubo(_r600) (0, 0)(0 , 4 ,0)
-     vec4 ssa_13 = intrinsic load_ubo(_r600) (0, 1)(0 , 4 ,0)
-     vec3 ssa_14 = fadd ssa_12.xyw, ssa_13.xyw
-  so why is the "w" component emitted?
-
-## Unknows
-
-- multi-function shaders, how to deal with them? fp64 seems to have lots
-  of them, one option is to inline them
-
-- can type information from variables be harvested?
-
-lowering passes in NIR:
-  - TESS IO address evaluation should be lowered
+  - struct IO is not lowered. lower_io would need a rewrite of most IO in
+    VS, GS, and FS
+  - fp64 needs additional lowering to replace load, split and merge with vec2 ops
+    nir_to_tgsi has some stuff there
 
 ## Work plan
 
-The idea is to create two conversions: a NIR to a new R600 IR that
-can be  used to run some finalizing optimizations (replacing the
-need for r600/sb) and the binary code generation.
-
 The implementation uses C++ to separate the code for the different
 shader types and the byte code generation backends. The initial attempt
 will use the already available r600_asm code
-