[AArch64] Add test cases for the repairing of physical registers.

llvm-svn: 266030

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index 4187179..12ff22d 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -37,6 +37,14 @@
     store i32 %toStore, i32* %dst
     ret void
   }
+  define void @defaultMappingUseRepairPhysReg() {
+  entry:
+    ret void
+  }
+  define void @defaultMappingDefRepairPhysReg() {
+  entry:
+    ret void
+  }
 ...
 
 ---
@@ -177,3 +185,43 @@ body: |
     STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst)
     RET_ReallyLR
 ...
+
+---
+# Make sure we can repair physical register uses as well.
+name:            defaultMappingUseRepairPhysReg
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: gpr }
+# CHECK-NEXT:   - { id: 1, class: gpr }
+# CHECK-NEXT:   - { id: 2, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %w0, %s0
+    ; CHECK:           %0(32) = COPY %w0
+    ; CHECK-NEXT:      %2(32) = COPY %s0
+    ; CHECK-NEXT:      %1(32) = G_ADD i32 %0, %2
+    %0(32) = COPY %w0
+    %1(32) = G_ADD i32 %0, %s0
+...
+
+---
+# Make sure we can repair physical register defs.
+name:            defaultMappingDefRepairPhysReg
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: gpr }
+# CHECK-NEXT:   - { id: 1, class: gpr }
+registers:
+  - { id: 0, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %w0
+    ; CHECK:           %0(32) = COPY %w0
+    ; CHECK-NEXT:      %1(32) = G_ADD i32 %0, %0
+    ; CHECK-NEXT:      %s0 = COPY %1
+    %0(32) = COPY %w0
+    %s0 = G_ADD i32 %0, %0
+...