RISC-V: Fix wrong use of s0 register name.

s0 is listed as both an int register name and an FP register name.  The FP reg
name is wrong.  This looks like a simple editting error, and has an easy fix.
Tested with riscv64-linux build and check, with no regressions.

	gdb/
	* riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 92ba43d..7d5fc45 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2019-01-03  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.
+
 2019-01-02  Tom Tromey  <tom@tromey.com>
 
        * xml-tdesc.c (xml_cache): Hold a target_desc_up.

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 33c1c44..7a21efc 100644 (file)
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -185,7 +185,7 @@ static const struct riscv_register_feature riscv_freg_feature =
    { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
    { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
    { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
-   { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
+   { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true },
    { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
    { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
    { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },