radeon: Fix occlusion queries on big endian.

diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
index 6539c36..452d044 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c
+++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
@@ -49,6 +49,7 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
 {
        radeonContextPtr radeon = RADEON_CONTEXT(ctx);
        struct radeon_query_object *query = (struct radeon_query_object *)q;
+        uint32_t *result;
        int i;
 
        radeon_print(RADEON_STATE, RADEON_VERBOSE,
@@ -56,6 +57,7 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
                        __FUNCTION__, query->Base.Id, (int) query->Base.Result);
 
        radeon_bo_map(query->bo, GL_FALSE);
+        result = query->bo->ptr;
 
        query->Base.Result = 0;
        if (IS_R600_CLASS(radeon->radeonScreen)) {
@@ -66,10 +68,11 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
                 * hw writes zpass end counts to qwords 1, 3, 5, 7.
                 * then we substract. MSB is the valid bit.
                 */
-               uint64_t *result = query->bo->ptr;
-               for (i = 0; i < 8; i += 2) {
-                       uint64_t start = result[i];
-                       uint64_t end = result[i + 1];
+               for (i = 0; i < 16; i += 4) {
+                       uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) |
+                                        (uint64_t)LE32_TO_CPU(result[i + 1]) << 32;
+                       uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) |
+                                      (uint64_t)LE32_TO_CPU(result[i + 3]) << 32;
                        if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) {
                                uint64_t query_count = end - start;
                                query->Base.Result += query_count;
@@ -79,10 +82,9 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q)
                                     "%d start: %lx, end: %lx %ld\n", i, start, end, end - start);
                }
        } else {
-               uint32_t *result = query->bo->ptr;
                for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
-                       query->Base.Result += result[i];
-                       radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, result[i]);
+                       query->Base.Result += LE32_TO_CPU(result[i]);
+                       radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
                }
        }