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Test commit
authorDaniel Cederman <cederman@gaisler.com>
Mon, 28 Nov 2016 15:33:03 +0000 (15:33 +0000)
committerDaniel Cederman <cederman@gaisler.com>
Mon, 28 Nov 2016 15:33:03 +0000 (15:33 +0000)
llvm-svn: 288036

llvm/lib/Target/Sparc/SparcRegisterInfo.td patch | blob | history

diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
index d1ef3b1..6ecfddf 100644 (file)
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
@@ -331,7 +331,6 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32,
                                  (sequence "L%u", 0, 7),
                                  (sequence "O%u", 0, 7))>;
 
-
 // Should be in the same order as IntRegs.
 def IntPair : RegisterClass<"SP", [v2i32], 64,
     (add I0_I1, I2_I3, I4_I5, I6_I7,
Domain: System / Toolchain;