drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
authorRex Zhu <Rex.Zhu@amd.com>
Thu, 15 Mar 2018 06:45:04 +0000 (14:45 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 16 Mar 2018 21:16:49 +0000 (16:16 -0500)
Refine commit f49e9bac191b ("drm/amd/pp: Get and save Rv smu version")

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c

index f2dd98d..37098c6 100644 (file)
@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
                                else
                                        strcpy(fw_name, "amdgpu/vega10_smc.bin");
                                break;
-                       case CHIP_CARRIZO:
-                       case CHIP_STONEY:
-                       case CHIP_RAVEN:
-                               adev->pm.fw_version = info->version;
-                               return 0;
                        default:
                                DRM_ERROR("SMC firmware not supported\n");
                                return -EINVAL;
index bef0b2d..bc53f2b 100644 (file)
@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
 
 static int smu10_start_smu(struct pp_hwmgr *hwmgr)
 {
-       struct cgs_firmware_info info = {0};
+       struct amdgpu_device *adev = hwmgr->adev;
 
        smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
        hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
-       info.version = hwmgr->smu_version >> 8;
-
-       cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+       adev->pm.fw_version = hwmgr->smu_version >> 8;
 
        if (smu10_verify_smc_interface(hwmgr))
                return -EINVAL;
index 480deb2..8c49704 100644 (file)
@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 {
        int ret = 0;
        uint32_t fw_to_check = 0;
-       struct cgs_firmware_info info = {0};
+       struct amdgpu_device *adev = hwmgr->adev;
+
        uint32_t index = SMN_MP1_SRAM_START_ADDR +
                         SMU8_FIRMWARE_HEADER_LOCATION +
                         offsetof(struct SMU8_Firmware_Header, Version);
@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
 
        cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
        hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
-       info.version = hwmgr->smu_version >> 8;
-       cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+       adev->pm.fw_version = hwmgr->smu_version >> 8;
 
        fw_to_check = UCODE_ID_RLC_G_MASK |
                        UCODE_ID_SDMA0_MASK |