drm/amdgpu: Add pci usage to nbio v7.9

Add implementation to get pcie usage for nbio v7.9.

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index 781f98655567f99aa50dab2e5cf637de7f848d60..9ea072374cb7b2ebf7f390d1fa52769c3627ff27 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -35,6 +35,15 @@
 /* Core 0 Port 0 counter */
 #define smnPCIEP_NAK_COUNTER 0x1A340218
 
+#define smnPCIE_PERF_CNTL_TXCLK3               0x1A38021c
+#define smnPCIE_PERF_CNTL_TXCLK7               0x1A380888
+#define smnPCIE_PERF_COUNT_CNTL                        0x1A380200
+#define smnPCIE_PERF_COUNT0_TXCLK3             0x1A380220
+#define smnPCIE_PERF_COUNT0_TXCLK7             0x1A38088C
+#define smnPCIE_PERF_COUNT0_UPVAL_TXCLK3       0x1A3808F8
+#define smnPCIE_PERF_COUNT0_UPVAL_TXCLK7       0x1A380918
+
+
 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
 {
        WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -446,6 +455,59 @@ static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)
        return (nak_r + nak_g);
 }
 
+static void nbio_v7_9_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                                    uint64_t *count1)
+{
+       uint32_t perfctrrx = 0;
+       uint32_t perfctrtx = 0;
+
+       /* This reports 0 on APUs, so return to avoid writing/reading registers
+        * that may or may not be different from their GPU counterparts
+        */
+       if (adev->flags & AMD_IS_APU)
+               return;
+
+       /* Use TXCLK3 counter group for rx event */
+       /* Use TXCLK7 counter group for tx event */
+       /* Set the 2 events that we wish to watch, defined above */
+       /* 40 is event# for received msgs */
+       /* 2 is event# of posted requests sent */
+       perfctrrx = REG_SET_FIELD(perfctrrx, PCIE_PERF_CNTL_TXCLK3, EVENT0_SEL, 40);
+       perfctrtx = REG_SET_FIELD(perfctrtx, PCIE_PERF_CNTL_TXCLK7, EVENT0_SEL, 2);
+
+       /* Write to enable desired perf counters */
+       WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx);
+       WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx);
+
+       /* Zero out and enable SHADOW_WR
+        * Write 0x6:
+        * Bit 1 = Global Shadow wr(1)
+        * Bit 2 = Global counter reset enable(1)
+        */
+       WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
+
+       /* Enable Gloabl Counter
+        * Write 0x1:
+        * Bit 0 = Global Counter Enable(1)
+        */
+       WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001);
+
+       msleep(1000);
+
+       /* Disable Global Counter, Reset and enable SHADOW_WR
+        * Write 0x6:
+        * Bit 1 = Global Shadow wr(1)
+        * Bit 2 = Global counter reset enable(1)
+        */
+       WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
+
+       /* Get the upper and lower count  */
+       *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) |
+                 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32);
+       *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) |
+                 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32);
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
        .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
@@ -470,6 +532,7 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
        .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
        .init_registers = nbio_v7_9_init_registers,
        .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
+       .get_pcie_usage = nbio_v7_9_get_pcie_usage,
 };
 
 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 158e611474ca82bd428800cf1605862a9056fec3..c45721ca916e40fda80c27e2ec7d699834acb110 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -893,7 +893,7 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
        .get_config_memsize = &soc15_get_config_memsize,
        .need_full_reset = &soc15_need_full_reset,
        .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
-       .get_pcie_usage = &vega20_get_pcie_usage,
+       .get_pcie_usage = &amdgpu_nbio_get_pcie_usage,
        .need_reset_on_init = &soc15_need_reset_on_init,
        .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
        .supports_baco = &soc15_supports_baco,

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h
index a22481e7bcdb405bb337cdfce9ddf785e32d7598..e0c28c29ddb0cb1a188fe5acffa5935fbdd56964 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h
@@ -38896,5 +38896,13 @@
 #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
 #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
 
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT                                                             0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK                                                               0x000000FFL
+
+//PCIE_PERF_CNTL_TXCLK7
+#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL__SHIFT                                                             0x0
+#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL_MASK                                                               0x000000FFL
+
 
 #endif