arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy

Drop the old node and add the new one in its place.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders: Adjusted due to DP not itself not in upstream dts yet]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 15e8149..d616a05 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2770,12 +2770,11 @@
                };
 
                usb_1_qmpphy: phy-wrapper@88e9000 {
-                       compatible = "qcom,sc7180-qmp-usb3-phy";
+                       compatible = "qcom,sc7180-qmp-usb3-dp-phy";
                        reg = <0 0x088e9000 0 0x18c>,
-                             <0 0x088e8000 0 0x38>;
-                       reg-names = "reg-base", "dp_com";
+                             <0 0x088e8000 0 0x38>,
+                             <0 0x088ea000 0 0x40>;
                        status = "disabled";
-                       #clock-cells = <1>;
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges;
@@ -2790,7 +2789,7 @@
                                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
                        reset-names = "phy", "common";
 
-                       usb_1_ssphy: phy@88e9200 {
+                       usb_1_ssphy: usb3-phy@88e9200 {
                                reg = <0 0x088e9200 0 0x128>,
                                      <0 0x088e9400 0 0x200>,
                                      <0 0x088e9c00 0 0x218>,
@@ -2803,6 +2802,16 @@
                                clock-names = "pipe0";
                                clock-output-names = "usb3_phy_pipe_clk_src";
                        };
+
+                       dp_phy: dp-phy@88ea200 {
+                               reg = <0 0x088ea200 0 0x200>,
+                                     <0 0x088ea400 0 0x200>,
+                                     <0 0x088eaa00 0 0x200>,
+                                     <0 0x088ea600 0 0x200>,
+                                     <0 0x088ea800 0 0x200>;
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+                       };
                };
 
                dc_noc: interconnect@9160000 {
@@ -3166,8 +3175,8 @@
                                 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
                                 <&dsi_phy 0>,
                                 <&dsi_phy 1>,
-                                <0>,
-                                <0>;
+                                <&dp_phy 0>,
+                                <&dp_phy 1>;
                        clock-names = "bi_tcxo",
                                      "gcc_disp_gpll0_clk_src",
                                      "dsi0_phy_pll_out_byteclk",