drm/amdgpu: implement tlbs invalidate on gfx9 gfx10

tlbs invalidate pointer function added to kiq_pm4_funcs struct.
This way, tlb flush can be done through kiq member.
TLBs invalidatation implemented for gfx9 and gfx10.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 8e88e0411662ebdb3d1b496af87201077ed45e91..af4bd279f42fa8c64eeb422effaf16aad61aa799 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -76,11 +76,15 @@ struct kiq_pm4_funcs {
                                        struct amdgpu_ring *ring,
                                        u64 addr,
                                        u64 seq);
+       void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
+                               uint16_t pasid, uint32_t flush_type,
+                               bool all_hub);
        /* Packet sizes */
        int set_resources_size;
        int map_queues_size;
        int unmap_queues_size;
        int query_status_size;
+       int invalidate_tlbs_size;
 };
 
 struct amdgpu_kiq {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6bc3b937fba2d2f362ef9cbb6be7f4723b161ee8..1a500bbcdd1d2ed2dfa3a3b34e544faaeeb1c128 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -40,6 +40,7 @@
 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
 
 #include "soc15.h"
+#include "soc15d.h"
 #include "soc15_common.h"
 #include "clearstate_gfx10.h"
 #include "v10_structs.h"
@@ -345,15 +346,29 @@ static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
        amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 }
 
+static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
+                               uint16_t pasid, uint32_t flush_type,
+                               bool all_hub)
+{
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+       amdgpu_ring_write(kiq_ring,
+                       PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+                       PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+                       PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+                       PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+}
+
 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
        .kiq_set_resources = gfx10_kiq_set_resources,
        .kiq_map_queues = gfx10_kiq_map_queues,
        .kiq_unmap_queues = gfx10_kiq_unmap_queues,
        .kiq_query_status = gfx10_kiq_query_status,
+       .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
        .set_resources_size = 8,
        .map_queues_size = 7,
        .unmap_queues_size = 6,
        .query_status_size = 7,
+       .invalidate_tlbs_size = 12,
 };
 
 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1883b09dadfc709c6c099c12f2cee889bad59d8c..84b7c14fdc278b30c6736ab175844957eca41b5b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -837,15 +837,29 @@ static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
        amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 }
 
+static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
+                               uint16_t pasid, uint32_t flush_type,
+                               bool all_hub)
+{
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+       amdgpu_ring_write(kiq_ring,
+                       PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+                       PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+                       PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+                       PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+}
+
 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {
        .kiq_set_resources = gfx_v9_0_kiq_set_resources,
        .kiq_map_queues = gfx_v9_0_kiq_map_queues,
        .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,
        .kiq_query_status = gfx_v9_0_kiq_query_status,
+       .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,
        .set_resources_size = 8,
        .map_queues_size = 7,
        .unmap_queues_size = 6,
        .query_status_size = 7,
+       .invalidate_tlbs_size = 12,
 };
 
 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)