imx9: add i.MX93 variants support

According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index a666271..cbd2717 100644 (file)
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -61,6 +61,13 @@
 #define MXC_CPU_MX7ULP         0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610          0xF6 /* dummy ID */
 #define MXC_CPU_IMX93          0xC1 /* dummy ID */
+#define MXC_CPU_IMX9351                0xC2 /* dummy ID */
+#define MXC_CPU_IMX9332                0xC3 /* dummy ID */
+#define MXC_CPU_IMX9331                0xC4 /* dummy ID */
+#define MXC_CPU_IMX9322                0xC5 /* dummy ID */
+#define MXC_CPU_IMX9321                0xC6 /* dummy ID */
+#define MXC_CPU_IMX9312                0xC7 /* dummy ID */
+#define MXC_CPU_IMX9311                0xC8 /* dummy ID */
 
 #define MXC_SOC_MX6            0x60
 #define MXC_SOC_MX7            0x70

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 2eacddb..85d9ca6 100644 (file)
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -82,7 +82,17 @@ struct bd_info;
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
-#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
+       is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
+       is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
+       is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
+#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
+#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
+#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
+#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
+#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
+#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
 
 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ca312ff..439f899 100644 (file)
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -159,11 +159,34 @@ static void set_cpu_info(struct sentinel_get_info_data *info)
        memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
 }
 
+static u32 get_cpu_variant_type(u32 type)
+{
+       /* word 19 */
+       u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
+       u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+       bool npu_disable = !!(val & BIT(13));
+       bool core1_disable = !!(val & BIT(15));
+       u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+
+       if ((val2 & pack_9x9_fused) == pack_9x9_fused)
+               type = MXC_CPU_IMX9322;
+
+       if (npu_disable && core1_disable)
+               return type + 3;
+       else if (npu_disable)
+               return type + 2;
+       else if (core1_disable)
+               return type + 1;
+
+       return type;
+}
+
 u32 get_cpu_rev(void)
 {
        u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
 
-       return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
+       return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+               (CHIP_REV_1_0 + rev);
 }
 
 #define UNLOCK_WORD 0xD928C520 /* unlock word */

diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 304d5e5..98ff95f 100644 (file)
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -39,6 +39,20 @@ static const char *get_imx_type_str(u32 imxtype)
                return "8QM";
        case MXC_CPU_IMX93:
                return "93(52)";/* iMX93 Dual core with NPU */
+       case MXC_CPU_IMX9351:
+               return "93(51)";/* iMX93 Single core with NPU */
+       case MXC_CPU_IMX9332:
+               return "93(32)";/* iMX93 Dual core without NPU */
+       case MXC_CPU_IMX9331:
+               return "93(31)";/* iMX93 Single core without NPU */
+       case MXC_CPU_IMX9322:
+               return "93(22)";/* iMX93 9x9 Dual core  */
+       case MXC_CPU_IMX9321:
+               return "93(21)";/* iMX93 9x9 Single core  */
+       case MXC_CPU_IMX9312:
+               return "93(12)";/* iMX93 9x9 Dual core without NPU */
+       case MXC_CPU_IMX9311:
+               return "93(11)";/* iMX93 9x9 Single core without NPU */
        default:
                return "??";
        }