Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv...

Pull RISC-V updates from Paul Walmsley:
 "Add the following new features:

   - Generic CPU topology description support for DT-based platforms,
     including ARM64, ARM and RISC-V.

   - Sparsemem support

   - Perf callchain support

   - SiFive PLIC irqchip modifications, in preparation for M-mode Linux

  and clean up the code base:

   - Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
     flushing, and the RISC-V CPU-local timer code

   - Kbuild cleanup from one of the Kbuild maintainers"

[ The CPU topology parts came in through the arm64 tree with a shared
  branch   - Linus ]

* tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  irqchip/sifive-plic: set max threshold for ignored handlers
  riscv: move the TLB flush logic out of line
  riscv: don't use the rdtime(h) pseudo-instructions
  riscv: cleanup riscv_cpuid_to_hartid_mask
  riscv: optimize send_ipi_single
  riscv: cleanup send_ipi_mask
  riscv: refactor the IPI code
  riscv: Add support for libdw
  riscv: Add support for perf registers sampling
  riscv: Add perf callchain support
  riscv: add arch/riscv/Kbuild
  RISC-V: Implement sparsemem
  riscv: Using CSR numbers to access CSRs

diff --combined arch/riscv/kernel/head.S
index 52eec0c1bf30c11079d285f7defdf000b6583f22,86049aed8251988d8ffbeddaece177dd953173f3..15a9189f91ad27f445f96983d56ab1f3186940b4
--- 1/arch/riscv/kernel/head.S
--- 2/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@@ -39,9 -39,9 +39,9 @@@ ENTRY(_start
        .word RISCV_HEADER_VERSION
        .word 0
        .dword 0
 -      .asciz RISCV_IMAGE_MAGIC
 -      .word 0
 +      .ascii RISCV_IMAGE_MAGIC
        .balign 4
 +      .ascii RISCV_IMAGE_MAGIC2
        .word 0
  
  .global _start_kernel
@@@ -61,7 -61,7 +61,7 @@@ _start_kernel
         * floating point in kernel space
         */
        li t0, SR_FS
-       csrc sstatus, t0
+       csrc CSR_SSTATUS, t0
  
        /* Pick one hart to run the main boot sequence */
        la a3, hart_lottery