arm64: zynqmp: List reset property for ethernet phy

Add information about reset gpio for ethernet phy in case someone wants to
use it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e153f0cda37a2a6ea1c6e11fb0a4af1d400f29e2.1623684253.git.michal.simek@xilinx.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 339a12b..5ddcfdf 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -204,6 +204,7 @@
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
                ti,dp83867-rxctrl-strap-quirk;
+               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
index d9ad8a4..f7d718f 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevB
  *
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -22,6 +22,7 @@
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
                ti,dp83867-rxctrl-strap-quirk;
+               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
        };
        /* Cleanup from RevA */
        /delete-node/ ethernet-phy@21;