rockchip: rk3588: Sync sdmmc node from linux-next

Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.

This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.

Fixes: 95c8656b72dc ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
index 3235bd3..373f369 100644 (file)
--- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -18,7 +18,5 @@
 
 &sdmmc {
        bus-width = <4>;
-       bootph-all;
-       u-boot,spl-fifo-mode;
        status = "okay";
 };

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index b61d6e0..4c6f031 100644 (file)
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -17,7 +17,5 @@
 
 &sdmmc {
        bus-width = <4>;
-       bootph-pre-ram;
-       u-boot,spl-fifo-mode;
        status = "okay";
 };

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 1e225d7..3cb22f3 100644 (file)
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -18,20 +18,6 @@
                reg = <0x0 0xfd58a000 0x0 0x2000>;
        };
 
-       sdmmc: mmc@fe2c0000 {
-               compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-               reg = <0x0 0xfe2c0000 0x0 0x4000>;
-               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>,
-                        <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
-               clock-names = "ciu-drive", "ciu-sample", "biu", "ciu";
-               fifo-depth = <0x100>;
-               max-frequency = <200000000>;
-               pinctrl-names = "default";
-               pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
-               status = "disabled";
-       };
-
        otp: nvmem@fecc0000 {
                compatible = "rockchip,rk3588-otp";
                reg = <0x0 0xfecc0000 0x0 0x400>;
@@ -60,6 +46,19 @@
        status = "okay";
 };
 
+&scmi {
+       bootph-pre-ram;
+};
+
+&scmi_clk {
+       bootph-pre-ram;
+};
+
+&sdmmc {
+       bootph-pre-ram;
+       u-boot,spl-fifo-mode;
+};
+
 &uart2 {
        clock-frequency = <24000000>;
        bootph-pre-ram;

diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index 005cde6..fca8503 100644 (file)
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -1099,6 +1099,21 @@
                };
        };
 
+       sdmmc: mmc@fe2c0000 {
+               compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xfe2c0000 0x0 0x4000>;
+               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
+                        <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               max-frequency = <200000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+               power-domains = <&power RK3588_PD_SDMMC>;
+               status = "disabled";
+       };
+
        sdhci: mmc@fe2e0000 {
                compatible = "rockchip,rk3588-dwcmshc";
                reg = <0x0 0xfe2e0000 0x0 0x10000>;

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ce632f7..327779a 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -316,6 +316,8 @@ config ROCKCHIP_RK3588
        imply OF_LIBFDT_OVERLAY
        imply ROCKCHIP_OTP
        imply MISC_INIT_R
+       imply CLK_SCMI
+       imply SCMI_FIRMWARE
        help
          The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
          quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,