"src/core/NEON/kernels/NEL2NormalizeLayerKernel.cpp",
"src/core/NEON/kernels/NELKTrackerKernel.cpp",
"src/core/NEON/kernels/NELocallyConnectedMatrixMultiplyKernel.cpp",
+ "src/core/NEON/kernels/NELogicalKernel.cpp",
"src/core/NEON/kernels/NEMagnitudePhaseKernel.cpp",
"src/core/NEON/kernels/NEMaxUnpoolingLayerKernel.cpp",
"src/core/NEON/kernels/NEMeanStdDevKernel.cpp",
"src/runtime/NEON/functions/NELaplacianPyramid.cpp",
"src/runtime/NEON/functions/NELaplacianReconstruct.cpp",
"src/runtime/NEON/functions/NELocallyConnectedLayer.cpp",
+ "src/runtime/NEON/functions/NELogical.cpp",
"src/runtime/NEON/functions/NEMagnitude.cpp",
"src/runtime/NEON/functions/NEMaxUnpoolingLayer.cpp",
"src/runtime/NEON/functions/NEMeanStdDev.cpp",
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_MACROS_H
+#define ARM_COMPUTE_MACROS_H
+
+#define ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE_INC(TypeName) \
+ TypeName(const TypeName &) = delete; \
+ TypeName &operator=(const TypeName &) = delete; \
+ TypeName(TypeName &&) = default; \
+ TypeName &operator =(TypeName &&);
+
+#endif /* ARM_COMPUTE_MACROS_H */
#include "arm_compute/runtime/NEON/functions/NELaplacianPyramid.h"
#include "arm_compute/runtime/NEON/functions/NELaplacianReconstruct.h"
#include "arm_compute/runtime/NEON/functions/NELocallyConnectedLayer.h"
+#include "arm_compute/runtime/NEON/functions/NELogical.h"
#include "arm_compute/runtime/NEON/functions/NEMagnitude.h"
#include "arm_compute/runtime/NEON/functions/NEMaxUnpoolingLayer.h"
#include "arm_compute/runtime/NEON/functions/NEMeanStdDev.h"
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_NELOGICAL_H
+#define ARM_COMPUTE_NELOGICAL_H
+
+#include "arm_compute/core/Error.h"
+#include "arm_compute/runtime/IFunction.h"
+#include "arm_compute/runtime/Macros.h"
+
+#include <memory>
+
+namespace arm_compute
+{
+// Forward declarations
+class ITensor;
+class ITensorInfo;
+
+/** Basic function to perform logical AND */
+class NELogicalAnd : public IFunction
+{
+public:
+ /** Constructor */
+ NELogicalAnd();
+ /** Destructor */
+ ~NELogicalAnd();
+ ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE_INC(NELogicalAnd)
+
+ /** Initialise the kernel's inputs and output
+ *
+ * @param[in] input1 First tensor input. Data type supported: U8.
+ * @param[in] input2 Second tensor input. Data type supported: U8.
+ * @param[out] output Output tensor. Data type supported: U8.
+ */
+ void configure(const ITensor *input1, const ITensor *input2, ITensor *output);
+ /** Static function to check if given info will lead to a valid configuration of @ref NELogicalAnd
+ *
+ * @param[in] input1 First input tensor info. Data types supported: U8.
+ * @param[in] input2 Second input tensor info. Data types supported: U8.
+ * @param[in] output Output tensor info. Data type supported: U8
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output);
+
+ // Inherited methods overridden
+ void run() override;
+
+private:
+ struct Impl;
+ std::unique_ptr<Impl> _impl;
+};
+
+/** Basic function to perform logical OR */
+class NELogicalOr : public IFunction
+{
+public:
+ /** Constructor */
+ NELogicalOr();
+ /** Destructor */
+ ~NELogicalOr();
+ ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE_INC(NELogicalOr)
+
+ /** Initialise the kernel's inputs and output
+ *
+ * @param[in] input1 First tensor input. Data type supported: U8.
+ * @param[in] input2 Second tensor input. Data type supported: U8.
+ * @param[out] output Output tensor. Data type supported: U8.
+ */
+ void configure(const ITensor *input1, const ITensor *input2, ITensor *output);
+ /** Static function to check if given info will lead to a valid configuration of @ref NELogicalOr
+ *
+ * @param[in] input1 First input tensor info. Data types supported: U8.
+ * @param[in] input2 Second input tensor info. Data types supported: U8.
+ * @param[in] output Output tensor info. Data type supported: U8
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output);
+
+ // Inherited methods overridden
+ void run() override;
+
+private:
+ struct Impl;
+ std::unique_ptr<Impl> _impl;
+};
+
+/** Basic function to perform logical NOT */
+class NELogicalNot : public IFunction
+{
+public:
+ /** Constructor */
+ NELogicalNot();
+ /** Destructor */
+ ~NELogicalNot();
+ ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE_INC(NELogicalNot)
+
+ /** Initialise the kernel's inputs and output
+ *
+ * @param[in] input Input tensor. Data type supported: U8.
+ * @param[out] output Output tensor. Data type supported: U8.
+ */
+ void configure(const ITensor *input, ITensor *output);
+ /** Static function to check if given info will lead to a valid configuration of @ref NELogicalNot
+ *
+ * @param[in] input Input tensor info. Data types supported: U8.
+ * @param[in] output Output tensor info. Data type supported: U8
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *input, const ITensorInfo *output);
+
+ // Inherited methods overridden
+ void run() override;
+
+private:
+ struct Impl;
+ std::unique_ptr<Impl> _impl;
+};
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_NELOGICAL_H */
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_KERNEL_TYPES_H
+#define ARM_COMPUTE_KERNEL_TYPES_H
+
+namespace arm_compute
+{
+namespace kernels
+{
+/** List of supported logical operations */
+enum class LogicalOperation
+{
+ Unknown, /**< Unknown */
+ And, /**< Logical And && */
+ Or, /**< Logical Or || */
+ Not, /**< Logical Not ! */
+};
+} // namespace kernels
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_KERNEL_TYPES_H */
#include "src/core/NEON/kernels/NEL2NormalizeLayerKernel.h"
#include "src/core/NEON/kernels/NELKTrackerKernel.h"
#include "src/core/NEON/kernels/NELocallyConnectedMatrixMultiplyKernel.h"
+#include "src/core/NEON/kernels/NELogicalKernel.h"
#include "src/core/NEON/kernels/NEMagnitudePhaseKernel.h"
#include "src/core/NEON/kernels/NEMaxUnpoolingLayerKernel.h"
#include "src/core/NEON/kernels/NEMeanStdDevKernel.h"
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "src/core/NEON/kernels/NELogicalKernel.h"
+
+#include "arm_compute/core/Helpers.h"
+#include "arm_compute/core/Validate.h"
+#include "src/core/common/Validate.h"
+#include "src/core/helpers/AutoConfiguration.h"
+#include "src/core/helpers/WindowHelpers.h"
+
+#include <arm_neon.h>
+
+namespace arm_compute
+{
+namespace kernels
+{
+namespace
+{
+static const uint8x8_t c0_x8 = vdup_n_u8(0);
+static const uint8x16_t c0_x16 = vdupq_n_u8(0);
+static const uint8x8_t c1_x8 = vdup_n_u8(1);
+static const uint8x16_t c1_x16 = vdupq_n_u8(1);
+static const int step = 16;
+static const int half_step = step / 2;
+
+void neon_logical_and(const uint8_t *src0, const uint8_t *src1, uint8_t *dst, int len)
+{
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src0);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src1);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(dst);
+ ARM_COMPUTE_ASSERT(len >= 0);
+
+ for(; len >= step; len -= step)
+ {
+ vst1q_u8(dst, vandq_u8(vminq_u8(vld1q_u8(src0), c1_x16), vminq_u8(vld1q_u8(src1), c1_x16)));
+ src0 += step;
+ src1 += step;
+ dst += step;
+ }
+
+ for(; len >= half_step; len -= half_step)
+ {
+ vst1_u8(dst, vand_u8(vmin_u8(vld1_u8(src0), c1_x8), vmin_u8(vld1_u8(src1), c1_x8)));
+ src0 += half_step;
+ src1 += half_step;
+ dst += half_step;
+ }
+
+ for(; len > 0; --len)
+ {
+ *dst = (*src0) && (*src1);
+ ++src0;
+ ++src1;
+ ++dst;
+ }
+}
+
+void neon_logical_and_broadcast(const uint8_t *src, uint8_t broadcast_val, uint8_t *dst, int len)
+{
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(dst);
+ ARM_COMPUTE_ASSERT(len >= 0);
+
+ const auto broadcast_val_clamped_s = std::min<uint8_t>(broadcast_val, 1);
+ const auto broadcast_val_clamped_x16 = vdupq_n_u8(broadcast_val_clamped_s);
+ const auto broadcast_val_clamped_x8 = vdup_n_u8(broadcast_val_clamped_s);
+
+ for(; len >= step; len -= step)
+ {
+ vst1q_u8(dst, vandq_u8(vminq_u8(vld1q_u8(src), c1_x16), broadcast_val_clamped_x16));
+ src += step;
+ dst += step;
+ }
+
+ for(; len >= half_step; len -= half_step)
+ {
+ vst1_u8(dst, vand_u8(vmin_u8(vld1_u8(src), c1_x8), broadcast_val_clamped_x8));
+ src += half_step;
+ dst += half_step;
+ }
+
+ for(; len > 0; --len)
+ {
+ *dst = (*src) && broadcast_val_clamped_s;
+ ++src;
+ ++dst;
+ }
+}
+
+void neon_logical_or(const uint8_t *src0, const uint8_t *src1, uint8_t *dst, int len)
+{
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src0);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src1);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(dst);
+ ARM_COMPUTE_ASSERT(len >= 0);
+
+ for(; len >= step; len -= step)
+ {
+ vst1q_u8(dst, vorrq_u8(vminq_u8(vld1q_u8(src0), c1_x16), vminq_u8(vld1q_u8(src1), c1_x16)));
+ src0 += step;
+ src1 += step;
+ dst += step;
+ }
+
+ for(; len >= half_step; len -= half_step)
+ {
+ vst1_u8(dst, vorr_u8(vmin_u8(vld1_u8(src0), c1_x8), vmin_u8(vld1_u8(src1), c1_x8)));
+ src0 += half_step;
+ src1 += half_step;
+ dst += half_step;
+ }
+
+ for(; len > 0; --len)
+ {
+ *dst = (*src0) || (*src1);
+ ++src0;
+ ++src1;
+ ++dst;
+ }
+}
+
+void neon_logical_or_broadcast(const uint8_t *src, uint8_t broadcast_val, uint8_t *dst, int len)
+{
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(dst);
+ ARM_COMPUTE_ASSERT(len >= 0);
+
+ const auto broadcast_val_clamped_s = std::min<uint8_t>(broadcast_val, 1);
+ const auto broadcast_val_clamped_x16 = vdupq_n_u8(broadcast_val_clamped_s);
+ const auto broadcast_val_clamped_x8 = vdup_n_u8(broadcast_val_clamped_s);
+
+ for(; len >= step; len -= step)
+ {
+ vst1q_u8(dst, vorrq_u8(vminq_u8(vld1q_u8(src), c1_x16), broadcast_val_clamped_x16));
+ src += step;
+ dst += step;
+ }
+
+ for(; len >= half_step; len -= half_step)
+ {
+ vst1_u8(dst, vorr_u8(vmin_u8(vld1_u8(src), c1_x8), broadcast_val_clamped_x8));
+ src += half_step;
+ dst += half_step;
+ }
+
+ for(; len > 0; --len)
+ {
+ *dst = (*src) || broadcast_val_clamped_s;
+ ++src;
+ ++dst;
+ }
+}
+
+void neon_logical_not(const uint8_t *src, uint8_t *dst, int len)
+{
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(src);
+ ARM_COMPUTE_ASSERT_NOT_NULLPTR(dst);
+ ARM_COMPUTE_ASSERT(len >= 0);
+
+ for(; len >= step; len -= step)
+ {
+ vst1q_u8(dst, vbslq_u8(vceqq_u8(vld1q_u8(src), c0_x16), c1_x16, c0_x16));
+ src += step;
+ dst += step;
+ }
+
+ for(; len >= half_step; len -= half_step)
+ {
+ vst1_u8(dst, vbsl_u8(vceq_u8(vld1_u8(src), c0_x8), c1_x8, c0_x8));
+ src += half_step;
+ dst += half_step;
+ }
+
+ for(; len > 0; --len)
+ {
+ *dst = !(*src);
+ ++src;
+ ++dst;
+ }
+}
+
+void run_unary(const Window &window, const ITensor *src, ITensor *dst)
+{
+ Window win{ window };
+ win.set(Window::DimX, Window::Dimension(0, 1, 1));
+ const auto len = static_cast<int>(window.x().end()) - static_cast<int>(window.x().start());
+
+ Iterator in(src, win);
+ Iterator out(dst, win);
+
+ execute_window_loop(win, [&](const Coordinates &)
+ {
+ neon_logical_not(in.ptr(), out.ptr(), len);
+ },
+ in, out);
+}
+
+void run_binary(const Window &window, const ITensor *src0, const ITensor *src1, ITensor *dst, LogicalOperation op)
+{
+ Window src0_win = window.broadcast_if_dimension_le_one(src0->info()->tensor_shape());
+ Window src1_win = window.broadcast_if_dimension_le_one(src1->info()->tensor_shape());
+
+ Window win{ window };
+ win.set(Window::DimX, Window::Dimension(0, 1, 1));
+
+ const bool is_broadcast_across_x = src0->info()->tensor_shape().x() != src1->info()->tensor_shape().x();
+ const auto len = static_cast<int>(window.x().end()) - static_cast<int>(window.x().start());
+
+ if(is_broadcast_across_x)
+ {
+ using LogicalBroadcastUKernelPtr = std::add_pointer<void(const uint8_t *, uint8_t, uint8_t *, int)>::type;
+ LogicalBroadcastUKernelPtr logical_func = op == LogicalOperation::Or ? &neon_logical_or_broadcast : &neon_logical_and_broadcast;
+
+ const bool is_broadcast_input_1 = src1_win.x().step() == 0;
+ Window broadcast_win = is_broadcast_input_1 ? src1_win : src0_win;
+ Window non_broadcast_win = !is_broadcast_input_1 ? src1_win : src0_win;
+ const ITensor *broadcast_tensor = is_broadcast_input_1 ? src1 : src0;
+ const ITensor *non_broadcast_tensor = !is_broadcast_input_1 ? src1 : src0;
+ non_broadcast_win.set(Window::DimX, Window::Dimension(0, 1, 1));
+
+ Iterator broadcast_in(broadcast_tensor, broadcast_win);
+ Iterator non_broadcast_in(non_broadcast_tensor, non_broadcast_win);
+ Iterator out(dst, win);
+
+ execute_window_loop(win, [&](const Coordinates &)
+ {
+ const uint8_t broadcast_value = *broadcast_in.ptr();
+ logical_func(non_broadcast_in.ptr(), broadcast_value, out.ptr(), len);
+
+ },
+ broadcast_in, non_broadcast_in, out);
+ }
+ else
+ {
+ using LogicalUKernelPtr = std::add_pointer<void(const uint8_t *, const uint8_t *, uint8_t *, int)>::type;
+ LogicalUKernelPtr logical_func = op == LogicalOperation::Or ? &neon_logical_or : &neon_logical_and;
+
+ src0_win.set(Window::DimX, Window::Dimension(0, 1, 1));
+ src1_win.set(Window::DimX, Window::Dimension(0, 1, 1));
+
+ Iterator in0(src0, src0_win);
+ Iterator in1(src1, src1_win);
+ Iterator out(dst, win);
+ execute_window_loop(win, [&](const Coordinates &)
+ {
+ logical_func(in0.ptr(), in1.ptr(), out.ptr(), len);
+ },
+ in0, in1, out);
+ }
+}
+} // namespace
+const char *NELogicalKernel::name() const
+{
+ return "NELogicalKernel";
+}
+
+void NELogicalKernel::configure(const ITensorInfo *input1, const ITensorInfo *input2, ITensorInfo *output, LogicalOperation op)
+{
+ ARM_COMPUTE_ERROR_ON_NULLPTR(input1, output);
+ ARM_COMPUTE_ERROR_THROW_ON(validate(input1, input2, output, op));
+
+ _op = op;
+
+ Window win = calculate_max_window(*input1, Steps());
+ TensorShape out_shape = input1->tensor_shape();
+ if(op != LogicalOperation::Not)
+ {
+ ARM_COMPUTE_ERROR_ON_NULLPTR(input2);
+ const std::pair<TensorShape, ValidRegion> broadcast_pair = ITensorInfo::broadcast_shape_and_valid_region(*input1, *input2);
+ out_shape = broadcast_pair.first;
+ win = calculate_max_window(broadcast_pair.second, Steps());
+ }
+ ICPPKernel::configure(win);
+
+ // Auto initialize if empty
+ set_shape_if_empty(*output, out_shape);
+ set_data_type_if_unknown(*output, input1->data_type());
+}
+
+Status NELogicalKernel::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output, LogicalOperation op)
+{
+ ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input1, 1, DataType::U8);
+ ARM_COMPUTE_RETURN_ERROR_ON(op == LogicalOperation::Unknown);
+
+ TensorShape out_shape = input1->tensor_shape();
+ if(op != LogicalOperation::Not)
+ {
+ out_shape = TensorShape::broadcast_shape(input1->tensor_shape(), input2->tensor_shape());
+ ARM_COMPUTE_RETURN_ERROR_ON_MSG(out_shape.total_size() == 0, "Inputs are not broadcast compatible");
+ ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input1, input2);
+ }
+
+ // Checks performed when output is configured
+ if((output != nullptr) && (output->total_size() != 0))
+ {
+ ARM_COMPUTE_RETURN_ERROR_ON(detail::have_different_dimensions(out_shape, output->tensor_shape(), 0));
+ ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input1, output);
+ }
+
+ return Status{};
+}
+
+void NELogicalKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
+{
+ ARM_COMPUTE_UNUSED(info);
+ ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
+ ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(INEKernel::window(), window);
+ ARM_COMPUTE_ERROR_ON(tensors.empty());
+
+ const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
+ const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
+ ITensor *dst = tensors.get_tensor(TensorType::ACL_DST);
+
+ if(_op == LogicalOperation::Not)
+ {
+ run_unary(window, src0, dst);
+ }
+ else
+ {
+ run_binary(window, src0, src1, dst, _op);
+ }
+}
+} // namespace kernels
+} // namespace arm_compute
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_NELOGICALKERNEL_H
+#define ARM_COMPUTE_NELOGICALKERNEL_H
+
+#include "src/core/KernelTypes.h"
+#include "src/core/NEON/INEKernel.h"
+
+namespace arm_compute
+{
+namespace kernels
+{
+/** Interface for the kernel to perform logical operations between two tensors
+ *
+ * Supported logical operations:
+ * - AND
+ * - OR
+ * - NOT
+ */
+class NELogicalKernel : public INEKernel
+{
+public:
+ /** Initialise the kernel's inputs and output
+ *
+ * @param[in] input1 An input tensor. Data type supported: U8.
+ * @param[in] input2 An input tensor. Data type supported: U8
+ * @param[out] output Output tensor. Data type supported: U8.
+ * @param[out] op Logical operation to perform
+ */
+ void configure(const ITensorInfo *input1, const ITensorInfo *input2, ITensorInfo *output, LogicalOperation op);
+ /** Static function to check if given info will lead to a valid configuration of @ref NELogicalKernel
+ *
+ * @param[in] input1 An input tensor. Data type supported: U8.
+ * @param[in] input2 An input tensor. Data type supported: U8
+ * @param[in] output Output tensor. Data type supported: U8.
+ * @param[in] op Logical operation to perform
+ *
+ * @return a status
+ */
+ static Status validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output, LogicalOperation op);
+
+ // Inherited methods overridden:
+ void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override;
+ const char *name() const override;
+
+private:
+ LogicalOperation _op{};
+};
+} // namespace kernels
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_NELOGICALKERNEL_H */
for(; len > 0; --len)
{
- *pdst++ = std::floor(*psrc++);
+ *pdst = std::floor(*psrc);
+ ++psrc;
+ ++pdst;
}
}
} // namespace cpu
for(; len > 0; --len)
{
- *pdst++ = std::floor(*psrc++);
+ *pdst = std::floor(*psrc);
+ ++pdst;
+ ++psrc;
}
}
} // namespace cpu
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/runtime/NEON/functions/NELogical.h"
+
+#include "arm_compute/runtime/NEON/NEScheduler.h"
+#include "arm_compute/runtime/Tensor.h"
+#include "src/core/NEON/kernels/NELogicalKernel.h"
+#include "support/MemorySupport.h"
+
+namespace arm_compute
+{
+struct LogicalArgs
+{
+ std::unique_ptr<kernels::NELogicalKernel> kernel{ nullptr };
+ ITensorPack pack{};
+};
+
+struct NELogicalAnd::Impl : public LogicalArgs
+{
+};
+NELogicalAnd::NELogicalAnd()
+ : _impl(support::cpp14::make_unique<Impl>())
+{
+}
+NELogicalAnd &NELogicalAnd::operator=(NELogicalAnd &&) = default;
+NELogicalAnd::~NELogicalAnd() = default;
+
+void NELogicalAnd::configure(const ITensor *input1, const ITensor *input2, ITensor *output)
+{
+ ARM_COMPUTE_ERROR_ON_NULLPTR(input1, input2, output);
+
+ _impl->kernel = arm_compute::support::cpp14::make_unique<kernels::NELogicalKernel>();
+ _impl->kernel->configure(input1->info(), input2->info(), output->info(), kernels::LogicalOperation::And);
+
+ _impl->pack = ITensorPack();
+ _impl->pack.add_tensor(TensorType::ACL_SRC_0, input1);
+ _impl->pack.add_tensor(TensorType::ACL_SRC_1, input2);
+ _impl->pack.add_tensor(TensorType::ACL_DST, output);
+}
+
+Status NELogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
+{
+ return kernels::NELogicalKernel::validate(input1, input2, output, kernels::LogicalOperation::And);
+}
+
+void NELogicalAnd::run()
+{
+ NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->pack);
+}
+
+struct NELogicalOr::Impl : public LogicalArgs
+{
+};
+NELogicalOr::NELogicalOr()
+ : _impl(support::cpp14::make_unique<Impl>())
+{
+}
+NELogicalOr &NELogicalOr::operator=(NELogicalOr &&) = default;
+NELogicalOr::~NELogicalOr() = default;
+
+void NELogicalOr::configure(const ITensor *input1, const ITensor *input2, ITensor *output)
+{
+ ARM_COMPUTE_ERROR_ON_NULLPTR(input1, input2, output);
+
+ _impl->kernel = arm_compute::support::cpp14::make_unique<kernels::NELogicalKernel>();
+ _impl->kernel->configure(input1->info(), input2->info(), output->info(), kernels::LogicalOperation::Or);
+
+ _impl->pack = ITensorPack();
+ _impl->pack.add_tensor(TensorType::ACL_SRC_0, input1);
+ _impl->pack.add_tensor(TensorType::ACL_SRC_1, input2);
+ _impl->pack.add_tensor(TensorType::ACL_DST, output);
+}
+
+Status NELogicalOr::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
+{
+ return kernels::NELogicalKernel::validate(input1, input2, output, kernels::LogicalOperation::Or);
+}
+
+void NELogicalOr::run()
+{
+ NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->pack);
+}
+
+struct NELogicalNot::Impl : public LogicalArgs
+{
+};
+NELogicalNot::NELogicalNot()
+ : _impl(support::cpp14::make_unique<Impl>())
+{
+}
+NELogicalNot &NELogicalNot::operator=(NELogicalNot &&) = default;
+NELogicalNot::~NELogicalNot() = default;
+
+void NELogicalNot::configure(const ITensor *input, ITensor *output)
+{
+ ARM_COMPUTE_ERROR_ON_NULLPTR(input, output);
+
+ _impl->kernel = arm_compute::support::cpp14::make_unique<kernels::NELogicalKernel>();
+ _impl->kernel->configure(input->info(), nullptr, output->info(), kernels::LogicalOperation::Not);
+
+ _impl->pack = ITensorPack();
+ _impl->pack.add_tensor(TensorType::ACL_SRC_0, input);
+ _impl->pack.add_tensor(TensorType::ACL_DST, output);
+}
+
+Status NELogicalNot::validate(const ITensorInfo *input, const ITensorInfo *output)
+{
+ return kernels::NELogicalKernel::validate(input, nullptr, output, kernels::LogicalOperation::Not);
+}
+
+void NELogicalNot::run()
+{
+ NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->pack);
+}
+} // namespace arm_compute
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/core/Types.h"
+#include "arm_compute/runtime/NEON/functions/NELogical.h"
+#include "arm_compute/runtime/Tensor.h"
+#include "tests/NEON/Accessor.h"
+#include "tests/datasets/ShapeDatasets.h"
+#include "tests/framework/Asserts.h"
+#include "tests/framework/Macros.h"
+#include "tests/validation/Validation.h"
+#include "tests/validation/fixtures/LogicalFixture.h"
+
+namespace arm_compute
+{
+namespace test
+{
+namespace validation
+{
+TEST_SUITE(NEON)
+
+TEST_SUITE(LogicalAnd)
+template <typename T>
+using NELogicalAndFixture = LogicalBinaryOperationValidationFixture<Tensor, Accessor, NELogicalAnd, reference::LogicalBinaryOperation::AND, T>;
+
+FIXTURE_DATA_TEST_CASE(RunSmall, NELogicalAndFixture<uint8_t>, framework::DatasetMode::ALL, zip(datasets::SmallShapes(), datasets::SmallShapes()))
+{
+ // Validate output
+ validate(Accessor(_target), _reference);
+}
+
+FIXTURE_DATA_TEST_CASE(RunSmallBroadcast, NELogicalAndFixture<uint8_t>, framework::DatasetMode::ALL, datasets::SmallShapesBroadcast())
+{
+ // Validate output
+ validate(Accessor(_target), _reference);
+}
+TEST_SUITE_END() // LogicalAnd
+
+TEST_SUITE(LogicalOr)
+template <typename T>
+using NELogicalOrFixture = LogicalBinaryOperationValidationFixture<Tensor, Accessor, NELogicalOr, reference::LogicalBinaryOperation::OR, T>;
+
+FIXTURE_DATA_TEST_CASE(RunSmall, NELogicalOrFixture<uint8_t>, framework::DatasetMode::ALL, zip(datasets::SmallShapes(), datasets::SmallShapes()))
+{
+ // Validate output
+ validate(Accessor(_target), _reference);
+}
+
+FIXTURE_DATA_TEST_CASE(RunSmallBroadcast, NELogicalOrFixture<uint8_t>, framework::DatasetMode::ALL, datasets::SmallShapesBroadcast())
+{
+ // Validate output
+ validate(Accessor(_target), _reference);
+}
+TEST_SUITE_END() // LogicalOr
+
+TEST_SUITE(LogicalNot)
+
+template <typename T>
+using NELogicalNotFixture = LogicalNotValidationFixture<Tensor, Accessor, NELogicalNot, T>;
+
+FIXTURE_DATA_TEST_CASE(RunSmall, NELogicalNotFixture<uint8_t>, framework::DatasetMode::ALL, combine(datasets::SmallShapes(), framework::dataset::make("DataType",
+ DataType::U8)))
+{
+ // Validate output
+ validate(Accessor(_target), _reference);
+}
+TEST_SUITE_END() // LogicalNot
+TEST_SUITE_END() // NEON
+} // namespace validation
+} // namespace test
+} // namespace arm_compute
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_TEST_LOGICAL_FIXTURE
+#define ARM_COMPUTE_TEST_LOGICAL_FIXTURE
+
+#include "arm_compute/core/TensorShape.h"
+#include "arm_compute/core/Types.h"
+#include "tests/AssetsLibrary.h"
+#include "tests/Globals.h"
+#include "tests/IAccessor.h"
+#include "tests/framework/Asserts.h"
+#include "tests/framework/Fixture.h"
+#include "tests/validation/reference/Logical.h"
+
+namespace arm_compute
+{
+namespace test
+{
+namespace validation
+{
+template <typename TensorType, typename AccessorType, typename FunctionType, typename T>
+class LogicalOperationValidationFixtureBase : public framework::Fixture
+{
+protected:
+ template <typename U>
+ void fill(U &&tensor, int i)
+ {
+ constexpr uint8_t zero = 0;
+ constexpr uint8_t one = 0x1;
+ constexpr uint8_t mixed = 0xAA;
+ constexpr uint8_t mixed_bitwise_not = ~(0xAA);
+
+ library->fill_static_values(tensor, i == 0 ?
+ std::vector<uint8_t> { zero, one, zero, one, mixed, zero, mixed } :
+ std::vector<uint8_t> { zero, zero, one, one, zero, mixed, mixed_bitwise_not });
+ }
+
+ void allocate_tensor(std::initializer_list<TensorType *> tensors)
+ {
+ for(auto t : tensors)
+ {
+ ARM_COMPUTE_EXPECT(t->info()->is_resizable(), framework::LogLevel::ERRORS);
+ t->allocator()->allocate();
+ ARM_COMPUTE_EXPECT(!t->info()->is_resizable(), framework::LogLevel::ERRORS);
+ }
+ }
+
+ TensorType _target{};
+ SimpleTensor<T> _reference{};
+};
+
+template <typename TensorType, typename AccessorType, typename FunctionType, reference::LogicalBinaryOperation Op, typename T>
+class LogicalBinaryOperationValidationFixture : public LogicalOperationValidationFixtureBase<TensorType, AccessorType, FunctionType, T>
+{
+ using Parent = LogicalOperationValidationFixtureBase<TensorType, AccessorType, FunctionType, T>;
+
+public:
+ template <typename...>
+ void setup(TensorShape shape0, TensorShape shape1)
+ {
+ Parent::_target = compute_target(shape0, shape1);
+ Parent::_reference = compute_reference(shape0, shape1);
+ }
+
+private:
+ TensorType compute_target(const TensorShape &shape0, const TensorShape &shape1)
+ {
+ TensorType src0 = create_tensor<TensorType>(shape0, _data_type);
+ TensorType src1 = create_tensor<TensorType>(shape1, _data_type);
+ TensorType dst = create_tensor<TensorType>(TensorShape::broadcast_shape(shape0, shape1), _data_type);
+
+ FunctionType logical_binary_op;
+
+ logical_binary_op.configure(&src0, &src1, &dst);
+
+ Parent::allocate_tensor({ &src0, &src1, &dst });
+
+ Parent::fill(AccessorType(src0), 0);
+ Parent::fill(AccessorType(src1), 1);
+
+ logical_binary_op.run();
+
+ return dst;
+ }
+
+ SimpleTensor<T> compute_reference(const TensorShape &shape0, const TensorShape &shape1)
+ {
+ // Create reference
+ SimpleTensor<T> src0{ shape0, _data_type };
+ SimpleTensor<T> src1{ shape1, _data_type };
+
+ // Fill reference
+ Parent::fill(src0, 0);
+ Parent::fill(src1, 1);
+
+ switch(Op)
+ {
+ case reference::LogicalBinaryOperation::OR:
+ return reference::logical_or<T>(src0, src1);
+ case reference::LogicalBinaryOperation::AND:
+ return reference::logical_and<T>(src0, src1);
+ case reference::LogicalBinaryOperation::UNKNOWN:
+ /* fall-through */
+ default:
+ ARM_COMPUTE_ASSERT_FAIL("unknown logical binary operator is given");
+ }
+
+ return SimpleTensor<T> {};
+ }
+
+ static constexpr auto _data_type{ DataType::U8 };
+};
+
+template <typename TensorType, typename AccessorType, typename FunctionType, typename T>
+class LogicalNotValidationFixture : public LogicalOperationValidationFixtureBase<TensorType, AccessorType, FunctionType, T>
+{
+ using Parent = LogicalOperationValidationFixtureBase<TensorType, AccessorType, FunctionType, T>;
+
+public:
+ template <typename...>
+ void setup(TensorShape shape, DataType data_type)
+ {
+ Parent::_target = compute_target(shape, data_type);
+ Parent::_reference = compute_reference(shape, data_type);
+ }
+
+private:
+ TensorType compute_target(const TensorShape &shape, DataType data_type)
+ {
+ TensorType src = create_tensor<TensorType>(shape, data_type);
+ TensorType dst = create_tensor<TensorType>(shape, data_type);
+
+ FunctionType logical_not;
+
+ logical_not.configure(&src, &dst);
+
+ Parent::allocate_tensor({ &src, &dst });
+
+ Parent::fill(AccessorType(src), 0);
+
+ logical_not.run();
+
+ return dst;
+ }
+
+ SimpleTensor<T> compute_reference(const TensorShape &shape, DataType data_type)
+ {
+ // Create reference
+ SimpleTensor<T> src{ shape, data_type };
+
+ // Fill reference
+ Parent::fill(src, 0);
+
+ return reference::logical_not<T>(src);
+ }
+};
+} // namespace validation
+} // namespace test
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_TEST_LOGICAL_FIXTURE */
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "tests/validation/reference/Logical.h"
+
+namespace arm_compute
+{
+namespace test
+{
+namespace validation
+{
+namespace reference
+{
+template <typename T>
+T logical_op(LogicalBinaryOperation op, T src1, T src2)
+{
+ switch(op)
+ {
+ case LogicalBinaryOperation::AND:
+ return src1 && src2;
+ case LogicalBinaryOperation::OR:
+ return src1 || src2;
+ case LogicalBinaryOperation::UNKNOWN:
+ default:
+ ARM_COMPUTE_ERROR_ON_MSG(true, "unknown logical binary operation is given");
+ }
+ return false;
+}
+
+template <size_t dim>
+struct BroadcastUnroll
+{
+ template <typename T>
+ static void unroll(LogicalBinaryOperation op,
+ const SimpleTensor<T> &src1, const SimpleTensor<T> &src2, SimpleTensor<T> &dst,
+ Coordinates &id_src1, Coordinates &id_src2, Coordinates &id_dst)
+ {
+ const bool src1_is_broadcast = (src1.shape()[dim - 1] != dst.shape()[dim - 1]);
+ const bool src2_is_broadcast = (src2.shape()[dim - 1] != dst.shape()[dim - 1]);
+
+ id_src1.set(dim - 1, 0);
+ id_src2.set(dim - 1, 0);
+ id_dst.set(dim - 1, 0);
+#if defined(_OPENMP)
+ #pragma omp parallel for
+#endif /* _OPENMP */
+ for(size_t i = 0; i < dst.shape()[dim - 1]; ++i)
+ {
+ BroadcastUnroll < dim - 1 >::unroll(op, src1, src2, dst, id_src1, id_src2, id_dst);
+
+ id_src1[dim - 1] += !src1_is_broadcast;
+ id_src2[dim - 1] += !src2_is_broadcast;
+ ++id_dst[dim - 1];
+ }
+ }
+};
+
+template <>
+struct BroadcastUnroll<0>
+{
+ template <typename T>
+ static void unroll(LogicalBinaryOperation op, const SimpleTensor<T> &src1, const SimpleTensor<T> &src2, SimpleTensor<T> &dst,
+ Coordinates &id_src1, Coordinates &id_src2, Coordinates &id_dst)
+ {
+ dst[coord2index(dst.shape(), id_dst)] = logical_op(op, src1[coord2index(src1.shape(), id_src1)], src2[coord2index(src2.shape(), id_src2)]);
+ }
+};
+
+template <typename T>
+SimpleTensor<T> logical_or(const SimpleTensor<T> &src1, const SimpleTensor<T> &src2)
+{
+ Coordinates id_src1{};
+ Coordinates id_src2{};
+ Coordinates id_dst{};
+ SimpleTensor<T> dst{ TensorShape::broadcast_shape(src1.shape(), src2.shape()), src1.data_type() };
+
+ BroadcastUnroll<Coordinates::num_max_dimensions>::unroll(LogicalBinaryOperation::OR, src1, src2, dst, id_src1, id_src2, id_dst);
+
+ return dst;
+}
+
+template <typename T>
+SimpleTensor<T> logical_and(const SimpleTensor<T> &src1, const SimpleTensor<T> &src2)
+{
+ Coordinates id_src1{};
+ Coordinates id_src2{};
+ Coordinates id_dst{};
+ SimpleTensor<T> dst{ TensorShape::broadcast_shape(src1.shape(), src2.shape()), src1.data_type() };
+
+ BroadcastUnroll<Coordinates::num_max_dimensions>::unroll(LogicalBinaryOperation::AND, src1, src2, dst, id_src1, id_src2, id_dst);
+
+ return dst;
+}
+
+template <typename T>
+SimpleTensor<T> logical_not(const SimpleTensor<T> &src)
+{
+ SimpleTensor<T> dst(src.shape(), src.data_type());
+#if defined(_OPENMP)
+ #pragma omp parallel for
+#endif /* _OPENMP */
+ for(int i = 0; i < src.num_elements(); ++i)
+ {
+ dst[i] = !src[i];
+ }
+
+ return dst;
+}
+
+template SimpleTensor<uint8_t> logical_or(const SimpleTensor<uint8_t> &src1, const SimpleTensor<uint8_t> &src2);
+template SimpleTensor<uint8_t> logical_and(const SimpleTensor<uint8_t> &src1, const SimpleTensor<uint8_t> &src2);
+template SimpleTensor<uint8_t> logical_not(const SimpleTensor<uint8_t> &src1);
+} // namespace reference
+} // namespace validation
+} // namespace test
+} // namespace arm_compute
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef ARM_COMPUTE_TEST_LOGICAL_H
+#define ARM_COMPUTE_TEST_LOGICAL_H
+
+#include "tests/SimpleTensor.h"
+
+namespace arm_compute
+{
+namespace test
+{
+namespace validation
+{
+namespace reference
+{
+enum class LogicalBinaryOperation
+{
+ UNKNOWN = 0,
+ AND = 1,
+ OR = 2
+};
+
+template <typename T>
+SimpleTensor<T> logical_or(const SimpleTensor<T> &src1, const SimpleTensor<T> &src2);
+template <typename T>
+SimpleTensor<T> logical_and(const SimpleTensor<T> &src1, const SimpleTensor<T> &src2);
+template <typename T>
+SimpleTensor<T> logical_not(const SimpleTensor<T> &src1);
+} // namespace reference
+} // namespace validation
+} // namespace test
+} // namespace arm_compute
+#endif /* ARM_COMPUTE_TEST_LOGICAL_H */
\ No newline at end of file
projects / platform / upstream / armcl.git / commitdiff