radeonsi/gfx11: instruction cache line size is 128 bytes

In gfx11, instruction cache line size is 128 bytes. This patch makes
the neccessary code changes.

v2: instruction store line size is 64 bytes (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>

diff --git a/src/amd/common/ac_rtld.c b/src/amd/common/ac_rtld.c
index 0da1a72..542d293 100644 (file)
--- a/src/amd/common/ac_rtld.c
+++ b/src/amd/common/ac_rtld.c
@@ -458,8 +458,12 @@ bool ac_rtld_open(struct ac_rtld_binary *binary, struct ac_rtld_open_info i)
    else if (i.info->chip_class >= GFX10)
       prefetch_distance = 3;
 
-   if (prefetch_distance)
-      binary->rx_size = align(binary->rx_size + prefetch_distance * 64, 64);
+   if (prefetch_distance) {
+      if (i.info->chip_class >= GFX11)
+         binary->rx_size = align(binary->rx_size + prefetch_distance * 64, 128);
+      else
+         binary->rx_size = align(binary->rx_size + prefetch_distance * 64, 64);
+   }
 
    return true;