i965/gen7.5: Fix lower bound on number of VS URB entries.

Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.

At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader.  But when we turn on support for geometry
shaders, this lower limit will become important.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d0b2fc1..4fcc9fb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -361,6 +361,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 70;
         brw->max_gs_threads = 70;
         brw->urb.size = 128;
+         brw->urb.min_vs_entries = 32;
         brw->urb.max_vs_entries = 640;
         brw->urb.max_gs_entries = 256;
       } else if (brw->gt == 2) {
@@ -368,6 +369,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 280;
         brw->max_gs_threads = 256;
         brw->urb.size = 256;
+         brw->urb.min_vs_entries = 64;
         brw->urb.max_vs_entries = 1664;
         brw->urb.max_gs_entries = 640;
       } else if (brw->gt == 3) {
@@ -375,6 +377,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 280;
         brw->max_gs_threads = 256;
         brw->urb.size = 512;
+         brw->urb.min_vs_entries = 64;
         brw->urb.max_vs_entries = 1664;
         brw->urb.max_gs_entries = 640;
       }
@@ -384,6 +387,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 36;
         brw->max_gs_threads = 36;
         brw->urb.size = 128;
+         brw->urb.min_vs_entries = 32;
         brw->urb.max_vs_entries = 512;
         brw->urb.max_gs_entries = 192;
       } else if (brw->gt == 2) {
@@ -391,6 +395,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 128;
         brw->max_gs_threads = 128;
         brw->urb.size = 256;
+         brw->urb.min_vs_entries = 32;
         brw->urb.max_vs_entries = 704;
         brw->urb.max_gs_entries = 320;
       } else {
@@ -402,6 +407,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 60;
         brw->max_gs_threads = 60;
         brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
+         brw->urb.min_vs_entries = 24;
         brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
         brw->urb.max_gs_entries = 256;
       } else {
@@ -409,6 +415,7 @@ brwCreateContext(int api,
         brw->max_vs_threads = 24;
         brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
         brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
+         brw->urb.min_vs_entries = 24;
         brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
         brw->urb.max_gs_entries = 256;
       }

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 64371cf..57f086b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1073,6 +1073,7 @@ struct brw_context
 
       bool constrained;
 
+      GLuint min_vs_entries;    /* Minimum number of VS entries */
       GLuint max_vs_entries;   /* Maximum number of VS entries */
       GLuint max_gs_entries;   /* Maximum number of GS entries */
 

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index e16d30a..bb4cfa8 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -83,7 +83,7 @@ gen6_upload_urb( struct brw_context *brw )
    brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4);
    brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4);
 
-   assert(brw->urb.nr_vs_entries >= 24);
+   assert(brw->urb.nr_vs_entries >= brw->urb.min_vs_entries);
    assert(brw->urb.nr_vs_entries % 4 == 0);
    assert(brw->urb.nr_gs_entries % 4 == 0);
    assert(vs_size < 5);

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 6683117..6dcdfe4 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -195,9 +195,10 @@ gen7_upload_urb(struct brw_context *brw)
     * additional space it could actually make use of).
     */
 
-   /* VS always requires at least 32 URB entries */
+   /* VS has a lower limit on the number of URB entries */
    unsigned vs_chunks =
-      ALIGN(32 * vs_entry_size_bytes, chunk_size_bytes) / chunk_size_bytes;
+      ALIGN(brw->urb.min_vs_entries * vs_entry_size_bytes, chunk_size_bytes) /
+      chunk_size_bytes;
    unsigned vs_wants =
       ALIGN(brw->urb.max_vs_entries * vs_entry_size_bytes,
             chunk_size_bytes) / chunk_size_bytes - vs_chunks;
@@ -261,7 +262,7 @@ gen7_upload_urb(struct brw_context *brw)
    /* Finally, sanity check to make sure we have at least the minimum number
     * of entries needed for each stage.
     */
-   assert(nr_vs_entries >= 32);
+   assert(nr_vs_entries >= brw->urb.min_vs_entries);
    if (gs_present)
       assert(nr_gs_entries >= 2);