Revert "pinctrl: intel: fix bug of register offset calculation"

This reverts commit c5cdcba3d54b9bd2443bd0afe9f4828f802a944f.

diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index 5979d38..e42d5d4 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -28,7 +28,6 @@
                .padcfglock_offset = BXT_PADCFGLOCK,    \
                .hostown_offset = BXT_HOSTSW_OWN,       \
                .ie_offset = BXT_GPI_IE,                \
-               .gpp_size = 32,                         \
                .pin_base = (s),                        \
                .npins = ((e) - (s) + 1),               \
        }

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 06004d8..392e28d 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -25,6 +25,9 @@
 
 #include "pinctrl-intel.h"
 
+/* Maximum number of pads in each group */
+#define NPADS_IN_GPP                   24
+
 /* Offset from regs */
 #define PADBAR                         0x00c
 #define GPI_IS                         0x100
@@ -170,11 +173,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
                return false;
 
        padno = pin_to_padno(community, pin);
-       gpp = padno / community->gpp_size;
+       gpp = padno / NPADS_IN_GPP;
        offset = community->hostown_offset + gpp * 4;
        hostown = community->regs + offset;
 
-       return !(readl(hostown) & BIT(padno % community->gpp_size));
+       return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
 }
 
 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
@@ -190,7 +193,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
                return false;
 
        padno = pin_to_padno(community, pin);
-       gpp = padno / community->gpp_size;
+       gpp = padno / NPADS_IN_GPP;
 
        /*
         * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
@@ -199,12 +202,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
         */
        offset = community->padcfglock_offset + gpp * 8;
        value = readl(community->regs + offset);
-       if (value & BIT(pin % community->gpp_size))
+       if (value & BIT(pin % NPADS_IN_GPP))
                return true;
 
        offset = community->padcfglock_offset + 4 + gpp * 8;
        value = readl(community->regs + offset);
-       if (value & BIT(pin % community->gpp_size))
+       if (value & BIT(pin % NPADS_IN_GPP))
                return true;
 
        return false;
@@ -660,8 +663,8 @@ static void intel_gpio_irq_ack(struct irq_data *d)
        community = intel_get_community(pctrl, pin);
        if (community) {
                unsigned padno = pin_to_padno(community, pin);
-               unsigned gpp_offset = padno % community->gpp_size;
-               unsigned gpp = padno / community->gpp_size;
+               unsigned gpp_offset = padno % NPADS_IN_GPP;
+               unsigned gpp = padno / NPADS_IN_GPP;
 
                writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
        }
@@ -682,8 +685,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
        community = intel_get_community(pctrl, pin);
        if (community) {
                unsigned padno = pin_to_padno(community, pin);
-               unsigned gpp_offset = padno % community->gpp_size;
-               unsigned gpp = padno / community->gpp_size;
+               unsigned gpp_offset = padno % NPADS_IN_GPP;
+               unsigned gpp = padno / NPADS_IN_GPP;
                void __iomem *reg;
                u32 value;
 
@@ -777,8 +780,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
                return -EINVAL;
 
        padno = pin_to_padno(community, pin);
-       gpp = padno / community->gpp_size;
-       gpp_offset = padno % community->gpp_size;
+       gpp = padno / NPADS_IN_GPP;
+       gpp_offset = padno % NPADS_IN_GPP;
 
        /* Clear the existing wake status */
        writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
@@ -816,14 +819,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
                /* Only interrupts that are enabled */
                pending &= enabled;
 
-               for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
+               for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
                        unsigned padno, irq;
 
                        /*
                         * The last group in community can have less pins
                         * than NPADS_IN_GPP.
                         */
-                       padno = gpp_offset + gpp * community->gpp_size;
+                       padno = gpp_offset + gpp * NPADS_IN_GPP;
                        if (padno >= community->npins)
                                break;
 
@@ -999,8 +1002,7 @@ int intel_pinctrl_probe(struct platform_device *pdev,
 
                community->regs = regs;
                community->pad_regs = regs + padbar;
-               community->ngpps = DIV_ROUND_UP(community->npins,
-                                               community->gpp_size);
+               community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
        }
 
        irq = platform_get_irq(pdev, 0);

diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index b602157..4ec8b57 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -55,8 +55,6 @@ struct intel_function {
  *                  ACPI).
  * @ie_offset: Register offset of GPI_IE from @regs.
  * @pin_base: Starting pin of pins in this community
- * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
- *            HOSTSW_OWN,  GPI_IS, GPI_IE, etc.
  * @npins: Number of pins in this community
  * @regs: Community specific common registers (reserved for core driver)
  * @pad_regs: Community specific pad registers (reserved for core driver)
@@ -70,7 +68,6 @@ struct intel_community {
        unsigned hostown_offset;
        unsigned ie_offset;
        unsigned pin_base;
-       unsigned gpp_size;
        size_t npins;
        void __iomem *regs;
        void __iomem *pad_regs;

diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
index c725a53..1de9ae5 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -30,7 +30,6 @@
                .padcfglock_offset = SPT_PADCFGLOCK,    \
                .hostown_offset = SPT_HOSTSW_OWN,       \
                .ie_offset = SPT_GPI_IE,                \
-               .gpp_size = 24,                         \
                .pin_base = (s),                        \
                .npins = ((e) - (s) + 1),               \
        }