if (csline == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
- priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000);
- dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP);
+ if (priv->gpiod_nre) {
+ priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000);
+ dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP);
+ }
priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000);
dev_dbg(dev, "using %u ns write pulse width\n", priv->tWP);
return err;
}
- priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_LOW);
+ priv->gpiod_nre = devm_gpiod_get_optional(&pdev->dev, "nre",
+ GPIOD_OUT_LOW);
if (IS_ERR(priv->gpiod_nre)) {
err = PTR_ERR(priv->gpiod_nre);
dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err);