+2016-06-15 David Edelsohn <dje.gcc@gmail.com>
+
+ Backport from mainline
+ 2016-06-13 David Edelsohn <dje.gcc@gmail.com>
+
+ * inclhack.def (aix_stdlib_malloc): New fix.
+ (aix_stdlib_realloc): New fix.
+ (aix_stdlib_calloc): New fix.
+ (aix_stdlib_valloc): New fix.
+ * fixincl.x: Regenerate.
+ * tests/base/stdlib.h [AIX_STDLIB_MALLOC]: New test.
+ [AIX_STDLIB_REALLOC]: New test.
+ [AIX_STDLIB_CALLOC]: New test.
+ [AIX_STDLIB_VALLOC]: New test.
+
2016-04-27 Release Manager
* GCC 6.1.0 released.
*
* DO NOT EDIT THIS FILE (fixincl.x)
*
- * It has been AutoGen-ed Sunday January 31, 2016 at 07:52:05 PM EST
+ * It has been AutoGen-ed June 10, 2016 at 12:56:52 PM by AutoGen 5.18.3
* From the definitions inclhack.def
* and the template file fixincl
*/
-/* DO NOT SVN-MERGE THIS FILE, EITHER Sun 31 Jan 2016 19:52:05 EST
+/* DO NOT SVN-MERGE THIS FILE, EITHER Fri Jun 10 12:56:52 UTC 2016
*
* You must regenerate it. Use the ./genfixes script.
*
* certain ANSI-incompatible system header files which are fixed to work
* correctly with ANSI C and placed in a directory that GNU C will search.
*
- * This file contains 231 fixup descriptions.
+ * This file contains 235 fixup descriptions.
*
* See README for more information.
*
/* * * * * * * * * * * * * * * * * * * * * * * * * *
*
+ * Description of Aix_Stdlib_Malloc fix
+ */
+tSCC zAix_Stdlib_MallocName[] =
+ "aix_stdlib_malloc";
+
+/*
+ * File name selection pattern
+ */
+tSCC zAix_Stdlib_MallocList[] =
+ "stdlib.h\0";
+/*
+ * Machine/OS name selection pattern
+ */
+tSCC* apzAix_Stdlib_MallocMachs[] = {
+ "*-*-aix*",
+ (const char*)NULL };
+
+/*
+ * content selection pattern - do fix if pattern found
+ */
+tSCC zAix_Stdlib_MallocSelect0[] =
+ "#define[ \t]+malloc[ \t]+__linux_malloc";
+
+#define AIX_STDLIB_MALLOC_TEST_CT 1
+static tTestDesc aAix_Stdlib_MallocTests[] = {
+ { TT_EGREP, zAix_Stdlib_MallocSelect0, (regex_t*)NULL }, };
+
+/*
+ * Fix Command Arguments for Aix_Stdlib_Malloc
+ */
+static const char* apzAix_Stdlib_MallocPatch[] = {
+ "format",
+ "extern void *malloc(size_t) __asm__(\"__linux_malloc\");",
+ (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
+ * Description of Aix_Stdlib_Realloc fix
+ */
+tSCC zAix_Stdlib_ReallocName[] =
+ "aix_stdlib_realloc";
+
+/*
+ * File name selection pattern
+ */
+tSCC zAix_Stdlib_ReallocList[] =
+ "stdlib.h\0";
+/*
+ * Machine/OS name selection pattern
+ */
+tSCC* apzAix_Stdlib_ReallocMachs[] = {
+ "*-*-aix*",
+ (const char*)NULL };
+
+/*
+ * content selection pattern - do fix if pattern found
+ */
+tSCC zAix_Stdlib_ReallocSelect0[] =
+ "#define[ \t]+realloc[ \t]+__linux_realloc";
+
+#define AIX_STDLIB_REALLOC_TEST_CT 1
+static tTestDesc aAix_Stdlib_ReallocTests[] = {
+ { TT_EGREP, zAix_Stdlib_ReallocSelect0, (regex_t*)NULL }, };
+
+/*
+ * Fix Command Arguments for Aix_Stdlib_Realloc
+ */
+static const char* apzAix_Stdlib_ReallocPatch[] = {
+ "format",
+ "extern void *realloc(void *, size_t) __asm__(\"__linux_realloc\");",
+ (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
+ * Description of Aix_Stdlib_Calloc fix
+ */
+tSCC zAix_Stdlib_CallocName[] =
+ "aix_stdlib_calloc";
+
+/*
+ * File name selection pattern
+ */
+tSCC zAix_Stdlib_CallocList[] =
+ "stdlib.h\0";
+/*
+ * Machine/OS name selection pattern
+ */
+tSCC* apzAix_Stdlib_CallocMachs[] = {
+ "*-*-aix*",
+ (const char*)NULL };
+
+/*
+ * content selection pattern - do fix if pattern found
+ */
+tSCC zAix_Stdlib_CallocSelect0[] =
+ "#define[ \t]+calloc[ \t]+__linux_calloc";
+
+#define AIX_STDLIB_CALLOC_TEST_CT 1
+static tTestDesc aAix_Stdlib_CallocTests[] = {
+ { TT_EGREP, zAix_Stdlib_CallocSelect0, (regex_t*)NULL }, };
+
+/*
+ * Fix Command Arguments for Aix_Stdlib_Calloc
+ */
+static const char* apzAix_Stdlib_CallocPatch[] = {
+ "format",
+ "extern void *calloc(size_t, size_t) __asm__(\"__linux_calloc\");",
+ (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
+ * Description of Aix_Stdlib_Valloc fix
+ */
+tSCC zAix_Stdlib_VallocName[] =
+ "aix_stdlib_valloc";
+
+/*
+ * File name selection pattern
+ */
+tSCC zAix_Stdlib_VallocList[] =
+ "stdlib.h\0";
+/*
+ * Machine/OS name selection pattern
+ */
+tSCC* apzAix_Stdlib_VallocMachs[] = {
+ "*-*-aix*",
+ (const char*)NULL };
+
+/*
+ * content selection pattern - do fix if pattern found
+ */
+tSCC zAix_Stdlib_VallocSelect0[] =
+ "#define[ \t]+valloc[ \t]+__linux_valloc";
+
+#define AIX_STDLIB_VALLOC_TEST_CT 1
+static tTestDesc aAix_Stdlib_VallocTests[] = {
+ { TT_EGREP, zAix_Stdlib_VallocSelect0, (regex_t*)NULL }, };
+
+/*
+ * Fix Command Arguments for Aix_Stdlib_Valloc
+ */
+static const char* apzAix_Stdlib_VallocPatch[] = {
+ "format",
+ "extern void *valloc(size_t) __asm__(\"__linux_valloc\");",
+ (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
* Description of Aix_Strtof_Const fix
*/
tSCC zAix_Strtof_ConstName[] =
*
* List of all fixes
*/
-#define REGEX_COUNT 268
+#define REGEX_COUNT 272
#define MACH_LIST_SIZE_LIMIT 187
-#define FIX_COUNT 231
+#define FIX_COUNT 235
/*
* Enumerate the fixes
AIX_STDINT_4_FIXIDX,
AIX_STDINT_5_FIXIDX,
AIX_STDIO_INLINE_FIXIDX,
+ AIX_STDLIB_MALLOC_FIXIDX,
+ AIX_STDLIB_REALLOC_FIXIDX,
+ AIX_STDLIB_CALLOC_FIXIDX,
+ AIX_STDLIB_VALLOC_FIXIDX,
AIX_STRTOF_CONST_FIXIDX,
AIX_SYSMACHINE_FIXIDX,
AIX_SYSWAIT_2_FIXIDX,
AIX_STDIO_INLINE_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
aAix_Stdio_InlineTests, apzAix_Stdio_InlinePatch, 0 },
+ { zAix_Stdlib_MallocName, zAix_Stdlib_MallocList,
+ apzAix_Stdlib_MallocMachs,
+ AIX_STDLIB_MALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+ aAix_Stdlib_MallocTests, apzAix_Stdlib_MallocPatch, 0 },
+
+ { zAix_Stdlib_ReallocName, zAix_Stdlib_ReallocList,
+ apzAix_Stdlib_ReallocMachs,
+ AIX_STDLIB_REALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+ aAix_Stdlib_ReallocTests, apzAix_Stdlib_ReallocPatch, 0 },
+
+ { zAix_Stdlib_CallocName, zAix_Stdlib_CallocList,
+ apzAix_Stdlib_CallocMachs,
+ AIX_STDLIB_CALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+ aAix_Stdlib_CallocTests, apzAix_Stdlib_CallocPatch, 0 },
+
+ { zAix_Stdlib_VallocName, zAix_Stdlib_VallocList,
+ apzAix_Stdlib_VallocMachs,
+ AIX_STDLIB_VALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+ aAix_Stdlib_VallocTests, apzAix_Stdlib_VallocPatch, 0 },
+
{ zAix_Strtof_ConstName, zAix_Strtof_ConstList,
apzAix_Strtof_ConstMachs,
AIX_STRTOF_CONST_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
test_text = "#ifdef __cplusplus\n}\n\n#ifdef ferror";
};
+/*
+ * stdlib.h on AIX uses #define on malloc and friends.
+ */
+fix = {
+ hackname = aix_stdlib_malloc;
+ mach = "*-*-aix*";
+ files = stdlib.h;
+ select = "#define[ \t]+malloc[ \t]+__linux_malloc";
+ c_fix = format;
+ c_fix_arg = "extern void *malloc(size_t) __asm__(\"__linux_malloc\");";
+ test_text = "#define malloc __linux_malloc";
+};
+
+fix = {
+ hackname = aix_stdlib_realloc;
+ mach = "*-*-aix*";
+ files = stdlib.h;
+ select = "#define[ \t]+realloc[ \t]+__linux_realloc";
+ c_fix = format;
+ c_fix_arg = "extern void *realloc(void *, size_t) __asm__(\"__linux_realloc\");";
+ test_text = "#define realloc __linux_realloc";
+};
+
+fix = {
+ hackname = aix_stdlib_calloc;
+ mach = "*-*-aix*";
+ files = stdlib.h;
+ select = "#define[ \t]+calloc[ \t]+__linux_calloc";
+ c_fix = format;
+ c_fix_arg = "extern void *calloc(size_t, size_t) __asm__(\"__linux_calloc\");";
+ test_text = "#define calloc __linux_calloc";
+};
+
+fix = {
+ hackname = aix_stdlib_valloc;
+ mach = "*-*-aix*";
+ files = stdlib.h;
+ select = "#define[ \t]+valloc[ \t]+__linux_valloc";
+ c_fix = format;
+ c_fix_arg = "extern void *valloc(size_t) __asm__(\"__linux_valloc\");";
+ test_text = "#define valloc __linux_valloc";
+};
/*
* stdlib.h on AIX 4.3 declares strtof() with a non-const first argument.
+#if defined( AIX_STDLIB_MALLOC_CHECK )
+extern void *malloc(size_t) __asm__("__linux_malloc");
+#endif /* AIX_STDLIB_MALLOC_CHECK */
+
+
+#if defined( AIX_STDLIB_REALLOC_CHECK )
+extern void *realloc(void *, size_t) __asm__("__linux_realloc");
+#endif /* AIX_STDLIB_REALLOC_CHECK */
+
+
+#if defined( AIX_STDLIB_CALLOC_CHECK )
+extern void *calloc(size_t, size_t) __asm__("__linux_calloc");
+#endif /* AIX_STDLIB_CALLOC_CHECK */
+
+
+#if defined( AIX_STDLIB_VALLOC_CHECK )
+extern void *valloc(size_t) __asm__("__linux_valloc");
+#endif /* AIX_STDLIB_VALLOC_CHECK */
+
+
#if defined( AIX_STRTOF_CONST_CHECK )
extern float strtof(const char *, char **);
#endif /* AIX_STRTOF_CONST_CHECK */
+2016-07-08 Martin Liska <mliska@suse.cz>
+
+ Backported from mainline
+ 2016-07-08 Martin Liska <mliska@suse.cz>
+
+ PR middle-end/71606
+ * fold-const.c (fold_convertible_p): As COMPLEX_TYPE
+ folding produces SAVE_EXPRs, thus return false for the type.
+
+2016-07-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000-builtin.def (BU_P9_MISC_1): Remove
+ redundant and erroneous definition of this macro accidentally
+ inserted during backporting.
+ (BU_P9_64BIT_MISC_0): Likewise.
+ (BU_P9_MISC_0): Likewise.
+
+2016-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ Back port from the trunk
+ 2016-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def (smax): Remove float
+ variants.
+ (smin): Likewise.
+ (fmax): New entry.
+ (fmin): Likewise.
+ * config/aarch64/arm_neon.h (vmaxnm_f32): Use
+ __builtin_aarch64_fmaxv2sf.
+ (vmaxnmq_f32): Likewise.
+ (vmaxnmq_f64): Likewise.
+ (vminnm_f32): Likewise.
+ (vminnmq_f32): Likewise.
+ (vminnmq_f64): Likewise.
+
+2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from trunk
+ 2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/71806
+ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Do not
+ enable -mfloat128-hardware by default.
+ (ISA_3_0_MASKS_IEEE): New macro to give all of the VSX options
+ that IEEE 128-bit hardware support needs.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): If
+ -mcpu=power9 -mfloat128, enable -mfloat128-hardware by default.
+ Use ISA_3_0_MASKS_IEEE as the set of options that IEEE 128-bit
+ floating point requires.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document
+ -mfloat128 and -mfloat128-hardware changes.
+
+2016-07-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from mainline r237912
+ 2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal):
+ Exchange the order of the second and third operands in the vpermr
+ instruction tmeplate.
+
+2016-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from the trunk
+ 2016-07-01 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/71720
+ * config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
+ the insns, use an insn form that does not adjust the offset on
+ little endian systems.
+
+2016-07-07 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from mainline r237885
+ 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.md (darn_32): Change the condition to
+ TARGET_P9_MISC instead of TARGET_MODULO.
+ (darn_raw): Replace TARGET_MODULO with TARGET_P9_MISC in the
+ condition expression.
+ (darn): Replace TARGET_MODULO with TARGET_P9_MISC in the
+ condition expression.
+ * config/rs6000/dfp.md (UNSPEC_DTSTSFI): New unspec constant.
+ (DFP_TEST): New code iterator.
+ (dfptstsfi_<code>_mode>): New define_expand.
+ (*dfp_sgnfcnc_<mode>): New define_insn.
+ * config/rs6000/rs6000-builtin.def (BU_P9_MISC_0): Move this macro
+ definition next to BU_P9_MISC_1 definition and change the MASK
+ value to RS6000_BTM_P9_MISC.
+ (BU_P9_MISC_1): Change the MASK value to RS6000_BTM_P9_MISC.
+ (BU_P9_64BIT_MISC_0): Likewise.
+ (BU_P9_DFP_MISC_0): New macro definition.
+ (BU_P9_DFP_MISC_1): New macro definition.
+ (BU_P9_DFP_MISC_2): New macro definition.
+ (BU_P9_DFP_OVERLOAD_1): New macro definition.
+ (BU_P9_DFP_OVERLOAD_2): New macro definition.
+ (BU_P9_DFP_OVERLOAD_3): New macro definition.
+ (TSTSFI_LT_DD): New BU_P9_DFP_MISC_2.
+ (TSTSFI_LT_TD): Likewise.
+ (TSTSFI_EQ_DD): Likewise.
+ (TSTSFI_EQ_TD): Likewise.
+ (TSTSFI_GT_DD): Likewise.
+ (TSTSFI_GT_TD): Likewise.
+ (TSTSFI_OV_DD): Likewise.
+ (TSTSFI_OV_TD): Likewise.
+ (TSTSFI_LT): New BU_P9_DFP_OVERLOAD_2.
+ (TSTSFI_LT_DD): Likewise.
+ (TSTSFI_LT_TD): Likewise.
+ (TSTSFI_EQ): Likewise.
+ (TSTSFI_EQ_DD): Likewise.
+ (TSTSFI_EQ_TD): Likewise.
+ (TSTSFI_GT): Likewise.
+ (TSTSFI_GT_DD): Likewise.
+ (TSTSFI_GT_TD): Likewise.
+ (TSTSFI_OV): Likewise.
+ (TSTSFI_OV_DD): Likewise.
+ (TSTSFI_OV_TD): Likewise.
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+ overloaded test significance functions.
+ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
+ OPTION_MASK_P9_MISC into the representation of this mask.
+ (POWERPC_MASKS): Add OPTION_MASK_P9_MISC into the representation
+ of this mask.
+ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Set the
+ RS6000_BTM_P9_MISC flag in the return value if TARGET_P9_MISC is
+ non-zero.
+ (rs6000_expand_binop_builtin): Enforce that argument 0 of the exp
+ argument is a 6-bit unsigned literal value if the icode argument
+ represents a DFP test significance built-in call.
+ (rs6000_invalid_builtin): Add support for the RS6000_BTM_P9_MISC
+ flag used independently and in combination with the
+ RS6000_BTM_64BIT flag.
+ (rs6000_opt_masks): Add entry for power9-misc command-line option.
+ (rs6000_builtin_mask_names): Add entry for power9-misc
+ command-line option.
+ * config/rs6000/rs6000.h: Redefine TARGET_P9_MISC as 0 if
+ HAVE_AS_POWER9 is not a defined macro. Define MASK_P9_MISC and
+ RS6000_BTM_P9_MISC macros.
+ * config/rs6000/rs6000.opt: Add support for the -mpower9-misc
+ option and change the description of the -mpower9-vector option to
+ enable only vector instructions, removing its erroneously claimed
+ support for scalar instructions.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
+ the ISA 3.0 digital floating point test significance built-in
+ functions.
+
+2016-07-07 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2016-06-13 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/64516
+ * fold-const.c (fold_unary_loc): Preserve alignment when
+ folding a VIEW_CONVERT_EXPR into a MEM_REF.
+
+2016-07-07 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2016-05-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71264
+ * tree-vect-stmts.c (vect_init_vector): Properly deal with
+ vector type val.
+
+ 2016-06-07 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/71423
+ * match.pd ((X | ~Y) -> Y <= X): Properly invert the comparison
+ for signed ops.
+
+ 2016-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71521
+ * tree-vrp.c (extract_range_from_binary_expr_1): Guard
+ division int_const_binop against zero divisor.
+
+ 2016-06-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71452
+ * tree-ssa.c (non_rewritable_lvalue_p): Make sure that the
+ type used for the SSA rewrite has enough precision to cover
+ the dynamic type of the location.
+
+ 2016-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71522
+ * tree-ssa.c (non_rewritable_lvalue_p): Do not rewrite non-float
+ copying into float copying.
+
+2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ Backport from mainline
+ 2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ PR target/50739
+ * config/avr/avr.c (avr_asm_select_section): Strip off
+ SECTION_DECLARED from flags when calling get_section.
+
+2016-07-05 Pat Haugen <pthaugen@us.ibm.com>
+
+ Backport from mainline
+ 2016-06-28 Pat Haugen <pthaugen@us.ibm.com>
+
+ * config/rs6000/rs6000.md ('type' attribute): Add htmsimple/dfp types.
+ ('size' attribute): Add '128'.
+ Include power9.md.
+ (*mov<mode>_hardfloat32, *mov<mode>_hardfloat64, *movdi_internal32,
+ *movdi_internal64, *movdf_update1): Set size attribute to '64'.
+ (add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2,
+ copysign<mode>3, neg<mode>2_hw, abs<mode>2_hw, *nabs<mode>2_hw,
+ *fma<mode>4_hw, *fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw,
+ extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw,
+ *xscvqp<su>wz_<mode>, *xscvqp<su>dz_<mode>, *xscv<su>dqp_<mode>,
+ *trunc<mode>df2_odd): Set size attribute to '128'.
+ (*cmp<mode>_hw): Change type to veccmp and set size attribute to '128'.
+ * config/rs6000/power6.md (power6-fp): Include dfp type.
+ * config/rs6000/power7.md (power7-fp): Likewise.
+ * config/rs6000/power8.md (power8-fp): Likewise.
+ * config/rs6000/power9.md: New file.
+ * config/rs6000/t-rs6000 (MD_INCLUDES): Add power9.md.
+ * config/rs6000/htm.md (*tabort, *tabort<wd>c, *tabort<wd>ci,
+ *trechkpt, *treclaim, *tsr, *ttest): Change type attribute to
+ htmsimple.
+ * config/rs6000/dfp.md (extendsddd2, truncddsd2, extendddtd2,
+ trunctddd2, adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3,
+ divtd3, *cmpdd_internal1, *cmptd_internal1, floatdidd2, floatditd2,
+ ftruncdd2, fixdddi2, ftrunctd2, fixtddi2, dfp_ddedpd_<mode>,
+ dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>, dfp_dscli_<mode>,
+ dfp_dscri_<mode>): Change type attribute to dfp.
+ * config/rs6000/crypto.md (crypto_vshasigma<CR_char>): Change type
+ attribute to vecsimple.
+ * config/rs6000/rs6000.c (power9_cost): Update costs, cache size
+ and prefetch streams.
+ (rs6000_option_override_internal): Remove temporary code setting
+ tuning to power8. Don't set rs6000_sched_groups for power9.
+ (last_scheduled_insn): Change to rtx_insn *.
+ (divide_cnt, vec_load_pendulum): New variables.
+ (rs6000_adjust_cost): Add Power9 to test for store->load separation.
+ (rs6000_issue_rate): Set issue rate for Power9.
+ (is_power9_pairable_vec_type): New.
+ (power9_sched_reorder2): New.
+ (rs6000_sched_reorder2): Call new function for Power9 specific
+ reordering.
+ (insn_must_be_first_in_group): Remove Power9.
+ (insn_must_be_last_in_group): Likewise.
+ (force_new_group): Likewise.
+ (rs6000_sched_init): Fix initialization of last_scheduled_insn.
+ Initialize divide_cnt/vec_load_pendulum.
+ (_rs6000_sched_context, rs6000_init_sched_context,
+ rs6000_set_sched_context): Handle context save/restore of new
+ variables.
+
+2016-07-05 Pat Haugen <pthaugen@us.ibm.com>
+
+ Backport from mainline
+ 2016-06-27 Pat Haugen <pthaugen@us.ibm.com>
+
+ * config/rs6000/rs6000.md ('type' attribute): Add
+ veclogical,veccmpfx,vecexts,vecmove insn types.
+ (*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
+ copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
+ p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
+ (*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
+ *nabs<mode>2_hw): Change type to vecmove.
+ (*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
+ *boolcc<mode>3_internal, *eqv<mode>3_internal,
+ *one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
+ *ieee_128bit_vsx_abs<mode>2_internal,
+ *ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
+ *ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
+ *ieee128_mtvsrd_32bit): Change type to veclogical.
+ (mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
+ *movdi_internal32, *movdi_internal64): Update insn types.
+ * config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
+ vsx_extract_<mode>): Change type to veclogical.
+ (*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
+ (vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
+ *vsx_sign_extend_si_v2di): Change type to vecexts.
+ * config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
+ type to veclogical.
+ (*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
+ *altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
+ *altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx.
+ (*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
+ * config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
+ negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
+ * config/rs6000/40x.md (ppc405-float): Add fpsimple.
+ * config/rs6000/440.md (ppc440-fp): Add fpsimple.
+ * config/rs6000/476.md (ppc476-fp): Add fpsimple.
+ * config/rs6000/601.md (ppc601-fp): Add fpsimple.
+ * config/rs6000/603.md (ppc603-fp): Add fpsimple.
+ * config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
+ * config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
+ (ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
+ (ppc7450-vecsimple): Add veclogical, vecmove.
+ (ppc7450-veccmp): Add veccmpfx.
+ * config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical,
+ vecmove.
+ (ppc8540_vector_compare): Add veccmpfx.
+ * config/rs6000/a2.md (ppca2-fp): Add fpsimple.
+ * config/rs6000/cell.md (cell-fp): Add fpsimple.
+ (cell-vecsimple): Add veclogical, vecmove.
+ (cell-veccmp): Add veccmpfx.
+ * config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple.
+ * config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove,
+ veccmpfx.
+ * config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
+ * config/rs6000/power4.md (power4-fp): Add fpsimple.
+ (power4-vecsimple): Add veclogical, vecmove.
+ (power4-veccmp): Add veccmpfx.
+ * config/rs6000/power5.md (power5-fp): Add fpsimple.
+ * config/rs6000/power6.md (power6-fp): Add fpsimple.
+ (power6-vecsimple): Add veclogical, vecmove.
+ (power6-veccmp): Add veccmpfx.
+ * config/rs6000/power7.md (power7-fp): Add fpsimple.
+ (power7-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/power8.md (power8-fp): Add fpsimple.
+ (power8-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
+ * config/rs6000/titan.md (titan_fp): Add fpsimple.
+ * config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
+ fpsimple.
+ * config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.
+
+2016-07-05 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from mainline r237391
+ 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000.h (RS6000_BTM_COMMON): Add the
+ RS6000_BTM_MODULO flag into the set of flags that are considered
+ to be part of the common configuration.
+
+2016-07-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/71739
+ * tree.c (attribute_value_equal): Use get_attribute_name instead of
+ directly using TREE_PURPOSE.
+
+2016-07-04 Segher Boessenkool <segher@kernel.crashing.org>
+
+ Backport from mainline
+ 2016-06-27 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/71670
+ * config/rs6000/rs6000.md (ashdi3_extswsli_dot): Use
+ gen_ashdi3_extswsli_dot2 instead of gen_ashdi3_extswsli_dot.
+
+2016-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71626
+ * config/i386/i386.c (ix86_expand_vector_move): For SUBREG of
+ a constant, force its SUBREG_REG into memory or register instead
+ of whole op1.
+
+ 2016-06-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/71559
+ * config/i386/i386.c (ix86_fp_cmp_code_to_pcmp_immediate): Fix up
+ returned values and add UN*/LTGT/*ORDERED cases with values matching
+ D operand modifier on vcmp for AVX.
+
+2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r237659
+ 2016-06-21 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/rs6000.h: Add conditional preprocessing directives
+ to disable Power9-specific compiler features if HAVE_AS_POWER9 is
+ not defined.
+
+2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ Backport from trunk
+ 2016-06-27 Peter Bergner <bergner@vnet.ibm.com>
+
+ PR target/71656
+ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
+ OPTION_MASK_P9_DFORM_VECTOR.
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
+ disable -mpower9-dform-vector when using reload.
+ (quad_address_p): Remove 'gpr_p' argument and all associated code.
+ New 'strict' argument. Update all callers. Add strict addressing
+ support.
+ (rs6000_legitimate_offset_address_p): Remove call to
+ virtual_stack_registers_memory_p.
+ (rs6000_legitimize_reload_address): Add quad address support.
+ (rs6000_legitimate_address_p): Move call to quad_address_p above
+ call to virtual_stack_registers_memory_p. Adjust quad_address_p args
+ to account for new strict usage.
+ (rs6000_output_move_128bit): Adjust quad_address_p args to account
+ for new strict usage.
+ * config/rs6000/predicates.md (quad_memory_operand): Likewise.
+
+2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ Backport from mainline
+ 2016-06-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): New #define.
+ (BU_FLOAT128_1): Likewise.
+ (FABSQ): Likewise.
+ (COPYSIGNQ): Likewise.
+ (RS6000_BUILTIN_NANQ): Likewise.
+ (RS6000_BUILTIN_NANSQ): Likewise.
+ (RS6000_BUILTIN_INFQ): Likewise.
+ (RS6000_BUILTIN_HUGE_VALQ): Likewise.
+ * config/rs6000/rs6000.c (rs6000_fold_builtin): New prototype.
+ (TARGET_FOLD_BUILTIN): New #define.
+ (rs6000_builtin_mask_calculate): Add TARGET_FLOAT128 entry.
+ (rs6000_invalid_builtin): Add handling for RS6000_BTM_FLOAT128.
+ (rs6000_fold_builtin): New target hook implementation, handling
+ folding of 128-bit NaNs and infinities.
+ (rs6000_init_builtins): Initialize const_str_type_node; ensure all
+ entries are filled in to avoid problems during bootstrap
+ self-test; define builtins for 128-bit NaNs and infinities.
+ (rs6000_opt_mask): Add entry for float128.
+ * config/rs6000/rs6000.h (RS6000_BTM_FLOAT128): New #define.
+ (RS6000_BTM_COMMON): Include RS6000_BTM_FLOAT128.
+ (rs6000_builtin_type_index): Add RS6000_BTI_const_str.
+ (const_str_type_node): New #define.
+ * config/rs6000/rs6000.md (copysign<mode>3 for IEEE128): Convert
+ to a define_expand that dispatches to either copysign<mode>3_soft
+ or copysign<mode>3_hard.
+ (copysign<mode>3_hard): Rename from copysign<mode>3.
+ (copysign<mode>3_soft): New define_insn.
+ * doc/extend.texi: Document new builtins.
+
+2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ Backport from trunk
+ 2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ PR target/71698
+ * config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow
+ TDmode values.
+
+2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r236992
+ 2016-06-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_slv): New macro.
+ (vec_srv): New macro.
+ * config/rs6000/altivec.md (UNSPEC_VSLV): New value.
+ (UNSPEC_VSRV): New value.
+ (vslv): New insn.
+ (vsrv): New insn.
+ * config/rs6000/rs6000-builtin.def (vslv): New builtin definition.
+ (vsrv): New builtin definition.
+ * config/rs6000/rs6000-c.c (P9V_BUILTIN_VSLV): Macro expansion to
+ define argument types for new builtin.
+ (P9V_BUILTIN_VSRV): Macro expansion to define argument types for
+ new builtin.
+ * doc/extend.texi: Document the new vec_vslv and vec_srv built-in
+ functions.
+
+2016-07-01 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/arm/arm.c (arm_function_ok_for_sibcall): Add another check
+ for NULL decl.
+
+2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r237390
+ 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * config/rs6000/altivec.h (vec_absd): New macro for vector absolute
+ difference unsigned.
+ (vec_absdb): New macro for vector absolute difference unsigned
+ byte.
+ (vec_absdh): New macro for vector absolute difference unsigned
+ half-word.
+ (vec_absdw): New macro for vector absolute difference unsigned word.
+ * config/rs6000/altivec.md (UNSPEC_VADU): New value.
+ (vadu<mode>3): New insn.
+ (*p9_vadu<mode>3): New insn.
+ * config/rs6000/rs6000-builtin.def (vadub): New built-in
+ definition.
+ (vaduh): New built-in definition.
+ (vaduw): New built-in definition.
+ (vadu): New overloaded built-in definition.
+ (vadub): New overloaded built-in definition.
+ (vaduh): New overloaded built-in definition.
+ (vaduw): New overloaded built-in definition.
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+ overloaded vector absolute difference unsigned functions.
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
+ the ISA 3.0 vector absolute difference unsigned built-in functions.
+
+2016-06-30 David Malcolm <dmalcolm@redhat.com>
+
+ Backport from trunk r237880.
+ 2016-06-30 David Malcolm <dmalcolm@redhat.com>
+
+ PR driver/71651
+ * gcc.c (driver::build_option_suggestions): Pass "option" to
+ add_misspelling_candidates.
+ * opts-common.c (add_misspelling_candidates): Add "option" param;
+ use it to avoid adding negated forms for options marked with
+ RejectNegative.
+ * opts.h (add_misspelling_candidates): Add "option" param.
+
+2016-06-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71693
+ * fold-const.c (fold_binary_loc) <case RROTATE_EXPR>: Cast
+ TREE_OPERAND (arg0, 0) and TREE_OPERAND (arg0, 1) to type
+ first when permuting bitwise operation with rotate. Cast
+ TREE_OPERAND (arg0, 0) to type when cancelling two rotations.
+
+2016-06-30 Martin Liska <mliska@suse.cz>
+
+ Parting backport from mainline
+ 2016-06-29 Martin Liska <mliska@suse.cz>
+
+ * ipa-inline-transform.c (inline_call): Remove unnecessary call
+ of build_optimization_node.
+
+2016-06-29 Eric Botcazou <ebotcazou@adacore.com>
+
+ Backport from mainline
+ 2016-06-09 Eric Botcazou <ebotcazou@adacore.com>
+
+ * df-problems.c (df_note_bb_compute): Guard use of DF_INSN_INFO_GET.
+
+2016-06-27 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from trunk
+ 2016-06-21 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * stor-layout.c (layout_type): Move setting complex MODE to
+ layout_type, instead of setting it ahead of time by the caller.
+
+ Back port from trunk
+ 2016-05-11 Alan Modra <amodra@gmail.com>
+
+ * config/rs6000/rs6000.c (is_complex_IBM_long_double,
+ abi_v4_pass_in_fpr): New functions.
+ (rs6000_function_arg_boundary): Exclude complex IBM long double
+ from 64-bit alignment when ABI_V4.
+ (rs6000_function_arg, rs6000_function_arg_advance_1,
+ rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.
+
+ Back port from trunk
+ 2016-05-02 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * machmode.h (mode_complex): Add support to give the complex mode
+ for a given mode.
+ (GET_MODE_COMPLEX_MODE): Likewise.
+ * stor-layout.c (layout_type): For COMPLEX_TYPE, use the mode
+ stored by build_complex_type and gfc_build_complex_type instead of
+ trying to figure out the appropriate mode based on the size. Raise
+ an assertion error, if the type was not set.
+ * genmodes.c (struct mode_data): Add field for the complex type of
+ the given type.
+ (blank_mode): Likewise.
+ (make_complex_modes): Remember the complex mode created in the
+ base type.
+ (emit_mode_complex): Write out the mode_complex array to map a
+ type mode to the complex version.
+ (emit_insn_modes_c): Likewise.
+ * tree.c (build_complex_type): Set the complex type to use before
+ calling layout_type.
+ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Add
+ support for __float128 complex datatypes.
+ (rs6000_hard_regno_mode_ok): Likewise.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_complex_function_value): Likewise.
+ * config/rs6000/rs6000.h (FLOAT128_IEEE_P): Likewise.
+ __float128 and __ibm128 complex.
+ (FLOAT128_IBM_P): Likewise.
+ (ALTIVEC_ARG_MAX_RETURN): Likewise.
+ * doc/extend.texi (Additional Floating Types): Document that
+ -mfloat128 must be used to enable __float128. Document complex
+ __float128 and __ibm128 support.
+
+2016-06-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/71647
+ * omp-low.c (lower_rec_input_clauses): Convert
+ omp_clause_aligned_alignment (c) to size_type_node for the
+ last argument of __builtin_assume_aligned.
+
+2016-06-22 Eric Botcazou <ebotcazou@adacore.com>
+
+ * function.c (assign_parm_setup_reg): Prevent sharing in another case.
+
+2016-06-21 Georg-Johann Lay <avr@gjlay.de>
+
+ Backport from 2016-06-21 trunk r237639.
+
+ PR target/30417
+ * config/avr/gen-avr-mmcu-specs.c (print_mcu):
+ [*link_data_start]: Wrap -Tdata into %{!Tdata:...}.
+ [*link_text_start]: Wrap -Ttext into %{!Ttext:...}.
+
+2016-06-21 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/71103
+ * config/avr/avr.md (movqi): Only handle loading subreg:qi of
+ constant addresses if can_create_pseudo_p.
+
+2016-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/71588
+ * tree-ssa-strlen.c (valid_builtin_call): New function.
+ (adjust_last_stmt, handle_builtin_memset, strlen_optimize_stmt): Use
+ it.
+
+ Backported from mainline
+ 2016-06-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71581
+ * tree-ssa-uninit.c (warn_uninit): If EXPR and VAR are NULL,
+ see if T isn't anonymous SSA_NAME with COMPLEX_EXPR created
+ for conversion of scalar user var to complex type and use the
+ underlying SSA_NAME_VAR in that case. If EXPR is still NULL,
+ punt.
+
+ 2016-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ * gimplify.c (gimplify_scan_omp_clauses): Handle COMPONENT_REFs
+ with base of reference to struct.
+
+2016-06-20 Ilya Enkovich <ilya.enkovich@intel.com>
+
+ Backport from mainline r237484.
+ 2016-06-15 Ilya Enkovich <ilya.enkovich@intel.com>
+
+ PR middle-end/71529
+ * ipa-chkp.c (chkp_build_instrumented_fndecl): Fix
+ DECL_CONTEXT for copied arguments.
+
+2016-06-20 Georg-Johann Lay <avr@gjlay.de>
+ Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+
+ Backport from 2016-06-20 trunk r237589, r236558.
+
+ PR target/71103
+ * config/avr/avr.md (movqi): Handle loading subreg:qi (const,
+ symbol_ref,label_ref).
+
+2016-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/71554
+ * config/i386/i386.md (setcc + movzbl peephole2): Use reg_set_p.
+ (setcc + and peephole2): Likewise.
+
+2016-06-15 Andreas Tobler <andreast@gcc.gnu.org>
+
+ Backported from mainline
+ 2016-06-14 Andreas Tobler <andreast@gcc.gnu.org>
+
+ * config/arm/freebsd.h: Only enable unaligned access for armv6 on
+ FreeBSD 11 and above.
+
+2016-06-15 Ilya Verbin <ilya.verbin@intel.com>
+
+ Backport from mainline
+ 2016-04-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * config/darwin.h (LINK_COMMAND_SPEC_A): Handle -fcilkplus.
+
2016-06-14 Jakub Jelinek <jakub@redhat.com>
Backported from mainline
+2016-07-05 Markus Trippelsdorf <markus@trippelsdorf.de>
+
+ PR c++/71214
+ * c-cppbuiltin.c (c_cpp_builtins): Define __cpp_rvalue_references.
+
2016-06-14 Jakub Jelinek <jakub@redhat.com>
Backported from mainline
cpp_define (pfile, "__cpp_decltype=200707");
cpp_define (pfile, "__cpp_attributes=200809");
cpp_define (pfile, "__cpp_rvalue_reference=200610");
+ cpp_define (pfile, "__cpp_rvalue_references=200610");
cpp_define (pfile, "__cpp_variadic_templates=200704");
cpp_define (pfile, "__cpp_initializer_lists=200806");
cpp_define (pfile, "__cpp_delegating_constructors=200604");
+2016-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-06-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/71685
+ * c-typeck.c (c_build_qualified_type): Don't clear
+ C_TYPE_INCOMPLETE_VARS for the main variant.
+
2016-06-10 Thomas Schwinge <thomas@codesourcery.com>
PR c/71381
: build_qualified_type (type, type_quals));
/* A variant type does not inherit the list of incomplete vars from the
type main variant. */
- if (RECORD_OR_UNION_TYPE_P (var_type))
+ if (RECORD_OR_UNION_TYPE_P (var_type)
+ && TYPE_MAIN_VARIANT (var_type) != var_type)
C_TYPE_INCOMPLETE_VARS (var_type) = 0;
return var_type;
}
/* Implemented by <maxmin><mode>3.
smax variants map to fmaxnm,
smax_nan variants map to fmax. */
- BUILTIN_VDQIF (BINOP, smax, 3)
- BUILTIN_VDQIF (BINOP, smin, 3)
+ BUILTIN_VDQ_BHSI (BINOP, smax, 3)
+ BUILTIN_VDQ_BHSI (BINOP, smin, 3)
BUILTIN_VDQ_BHSI (BINOP, umax, 3)
BUILTIN_VDQ_BHSI (BINOP, umin, 3)
BUILTIN_VDQF (BINOP, smax_nan, 3)
BUILTIN_VDQF (BINOP, smin_nan, 3)
+ /* Implemented by <fmaxmin><mode>3. */
+ BUILTIN_VDQF (BINOP, fmax, 3)
+ BUILTIN_VDQF (BINOP, fmin, 3)
+
/* Implemented by aarch64_<maxmin_uns>p<mode>. */
BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vmaxnm_f32 (float32x2_t __a, float32x2_t __b)
{
- return __builtin_aarch64_smaxv2sf (__a, __b);
+ return __builtin_aarch64_fmaxv2sf (__a, __b);
}
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
{
- return __builtin_aarch64_smaxv4sf (__a, __b);
+ return __builtin_aarch64_fmaxv4sf (__a, __b);
}
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vmaxnmq_f64 (float64x2_t __a, float64x2_t __b)
{
- return __builtin_aarch64_smaxv2df (__a, __b);
+ return __builtin_aarch64_fmaxv2df (__a, __b);
}
/* vmaxv */
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vminnm_f32 (float32x2_t __a, float32x2_t __b)
{
- return __builtin_aarch64_sminv2sf (__a, __b);
+ return __builtin_aarch64_fminv2sf (__a, __b);
}
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vminnmq_f32 (float32x4_t __a, float32x4_t __b)
{
- return __builtin_aarch64_sminv4sf (__a, __b);
+ return __builtin_aarch64_fminv4sf (__a, __b);
}
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vminnmq_f64 (float64x2_t __a, float64x2_t __b)
{
- return __builtin_aarch64_sminv2df (__a, __b);
+ return __builtin_aarch64_fminv2df (__a, __b);
}
/* vminv */
/* The PIC register is live on entry to VxWorks PLT entries, so we
must make the call before restoring the PIC register. */
- if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
+ if (TARGET_VXWORKS_RTP && flag_pic && decl && !targetm.binds_local_p (decl))
return false;
/* If we are interworking and the function is not declared static
#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9
#endif
+/* FreeBSD 10 does not support unaligned access for armv6 and up.
+ Unaligned access support was added in FreeBSD 11. */
+#if FBSD_MAJOR < 11
#define SUBTARGET_OVERRIDE_INTERNAL_OPTIONS \
do { \
if (opts_set->x_unaligned_access == 1) \
if (opts->x_unaligned_access) \
opts->x_unaligned_access = 0; \
} while (0)
+#endif
#undef MAX_SYNC_LIBFUNC_SIZE
#define MAX_SYNC_LIBFUNC_SIZE 4 /* UNITS_PER_WORD not defined yet. */
{
const char *sname = ACONCAT ((new_prefix,
name + strlen (old_prefix), NULL));
- return get_section (sname, sect->common.flags, sect->named.decl);
+ return get_section (sname,
+ sect->common.flags & ~SECTION_DECLARED,
+ sect->named.decl);
}
}
if (avr_mem_flash_p (dest))
DONE;
+ if (QImode == <MODE>mode
+ && SUBREG_P (src)
+ && CONSTANT_ADDRESS_P (SUBREG_REG (src))
+ && can_create_pseudo_p())
+ {
+ // store_bitfield may want to store a SYMBOL_REF or CONST in a
+ // structure that's represented as PSImode. As the upper 16 bits
+ // of PSImode cannot be expressed as an HImode subreg, the rhs is
+ // decomposed into QImode (word_mode) subregs of SYMBOL_REF,
+ // CONST or LABEL_REF; cf. PR71103.
+
+ rtx const_addr = SUBREG_REG (src);
+ operands[1] = src = copy_rtx (src);
+ SUBREG_REG (src) = copy_to_mode_reg (GET_MODE (const_addr), const_addr);
+ }
+
/* One of the operands has to be in a register. */
if (!register_operand (dest, <MODE>mode)
&& !reg_or_0_operand (src, <MODE>mode))
#include "avr-devices.c"
-// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBS' and
+// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBC' and
// and `WITH_RTEMS'. */
#define GCC_DEFAULTS_H
fprintf (f, "*link_data_start:\n");
if (mcu->data_section_start
!= arch->default_data_section_start)
- fprintf (f, "\t-Tdata 0x%lX", 0x800000UL + mcu->data_section_start);
+ fprintf (f, "\t%%{!Tdata:-Tdata 0x%lX}",
+ 0x800000UL + mcu->data_section_start);
fprintf (f, "\n\n");
fprintf (f, "*link_text_start:\n");
if (mcu->text_section_start != 0x0)
- fprintf (f, "\t-Ttext 0x%lX", 0UL + mcu->text_section_start);
+ fprintf (f, "\t%%{!Ttext:-Ttext 0x%lX}", 0UL + mcu->text_section_start);
fprintf (f, "\n\n");
}
%{L*} %(link_libgcc) %o %{fprofile-arcs|fprofile-generate*|coverage:-lgcov} \
%{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1): \
%{static|static-libgcc|static-libstdc++|static-libgfortran: libgomp.a%s; : -lgomp } } \
+ %{fcilkplus:%:include(libcilkrts.spec)%(link_cilkrts)} \
%{fgnu-tm: \
%{static|static-libgcc|static-libstdc++|static-libgfortran: libitm.a%s; : -litm } } \
%{!nostdlib:%{!nodefaultlibs:\
of the register, once we have that information we may be able
to handle some of them more efficiently. */
if (can_create_pseudo_p ()
- && register_operand (op0, mode)
&& (CONSTANT_P (op1)
|| (SUBREG_P (op1)
&& CONSTANT_P (SUBREG_REG (op1))))
- && !standard_sse_constant_p (op1))
- op1 = validize_mem (force_const_mem (mode, op1));
+ && ((register_operand (op0, mode)
+ && !standard_sse_constant_p (op1))
+ /* ix86_expand_vector_move_misalign() does not like constants. */
+ || (SSE_REG_MODE_P (mode)
+ && MEM_P (op0)
+ && MEM_ALIGN (op0) < align)))
+ {
+ if (SUBREG_P (op1))
+ {
+ machine_mode imode = GET_MODE (SUBREG_REG (op1));
+ rtx r = force_const_mem (imode, SUBREG_REG (op1));
+ if (r)
+ r = validize_mem (r);
+ else
+ r = force_reg (imode, SUBREG_REG (op1));
+ op1 = simplify_gen_subreg (mode, r, imode, SUBREG_BYTE (op1));
+ }
+ else
+ op1 = validize_mem (force_const_mem (mode, op1));
+ }
/* We need to check memory alignment for SSE mode since attribute
can make operands unaligned. */
{
rtx tmp[2];
- /* ix86_expand_vector_move_misalign() does not like constants ... */
- if (CONSTANT_P (op1)
- || (SUBREG_P (op1)
- && CONSTANT_P (SUBREG_REG (op1))))
- op1 = validize_mem (force_const_mem (mode, op1));
-
- /* ... nor both arguments in memory. */
+ /* ix86_expand_vector_move_misalign() does not like both
+ arguments in memory. */
if (!register_operand (op0, mode)
&& !register_operand (op1, mode))
op1 = force_reg (mode, op1);
switch (code)
{
case EQ:
- return 0x08;
+ return 0x00;
case NE:
return 0x04;
case GT:
- return 0x16;
+ return 0x0e;
case LE:
- return 0x1a;
+ return 0x02;
case GE:
- return 0x15;
+ return 0x0d;
case LT:
- return 0x19;
+ return 0x01;
+ case UNLE:
+ return 0x0a;
+ case UNLT:
+ return 0x09;
+ case UNGE:
+ return 0x05;
+ case UNGT:
+ return 0x06;
+ case UNEQ:
+ return 0x18;
+ case LTGT:
+ return 0x0c;
+ case ORDERED:
+ return 0x07;
+ case UNORDERED:
+ return 0x03;
default:
gcc_unreachable ();
}
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
&& ! reg_overlap_mentioned_p (operands[3], operands[0])
- && ! (GET_CODE (operands[4]) == CLOBBER
- && reg_mentioned_p (operands[3], operands[4]))"
+ && ! reg_set_p (operands[3], operands[4])"
[(parallel [(set (match_dup 5) (match_dup 0))
(match_dup 4)])
(set (strict_low_part (match_dup 6))
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
&& ! reg_overlap_mentioned_p (operands[3], operands[0])
- && ! (GET_CODE (operands[4]) == CLOBBER
- && reg_mentioned_p (operands[3], operands[4]))"
+ && ! reg_set_p (operands[3], operands[4])"
[(parallel [(set (match_dup 5) (match_dup 0))
(match_dup 4)])
(set (strict_low_part (match_dup 6))
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
- (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
+ (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
ppc476_f_pipe+ppc476_i_pipe")
(define_insn_reservation "ppc476-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe")
"(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601")
(define_insn_reservation "ppc601-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601")
"(fpu_603+iu_603*2),bpu_603")
(define_insn_reservation "ppc603-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc603"))
"fpu_603")
"fpu_6xx")
(define_insn_reservation "ppc604-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
"ppc7450_du,fpu_7450")
(define_insn_reservation "ppc7450-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
;; Altivec
(define_insn_reservation "ppc7450-vecsimple" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-veccmp" 2
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
;; Altivec
(define_insn_reservation "ppc7400-vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; D.8.1
(define_insn_reservation "ppca2-fp" 6
- (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppca2"))
"axu")
#ifdef _ARCH_PPC64
#define vec_vprtybq __builtin_vec_vprtybq
#endif
+
+#define vec_slv __builtin_vec_vslv
+#define vec_srv __builtin_vec_vsrv
+
+#define vec_absd __builtin_vec_vadu
+#define vec_absdb __builtin_vec_vadub
+#define vec_absdh __builtin_vec_vaduh
+#define vec_absdw __builtin_vec_vaduw
#endif
/* Predicates.
UNSPEC_STVLXL
UNSPEC_STVRX
UNSPEC_STVRXL
+ UNSPEC_VSLV
+ UNSPEC_VSRV
+ UNSPEC_VADU
UNSPEC_VMULWHUB
UNSPEC_VMULWLUB
UNSPEC_VMULWHSB
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*")
+ [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*")
(set_attr "length" "4,4,4,20,20,20,4,8,32")])
;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
+ [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")])
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpequ<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_gt<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgts<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_gtu<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgtu<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_eqv4sf"
[(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*altivec_vsel<mode>_uns"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Fused multiply add.
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
+(define_insn "vslv"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+ (match_operand:V16QI 2 "register_operand" "v")]
+ UNSPEC_VSLV))]
+ "TARGET_P9_VECTOR"
+ "vslv %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "vsrv"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+ (match_operand:V16QI 2 "register_operand" "v")]
+ UNSPEC_VSRV))]
+ "TARGET_P9_VECTOR"
+ "vsrv %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "*altivec_vsl<VI_char>"
[(set (match_operand:VI2 0 "register_operand" "=v")
(ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
UNSPEC_VPERMR))]
"TARGET_P9_VECTOR"
"@
- vpermr %0,%1,%2,%3
+ vpermr %0,%2,%1,%3
xxpermr %x0,%x2,%x3"
[(set_attr "type" "vecperm")
(set_attr "length" "4")])
(match_dup 2)))]
"<VI_unit>"
"vcmpequ<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgts<VI_char>_p"
[(set (reg:CC 74)
(match_dup 2)))]
"<VI_unit>"
"vcmpgts<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgtu<VI_char>_p"
[(set (reg:CC 74)
(match_dup 2)))]
"<VI_unit>"
"vcmpgtu<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpeqfp_p"
[(set (reg:CC 74)
[(set_attr "length" "4")
(set_attr "type" "vecsimple")])
+;; Vector absolute difference unsigned
+(define_expand "vadu<mode>3"
+ [(set (match_operand:VI 0 "register_operand")
+ (unspec:VI [(match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "register_operand")]
+ UNSPEC_VADU))]
+ "TARGET_P9_VECTOR")
+
+;; Vector absolute difference unsigned
+(define_insn "*p9_vadu<mode>3"
+ [(set (match_operand:VI 0 "register_operand" "=v")
+ (unspec:VI [(match_operand:VI 1 "register_operand" "v")
+ (match_operand:VI 2 "register_operand" "v")]
+ UNSPEC_VADU))]
+ "TARGET_P9_VECTOR"
+ "vabsdu<wd> %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
;; Vector count trailing zeros
(define_insn "*p9v_ctz<mode>2"
[(set (match_operand:VI2 0 "register_operand" "=v")
(define_insn "darn_32"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
- "TARGET_MODULO"
+ "TARGET_P9_MISC"
"darn %0,0"
[(set_attr "type" "integer")])
(define_insn "darn_raw"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
- "TARGET_MODULO && TARGET_64BIT"
+ "TARGET_P9_MISC && TARGET_64BIT"
"darn %0,2"
[(set_attr "type" "integer")])
(define_insn "darn"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] UNSPEC_DARN))]
- "TARGET_MODULO && TARGET_64BIT"
+ "TARGET_P9_MISC && TARGET_64BIT"
"darn %0,1"
[(set_attr "type" "integer")])
; Basic FP latency is 10 cycles, thoughput is 1/cycle
(define_insn_reservation "cell-fp" 10
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*8")
; VMX
(define_insn_reservation "cell-vecsimple" 4
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
;; TODO: add support for recording instructions
(define_insn_reservation "cell-veccmp" 4
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
UNSPEC_VSHASIGMA))]
"TARGET_CRYPTO"
"vshasigma<CR_char> %0,%1,%2,%3"
- [(set_attr "type" "crypto")])
+ [(set_attr "type" "vecsimple")])
(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
"TARGET_DFP"
"dctdp %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_expand "extendsdtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drsp %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_expand "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_expand "abstd2"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_insn "*nabstd2_fpr"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
;; Hardware support for decimal floating point operations.
(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctqpq %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
;; The result of drdpq is an even/odd register pair with the converted
;; value in the even register and zero in the odd register.
(clobber (match_scratch:TD 2 "=d"))]
"TARGET_DFP"
"drdpq %2,%1\;fmr %0,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "adddd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dadd %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "addtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"daddq %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "subdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dsub %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "subtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dsubq %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "muldd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dmul %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "multd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dmulq %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "divdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"ddiv %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "divtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"ddivq %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "*cmpdd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcmpu %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "dfp")])
(define_insn "*cmptd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcmpuq %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "dfp")])
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "floatditd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcffixq %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
;; Convert a decimal64 to a decimal64 whose value is an integer.
;; This is the first stage of converting it to an integer type.
(fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drintn. 0,%0,%1,1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
;; Convert a decimal64 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.
(fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctfix %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
;; Convert a decimal128 to a decimal128 whose value is an integer.
;; This is the first stage of converting it to an integer type.
(fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drintnq. 0,%0,%1,1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
;; Convert a decimal128 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.
(fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctfixq %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
\f
;; Decimal builtin support
UNSPEC_DXEX
UNSPEC_DIEX
UNSPEC_DSCLI
+ UNSPEC_DTSTSFI
UNSPEC_DSCRI])
+(define_code_iterator DFP_TEST [eq lt gt unordered])
+
(define_mode_iterator D64_D128 [DD TD])
(define_mode_attr dfp_suffix [(DD "")
UNSPEC_DDEDPD))]
"TARGET_DFP"
"ddedpd<dfp_suffix> %1,%0,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "dfp_denbcd_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
UNSPEC_DENBCD))]
"TARGET_DFP"
"denbcd<dfp_suffix> %1,%0,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "dfp_dxex_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
UNSPEC_DXEX))]
"TARGET_DFP"
"dxex<dfp_suffix> %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "dfp_diex_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
UNSPEC_DXEX))]
"TARGET_DFP"
"diex<dfp_suffix> %0,%1,%2"
+ [(set_attr "type" "dfp")])
+
+(define_expand "dfptstsfi_<code>_<mode>"
+ [(set (match_dup 3)
+ (compare:CCFP
+ (unspec:D64_D128
+ [(match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+ UNSPEC_DTSTSFI)
+ (match_dup 4)))
+ (set (match_operand:SI 0 "register_operand" "")
+ (DFP_TEST:SI (match_dup 3)
+ (const_int 0)))
+ ]
+ "TARGET_P9_MISC"
+{
+ operands[3] = gen_reg_rtx (CCFPmode);
+ operands[4] = const0_rtx;
+})
+
+(define_insn "*dfp_sgnfcnc_<mode>"
+ [(set (match_operand:CCFP 0 "" "=y")
+ (compare:CCFP
+ (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+ UNSPEC_DTSTSFI)
+ (match_operand:SI 3 "zero_constant" "j")))]
+ "TARGET_P9_MISC"
+{
+ /* If immediate operand is greater than 63, it will behave as if
+ the value had been 63. The code generator does not support
+ immediate operand values greater than 63. */
+ if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
+ operands[1] = GEN_INT (63);
+ return "dtstsfi<dfp_suffix> %0,%1,%2";
+}
[(set_attr "type" "fp")])
(define_insn "dfp_dscli_<mode>"
UNSPEC_DSCLI))]
"TARGET_DFP"
"dscli<dfp_suffix> %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
(define_insn "dfp_dscri_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
UNSPEC_DSCRI))]
"TARGET_DFP"
"dscri<dfp_suffix> %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "dfp")])
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
;; VSFX.
(define_insn_reservation "e6500_vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort. %0"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tabort<wd>c"
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>c. %0,%1,%2"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tabort<wd>ci"
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>ci. %0,%1,%2"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tbegin"
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"trechkpt."
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "treclaim"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"treclaim. %0"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tsr"
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tsr. %0"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "ttest"
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabortwci. 0,1,0"
- [(set_attr "type" "htm")
+ [(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_insn "htm_mfspr_<mode>"
"fpu_mpc,bpu_mpc")
(define_insn_reservation "mpccore-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*2")
; Basic FP latency is 6 cycles
(define_insn_reservation "power4-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power4"))
"fpq_power4")
; VMX
(define_insn_reservation "power4-vecsimple" 2
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power4"))
"vq_power4")
; vecfp compare
(define_insn_reservation "power4-veccmp" 8
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power4"))
"vq_power4")
; Basic FP latency is 6 cycles
(define_insn_reservation "power5-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power5"))
"fpq_power5")
(define_bypass 9 "power6-mtcr" "power6-branch")
(define_insn_reservation "power6-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power6"))
"FPU_power6")
"LSF_power6")
(define_insn_reservation "power6-vecsimple" 3
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
(define_insn_reservation "power6-veccmp" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power6"))
"FPU_power6")
; VS Unit (includes FP/VSX/VMX/DFP)
(define_insn_reservation "power7-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
"DU_power7,VSU_power7")
(define_insn_reservation "power7-vecsimple" 2
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
(define_insn_reservation "power8-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecsimple" 2
- (and (eq_attr "type" "vecperm,vecsimple,veccmp")
+ (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp,
+ veccmpfx")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
--- /dev/null
+;; Scheduling description for IBM POWER9 processor.
+;; Copyright (C) 2016 Free Software Foundation, Inc.
+;;
+;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "power9dsp,power9lsu,power9vsu,power9misc")
+
+(define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu")
+(define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu")
+; Two vector permute units, part of vsu
+(define_cpu_unit "prm0_power9,prm1_power9" "power9vsu")
+; Two fixed point divide units, not pipelined
+(define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc")
+(define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc")
+
+(define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9,
+ x2_power9,x3_power9,xb0_power9,xb1_power9,
+ br0_power9,br1_power9" "power9dsp")
+
+
+; Dispatch port reservations
+;
+; Power9 can dispatch a maximum of 6 iops per cycle with the following
+; general restrictions (other restrictions also apply):
+; 1) At most 2 iops per execution slice
+; 2) At most 2 iops to the branch unit
+; Note that insn position in a dispatch group of 6 insns does not infer which
+; execution slice the insn is routed to. The units are used to infer the
+; conflicts that exist (i.e. an 'even' requirement will preclude dispatch
+; with 2 insns with 'superslice' requirement).
+
+; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but
+; are listed as separate units to allow those insns that preclude its use to
+; still be scheduled two to a superslice while reserving the 3rd slot. The
+; same applies for xb0/xb1.
+(define_reservation "DU_xa_power9" "xa0_power9+xa1_power9")
+(define_reservation "DU_xb_power9" "xb0_power9+xb1_power9")
+
+; Any execution slice dispatch
+(define_reservation "DU_any_power9"
+ "x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9|
+ DU_xb_power9")
+
+; Even slice, actually takes even/odd slots
+(define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9")
+
+; Slice plus 3rd slot
+(define_reservation "DU_slice_3_power9"
+ "x0_power9+xa0_power9|x1_power9+xa1_power9|
+ x2_power9+xb0_power9|x3_power9+xb1_power9")
+
+; Superslice
+(define_reservation "DU_super_power9"
+ "x0_power9+x1_power9|x2_power9+x3_power9")
+
+; 2-way cracked
+(define_reservation "DU_C2_power9" "x0_power9+x1_power9|
+ x1_power9+DU_xa_power9|
+ x1_power9+x2_power9|
+ DU_xa_power9+x2_power9|
+ x2_power9+x3_power9|
+ x3_power9+DU_xb_power9")
+
+; 2-way cracked plus 3rd slot
+(define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9|
+ x1_power9+x2_power9+xa0_power9|
+ x1_power9+x2_power9+xb0_power9|
+ x2_power9+x3_power9+xb0_power9")
+
+; 3-way cracked (consumes whole decode/dispatch cycle)
+(define_reservation "DU_C3_power9"
+ "x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+
+ x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9")
+
+; Branch ports
+(define_reservation "DU_branch_power9" "br0_power9|br1_power9")
+
+
+; Execution unit reservations
+(define_reservation "LSU_power9"
+ "lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9")
+
+(define_reservation "LSU_pair_power9"
+ "lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9|
+ lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9")
+
+(define_reservation "VSU_power9"
+ "vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9")
+
+(define_reservation "VSU_super_power9"
+ "vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9")
+
+(define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9")
+
+
+; LS Unit
+(define_insn_reservation "power9-load" 4
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "no")
+ (eq_attr "update" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,LSU_power9")
+
+(define_insn_reservation "power9-load-update" 4
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "no")
+ (eq_attr "update" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-load-ext" 6
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "yes")
+ (eq_attr "update" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,LSU_power9")
+
+(define_insn_reservation "power9-load-ext-update" 6
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "yes")
+ (eq_attr "update" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C3_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-fpload-double" 4
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "no")
+ (eq_attr "size" "64")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,LSU_power9")
+
+(define_insn_reservation "power9-fpload-update-double" 4
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "yes")
+ (eq_attr "size" "64")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9+VSU_power9")
+
+; SFmode loads are cracked and have additional 2 cycles over DFmode
+(define_insn_reservation "power9-fpload-single" 6
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "no")
+ (eq_attr "size" "32")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9")
+
+(define_insn_reservation "power9-fpload-update-single" 6
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "yes")
+ (eq_attr "size" "32")
+ (eq_attr "cpu" "power9"))
+ "DU_C3_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-vecload" 5
+ (and (eq_attr "type" "vecload")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,LSU_pair_power9")
+
+; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store
+(define_insn_reservation "power9-store" 0
+ (and (eq_attr "type" "store")
+ (eq_attr "update" "no")
+ (eq_attr "indexed" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,LSU_power9")
+
+(define_insn_reservation "power9-store-indexed" 0
+ (and (eq_attr "type" "store")
+ (eq_attr "update" "no")
+ (eq_attr "indexed" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,LSU_power9")
+
+; Update forms have 2 cycle latency for updated addr reg
+(define_insn_reservation "power9-store-update" 2
+ (and (eq_attr "type" "store")
+ (eq_attr "update" "yes")
+ (eq_attr "indexed" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9+VSU_power9")
+
+; Update forms have 2 cycle latency for updated addr reg
+(define_insn_reservation "power9-store-update-indexed" 2
+ (and (eq_attr "type" "store")
+ (eq_attr "update" "yes")
+ (eq_attr "indexed" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-fpstore" 0
+ (and (eq_attr "type" "fpstore")
+ (eq_attr "update" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,LSU_power9")
+
+; Update forms have 2 cycle latency for updated addr reg
+(define_insn_reservation "power9-fpstore-update" 2
+ (and (eq_attr "type" "fpstore")
+ (eq_attr "update" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-vecstore" 0
+ (and (eq_attr "type" "vecstore")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,LSU_pair_power9")
+
+(define_insn_reservation "power9-larx" 4
+ (and (eq_attr "type" "load_l")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,LSU_power9")
+
+(define_insn_reservation "power9-stcx" 2
+ (and (eq_attr "type" "store_c")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_3_power9,LSU_power9+VSU_power9")
+
+(define_insn_reservation "power9-sync" 4
+ (and (eq_attr "type" "sync,isync")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,LSU_power9")
+
+
+; VSU Execution Unit
+
+; Fixed point ops
+
+; Most ALU insns are simple 2 cycle, including record form
+(define_insn_reservation "power9-alu" 2
+ (and (ior (eq_attr "type" "add,cmp,exts,integer,logical,isel")
+ (and (eq_attr "type" "insert,shift")
+ (eq_attr "dot" "no")))
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+; Record form rotate/shift are cracked
+(define_insn_reservation "power9-cracked-alu" 2
+ (and (eq_attr "type" "insert,shift")
+ (eq_attr "dot" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,VSU_power9")
+; 4 cycle CR latency
+(define_bypass 4 "power9-cracked-alu"
+ "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+
+(define_insn_reservation "power9-alu2" 3
+ (and (eq_attr "type" "cntlz,popcnt,trap")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+; Treat 'two' and 'three' types as 2 or 3 way cracked
+(define_insn_reservation "power9-two" 4
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,VSU_power9")
+
+(define_insn_reservation "power9-three" 6
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "power9"))
+ "DU_C3_power9,VSU_power9")
+
+(define_insn_reservation "power9-mul" 4
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+(define_insn_reservation "power9-mul-compare" 4
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,VSU_power9")
+; 6 cycle CR latency
+(define_bypass 6 "power9-mul-compare"
+ "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+
+; Fixed point divides reserve the divide units for a minimum of 8 cycles
+(define_insn_reservation "power9-idiv" 16
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
+ (eq_attr "cpu" "power9"))
+ "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
+
+(define_insn_reservation "power9-ldiv" 24
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
+ (eq_attr "cpu" "power9"))
+ "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
+
+(define_insn_reservation "power9-crlogical" 2
+ (and (eq_attr "type" "cr_logical,delayed_cr")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+(define_insn_reservation "power9-mfcrf" 2
+ (and (eq_attr "type" "mfcrf")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+(define_insn_reservation "power9-mfcr" 6
+ (and (eq_attr "type" "mfcr")
+ (eq_attr "cpu" "power9"))
+ "DU_C3_power9,VSU_power9")
+
+; Should differentiate between 1 cr field and > 1 since target of > 1 cr
+; is cracked
+(define_insn_reservation "power9-mtcr" 2
+ (and (eq_attr "type" "mtcr")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+; Move to LR/CTR are executed in VSU
+(define_insn_reservation "power9-mtjmpr" 5
+ (and (eq_attr "type" "mtjmpr")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+; Floating point/Vector ops
+(define_insn_reservation "power9-fpsimple" 2
+ (and (eq_attr "type" "fpsimple")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-fp" 7
+ (and (eq_attr "type" "fp,dmul")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-fpcompare" 3
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other
+; divide insns, but for the most part do not block pipelined ops.
+(define_insn_reservation "power9-sdiv" 22
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-ddiv" 33
+ (and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-sqrt" 26
+ (and (eq_attr "type" "ssqrt")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-dsqrt" 36
+ (and (eq_attr "type" "dsqrt")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-vec-2cyc" 2
+ (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-veccmp" 3
+ (and (eq_attr "type" "veccmp")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-vecsimple" 3
+ (and (eq_attr "type" "vecsimple")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-vecnormal" 7
+ (and (eq_attr "type" "vecfloat,vecdouble")
+ (eq_attr "size" "!128")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+; Quad-precision FP ops, execute in DFU
+(define_insn_reservation "power9-qp" 12
+ (and (eq_attr "type" "vecfloat,vecdouble")
+ (eq_attr "size" "128")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,dfu_power9")
+
+(define_insn_reservation "power9-vecperm" 3
+ (and (eq_attr "type" "vecperm")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_PRM_power9")
+
+(define_insn_reservation "power9-veccomplex" 7
+ (and (eq_attr "type" "veccomplex")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-vecfdiv" 28
+ (and (eq_attr "type" "vecfdiv")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-vecdiv" 32
+ (and (eq_attr "type" "vecdiv")
+ (eq_attr "size" "!128")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,VSU_super_power9")
+
+(define_insn_reservation "power9-qpdiv" 56
+ (and (eq_attr "type" "vecdiv")
+ (eq_attr "size" "128")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,dfu_power9")
+
+(define_insn_reservation "power9-mffgpr" 2
+ (and (eq_attr "type" "mffgpr")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+(define_insn_reservation "power9-mftgpr" 2
+ (and (eq_attr "type" "mftgpr")
+ (eq_attr "cpu" "power9"))
+ "DU_slice_3_power9,VSU_power9")
+
+
+; Branch Unit
+; Move from LR/CTR are executed in BRU but consume a writeback port from an
+; execution slice.
+(define_insn_reservation "power9-mfjmpr" 6
+ (and (eq_attr "type" "mfjmpr")
+ (eq_attr "cpu" "power9"))
+ "DU_branch_power9,bru_power9+VSU_power9")
+
+; Branch is 2 cycles
+(define_insn_reservation "power9-branch" 2
+ (and (eq_attr "type" "jmpreg,branch")
+ (eq_attr "cpu" "power9"))
+ "DU_branch_power9,bru_power9")
+
+
+; Crypto Unit
+(define_insn_reservation "power9-crypto" 6
+ (and (eq_attr "type" "crypto")
+ (eq_attr "cpu" "power9"))
+ "DU_super_power9,cryptu_power9")
+
+
+; HTM Unit
+(define_insn_reservation "power9-htm" 4
+ (and (eq_attr "type" "htm")
+ (eq_attr "cpu" "power9"))
+ "DU_C2_power9,LSU_power9")
+
+(define_insn_reservation "power9-htm-simple" 2
+ (and (eq_attr "type" "htmsimple")
+ (eq_attr "cpu" "power9"))
+ "DU_any_power9,VSU_power9")
+
+
+; DFP Unit
+(define_insn_reservation "power9-dfp" 12
+ (and (eq_attr "type" "dfp")
+ (eq_attr "cpu" "power9"))
+ "DU_even_power9,dfu_power9")
+
if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
return false;
- return quad_address_p (XEXP (op, 0), mode, true);
+ return quad_address_p (XEXP (op, 0), mode, false);
})
;; Return 1 if the operand is suitable for load/store to vector registers with
/* Miscellaneous builtins for instructions added in ISA 3.0. These
instructions don't require either the DFP or VSX options, just the basic
ISA 3.0 enablement since they operate on general purpose registers. */
+#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_" NAME, /* NAME */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_SPECIAL), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO, /* MASK */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO \
+ RS6000_BTM_P9_MISC \
| RS6000_BTM_64BIT, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* Miscellaneous builtins for instructions added in ISA 3.0. These
- instructions don't require either the DFP or VSX options, just the basic
- ISA 3.0 enablement since they operate on general purpose registers. */
-#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \
+/* Miscellaneous builtins for decimal floating point instructions
+ added in ISA 3.0. These instructions don't require the VSX
+ options, just the basic ISA 3.0 enablement since they operate on
+ general purpose registers. */
+#define BU_P9_DFP_MISC_0(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO, /* MASK */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* 128-bit long double floating point builtins. */
-#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_" NAME, /* NAME */ \
- (RS6000_BTM_HARD_FLOAT /* MASK */ \
- | RS6000_BTM_LDBL128), \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_BINARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-
-/* Miscellaneous builtins for instructions added in ISA 3.0. These
- instructions don't require either the DFP or VSX options, just the basic
- ISA 3.0 enablement since they operate on general purpose registers. */
-#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \
+#define BU_P9_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO, /* MASK */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_UNARY), \
+ | RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* Miscellaneous builtins for instructions added in ISA 3.0. These
- instructions don't require either the DFP or VSX options, just the basic
- ISA 3.0 enablement since they operate on general purpose registers,
- and they require 64-bit addressing. */
-#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
+#define BU_P9_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO \
- | RS6000_BTM_64BIT, /* MASK */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* Miscellaneous builtins for instructions added in ISA 3.0. These
- instructions don't require either the DFP or VSX options, just the basic
- ISA 3.0 enablement since they operate on general purpose registers. */
-#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
+/* Decimal floating point overloaded functions added in ISA 3.0 */
+#define BU_P9_DFP_OVERLOAD_1(ENUM, NAME) \
+ RS6000_BUILTIN_1 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \
+ "__builtin_dfp_" NAME, /* NAME */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
+ (RS6000_BTC_OVERLOADED /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_nothing) /* ICODE */
+
+#define BU_P9_DFP_OVERLOAD_2(ENUM, NAME) \
+ RS6000_BUILTIN_2 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \
+ "__builtin_dfp_" NAME, /* NAME */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
+ (RS6000_BTC_OVERLOADED /* ATTR */ \
+ | RS6000_BTC_BINARY), \
+ CODE_FOR_nothing) /* ICODE */
+
+#define BU_P9_DFP_OVERLOAD_3(ENUM, NAME) \
+ RS6000_BUILTIN_3 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \
+ "__builtin_dfp_" NAME, /* NAME */ \
+ RS6000_BTM_P9_MISC, /* MASK */ \
+ (RS6000_BTC_OVERLOADED /* ATTR */ \
+ | RS6000_BTC_TERNARY), \
+ CODE_FOR_nothing) /* ICODE */
+
+/* 128-bit long double floating point builtins. */
+#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
- RS6000_BTM_MODULO, /* MASK */ \
+ (RS6000_BTM_HARD_FLOAT /* MASK */ \
+ | RS6000_BTM_LDBL128), \
(RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_SPECIAL), \
+ | RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
+/* IEEE 128-bit floating-point builtins. */
+#define BU_FLOAT128_2(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_" NAME, /* NAME */ \
+ RS6000_BTM_FLOAT128, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_BINARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
+#define BU_FLOAT128_1(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_" NAME, /* NAME */ \
+ RS6000_BTM_FLOAT128, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
/* ISA 3.0 (power9) vector convenience macros. */
/* For the instructions that are encoded as altivec instructions use
__builtin_altivec_ as the builtin name. */
BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq")
BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm")
+/* ISA 3.0 vector overloaded 2-argument functions. */
+BU_P9V_AV_2 (VSLV, "vslv", CONST, vslv)
+BU_P9V_AV_2 (VSRV, "vsrv", CONST, vsrv)
+
+/* ISA 3.0 vector overloaded 2-argument functions. */
+BU_P9V_OVERLOAD_2 (VSLV, "vslv")
+BU_P9V_OVERLOAD_2 (VSRV, "vsrv")
+
+/* 2 argument vector functions added in ISA 3.0 (power9). */
+BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3)
+BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3)
+BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3)
+
+/* ISA 3.0 vector overloaded 2 argument functions. */
+BU_P9V_OVERLOAD_2 (VADU, "vadu")
+BU_P9V_OVERLOAD_2 (VADUB, "vadub")
+BU_P9V_OVERLOAD_2 (VADUH, "vaduh")
+BU_P9V_OVERLOAD_2 (VADUW, "vaduw")
+
\f
/* 2 argument extended divide functions added in ISA 2.06. */
BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)
BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)
BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)
+/* 2 argument DFP (Decimal Floating Point) functions added in ISA 3.0. */
+BU_P9_DFP_MISC_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, dfptstsfi_lt_dd)
+BU_P9_DFP_MISC_2 (TSTSFI_LT_TD, "dtstsfi_lt_td", CONST, dfptstsfi_lt_td)
+
+BU_P9_DFP_MISC_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd", CONST, dfptstsfi_eq_dd)
+BU_P9_DFP_MISC_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td", CONST, dfptstsfi_eq_td)
+
+BU_P9_DFP_MISC_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd", CONST, dfptstsfi_gt_dd)
+BU_P9_DFP_MISC_2 (TSTSFI_GT_TD, "dtstsfi_gt_td", CONST, dfptstsfi_gt_td)
+
+BU_P9_DFP_MISC_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd", CONST, dfptstsfi_unordered_dd)
+BU_P9_DFP_MISC_2 (TSTSFI_OV_TD, "dtstsfi_ov_td", CONST, dfptstsfi_unordered_td)
+
+/* 2 argument overloaded DFP functions added in ISA 3.0. */
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT, "dtstsfi_lt")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_TD, "dtstsfi_lt_td")
+
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ, "dtstsfi_eq")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td")
+
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT, "dtstsfi_gt")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_TD, "dtstsfi_gt_td")
+
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV, "dtstsfi_ov")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd")
+BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_TD, "dtstsfi_ov_td")
+
/* 1 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2)
BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2)
BU_P9V_OVERLOAD_1 (VPRTYBQ, "vprtybq")
BU_P9V_OVERLOAD_1 (VPRTYBW, "vprtybw")
+/* 1 argument IEEE 128-bit floating-point functions. */
+BU_FLOAT128_1 (FABSQ, "fabsq", CONST, abskf2)
+
+/* 2 argument IEEE 128-bit floating-point functions. */
+BU_FLOAT128_2 (COPYSIGNQ, "copysignq", CONST, copysignkf3)
\f
/* 1 argument crypto functions. */
BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox)
BU_SPECIAL_X (RS6000_BUILTIN_CPU_SUPPORTS, "__builtin_cpu_supports",
RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
+BU_SPECIAL_X (RS6000_BUILTIN_NANQ, "__builtin_nanq",
+ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
+
+BU_SPECIAL_X (RS6000_BUILTIN_NANSQ, "__builtin_nansq",
+ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
+
+BU_SPECIAL_X (RS6000_BUILTIN_INFQ, "__builtin_infq",
+ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
+
+BU_SPECIAL_X (RS6000_BUILTIN_HUGE_VALQ, "__builtin_huge_valq",
+ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
+
/* Darwin CfString builtin. */
BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC)
{ P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
+ { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
+ { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
+ RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
+
{ P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
{ P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
+ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_unsigned_V16QI, 0 },
+ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
+ RS6000_BTI_unsigned_V8HI, 0 },
+ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
+ RS6000_BTI_unsigned_V4SI, 0 },
+
+ { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_unsigned_V16QI, 0 },
+
+ { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
+ RS6000_BTI_unsigned_V8HI, 0 },
+
+ { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
+ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
+ RS6000_BTI_unsigned_V4SI, 0 },
+
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
+ { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_unsigned_V16QI, 0 },
+ { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_unsigned_V16QI, 0 },
+
/* Crypto builtins. */
{ CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
| OPTION_MASK_UPPER_REGS_SF)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- P9_MINMAX until the hardware that supports it is available. Do not add
- P9_DFORM_VECTOR until LRA is the default register allocator. */
+ P9_MINMAX until the hardware that supports it is available. Do not add
+ FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
- | OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_DFORM_SCALAR \
+ | OPTION_MASK_P9_DFORM_VECTOR \
+ | OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR)
+/* Support for the IEEE 128-bit floating point hardware requires a lot of the
+ VSX instructions that are part of ISA 3.0. */
+#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
+ | OPTION_MASK_P8_VECTOR \
+ | OPTION_MASK_P9_VECTOR \
+ | OPTION_MASK_DIRECT_MOVE \
+ | OPTION_MASK_UPPER_REGS_DF \
+ | OPTION_MASK_UPPER_REGS_SF)
+
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
/* Deal with ports that do not have -mstrict-align. */
| OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_MINMAX \
+ | OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_POPCNTB \
| OPTION_MASK_POPCNTD \
COSTS_N_INSNS (3), /* mulsi_const */
COSTS_N_INSNS (3), /* mulsi_const9 */
COSTS_N_INSNS (3), /* muldi */
- COSTS_N_INSNS (19), /* divsi */
- COSTS_N_INSNS (35), /* divdi */
+ COSTS_N_INSNS (8), /* divsi */
+ COSTS_N_INSNS (12), /* divdi */
COSTS_N_INSNS (3), /* fp */
COSTS_N_INSNS (3), /* dmul */
- COSTS_N_INSNS (14), /* sdiv */
- COSTS_N_INSNS (17), /* ddiv */
+ COSTS_N_INSNS (13), /* sdiv */
+ COSTS_N_INSNS (18), /* ddiv */
128, /* cache line size */
32, /* l1 cache */
- 256, /* l2 cache */
- 12, /* prefetch streams */
+ 512, /* l2 cache */
+ 8, /* prefetch streams */
COSTS_N_INSNS (3), /* SF->DF convert */
};
bool);
rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
+static tree rs6000_fold_builtin (tree, int, tree *, bool);
/* Hash table stuff for keeping track of TOC entries. */
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL rs6000_builtin_decl
+#undef TARGET_FOLD_BUILTIN
+#define TARGET_FOLD_BUILTIN rs6000_fold_builtin
+
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
128-bit floating point that can go in vector registers, which has VSX
memory addressing. */
if (FP_REGNO_P (regno))
- reg_size = (VECTOR_MEM_VSX_P (mode)
+ reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ if (COMPLEX_MODE_P (mode))
+ mode = GET_MODE_INNER (mode);
+
/* PTImode can only go in GPRs. Quad word memory operations require even/odd
register combinations, and use PTImode where we need to deal with quad
word memory operations. Don't allow quad words in the argument or frame
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
- machine_mode m2 = (machine_mode)m;
- unsigned short msize = GET_MODE_SIZE (m2);
+ machine_mode m2 = (machine_mode) m;
+ bool complex_p = false;
+ size_t msize;
+
+ if (COMPLEX_MODE_P (m2))
+ {
+ complex_p = true;
+ m2 = GET_MODE_INNER (m2);
+ }
+
+ msize = GET_MODE_SIZE (m2);
/* SDmode is special in that we want to access it only via REG+REG
addressing on power7 and above, since we want to use the LFIWZX and
/* Indicate if the mode takes more than 1 physical register. If
it takes a single register, indicate it can do REG+REG
addressing. */
- if (nregs > 1 || m == BLKmode)
+ if (nregs > 1 || m == BLKmode || complex_p)
addr_mask |= RELOAD_REG_MULTIPLE;
else
addr_mask |= RELOAD_REG_INDEXED;
&& msize <= 8
&& !VECTOR_MODE_P (m2)
&& !FLOAT128_VECTOR_P (m2)
- && !COMPLEX_MODE_P (m2)
+ && !complex_p
&& (m2 != DFmode || !TARGET_UPPER_REGS_DF)
&& (m2 != SFmode || !TARGET_UPPER_REGS_SF)
&& !(TARGET_E500_DOUBLE && msize == 8))
| ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
| ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
| ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
+ | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
| ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
| ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
| ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
| ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
| ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
| ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
- | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0));
+ | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
+ | ((TARGET_FLOAT128) ? RS6000_BTM_FLOAT128 : 0));
}
/* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
if (rs6000_tune_index >= 0)
tune_index = rs6000_tune_index;
else if (have_cpu)
- {
- /* Until power9 tuning is available, use power8 tuning if -mcpu=power9. */
- if (processor_target_table[cpu_index].processor != PROCESSOR_POWER9)
- rs6000_tune_index = tune_index = cpu_index;
- else
- {
- size_t i;
- tune_index = -1;
- for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
- if (processor_target_table[i].processor == PROCESSOR_POWER8)
- {
- rs6000_tune_index = tune_index = i;
- break;
- }
- }
- }
+ rs6000_tune_index = tune_index = cpu_index;
else
{
size_t i;
rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
/* -mpower9-dform turns on both -mpower9-dform-scalar and
- -mpower9-dform-vector. There are currently problems if
- -mpower9-dform-vector instructions are enabled when we use the RELOAD
- register allocator. */
+ -mpower9-dform-vector. */
if (TARGET_P9_DFORM_BOTH > 0)
{
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR)
- && TARGET_LRA)
+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR))
rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR;
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR))
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
}
- /* There have been bugs with both -mvsx-timode and -mpower9-dform-vector that
- don't show up with -mlra, but do show up with -mno-lra. Given -mlra will
- become the default once PR 69847 is fixed, turn off the options with
- problems by default if -mno-lra was used, and warn if the user explicitly
- asked for the option.
+ /* There have been bugs with -mvsx-timode that don't show up with -mlra,
+ but do show up with -mno-lra. Given -mlra will become the default once
+ PR 69847 is fixed, turn off the options with problems by default if
+ -mno-lra was used, and warn if the user explicitly asked for the option.
Enable -mpower9-dform-vector by default if LRA and other power9 options.
Enable -mvsx-timode by default if LRA and VSX. */
else
rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
}
-
- if (TARGET_P9_DFORM_VECTOR)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) != 0)
- warning (0, "-mpower9-dform-vector might need -mlra");
-
- else
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_VECTOR;
- }
}
else
if (TARGET_VSX && !TARGET_VSX_TIMODE
&& (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0)
rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE;
-
- if (TARGET_VSX && TARGET_P9_VECTOR && !TARGET_P9_DFORM_VECTOR
- && TARGET_P9_DFORM_SCALAR && TARGET_P9_DFORM_BOTH < 0
- && (rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) == 0)
- rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR;
}
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128 | OPTION_MASK_FLOAT128_HW);
}
+ /* If we have -mfloat128 and full ISA 3.0 support, enable -mfloat128-hardware
+ by default. */
+ if (TARGET_FLOAT128 && !TARGET_FLOAT128_HW
+ && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
+ && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
+ {
+ rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
+ if ((rs6000_isa_flags & OPTION_MASK_FLOAT128) != 0)
+ rs6000_isa_flags_explicit |= OPTION_MASK_FLOAT128_HW;
+ }
+
/* IEEE 128-bit floating point hardware instructions imply enabling
__float128. */
if (TARGET_FLOAT128_HW
- && (rs6000_isa_flags & (OPTION_MASK_P9_VECTOR
- | OPTION_MASK_DIRECT_MOVE
- | OPTION_MASK_UPPER_REGS_DF
- | OPTION_MASK_UPPER_REGS_SF)) == 0)
+ && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
{
if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
error ("-mfloat128-hardware requires full ISA 3.0 support");
rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
}
- else if (TARGET_P9_VECTOR && !TARGET_FLOAT128_HW
- && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) == 0)
- rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
-
if (TARGET_FLOAT128_HW
&& (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128) == 0)
rs6000_isa_flags |= OPTION_MASK_FLOAT128;
rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
|| rs6000_cpu == PROCESSOR_POWER5
|| rs6000_cpu == PROCESSOR_POWER7
- || rs6000_cpu == PROCESSOR_POWER8
- || rs6000_cpu == PROCESSOR_POWER9);
+ || rs6000_cpu == PROCESSOR_POWER8);
rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
|| rs6000_cpu == PROCESSOR_POWER5
|| rs6000_cpu == PROCESSOR_POWER6
3.0 LXV/STXV instruction. */
bool
-quad_address_p (rtx addr, machine_mode mode, bool gpr_p)
+quad_address_p (rtx addr, machine_mode mode, bool strict)
{
rtx op0, op1;
if (GET_MODE_SIZE (mode) != 16)
return false;
- if (gpr_p)
- {
- if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
- return false;
-
- /* LQ/STQ can handle indirect addresses. */
- if (base_reg_operand (addr, Pmode))
- return true;
- }
+ if (legitimate_indirect_address_p (addr, strict))
+ return true;
- else
- {
- if (!mode_supports_vsx_dform_quad (mode))
- return false;
- }
+ if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
+ return false;
if (GET_CODE (addr) != PLUS)
return false;
op0 = XEXP (addr, 0);
- if (!base_reg_operand (op0, Pmode))
+ if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
return false;
op1 = XEXP (addr, 1);
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
if (mode_supports_vsx_dform_quad (mode))
- return (virtual_stack_registers_memory_p (x)
- || quad_address_p (x, mode, false));
+ return quad_address_p (x, mode, strict);
if (!reg_offset_addressing_ok_p (mode))
return virtual_stack_registers_memory_p (x);
if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
int ind_levels ATTRIBUTE_UNUSED, int *win)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
+ bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
/* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
if (TARGET_CMODEL != CMODEL_SMALL
&& reg_offset_p
+ && !quad_offset_p
&& small_toc_ref (x, VOIDmode))
{
rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
}
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
&& INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& reg_offset_p
&& !SPE_VECTOR_MODE (mode)
&& !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
- && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
+ && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
HOST_WIDE_INT high
= (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
- /* Check for 32-bit overflow. */
- if (high + low != val)
+ /* Check for 32-bit overflow or quad addresses with one of the
+ four least significant bits set. */
+ if (high + low != val
+ || (quad_offset_p && (low & 0xf)))
{
*win = 0;
return x;
if (GET_CODE (x) == SYMBOL_REF
&& reg_offset_p
+ && !quad_offset_p
&& (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
&& !SPE_VECTOR_MODE (mode)
#if TARGET_MACHO
if (TARGET_TOC
&& reg_offset_p
+ && !quad_offset_p
&& GET_CODE (x) == SYMBOL_REF
&& use_toc_relative_ref (x, mode))
{
&& mode_supports_pre_incdec_p (mode)
&& legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
return 1;
- if (virtual_stack_registers_memory_p (x))
- return 1;
-
/* Handle restricted vector d-form offsets in ISA 3.0. */
if (quad_offset_p)
{
- if (quad_address_p (x, mode, false))
+ if (quad_address_p (x, mode, reg_ok_strict))
return 1;
}
+ else if (virtual_stack_registers_memory_p (x))
+ return 1;
else if (reg_offset_p)
{
return must_pass_in_stack_var_size_or_pad (mode, type);
}
+static inline bool
+is_complex_IBM_long_double (machine_mode mode)
+{
+ return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode);
+}
+
+/* Whether ABI_V4 passes MODE args to a function in floating point
+ registers. */
+
+static bool
+abi_v4_pass_in_fpr (machine_mode mode)
+{
+ if (!TARGET_FPRS || !TARGET_HARD_FLOAT)
+ return false;
+ if (TARGET_SINGLE_FLOAT && mode == SFmode)
+ return true;
+ if (TARGET_DOUBLE_FLOAT && mode == DFmode)
+ return true;
+ /* ABI_V4 passes complex IBM long double in 8 gprs.
+ Stupid, but we can't change the ABI now. */
+ if (is_complex_IBM_long_double (mode))
+ return false;
+ if (FLOAT128_2REG_P (mode))
+ return true;
+ if (DECIMAL_FLOAT_MODE_P (mode))
+ return true;
+ return false;
+}
+
/* If defined, a C expression which determines whether, and in which
direction, to pad out an argument with extra space. The value
should be of type `enum direction': either `upward' to pad above
&& (GET_MODE_SIZE (mode) == 8
|| (TARGET_HARD_FLOAT
&& TARGET_FPRS
+ && !is_complex_IBM_long_double (mode)
&& FLOAT128_2REG_P (mode))))
return 64;
else if (FLOAT128_VECTOR_P (mode))
}
else if (DEFAULT_ABI == ABI_V4)
{
- if (TARGET_HARD_FLOAT && TARGET_FPRS
- && ((TARGET_SINGLE_FLOAT && mode == SFmode)
- || (TARGET_DOUBLE_FLOAT && mode == DFmode)
- || FLOAT128_2REG_P (mode)
- || DECIMAL_FLOAT_MODE_P (mode)))
+ if (abi_v4_pass_in_fpr (mode))
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */
else if (abi == ABI_V4)
{
- if (TARGET_HARD_FLOAT && TARGET_FPRS
- && ((TARGET_SINGLE_FLOAT && mode == SFmode)
- || (TARGET_DOUBLE_FLOAT && mode == DFmode)
- || FLOAT128_2REG_P (mode)
- || DECIMAL_FLOAT_MODE_P (mode)))
+ if (abi_v4_pass_in_fpr (mode))
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */
rsize = (size + 3) / 4;
align = 1;
- if (TARGET_HARD_FLOAT && TARGET_FPRS
- && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
- || (TARGET_DOUBLE_FLOAT
- && (TYPE_MODE (type) == DFmode
- || FLOAT128_2REG_P (TYPE_MODE (type))
- || DECIMAL_FLOAT_MODE_P (TYPE_MODE (type))))))
+ machine_mode mode = TYPE_MODE (type);
+ if (abi_v4_pass_in_fpr (mode))
{
/* FP args go in FP registers, if present. */
reg = fpr;
n_reg = (size + 7) / 8;
sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
- if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
+ if (mode != SFmode && mode != SDmode)
align = 8;
}
else
addr = create_tmp_var (ptr_type_node, "addr");
/* AltiVec vectors never go in registers when -mabi=altivec. */
- if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
+ if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
align = 16;
else
{
}
/* _Decimal128 is passed in even/odd fpr pairs; the stored
reg number is 0 for f1, so we want to make it odd. */
- else if (reg == fpr && TYPE_MODE (type) == TDmode)
+ else if (reg == fpr && mode == TDmode)
{
t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
build_int_cst (TREE_TYPE (reg), 1));
FP register for 32-bit binaries. */
if (TARGET_32BIT
&& TARGET_HARD_FLOAT && TARGET_FPRS
- && TYPE_MODE (type) == SDmode)
+ && mode == SDmode)
t = fold_build_pointer_plus_hwi (t, size);
gimplify_assign (addr, t, pre_p);
return const0_rtx;
}
}
+ else if (icode == CODE_FOR_dfptstsfi_eq_dd
+ || icode == CODE_FOR_dfptstsfi_lt_dd
+ || icode == CODE_FOR_dfptstsfi_gt_dd
+ || icode == CODE_FOR_dfptstsfi_unordered_dd
+ || icode == CODE_FOR_dfptstsfi_eq_td
+ || icode == CODE_FOR_dfptstsfi_lt_td
+ || icode == CODE_FOR_dfptstsfi_gt_td
+ || icode == CODE_FOR_dfptstsfi_unordered_td)
+ {
+ /* Only allow 6-bit unsigned literals. */
+ STRIP_NOPS (arg0);
+ if (TREE_CODE (arg0) != INTEGER_CST
+ || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
+ {
+ error ("argument 1 must be a 6-bit unsigned literal");
+ return CONST0_RTX (tmode);
+ }
+ }
if (target == 0
|| GET_MODE (target) != tmode
error ("Builtin function %s requires the -mpower8-vector option", name);
else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
error ("Builtin function %s requires the -mpower9-vector option", name);
+ else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+ == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+ error ("Builtin function %s requires the -mpower9-misc and"
+ " -m64 options", name);
+ else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
+ error ("Builtin function %s requires the -mpower9-misc option", name);
else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
error ("Builtin function %s requires the -mhard-float and"
" -mlong-double-128 options", name);
else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
error ("Builtin function %s requires the -mhard-float option", name);
+ else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
+ error ("Builtin function %s requires the -mfloat128 option", name);
else
error ("Builtin function %s is not supported with the current options",
name);
}
+/* Target hook for early folding of built-ins, shamelessly stolen
+ from ia64.c. */
+
+static tree
+rs6000_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
+ tree *args, bool ignore ATTRIBUTE_UNUSED)
+{
+ if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
+ {
+ enum rs6000_builtins fn_code
+ = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
+ switch (fn_code)
+ {
+ case RS6000_BUILTIN_NANQ:
+ case RS6000_BUILTIN_NANSQ:
+ {
+ tree type = TREE_TYPE (TREE_TYPE (fndecl));
+ const char *str = c_getstr (*args);
+ int quiet = fn_code == RS6000_BUILTIN_NANQ;
+ REAL_VALUE_TYPE real;
+
+ if (str && real_nan (&real, str, quiet, TYPE_MODE (type)))
+ return build_real (type, real);
+ return NULL_TREE;
+ }
+ case RS6000_BUILTIN_INFQ:
+ case RS6000_BUILTIN_HUGE_VALQ:
+ {
+ tree type = TREE_TYPE (TREE_TYPE (fndecl));
+ REAL_VALUE_TYPE inf;
+ real_inf (&inf);
+ return build_real (type, inf);
+ }
+ default:
+ break;
+ }
+ }
+#ifdef SUBTARGET_FOLD_BUILTIN
+ return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
+#else
+ return NULL_TREE;
+#endif
+}
+
/* Expand an expression EXP that calls a built-in function,
with result going to TARGET if that's convenient
(and in mode MODE if that's convenient).
opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
+ const_str_type_node
+ = build_pointer_type (build_qualified_type (char_type_node,
+ TYPE_QUAL_CONST));
+
/* We use V1TI mode as a special container to hold __int128_t items that
must live in VSX registers. */
if (intTI_type_node)
lang_hooks.types.register_builtin_type (ibm128_float_type_node,
"__ibm128");
}
+ else
+ {
+ /* All types must be nonzero, or self-test barfs during bootstrap. */
+ ieee128_float_type_node = long_double_type_node;
+ ibm128_float_type_node = long_double_type_node;
+ }
/* Initialize the modes for builtin_function_type, mapping a machine mode to
tree type node. */
if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
rs6000_common_init_builtins ();
+ ftype = build_function_type_list (ieee128_float_type_node,
+ const_str_type_node, NULL_TREE);
+ def_builtin ("__builtin_nanq", ftype, RS6000_BUILTIN_NANQ);
+ def_builtin ("__builtin_nansq", ftype, RS6000_BUILTIN_NANSQ);
+
+ ftype = build_function_type_list (ieee128_float_type_node, NULL_TREE);
+ def_builtin ("__builtin_infq", ftype, RS6000_BUILTIN_INFQ);
+ def_builtin ("__builtin_huge_valq", ftype, RS6000_BUILTIN_HUGE_VALQ);
+
ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
& ~RELOAD_REG_AND_M16);
- else
+ /* If the register allocator hasn't made up its mind yet on the register
+ class to use, settle on defaults to use. */
+ else if (rclass == NO_REGS)
{
- if (TARGET_DEBUG_ADDR)
- fprintf (stderr,
- "rs6000_secondary_reload_memory: mode = %s, class = %s, "
- "class is not GPR, FPR, VMX\n",
- GET_MODE_NAME (mode), reg_class_names[rclass]);
+ addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
+ & ~RELOAD_REG_AND_M16);
- return -1;
+ if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
+ addr_mask &= ~(RELOAD_REG_INDEXED
+ | RELOAD_REG_PRE_INCDEC
+ | RELOAD_REG_PRE_MODIFY);
}
+ else
+ addr_mask = 0;
+
/* If the register isn't valid in this register class, just return now. */
if ((addr_mask & RELOAD_REG_VALID) == 0)
{
if (TARGET_DEBUG_ADDR)
- fprintf (stderr,
- "rs6000_secondary_reload_memory: mode = %s, class = %s, "
- "not valid in class\n",
- GET_MODE_NAME (mode), reg_class_names[rclass]);
+ {
+ fprintf (stderr,
+ "rs6000_secondary_reload_memory: mode = %s, class = %s, "
+ "not valid in class\n",
+ GET_MODE_NAME (mode), reg_class_names[rclass]);
+ debug_rtx (addr);
+ }
return -1;
}
simple move insns are issued. At present, 32-bit integers are not allowed
in FPR/VSX registers. Single precision binary floating is not a simple
move because we need to convert to the single precision memory layout.
- The 4-byte SDmode can be moved. */
+ The 4-byte SDmode can be moved. TDmode values are disallowed since they
+ need special direct move handling, which we do not support yet. */
size = GET_MODE_SIZE (mode);
if (TARGET_DIRECT_MOVE
&& ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))
|| (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
return true;
- else if (TARGET_DIRECT_MOVE_128 && size == 16
+ else if (TARGET_DIRECT_MOVE_128 && size == 16 && mode != TDmode
&& ((to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
|| (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)))
return true;
fprintf (stderr, ", reload func = %s, extra cost = %d",
insn_data[sri->icode].name, sri->extra_cost);
+ else if (sri->extra_cost > 0)
+ fprintf (stderr, ", extra cost = %d", sri->extra_cost);
+
fputs ("\n", stderr);
debug_rtx (x);
}
machine_mode mode = GET_MODE (x);
bool is_constant = CONSTANT_P (x);
+ /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
+ reload class for it. */
+ if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
+ && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
+ return NO_REGS;
+
+ if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
+ && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
+ return NO_REGS;
+
/* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
the reloading of address expressions using PLUS into floating point
registers. */
return NO_REGS;
}
+ /* If we haven't picked a register class, and the type is a vector or
+ floating point type, prefer to use the VSX, FPR, or Altivec register
+ classes. */
+ if (rclass == NO_REGS)
+ {
+ if (TARGET_VSX && VECTOR_MEM_VSX_OR_P8_VECTOR_P (mode))
+ return VSX_REGS;
+
+ if (TARGET_ALTIVEC && VECTOR_MEM_ALTIVEC_P (mode))
+ return ALTIVEC_REGS;
+
+ if (DECIMAL_FLOAT_MODE_P (mode))
+ return TARGET_DFP ? FLOAT_REGS : NO_REGS;
+
+ if (TARGET_FPRS && TARGET_HARD_FLOAT && FLOAT_MODE_P (mode)
+ && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
+ return FLOAT_REGS;
+ }
+
if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
return GENERAL_REGS;
else if (TARGET_VSX && dest_vsx_p)
{
if (mode_supports_vsx_dform_quad (mode)
- && quad_address_p (XEXP (src, 0), mode, false))
+ && quad_address_p (XEXP (src, 0), mode, true))
return "lxv %x0,%1";
else if (TARGET_P9_VECTOR)
else if (TARGET_VSX && src_vsx_p)
{
if (mode_supports_vsx_dform_quad (mode)
- && quad_address_p (XEXP (dest, 0), mode, false))
+ && quad_address_p (XEXP (dest, 0), mode, true))
return "stxv %x1,%0";
else if (TARGET_P9_VECTOR)
/* The following variable value is the last issued insn. */
-static rtx last_scheduled_insn;
+static rtx_insn *last_scheduled_insn;
/* The following variable helps to balance issuing of load and
store instructions */
static int load_store_pendulum;
+/* The following variable helps pair divide insns during scheduling. */
+static int divide_cnt;
+/* The following variable helps pair and alternate vector and vector load
+ insns during scheduling. */
+static int vec_load_pendulum;
+
+
/* Power4 load update and store update instructions are cracked into a
load or store and an integer insn which are executed in the same cycle.
Branches have their own dispatch slot which does not count against the
some cycles later. */
/* Separate a load from a narrower, dependent store. */
- if (rs6000_sched_groups
+ if ((rs6000_sched_groups || rs6000_cpu_attr == CPU_POWER9)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
switch (attr_type)
{
case TYPE_FP:
- if (get_attr_type (dep_insn) == TYPE_FP)
+ case TYPE_FPSIMPLE:
+ if (get_attr_type (dep_insn) == TYPE_FP
+ || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
return 1;
break;
case TYPE_FPLOAD:
break;
}
}
+ /* Fall through, no cost for output dependency. */
+
case REG_DEP_ANTI:
/* Anti dependency; DEP_INSN reads a register that INSN writes some
cycles later. */
case CPU_POWER7:
return 5;
case CPU_POWER8:
- case CPU_POWER9:
return 7;
+ case CPU_POWER9:
+ return 6;
default:
return 1;
}
return is_store_insn1 (PATTERN (insn), str_mem);
}
+/* Return whether TYPE is a Power9 pairable vector instruction type. */
+
+static bool
+is_power9_pairable_vec_type (enum attr_type type)
+{
+ switch (type)
+ {
+ case TYPE_VECSIMPLE:
+ case TYPE_VECCOMPLEX:
+ case TYPE_VECDIV:
+ case TYPE_VECCMP:
+ case TYPE_VECPERM:
+ case TYPE_VECFLOAT:
+ case TYPE_VECFDIV:
+ case TYPE_VECDOUBLE:
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
/* Returns whether the dependence between INSN and NEXT is considered
costly by the given target. */
return insn;
}
+/* Do Power9 specific sched_reorder2 reordering of ready list. */
+
+static int
+power9_sched_reorder2 (rtx_insn **ready, int lastpos)
+{
+ int pos;
+ int i;
+ rtx_insn *tmp;
+ enum attr_type type;
+
+ type = get_attr_type (last_scheduled_insn);
+
+ /* Try to issue fixed point divides back-to-back in pairs so they will be
+ routed to separate execution units and execute in parallel. */
+ if (type == TYPE_DIV && divide_cnt == 0)
+ {
+ /* First divide has been scheduled. */
+ divide_cnt = 1;
+
+ /* Scan the ready list looking for another divide, if found move it
+ to the end of the list so it is chosen next. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && get_attr_type (ready[pos]) == TYPE_DIV)
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ break;
+ }
+ pos--;
+ }
+ }
+ else
+ {
+ /* Last insn was the 2nd divide or not a divide, reset the counter. */
+ divide_cnt = 0;
+
+ /* Power9 can execute 2 vector operations and 2 vector loads in a single
+ cycle. So try to pair up and alternate groups of vector and vector
+ load instructions.
+
+ To aid this formation, a counter is maintained to keep track of
+ vec/vecload insns issued. The value of vec_load_pendulum maintains
+ the current state with the following values:
+
+ 0 : Initial state, no vec/vecload group has been started.
+
+ -1 : 1 vector load has been issued and another has been found on
+ the ready list and moved to the end.
+
+ -2 : 2 vector loads have been issued and a vector operation has
+ been found and moved to the end of the ready list.
+
+ -3 : 2 vector loads and a vector insn have been issued and a
+ vector operation has been found and moved to the end of the
+ ready list.
+
+ 1 : 1 vector insn has been issued and another has been found and
+ moved to the end of the ready list.
+
+ 2 : 2 vector insns have been issued and a vector load has been
+ found and moved to the end of the ready list.
+
+ 3 : 2 vector insns and a vector load have been issued and another
+ vector load has been found and moved to the end of the ready
+ list. */
+ if (type == TYPE_VECLOAD)
+ {
+ /* Issued a vecload. */
+ if (vec_load_pendulum == 0)
+ {
+ /* We issued a single vecload, look for another and move it to
+ the end of the ready list so it will be scheduled next.
+ Set pendulum if found. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && get_attr_type (ready[pos]) == TYPE_VECLOAD)
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ vec_load_pendulum = -1;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ else if (vec_load_pendulum == -1)
+ {
+ /* This is the second vecload we've issued, search the ready
+ list for a vector operation so we can try to schedule a
+ pair of those next. If found move to the end of the ready
+ list so it is scheduled next and set the pendulum. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && is_power9_pairable_vec_type (
+ get_attr_type (ready[pos])))
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ vec_load_pendulum = -2;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ else if (vec_load_pendulum == 2)
+ {
+ /* Two vector ops have been issued and we've just issued a
+ vecload, look for another vecload and move to end of ready
+ list if found. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && get_attr_type (ready[pos]) == TYPE_VECLOAD)
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ /* Set pendulum so that next vecload will be seen as
+ finishing a group, not start of one. */
+ vec_load_pendulum = 3;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ }
+ else if (is_power9_pairable_vec_type (type))
+ {
+ /* Issued a vector operation. */
+ if (vec_load_pendulum == 0)
+ /* We issued a single vec op, look for another and move it
+ to the end of the ready list so it will be scheduled next.
+ Set pendulum if found. */
+ {
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && is_power9_pairable_vec_type (
+ get_attr_type (ready[pos])))
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ vec_load_pendulum = 1;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ else if (vec_load_pendulum == 1)
+ {
+ /* This is the second vec op we've issued, search the ready
+ list for a vecload operation so we can try to schedule a
+ pair of those next. If found move to the end of the ready
+ list so it is scheduled next and set the pendulum. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && get_attr_type (ready[pos]) == TYPE_VECLOAD)
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ vec_load_pendulum = 2;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ else if (vec_load_pendulum == -2)
+ {
+ /* Two vecload ops have been issued and we've just issued a
+ vec op, look for another vec op and move to end of ready
+ list if found. */
+ pos = lastpos;
+ while (pos >= 0)
+ {
+ if (recog_memoized (ready[pos]) >= 0
+ && is_power9_pairable_vec_type (
+ get_attr_type (ready[pos])))
+ {
+ tmp = ready[pos];
+ for (i = pos; i < lastpos; i++)
+ ready[i] = ready[i + 1];
+ ready[lastpos] = tmp;
+ /* Set pendulum so that next vec op will be seen as
+ finishing a group, not start of one. */
+ vec_load_pendulum = -3;
+ return cached_can_issue_more;
+ }
+ pos--;
+ }
+ }
+ }
+
+ /* We've either finished a vec/vecload group, couldn't find an insn to
+ continue the current group, or the last insn had nothing to do with
+ with a group. In any case, reset the pendulum. */
+ vec_load_pendulum = 0;
+ }
+
+ return cached_can_issue_more;
+}
+
/* We are about to begin issuing insns for this clock cycle. */
static int
}
}
+ /* Do Power9 dependent reordering if necessary. */
+ if (rs6000_cpu == PROCESSOR_POWER9 && last_scheduled_insn
+ && recog_memoized (last_scheduled_insn) >= 0)
+ return power9_sched_reorder2 (ready, *pn_ready - 1);
+
return cached_can_issue_more;
}
}
break;
case PROCESSOR_POWER8:
- case PROCESSOR_POWER9:
type = get_attr_type (insn);
switch (type)
}
break;
case PROCESSOR_POWER8:
- case PROCESSOR_POWER9:
type = get_attr_type (insn);
switch (type)
/* Do we have a special group ending nop? */
if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
- || rs6000_cpu_attr == CPU_POWER8 || rs6000_cpu_attr == CPU_POWER9)
+ || rs6000_cpu_attr == CPU_POWER8)
{
nop = gen_group_ending_nop ();
emit_insn_before (nop, next_insn);
int sched_verbose ATTRIBUTE_UNUSED,
int max_ready ATTRIBUTE_UNUSED)
{
- last_scheduled_insn = NULL_RTX;
+ last_scheduled_insn = NULL;
load_store_pendulum = 0;
+ divide_cnt = 0;
+ vec_load_pendulum = 0;
}
/* The following function is called at the end of scheduling BB.
}
}
-struct _rs6000_sched_context
+struct rs6000_sched_context
{
short cached_can_issue_more;
- rtx last_scheduled_insn;
+ rtx_insn *last_scheduled_insn;
int load_store_pendulum;
+ int divide_cnt;
+ int vec_load_pendulum;
};
-typedef struct _rs6000_sched_context rs6000_sched_context_def;
+typedef struct rs6000_sched_context rs6000_sched_context_def;
typedef rs6000_sched_context_def *rs6000_sched_context_t;
/* Allocate store for new scheduling context. */
if (clean_p)
{
sc->cached_can_issue_more = 0;
- sc->last_scheduled_insn = NULL_RTX;
+ sc->last_scheduled_insn = NULL;
sc->load_store_pendulum = 0;
+ sc->divide_cnt = 0;
+ sc->vec_load_pendulum = 0;
}
else
{
sc->cached_can_issue_more = cached_can_issue_more;
sc->last_scheduled_insn = last_scheduled_insn;
sc->load_store_pendulum = load_store_pendulum;
+ sc->divide_cnt = divide_cnt;
+ sc->vec_load_pendulum = vec_load_pendulum;
}
}
cached_can_issue_more = sc->cached_can_issue_more;
last_scheduled_insn = sc->last_scheduled_insn;
load_store_pendulum = sc->load_store_pendulum;
+ divide_cnt = sc->divide_cnt;
+ vec_load_pendulum = sc->vec_load_pendulum;
}
/* Free _SC. */
machine_mode inner = GET_MODE_INNER (mode);
unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
- if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ if (TARGET_FLOAT128
+ && (mode == KCmode
+ || (mode == TCmode && TARGET_IEEEQUAD)))
+ regno = ALTIVEC_ARG_RETURN;
+
+ else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
regno = FP_ARG_RETURN;
+
else
{
regno = GP_ARG_RETURN;
{ "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR, false, true },
{ "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
+ { "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "cell", RS6000_BTM_CELL, false, false },
{ "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
{ "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
+ { "power9-misc", RS6000_BTM_P9_MISC, false, false },
{ "crypto", RS6000_BTM_CRYPTO, false, false },
{ "htm", RS6000_BTM_HTM, false, false },
{ "hard-dfp", RS6000_BTM_DFP, false, false },
{ "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
{ "long-double-128", RS6000_BTM_LDBL128, false, false },
+ { "float128", RS6000_BTM_FLOAT128, false, false },
};
/* Option variables that we want to support inside attribute((target)) and
#define TARGET_P8_VECTOR 0
#endif
+/* Define the ISA 3.0 flags as 0 if the target assembler does not support
+ Power9 instructions. Allow -mpower9-fusion, since it does not add new
+ instructions. Allow -misel, since it predates ISA 3.0 and does
+ not require any Power9 features. */
+
+#ifndef HAVE_AS_POWER9
+#undef TARGET_FLOAT128_HW
+#undef TARGET_MODULO
+#undef TARGET_P9_VECTOR
+#undef TARGET_P9_MINMAX
+#undef TARGET_P9_DFORM_SCALAR
+#undef TARGET_P9_DFORM_VECTOR
+#undef TARGET_P9_MISC
+#define TARGET_FLOAT128_HW 0
+#define TARGET_MODULO 0
+#define TARGET_P9_VECTOR 0
+#define TARGET_P9_MINMAX 0
+#define TARGET_P9_DFORM_SCALAR 0
+#define TARGET_P9_DFORM_VECTOR 0
+#define TARGET_P9_MISC 0
+#endif
+
/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
not, generate the lwsync code as an integer constant. */
#ifdef HAVE_AS_LWSYNC
Similarly IFmode is the IBM long double format even if the default is IEEE
128-bit. */
#define FLOAT128_IEEE_P(MODE) \
- (((MODE) == TFmode && TARGET_IEEEQUAD) \
- || ((MODE) == KFmode))
+ ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
+ || ((MODE) == KFmode) || ((MODE) == KCmode))
#define FLOAT128_IBM_P(MODE) \
- (((MODE) == TFmode && !TARGET_IEEEQUAD) \
- || ((MODE) == IFmode))
+ ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
+ || ((MODE) == IFmode) || ((MODE) == ICmode))
/* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */
#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
+#define MASK_P9_MISC OPTION_MASK_P9_MISC
#define MASK_POPCNTB OPTION_MASK_POPCNTB
#define MASK_POPCNTD OPTION_MASK_POPCNTD
#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
: (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
-#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \
+#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
+ ? (ALTIVEC_ARG_RETURN \
+ + (TARGET_FLOAT128 ? 1 : 0)) \
: (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
/* Flags for the call/call_value rtl operations set up by function_arg */
#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.00 vector. */
+#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector. */
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_SPE MASK_STRING /* E500 */
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
+#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
| RS6000_BTM_P8_VECTOR \
| RS6000_BTM_P9_VECTOR \
+ | RS6000_BTM_P9_MISC \
+ | RS6000_BTM_MODULO \
| RS6000_BTM_CRYPTO \
| RS6000_BTM_FRE \
| RS6000_BTM_FRES \
| RS6000_BTM_CELL \
| RS6000_BTM_DFP \
| RS6000_BTM_HARD_FLOAT \
- | RS6000_BTM_LDBL128)
+ | RS6000_BTM_LDBL128 \
+ | RS6000_BTM_FLOAT128)
/* Define builtin enum index. */
RS6000_BTI_void, /* void_type_node */
RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
+ RS6000_BTI_const_str, /* pointer to const char * */
RS6000_BTI_MAX
};
#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
#define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
#define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
+#define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
brinc,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
- htm"
+ veclogical,veccmpfx,vecexts,vecmove,
+ htm,htmsimple,dfp"
(const_string "integer"))
;; What data size does this instruction work on?
-;; This is used for insert, mul.
-(define_attr "size" "8,16,32,64" (const_string "32"))
+;; This is used for insert, mul and others as necessary.
+(define_attr "size" "8,16,32,64,128" (const_string "32"))
;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
;; This is used for add, logical, shift, exts, mul.
(include "power6.md")
(include "power7.md")
(include "power8.md")
+(include "power9.md")
(include "cell.md")
(include "xfpu.md")
(include "a2.md")
if (REGNO (cr) == CR0_REGNO)
{
- emit_insn (gen_ashdi3_extswsli_dot (dest, src2, shift, cr));
+ emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
DONE;
}
"@
fabs %0,%1
xsabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "*nabs<mode>2_fpr"
"@
fnabs %0,%1
xsnabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "neg<mode>2"
"@
fneg %0,%1
xsnegdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "add<mode>3"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")])
+ [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")])
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
;; fsel instruction and some auxiliary computations. Then we just have a
(match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
"TARGET_P9_MINMAX"
"xxsel %x0,%x1,%x3,%x4"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
\f
;; Conversions to and from floating-point.
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
mt%0 %1
mf%1 %0
nop"
- [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
+ [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat"
#
#
#"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
+ (set_attr "size" "64")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
(define_insn "*mov<mode>_softfloat32"
mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+ (set_attr "size" "64")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat64"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "trunc<mode>df2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
else
return \"fneg %0,%1\;fneg %L0,%L1\";
}"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "8")])
(define_expand "abs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlxor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; IEEE 128-bit absolute value
(define_insn_and_split "ieee_128bit_vsx_abs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlandc %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; IEEE 128-bit negative absolute value
(define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; Float128 conversion functions. These expand to library function calls.
;; We use expand to convert from IBM double double to IEEE 128-bit
UNSPEC_P8V_FMRGOW))]
"!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"fmrgow %0,%1,%2"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "fpsimple")])
(define_insn "p8_mtvsrwz"
[(set (match_operand:DF 0 "register_operand" "=d")
lfd%U1%X1 %0,%1
fmr %0,%1
#"
- [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
+ [(set_attr "type" "store,load,*,fpstore,fpload,fpsimple,*")
+ (set_attr "size" "64")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
mfvsrd %0,%x1
mtvsrd %x0,%1
xxlxor %x0,%x0,%x0"
- [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
+ [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fpsimple,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,veclogical")
+ (set_attr "size" "64")
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
; Some DImode loads are best done as a load of -1 followed by a mask
lfdu %3,%2(%0)"
[(set_attr "type" "fpload")
(set_attr "update" "yes")
- (set_attr "indexed" "yes,no")])
+ (set_attr "indexed" "yes,no")
+ (set_attr "size" "64")])
(define_insn "*movdf_update2"
[(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
}
- [(set_attr "type" "fp,fp")
+ [(set_attr "type" "fpsimple,fp")
(set_attr "length" "4,8")])
(define_insn "unpack<mode>"
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsaddqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "sub<mode>3"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssubqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "mul<mode>3"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "div<mode>3"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsdivqp %0,%1,%2"
- [(set_attr "type" "vecdiv")])
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
(define_insn "sqrt<mode>2"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssqrtqp %0,%1"
- [(set_attr "type" "vecdiv")])
+ [(set_attr "type" "vecdiv")
+ (set_attr "size" "128")])
-(define_insn "copysign<mode>3"
+(define_expand "copysign<mode>3"
+ [(use (match_operand:IEEE128 0 "altivec_register_operand"))
+ (use (match_operand:IEEE128 1 "altivec_register_operand"))
+ (use (match_operand:IEEE128 2 "altivec_register_operand"))]
+ "FLOAT128_IEEE_P (<MODE>mode)"
+{
+ if (TARGET_FLOAT128_HW)
+ emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
+ operands[2]));
+ else
+ {
+ rtx tmp = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
+ operands[2], tmp));
+ }
+ DONE;
+})
+
+(define_insn "copysign<mode>3_hard"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
UNSPEC_COPYSIGN))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscpsgnqp %0,%2,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecmove")
+ (set_attr "size" "128")])
+
+(define_insn "copysign<mode>3_soft"
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
+ (unspec:IEEE128
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
+ UNSPEC_COPYSIGN))]
+ "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
+ [(set_attr "type" "veccomplex")
+ (set_attr "length" "8")])
(define_insn "neg<mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnegqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")
+ (set_attr "size" "128")])
(define_insn "abs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")
+ (set_attr "size" "128")])
(define_insn "*nabs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")
+ (set_attr "size" "128")])
;; Initially don't worry about doing fusion
(define_insn "*fma<mode>4_hw"
(match_operand:IEEE128 3 "altivec_register_operand" "0")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*fms<mode>4_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*nfma<mode>4_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*nfms<mode>4_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqp %0,%1,%2"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "extend<SFDF:mode><IEEE128:mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:SFDF 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
"xscvdpqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating
;; point is a simple copy.
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,veclogical")
(set_attr "length" "0,4")])
(define_insn_and_split "trunctfkf2"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,veclogical")
(set_attr "length" "0,4")])
(define_insn "trunc<mode>df2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqpdp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
;; There is no KFmode -> SFmode instruction. Preserve the accuracy by doing
;; the KFmode -> DFmode conversion using round to odd rather than the normal
UNSPEC_IEEE128_CONVERT))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqp<su>wz %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*xscvqp<su>dz_<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
UNSPEC_IEEE128_CONVERT))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqp<su>dz %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*xscv<su>dqp_<mode>"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
UNSPEC_IEEE128_CONVERT)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscv<su>dqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
(define_insn "*ieee128_mfvsrd_64bit"
[(set (match_operand:DI 0 "reg_or_indexed_operand" "=wr,Z,wi")
mfvsrd %0,%x1
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mftgpr,fpstore,vecsimple")])
+ [(set_attr "type" "mftgpr,fpstore,veclogical")])
(define_insn "*ieee128_mfvsrd_32bit"
"@
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpstore,vecsimple")])
+ [(set_attr "type" "fpstore,veclogical")])
(define_insn "*ieee128_mfvsrwz"
[(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")
mtvsrd %x0,%1
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mffgpr,fpload,vecsimple")])
+ [(set_attr "type" "mffgpr,fpload,veclogical")])
(define_insn "*ieee128_mtvsrd_32bit"
[(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v")
"@
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpload,vecsimple")])
+ [(set_attr "type" "fpload,veclogical")])
;; IEEE 128-bit instructions with round to odd semantics
(define_insn "*trunc<mode>df2_odd"
UNSPEC_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqpdpo %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecfloat")
+ (set_attr "size" "128")])
;; IEEE 128-bit comparisons
(define_insn "*cmp<mode>_hw"
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscmpuqp %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmp")
+ (set_attr "size" "128")])
\f
Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
Fuse certain operations together for better performance on power9.
+mpower9-misc
+Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
+Use/do not use certain scalar instructions added in ISA 3.0.
+
mpower9-vector
Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
-Use/do not use vector and scalar instructions added in ISA 3.0.
+Use/do not use vector instructions added in ISA 3.0.
mpower9-dform-scalar
Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
"mciu_rs64,fpu_rs64,bpu_rs64")
(define_insn_reservation "rs64a-fp" 4
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64")
$(srcdir)/config/rs6000/power6.md \
$(srcdir)/config/rs6000/power7.md \
$(srcdir)/config/rs6000/power8.md \
+ $(srcdir)/config/rs6000/power9.md \
$(srcdir)/config/rs6000/cell.md \
$(srcdir)/config/rs6000/xfpu.md \
$(srcdir)/config/rs6000/a2.md \
;; Make sure the "titan_fp" rule stays last, as it's a catch all for
;; double-precision and unclassified (e.g. fsel) FP-instructions
(define_insn_reservation "titan_fp" 10
- (and (eq_attr "type" "fpcompare,fp,dmul")
+ (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
}
}
[(set_attr "length" "0,4")
- (set_attr "type" "vecsimple")])
+ (set_attr "type" "veclogical")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*vsx_xxsel<mode>_uns"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
return "xxlor %x0,%x1,%x1";
}
- [(set_attr "type" "fp,vecsimple,mftgpr,mftgpr")
+ [(set_attr "type" "fpsimple,veclogical,mftgpr,mftgpr")
(set_attr "length" "4")])
(define_insn "*vsx_extract_<mode>_internal2"
operands[3] = GEN_INT (fldDM);
return "xxpermdi %x0,%x1,%x1,%3";
}
- [(set_attr "type" "fp,vecsimple,vecperm")
+ [(set_attr "type" "fpsimple,veclogical,vecperm")
(set_attr "length" "4")])
;; Optimize extracting a single scalar element from memory if the scalar is in
[(set (match_dup 0)
(unspec:V4SF [(match_dup 1)] UNSPEC_VSX_CVDPSPN))
(set (match_dup 0)
- (vec_duplicate:V4SF
- (vec_select:SF (match_dup 0)
- (parallel [(const_int 0)]))))]
+ (unspec:V4SF [(match_dup 0)
+ (const_int 0)] UNSPEC_VSX_XXSPLTW))]
""
[(set_attr "type" "vecload,vecperm,mftgpr")
(set_attr "length" "4,8,4")])
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsb2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
(define_insn "*vsx_sign_extend_hi_<mode>"
[(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v")
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsh2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
(define_insn "*vsx_sign_extend_si_v2di"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsw2d %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
(define_insn_reservation "fp-default" 2
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_default"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2")
(define_insn_reservation "fp-addsub-s" 14
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-addsub-d" 18
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
+2016-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-06-17 Jakub Jelinek <jakub@redhat.com>
+
+ * semantics.c (handle_omp_array_sections_1): Don't ICE when
+ processing_template_decl when checking for bitfields and unions.
+ Look through REFERENCE_REF_P as base of COMPONENT_REF.
+ (finish_omp_clauses): Look through REFERENCE_REF_P even for
+ array sections with COMPONENT_REF bases.
+
+ 2016-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ * parser.c (cp_parser_omp_var_list_no_open): Call
+ convert_from_reference before cp_parser_postfix_dot_deref_expression.
+ * semantics.c (finish_omp_clauses): Don't ICE when
+ processing_template_decl when checking for bitfields and unions.
+ Look through REFERENCE_REF_P as base of COMPONENT_REF.
+
+ 2016-06-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/71528
+ * decl.c (duplicate_decls): For DECL_INITIALIZED_P non-external
+ olddecl vars, preserve their TREE_READONLY bit.
+
2016-06-14 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/70572
if (VAR_P (newdecl))
{
DECL_THIS_EXTERN (newdecl) |= DECL_THIS_EXTERN (olddecl);
+ /* For already initialized vars, TREE_READONLY could have been
+ cleared in cp_finish_decl, because the var needs runtime
+ initialization or destruction. Make sure not to set
+ TREE_READONLY on it again. */
+ if (DECL_INITIALIZED_P (olddecl)
+ && !DECL_EXTERNAL (olddecl)
+ && !TREE_READONLY (olddecl))
+ TREE_READONLY (newdecl) = 0;
DECL_INITIALIZED_P (newdecl) |= DECL_INITIALIZED_P (olddecl);
DECL_NONTRIVIALLY_INITIALIZED_P (newdecl)
|= DECL_NONTRIVIALLY_INITIALIZED_P (olddecl);
= cp_lexer_peek_token (parser->lexer)->location;
cp_id_kind idk = CP_ID_KIND_NONE;
cp_lexer_consume_token (parser->lexer);
+ decl = convert_from_reference (decl);
decl
= cp_parser_postfix_dot_deref_expression (parser, CPP_DOT,
decl, false,
|| OMP_CLAUSE_CODE (c) == OMP_CLAUSE_FROM)
&& !type_dependent_expression_p (t))
{
- if (DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
+ if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL
+ && DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
{
error_at (OMP_CLAUSE_LOCATION (c),
"bit-field %qE in %qs clause",
}
while (TREE_CODE (t) == COMPONENT_REF)
{
- if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE)
+ if (TREE_TYPE (TREE_OPERAND (t, 0))
+ && TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE)
{
error_at (OMP_CLAUSE_LOCATION (c),
"%qE is a member of a union", t);
}
t = TREE_OPERAND (t, 0);
}
+ if (REFERENCE_REF_P (t))
+ t = TREE_OPERAND (t, 0);
}
if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL)
{
{
while (TREE_CODE (t) == COMPONENT_REF)
t = TREE_OPERAND (t, 0);
+ if (REFERENCE_REF_P (t))
+ t = TREE_OPERAND (t, 0);
if (bitmap_bit_p (&map_field_head, DECL_UID (t)))
break;
if (bitmap_bit_p (&map_head, DECL_UID (t)))
{
if (type_dependent_expression_p (t))
break;
- if (DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
+ if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL
+ && DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
{
error_at (OMP_CLAUSE_LOCATION (c),
"bit-field %qE in %qs clause",
}
while (TREE_CODE (t) == COMPONENT_REF)
{
- if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0)))
- == UNION_TYPE)
+ if (TREE_TYPE (TREE_OPERAND (t, 0))
+ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0)))
+ == UNION_TYPE))
{
error_at (OMP_CLAUSE_LOCATION (c),
"%qE is a member of a union", t);
}
if (remove)
break;
+ if (REFERENCE_REF_P (t))
+ t = TREE_OPERAND (t, 0);
if (VAR_P (t) || TREE_CODE (t) == PARM_DECL)
{
if (bitmap_bit_p (&map_field_head, DECL_UID (t)))
FOR_BB_INSNS_REVERSE (bb, insn)
{
+ if (!INSN_P (insn))
+ continue;
+
df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
df_mw_hardreg *mw;
int debug_insn;
- if (!INSN_P (insn))
- continue;
-
debug_insn = DEBUG_INSN_P (insn);
bitmap_clear (do_not_gen);
would use the following syntax to declare @code{_Complex128} to be a
complex @code{__float128} type:
+On the PowerPC Linux VSX targets, you can declare complex types using
+the corresponding internal complex type, @code{KCmode} for
+@code{__float128} type and @code{ICmode} for @code{__ibm128} type:
+
@smallexample
-typedef _Complex float __attribute__((mode(KC))) _Complex128;
+typedef _Complex float __attribute__((mode(KC))) _Complex_float128;
+typedef _Complex float __attribute__((mode(IC))) _Complex_ibm128;
@end smallexample
Not all targets support additional floating-point types.
returns the Time Base Register value as an unsigned long, throwing away
the most significant word on 32-bit environments.
+Additional built-in functions are available for the 64-bit PowerPC
+family of processors, for efficient use of 128-bit floating point
+(@code{__float128}) values.
+
+The following floating-point built-in functions are available with
+@code{-mfloat128} and Altivec support. All of them implement the
+function that is part of the name.
+
+@smallexample
+__float128 __builtin_fabsq (__float128)
+__float128 __builtin_copysignq (__float128, __float128)
+@end smallexample
+
+The following built-in functions are available with @code{-mfloat128}
+and Altivec support.
+
+@table @code
+@item __float128 __builtin_infq (void)
+Similar to @code{__builtin_inf}, except the return type is @code{__float128}.
+@findex __builtin_infq
+
+@item __float128 __builtin_huge_valq (void)
+Similar to @code{__builtin_huge_val}, except the return type is @code{__float128}.
+@findex __builtin_huge_valq
+
+@item __float128 __builtin_nanq (void)
+Similar to @code{__builtin_nan}, except the return type is @code{__float128}.
+@findex __builtin_nanq
+
+@item __float128 __builtin_nansq (void)
+Similar to @code{__builtin_nans}, except the return type is @code{__float128}.
+@findex __builtin_nansq
+@end table
+
The following built-in functions are available for the PowerPC family
of processors, starting with ISA 2.06 or later (@option{-mcpu=power7}
or @option{-mpopcntd}):
64-bit environment support ISA 2.06 or later.
The following built-in functions are available for the PowerPC family
-of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}
-or @option{-mmodulo}):
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
@smallexample
long long __builtin_darn (void);
long long __builtin_darn_raw (void);
int __builtin_darn_32 (void);
+
+int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal128 value);
+int __builtin_dfp_dtstsfi_lt_dd (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_lt_td (unsigned int comparison, _Decimal128 value);
+
+int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal128 value);
+int __builtin_dfp_dtstsfi_gt_dd (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_gt_td (unsigned int comparison, _Decimal128 value);
+
+int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal128 value);
+int __builtin_dfp_dtstsfi_eq_dd (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_eq_td (unsigned int comparison, _Decimal128 value);
+
+int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal128 value);
+int __builtin_dfp_dtstsfi_ov_dd (unsigned int comparison, _Decimal64 value);
+int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value);
@end smallexample
The @code{__builtin_darn} and @code{__builtin_darn_raw}
64-bit raw random number. The @code{__builtin_darn_32} function
provides a 32-bit random number.
+The @code{__builtin_dfp_dtstsfi_lt} function returns a non-zero value
+if and only if the number of signficant digits of its @code{value} argument
+is less than its @code{comparison} argument. The
+@code{__builtin_dfp_dtstsfi_lt_dd} and
+@code{__builtin_dfp_dtstsfi_lt_td} functions behave similarly, but
+require that the type of the @code{value} argument be
+@code{__Decimal64} and @code{__Decimal128} respectively.
+
+The @code{__builtin_dfp_dtstsfi_gt} function returns a non-zero value
+if and only if the number of signficant digits of its @code{value} argument
+is greater than its @code{comparison} argument. The
+@code{__builtin_dfp_dtstsfi_gt_dd} and
+@code{__builtin_dfp_dtstsfi_gt_td} functions behave similarly, but
+require that the type of the @code{value} argument be
+@code{__Decimal64} and @code{__Decimal128} respectively.
+
+The @code{__builtin_dfp_dtstsfi_eq} function returns a non-zero value
+if and only if the number of signficant digits of its @code{value} argument
+equals its @code{comparison} argument. The
+@code{__builtin_dfp_dtstsfi_eq_dd} and
+@code{__builtin_dfp_dtstsfi_eq_td} functions behave similarly, but
+require that the type of the @code{value} argument be
+@code{__Decimal64} and @code{__Decimal128} respectively.
+
+The @code{__builtin_dfp_dtstsfi_ov} function returns a non-zero value
+if and only if its @code{value} argument has an undefined number of
+significant digits, such as when @code{value} is an encoding of @code{NaN}.
+The @code{__builtin_dfp_dtstsfi_ov_dd} and
+@code{__builtin_dfp_dtstsfi_ov_td} functions behave similarly, but
+require that the type of the @code{value} argument be
+@code{__Decimal64} and @code{__Decimal128} respectively.
+
The following built-in functions are available for the PowerPC family
of processors when hardware decimal floating point
(@option{-mhard-dfp}) is available:
vector __uint128_t vec_vprtybd (vector __uint128_t);
@end smallexample
+The following built-in vector functions are available for the PowerPC family
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
+or with @option{-mpower9-vector}:
+
+@smallexample
+__vector unsigned char
+vec_absd (__vector unsigned char arg1, __vector unsigned char arg2);
+__vector unsigned short
+vec_absd (__vector unsigned short arg1, __vector unsigned short arg2);
+__vector unsigned int
+vec_absd (__vector unsigned int arg1, __vector unsigned int arg2);
+
+__vector unsigned char
+vec_absdb (__vector unsigned char arg1, __vector unsigned char arg2);
+__vector unsigned short
+vec_absdh (__vector unsigned short arg1, __vector unsigned short arg2);
+__vector unsigned int
+vec_absdw (__vector unsigned int arg1, __vector unsigned int arg2);
+
+__vector unsigned char
+vec_slv (__vector unsigned char src, __vector unsigned char shift_distance);
+__vector unsigned char
+vec_srv (__vector unsigned char src, __vector unsigned char shift_distance);
+@end smallexample
+
+The @code{vec_absd}, @code{vec_absdb}, @code{vec_absdh}, and
+@code{vec_absdw} built-in functions each computes the absolute
+differences of the pairs of vector elements supplied in its two vector
+arguments, placing the absolute differences into the corresponding
+elements of the vector result.
+
+The @code{vec_slv} and @code{vec_srv} functions operate on
+all of the bytes of their @code{src} and @code{shift_distance}
+arguments in parallel. The behavior of the @code{vec_slv} is as if
+there existed a temporary array of 17 unsigned characters
+@code{slv_array} within which elements 0 through 15 are the same as
+the entries in the @code{src} array and element 16 equals 0. The
+result returned from the @code{vec_slv} function is a
+@code{__vector} of 16 unsigned characters within which element
+@code{i} is computed using the C expression
+@code{0xff & (*((unsigned short *)(slv_array + i)) << (0x07 &
+shift_distance[i]))},
+with this resulting value coerced to the @code{unsigned char} type.
+The behavior of the @code{vec_srv} is as if
+there existed a temporary array of 17 unsigned characters
+@code{srv_array} within which element 0 equals zero and
+elements 1 through 16 equal the elements 0 through 15 of
+the @code{src} array. The
+result returned from the @code{vec_srv} function is a
+@code{__vector} of 16 unsigned characters within which element
+@code{i} is computed using the C expression
+@code{0xff & (*((unsigned short *)(srv_array + i)) >>
+(0x07 & shift_distance[i]))},
+with this resulting value coerced to the @code{unsigned char} type.
+
If the cryptographic instructions are enabled (@option{-mcrypto} or
@option{-mcpu=power8}), the following builtins are enabled.
The VSX instruction set (@option{-mvsx}, @option{-mcpu=power7}, or
@option{-mcpu=power8}) must be enabled to use the @option{-mfloat128}
-option. The @code{-mfloat128} option only works on PowerPC 64-bit
+option. The @option{-mfloat128} option only works on PowerPC 64-bit
Linux systems.
+If you use the ISA 3.0 instruction set (@option{-mcpu=power9}), the
+@option{-mfloat128} option will also enable the generation of ISA 3.0
+IEEE 128-bit floating point instructions. Otherwise, IEEE 128-bit
+floating point will be done with software emulation.
+
@item -mfloat128-hardware
@itemx -mno-float128-hardware
@opindex mfloat128-hardware
Enable/disable using ISA 3.0 hardware instructions to support the
@var{__float128} data type.
+If you use @option{-mfloat128-hardware}, it will enable the option
+@option{-mfloat128} as well.
+
+If you select ISA 3.0 instructions with @option{-mcpu=power9}, but do
+not use either @option{-mfloat128} or @option{-mfloat128-hardware},
+the IEEE 128-bit floating point support will not be enabled.
+
@item -mmodulo
@itemx -mno-modulo
@opindex mmodulo
case REAL_TYPE:
case FIXED_POINT_TYPE:
- case COMPLEX_TYPE:
case VECTOR_TYPE:
case VOID_TYPE:
return TREE_CODE (type) == TREE_CODE (orig);
case VIEW_CONVERT_EXPR:
if (TREE_CODE (op0) == MEM_REF)
{
+ if (TYPE_ALIGN (TREE_TYPE (op0)) != TYPE_ALIGN (type))
+ type = build_aligned_type (type, TYPE_ALIGN (TREE_TYPE (op0)));
tem = fold_build2_loc (loc, MEM_REF, type,
TREE_OPERAND (op0, 0), TREE_OPERAND (op0, 1));
REF_REVERSE_STORAGE_ORDER (tem) = REF_REVERSE_STORAGE_ORDER (op0);
|| TREE_CODE (arg0) == BIT_IOR_EXPR
|| TREE_CODE (arg0) == BIT_XOR_EXPR)
&& TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST)
- return fold_build2_loc (loc, TREE_CODE (arg0), type,
- fold_build2_loc (loc, code, type,
- TREE_OPERAND (arg0, 0), arg1),
- fold_build2_loc (loc, code, type,
- TREE_OPERAND (arg0, 1), arg1));
+ {
+ tree arg00 = fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));
+ tree arg01 = fold_convert_loc (loc, type, TREE_OPERAND (arg0, 1));
+ return fold_build2_loc (loc, TREE_CODE (arg0), type,
+ fold_build2_loc (loc, code, type,
+ arg00, arg1),
+ fold_build2_loc (loc, code, type,
+ arg01, arg1));
+ }
/* Two consecutive rotates adding up to the some integer
multiple of the precision of the type can be ignored. */
&& TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST
&& wi::umod_trunc (wi::add (arg1, TREE_OPERAND (arg0, 1)),
prec) == 0)
- return TREE_OPERAND (arg0, 0);
+ return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));
return NULL_TREE;
+2016-07-09 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk:
+ PR fortran/71783
+ * frontend-passes.c (create_var): Always allocate a charlen
+ for character variables.
+
+2016-07-08 Cesar Philippidis <cesar@codesourcery.com>
+
+ Backport from trunk:
+ 2016-07-08 Cesar Philippidis <cesar@codesourcery.com>
+
+ * parse.c (matcha): Define.
+ (decode_oacc_directive): Add spec_only local var and set it. Use
+ matcha to parse acc directives except for routine and declare. Return
+ ST_GET_FCN_CHARACTERISTICS if a non-declarative directive could be
+ matched.
+
+2016-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-07-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/71687
+ * f95-lang.c (struct binding_level): Add reversed field.
+ (clear_binding_level): Adjust initializer.
+ (getdecls): If reversed is clear, set it and nreverse the names
+ chain before returning it.
+ (poplevel): Use getdecls.
+ * trans-decl.c (gfc_generate_function_code, gfc_process_block_locals):
+ Use nreverse to pushdecl decls in the declaration order.
+
+ PR fortran/71717
+ * trans-openmp.c (gfc_omp_privatize_by_reference): Return false
+ for GFC_DECL_ASSOCIATE_VAR_P with POINTER_TYPE.
+
+ 2016-06-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/71704
+ * parse.c (matchs, matcho): Move right before decode_omp_directive.
+ If spec_only, only gfc_match the keyword and if successful, goto
+ do_spec_only.
+ (matchds, matchdo): Define.
+ (decode_omp_directive): Add spec_only local var and set it.
+ Use matchds or matchdo macros instead of matchs or matcho
+ for declare target, declare simd, declare reduction and threadprivate
+ directives. Return ST_GET_FCN_CHARACTERISTICS if a non-declarative
+ directive could be matched.
+ (next_statement): For ST_GET_FCN_CHARACTERISTICS restore
+ gfc_current_locus from old_locus even if there is no label.
+
+ PR fortran/71705
+ * trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on
+ decls in to/from clauses.
+
+2016-06-29 Cesar Philippidis <cesar@codesourcery.com>
+
+ Back port from trunk
+ 2016-06-29 Cesar Philippidis <cesar@codesourcery.com>
+
+ * openmp.c (match_oacc_clause_gang): Rename to ...
+ (match_oacc_clause_gwv): this. Add support for OpenACC worker and
+ vector clauses.
+ (gfc_match_omp_clauses): Use match_oacc_clause_gwv for
+ OMP_CLAUSE_{GANG,WORKER,VECTOR}. Propagate any MATCH_ERRORs for
+ invalid OMP_CLAUSE_{ASYNC,WAIT,GANG,WORKER,VECTOR} clauses.
+ (gfc_match_oacc_wait): Propagate MATCH_ERROR for invalid
+ oacc_expr_lists. Adjust the first and needs_space arguments to
+ gfc_match_omp_clauses.
+
+2016-06-27 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/70673
+ * frontend-passes.c (realloc_string_callback): Add a call to
+ gfc_dep_compare_expr.
+
2016-06-12 Dominique d'Humieres <dominiq@lps.ens.fr>
PR fortran/60751
tree blocks;
/* The binding level containing this one (the enclosing binding level). */
struct binding_level *level_chain;
+ /* True if nreverse has been already called on names; if false, names
+ are ordered from newest declaration to oldest one. */
+ bool reversed;
};
/* The binding level currently in effect. */
static GTY(()) struct binding_level *global_binding_level;
/* Binding level structures are initialized by copying this one. */
-static struct binding_level clear_binding_level = { NULL, NULL, NULL };
+static struct binding_level clear_binding_level = { NULL, NULL, NULL, false };
/* Return true if we are in the global binding level. */
tree
getdecls (void)
{
+ if (!current_binding_level->reversed)
+ {
+ current_binding_level->reversed = true;
+ current_binding_level->names = nreverse (current_binding_level->names);
+ }
return current_binding_level->names;
}
binding level that we are about to exit and which is returned by this
routine. */
tree block_node = NULL_TREE;
- tree decl_chain = current_binding_level->names;
+ tree decl_chain = getdecls ();
tree subblock_chain = current_binding_level->blocks;
tree subblock_node;
if (!gfc_check_dependency (expr1, expr2, true))
return 0;
+ /* gfc_check_dependency doesn't always pick up identical expressions.
+ However, eliminating the above sends the compiler into an infinite
+ loop on valid expressions. Without this check, the gimplifier emits
+ an ICE for a = a, where a is deferred character length. */
+ if (!gfc_dep_compare_expr (expr1, expr2))
+ return 0;
+
current_code = c;
inserted_block = NULL;
changed_statement = NULL;
{
gfc_expr *length;
+ symbol->ts.u.cl = gfc_new_charlen (ns, NULL);
length = constant_string_length (e);
if (length)
- {
- symbol->ts.u.cl = gfc_new_charlen (ns, NULL);
- symbol->ts.u.cl->length = length;
- }
+ symbol->ts.u.cl->length = length;
else
symbol->attr.allocatable = 1;
}
}
static match
-match_oacc_clause_gang (gfc_omp_clauses *cp)
+match_oacc_clause_gwv (gfc_omp_clauses *cp, unsigned gwv)
{
match ret = MATCH_YES;
if (gfc_match (" ( ") != MATCH_YES)
return MATCH_NO;
- /* The gang clause accepts two optional arguments, num and static.
- The num argument may either be explicit (num: <val>) or
- implicit without (<val> without num:). */
-
- while (ret == MATCH_YES)
+ if (gwv == GOMP_DIM_GANG)
{
- if (gfc_match (" static :") == MATCH_YES)
+ /* The gang clause accepts two optional arguments, num and static.
+ The num argument may either be explicit (num: <val>) or
+ implicit without (<val> without num:). */
+
+ while (ret == MATCH_YES)
{
- if (cp->gang_static)
- return MATCH_ERROR;
+ if (gfc_match (" static :") == MATCH_YES)
+ {
+ if (cp->gang_static)
+ return MATCH_ERROR;
+ else
+ cp->gang_static = true;
+ if (gfc_match_char ('*') == MATCH_YES)
+ cp->gang_static_expr = NULL;
+ else if (gfc_match (" %e ", &cp->gang_static_expr) != MATCH_YES)
+ return MATCH_ERROR;
+ }
else
- cp->gang_static = true;
- if (gfc_match_char ('*') == MATCH_YES)
- cp->gang_static_expr = NULL;
- else if (gfc_match (" %e ", &cp->gang_static_expr) != MATCH_YES)
- return MATCH_ERROR;
- }
- else
- {
- /* This is optional. */
- if (cp->gang_num_expr || gfc_match (" num :") == MATCH_ERROR)
- return MATCH_ERROR;
- else if (gfc_match (" %e ", &cp->gang_num_expr) != MATCH_YES)
- return MATCH_ERROR;
+ {
+ if (cp->gang_num_expr)
+ return MATCH_ERROR;
+
+ /* The 'num' argument is optional. */
+ gfc_match (" num :");
+
+ if (gfc_match (" %e ", &cp->gang_num_expr) != MATCH_YES)
+ return MATCH_ERROR;
+ }
+
+ ret = gfc_match (" , ");
}
+ }
+ else if (gwv == GOMP_DIM_WORKER)
+ {
+ /* The 'num' argument is optional. */
+ gfc_match (" num :");
- ret = gfc_match (" , ");
+ if (gfc_match (" %e ", &cp->worker_expr) != MATCH_YES)
+ return MATCH_ERROR;
}
+ else if (gwv == GOMP_DIM_VECTOR)
+ {
+ /* The 'length' argument is optional. */
+ gfc_match (" length :");
- return gfc_match (" ) ");
+ if (gfc_match (" %e ", &cp->vector_expr) != MATCH_YES)
+ return MATCH_ERROR;
+ }
+ else
+ gfc_fatal_error ("Unexpected OpenACC parallelism.");
+
+ return gfc_match (" )");
}
static match
needs_space = false;
first = false;
gfc_gobble_whitespace ();
+ old_loc = gfc_current_locus;
if ((mask & OMP_CLAUSE_ASYNC) && !c->async)
if (gfc_match ("async") == MATCH_YES)
{
c->async = true;
- needs_space = false;
- if (gfc_match (" ( %e )", &c->async_expr) != MATCH_YES)
+ match m = gfc_match (" ( %e )", &c->async_expr);
+ if (m == MATCH_ERROR)
+ {
+ gfc_current_locus = old_loc;
+ break;
+ }
+ else if (m == MATCH_NO)
{
- c->async_expr = gfc_get_constant_expr (BT_INTEGER,
- gfc_default_integer_kind,
- &gfc_current_locus);
+ c->async_expr
+ = gfc_get_constant_expr (BT_INTEGER,
+ gfc_default_integer_kind,
+ &gfc_current_locus);
mpz_set_si (c->async_expr->value.integer, GOMP_ASYNC_NOVAL);
+ needs_space = true;
}
continue;
}
if (gfc_match ("gang") == MATCH_YES)
{
c->gang = true;
- if (match_oacc_clause_gang(c) == MATCH_YES)
- needs_space = false;
- else
+ match m = match_oacc_clause_gwv (c, GOMP_DIM_GANG);
+ if (m == MATCH_ERROR)
+ {
+ gfc_current_locus = old_loc;
+ break;
+ }
+ else if (m == MATCH_NO)
needs_space = true;
continue;
}
if (gfc_match ("worker") == MATCH_YES)
{
c->worker = true;
- if (gfc_match (" ( num : %e )", &c->worker_expr) == MATCH_YES
- || gfc_match (" ( %e )", &c->worker_expr) == MATCH_YES)
- needs_space = false;
- else
+ match m = match_oacc_clause_gwv (c, GOMP_DIM_WORKER);
+ if (m == MATCH_ERROR)
+ {
+ gfc_current_locus = old_loc;
+ break;
+ }
+ else if (m == MATCH_NO)
needs_space = true;
continue;
}
if (gfc_match ("vector") == MATCH_YES)
{
c->vector = true;
- if (gfc_match (" ( length : %e )", &c->vector_expr) == MATCH_YES
- || gfc_match (" ( %e )", &c->vector_expr) == MATCH_YES)
- needs_space = false;
- else
+ match m = match_oacc_clause_gwv (c, GOMP_DIM_VECTOR);
+ if (m == MATCH_ERROR)
+ {
+ gfc_current_locus = old_loc;
+ break;
+ }
+ if (m == MATCH_NO)
needs_space = true;
continue;
}
&& gfc_match ("wait") == MATCH_YES)
{
c->wait = true;
- match_oacc_expr_list (" (", &c->wait_list, false);
+ match m = match_oacc_expr_list (" (", &c->wait_list, false);
+ if (m == MATCH_ERROR)
+ {
+ gfc_current_locus = old_loc;
+ break;
+ }
+ else if (m == MATCH_NO)
+ needs_space = true;
continue;
}
- old_loc = gfc_current_locus;
if ((mask & OMP_CLAUSE_REDUCTION)
&& gfc_match ("reduction ( ") == MATCH_YES)
{
{
gfc_omp_clauses *c = gfc_get_omp_clauses ();
gfc_expr_list *wait_list = NULL, *el;
+ bool space = true;
+ match m;
- match_oacc_expr_list (" (", &wait_list, true);
- gfc_match_omp_clauses (&c, OACC_WAIT_CLAUSES, false, false, true);
+ m = match_oacc_expr_list (" (", &wait_list, true);
+ if (m == MATCH_ERROR)
+ return m;
+ else if (m == MATCH_YES)
+ space = false;
- if (gfc_match_omp_eos () != MATCH_YES)
- {
- gfc_error ("Unexpected junk in !$ACC WAIT at %C");
- return MATCH_ERROR;
- }
+ if (gfc_match_omp_clauses (&c, OACC_WAIT_CLAUSES, space, space, true)
+ == MATCH_ERROR)
+ return MATCH_ERROR;
if (wait_list)
for (el = wait_list; el; el = el->next)
return ST_NONE;
}
-/* Like match, but set a flag simd_matched if keyword matched. */
-#define matchs(keyword, subr, st) \
+/* Like match and if spec_only, goto do_spec_only without actually
+ matching. */
+#define matcha(keyword, subr, st) \
do { \
- if (match_word_omp_simd (keyword, subr, &old_locus, \
- &simd_matched) == MATCH_YES) \
- return st; \
- else \
- undo_new_statement (); \
- } while (0);
-
-/* Like match, but don't match anything if not -fopenmp. */
-#define matcho(keyword, subr, st) \
- do { \
- if (!flag_openmp) \
- ; \
+ if (spec_only && gfc_match (keyword) == MATCH_YES) \
+ goto do_spec_only; \
else if (match_word (keyword, subr, &old_locus) \
== MATCH_YES) \
return st; \
{
locus old_locus;
char c;
+ bool spec_only = false;
gfc_enforce_clean_symbol_state ();
return ST_NONE;
}
+ if (gfc_current_state () == COMP_FUNCTION
+ && gfc_current_block ()->result->ts.kind == -1)
+ spec_only = true;
+
gfc_unset_implicit_pure (NULL);
old_locus = gfc_current_locus;
switch (c)
{
case 'a':
- match ("atomic", gfc_match_oacc_atomic, ST_OACC_ATOMIC);
+ matcha ("atomic", gfc_match_oacc_atomic, ST_OACC_ATOMIC);
break;
case 'c':
- match ("cache", gfc_match_oacc_cache, ST_OACC_CACHE);
+ matcha ("cache", gfc_match_oacc_cache, ST_OACC_CACHE);
break;
case 'd':
- match ("data", gfc_match_oacc_data, ST_OACC_DATA);
+ matcha ("data", gfc_match_oacc_data, ST_OACC_DATA);
match ("declare", gfc_match_oacc_declare, ST_OACC_DECLARE);
break;
case 'e':
- match ("end atomic", gfc_match_omp_eos, ST_OACC_END_ATOMIC);
- match ("end data", gfc_match_omp_eos, ST_OACC_END_DATA);
- match ("end host_data", gfc_match_omp_eos, ST_OACC_END_HOST_DATA);
- match ("end kernels loop", gfc_match_omp_eos, ST_OACC_END_KERNELS_LOOP);
- match ("end kernels", gfc_match_omp_eos, ST_OACC_END_KERNELS);
- match ("end loop", gfc_match_omp_eos, ST_OACC_END_LOOP);
- match ("end parallel loop", gfc_match_omp_eos, ST_OACC_END_PARALLEL_LOOP);
- match ("end parallel", gfc_match_omp_eos, ST_OACC_END_PARALLEL);
- match ("enter data", gfc_match_oacc_enter_data, ST_OACC_ENTER_DATA);
- match ("exit data", gfc_match_oacc_exit_data, ST_OACC_EXIT_DATA);
+ matcha ("end atomic", gfc_match_omp_eos, ST_OACC_END_ATOMIC);
+ matcha ("end data", gfc_match_omp_eos, ST_OACC_END_DATA);
+ matcha ("end host_data", gfc_match_omp_eos, ST_OACC_END_HOST_DATA);
+ matcha ("end kernels loop", gfc_match_omp_eos, ST_OACC_END_KERNELS_LOOP);
+ matcha ("end kernels", gfc_match_omp_eos, ST_OACC_END_KERNELS);
+ matcha ("end loop", gfc_match_omp_eos, ST_OACC_END_LOOP);
+ matcha ("end parallel loop", gfc_match_omp_eos,
+ ST_OACC_END_PARALLEL_LOOP);
+ matcha ("end parallel", gfc_match_omp_eos, ST_OACC_END_PARALLEL);
+ matcha ("enter data", gfc_match_oacc_enter_data, ST_OACC_ENTER_DATA);
+ matcha ("exit data", gfc_match_oacc_exit_data, ST_OACC_EXIT_DATA);
break;
case 'h':
- match ("host_data", gfc_match_oacc_host_data, ST_OACC_HOST_DATA);
+ matcha ("host_data", gfc_match_oacc_host_data, ST_OACC_HOST_DATA);
break;
case 'p':
- match ("parallel loop", gfc_match_oacc_parallel_loop, ST_OACC_PARALLEL_LOOP);
- match ("parallel", gfc_match_oacc_parallel, ST_OACC_PARALLEL);
+ matcha ("parallel loop", gfc_match_oacc_parallel_loop,
+ ST_OACC_PARALLEL_LOOP);
+ matcha ("parallel", gfc_match_oacc_parallel, ST_OACC_PARALLEL);
break;
case 'k':
- match ("kernels loop", gfc_match_oacc_kernels_loop, ST_OACC_KERNELS_LOOP);
- match ("kernels", gfc_match_oacc_kernels, ST_OACC_KERNELS);
+ matcha ("kernels loop", gfc_match_oacc_kernels_loop,
+ ST_OACC_KERNELS_LOOP);
+ matcha ("kernels", gfc_match_oacc_kernels, ST_OACC_KERNELS);
break;
case 'l':
- match ("loop", gfc_match_oacc_loop, ST_OACC_LOOP);
+ matcha ("loop", gfc_match_oacc_loop, ST_OACC_LOOP);
break;
case 'r':
match ("routine", gfc_match_oacc_routine, ST_OACC_ROUTINE);
break;
case 'u':
- match ("update", gfc_match_oacc_update, ST_OACC_UPDATE);
+ matcha ("update", gfc_match_oacc_update, ST_OACC_UPDATE);
break;
case 'w':
- match ("wait", gfc_match_oacc_wait, ST_OACC_WAIT);
+ matcha ("wait", gfc_match_oacc_wait, ST_OACC_WAIT);
break;
}
gfc_error_recovery ();
return ST_NONE;
+
+ do_spec_only:
+ reject_statement ();
+ gfc_clear_error ();
+ gfc_buffer_error (false);
+ gfc_current_locus = old_locus;
+ return ST_GET_FCN_CHARACTERISTICS;
}
+/* Like match, but set a flag simd_matched if keyword matched
+ and if spec_only, goto do_spec_only without actually matching. */
+#define matchs(keyword, subr, st) \
+ do { \
+ if (spec_only && gfc_match (keyword) == MATCH_YES) \
+ goto do_spec_only; \
+ if (match_word_omp_simd (keyword, subr, &old_locus, \
+ &simd_matched) == MATCH_YES) \
+ return st; \
+ else \
+ undo_new_statement (); \
+ } while (0);
+
+/* Like match, but don't match anything if not -fopenmp
+ and if spec_only, goto do_spec_only without actually matching. */
+#define matcho(keyword, subr, st) \
+ do { \
+ if (!flag_openmp) \
+ ; \
+ else if (spec_only && gfc_match (keyword) == MATCH_YES) \
+ goto do_spec_only; \
+ else if (match_word (keyword, subr, &old_locus) \
+ == MATCH_YES) \
+ return st; \
+ else \
+ undo_new_statement (); \
+ } while (0);
+
+/* Like match, but set a flag simd_matched if keyword matched. */
+#define matchds(keyword, subr, st) \
+ do { \
+ if (match_word_omp_simd (keyword, subr, &old_locus, \
+ &simd_matched) == MATCH_YES) \
+ return st; \
+ else \
+ undo_new_statement (); \
+ } while (0);
+
+/* Like match, but don't match anything if not -fopenmp. */
+#define matchdo(keyword, subr, st) \
+ do { \
+ if (!flag_openmp) \
+ ; \
+ else if (match_word (keyword, subr, &old_locus) \
+ == MATCH_YES) \
+ return st; \
+ else \
+ undo_new_statement (); \
+ } while (0);
+
static gfc_statement
decode_omp_directive (void)
{
locus old_locus;
char c;
bool simd_matched = false;
+ bool spec_only = false;
gfc_enforce_clean_symbol_state ();
return ST_NONE;
}
+ if (gfc_current_state () == COMP_FUNCTION
+ && gfc_current_block ()->result->ts.kind == -1)
+ spec_only = true;
+
gfc_unset_implicit_pure (NULL);
old_locus = gfc_current_locus;
matcho ("critical", gfc_match_omp_critical, ST_OMP_CRITICAL);
break;
case 'd':
- matchs ("declare reduction", gfc_match_omp_declare_reduction,
- ST_OMP_DECLARE_REDUCTION);
- matchs ("declare simd", gfc_match_omp_declare_simd,
- ST_OMP_DECLARE_SIMD);
- matcho ("declare target", gfc_match_omp_declare_target,
- ST_OMP_DECLARE_TARGET);
+ matchds ("declare reduction", gfc_match_omp_declare_reduction,
+ ST_OMP_DECLARE_REDUCTION);
+ matchds ("declare simd", gfc_match_omp_declare_simd,
+ ST_OMP_DECLARE_SIMD);
+ matchdo ("declare target", gfc_match_omp_declare_target,
+ ST_OMP_DECLARE_TARGET);
matchs ("distribute parallel do simd",
gfc_match_omp_distribute_parallel_do_simd,
ST_OMP_DISTRIBUTE_PARALLEL_DO_SIMD);
matcho ("teams distribute", gfc_match_omp_teams_distribute,
ST_OMP_TEAMS_DISTRIBUTE);
matcho ("teams", gfc_match_omp_teams, ST_OMP_TEAMS);
- matcho ("threadprivate", gfc_match_omp_threadprivate,
- ST_OMP_THREADPRIVATE);
+ matchdo ("threadprivate", gfc_match_omp_threadprivate,
+ ST_OMP_THREADPRIVATE);
break;
case 'w':
matcho ("workshare", gfc_match_omp_workshare, ST_OMP_WORKSHARE);
gfc_error_recovery ();
return ST_NONE;
+
+ do_spec_only:
+ reject_statement ();
+ gfc_clear_error ();
+ gfc_buffer_error (false);
+ gfc_current_locus = old_locus;
+ return ST_GET_FCN_CHARACTERISTICS;
}
static gfc_statement
gfc_buffer_error (false);
- if (st == ST_GET_FCN_CHARACTERISTICS && gfc_statement_label != NULL)
+ if (st == ST_GET_FCN_CHARACTERISTICS)
{
- gfc_free_st_label (gfc_statement_label);
- gfc_statement_label = NULL;
+ if (gfc_statement_label != NULL)
+ {
+ gfc_free_st_label (gfc_statement_label);
+ gfc_statement_label = NULL;
+ }
gfc_current_locus = old_locus;
}
gfc_finish_block (&cleanup));
/* Add all the decls we created during processing. */
- decl = saved_function_decls;
+ decl = nreverse (saved_function_decls);
while (decl)
{
tree next;
if (flag_coarray == GFC_FCOARRAY_LIB && has_coarray_vars)
generate_coarray_init (ns);
- decl = saved_local_decls;
+ decl = nreverse (saved_local_decls);
while (decl)
{
tree next;
if (GFC_DECL_GET_SCALAR_POINTER (decl)
|| GFC_DECL_GET_SCALAR_ALLOCATABLE (decl)
|| GFC_DECL_CRAY_POINTEE (decl)
+ || GFC_DECL_ASSOCIATE_VAR_P (decl)
|| VOID_TYPE_P (TREE_TYPE (TREE_TYPE (decl))))
return false;
tree decl = gfc_get_symbol_decl (n->sym);
if (gfc_omp_privatize_by_reference (decl))
decl = build_fold_indirect_ref (decl);
+ else if (DECL_P (decl))
+ TREE_ADDRESSABLE (decl) = 1;
if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)))
{
tree type = TREE_TYPE (decl);
set_mem_attributes (parmreg, parm, 1);
}
+ /* We need to preserve an address based on VIRTUAL_STACK_VARS_REGNUM for
+ the debug info in case it is not legitimate. */
if (GET_MODE (parmreg) != GET_MODE (rtl))
{
rtx tempreg = gen_reg_rtx (GET_MODE (rtl));
all->last_conversion_insn);
emit_move_insn (tempreg, rtl);
tempreg = convert_to_mode (GET_MODE (parmreg), tempreg, unsigned_p);
- emit_move_insn (parmreg, tempreg);
+ emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg,
+ tempreg);
all->first_conversion_insn = get_insns ();
all->last_conversion_insn = get_last_insn ();
end_sequence ();
did_conversion = true;
}
else
- emit_move_insn (parmreg, rtl);
+ emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg, rtl);
rtl = parmreg;
for (unsigned j = 0; e->values[j].arg != NULL; j++)
{
char *with_arg = concat (opt_text, e->values[j].arg, NULL);
- add_misspelling_candidates (m_option_suggestions, with_arg);
+ add_misspelling_candidates (m_option_suggestions, option,
+ with_arg);
free (with_arg);
}
}
else
- add_misspelling_candidates (m_option_suggestions, opt_text);
+ add_misspelling_candidates (m_option_suggestions, option,
+ opt_text);
break;
case OPT_fsanitize_:
/* Add with_arg and all of its variant spellings e.g.
"-fno-sanitize=address" to candidates (albeit without
leading dashes). */
- add_misspelling_candidates (m_option_suggestions, with_arg);
+ add_misspelling_candidates (m_option_suggestions, option,
+ with_arg);
free (with_arg);
}
}
this mode as a component. */
struct mode_data *next_cont; /* Next mode in that list. */
+ struct mode_data *complex; /* complex type with mode as component. */
const char *file; /* file and line of definition, */
unsigned int line; /* for error reporting */
unsigned int counter; /* Rank ordering of modes */
static const struct mode_data blank_mode = {
0, "<unknown>", MAX_MODE_CLASS,
-1U, -1U, -1U, -1U,
- 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0,
"<unknown>", 0, 0, 0, 0, false, 0
};
c = new_mode (cclass, buf, file, line);
c->component = m;
+ m->complex = c;
}
}
}
static void
+emit_mode_complex (void)
+{
+ int c;
+ struct mode_data *m;
+
+ print_decl ("unsigned char", "mode_complex", "NUM_MACHINE_MODES");
+
+ for_all_modes (c, m)
+ tagged_printf ("%smode",
+ m->complex ? m->complex->name : void_mode->name,
+ m->name);
+
+ print_closer ();
+}
+
+static void
emit_mode_mask (void)
{
int c;
emit_mode_size ();
emit_mode_nunits ();
emit_mode_wider ();
+ emit_mode_complex ();
emit_mode_mask ();
emit_mode_inner ();
emit_mode_unit_size ();
{
while (TREE_CODE (decl) == COMPONENT_REF)
decl = TREE_OPERAND (decl, 0);
+ if (TREE_CODE (decl) == INDIRECT_REF
+ && DECL_P (TREE_OPERAND (decl, 0))
+ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (decl, 0)))
+ == REFERENCE_TYPE))
+ decl = TREE_OPERAND (decl, 0);
}
if (gimplify_expr (pd, pre_p, NULL, is_gimple_lvalue, fb_lvalue)
== GS_ERROR)
break;
}
- if (TYPE_SIZE_UNIT (TREE_TYPE (decl)) == NULL
- || (TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (decl)))
- != INTEGER_CST))
+ tree stype = TREE_TYPE (decl);
+ if (TREE_CODE (stype) == REFERENCE_TYPE)
+ stype = TREE_TYPE (stype);
+ if (TYPE_SIZE_UNIT (stype) == NULL
+ || TREE_CODE (TYPE_SIZE_UNIT (stype)) != INTEGER_CST)
{
error_at (OMP_CLAUSE_LOCATION (c),
"mapping field %qE of variable length "
base = get_inner_reference (base, &bitsize, &bitpos, &offset,
&mode, &unsignedp, &reversep,
&volatilep, false);
+ tree orig_base = base;
+ if ((TREE_CODE (base) == INDIRECT_REF
+ || (TREE_CODE (base) == MEM_REF
+ && integer_zerop (TREE_OPERAND (base, 1))))
+ && DECL_P (TREE_OPERAND (base, 0))
+ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base, 0)))
+ == REFERENCE_TYPE))
+ base = TREE_OPERAND (base, 0);
gcc_assert (base == decl
&& (offset == NULL_TREE
|| TREE_CODE (offset) == INTEGER_CST));
tree l = build_omp_clause (OMP_CLAUSE_LOCATION (c),
OMP_CLAUSE_MAP);
OMP_CLAUSE_SET_MAP_KIND (l, GOMP_MAP_STRUCT);
- OMP_CLAUSE_DECL (l) = decl;
+ if (orig_base != base)
+ OMP_CLAUSE_DECL (l) = unshare_expr (orig_base);
+ else
+ OMP_CLAUSE_DECL (l) = decl;
OMP_CLAUSE_SIZE (l) = size_int (1);
if (struct_map_to_clause == NULL)
struct_map_to_clause = new hash_map<tree, tree>;
*list_p = l;
list_p = &OMP_CLAUSE_CHAIN (l);
}
+ if (orig_base != base && code == OMP_TARGET)
+ {
+ tree c2 = build_omp_clause (OMP_CLAUSE_LOCATION (c),
+ OMP_CLAUSE_MAP);
+ enum gomp_map_kind mkind
+ = GOMP_MAP_FIRSTPRIVATE_REFERENCE;
+ OMP_CLAUSE_SET_MAP_KIND (c2, mkind);
+ OMP_CLAUSE_DECL (c2) = decl;
+ OMP_CLAUSE_SIZE (c2) = size_zero_node;
+ OMP_CLAUSE_CHAIN (c2) = OMP_CLAUSE_CHAIN (l);
+ OMP_CLAUSE_CHAIN (l) = c2;
+ }
flags = GOVD_MAP | GOVD_EXPLICIT;
if (GOMP_MAP_ALWAYS_P (OMP_CLAUSE_MAP_KIND (c)) || ptr)
flags |= GOVD_SEEN;
o1 = 0;
if (bitpos)
o1 = o1 + bitpos / BITS_PER_UNIT;
- for (sc = &OMP_CLAUSE_CHAIN (*osc);
- *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc))
+ sc = &OMP_CLAUSE_CHAIN (*osc);
+ if (*sc != c
+ && (OMP_CLAUSE_MAP_KIND (*sc)
+ == GOMP_MAP_FIRSTPRIVATE_REFERENCE))
+ sc = &OMP_CLAUSE_CHAIN (*sc);
+ for (; *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc))
if (ptr && sc == prev_list_p)
break;
else if (TREE_CODE (OMP_CLAUSE_DECL (*sc))
&mode, &unsignedp,
&reversep, &volatilep,
false);
+ if ((TREE_CODE (base) == INDIRECT_REF
+ || (TREE_CODE (base) == MEM_REF
+ && integer_zerop (TREE_OPERAND (base,
+ 1))))
+ && DECL_P (TREE_OPERAND (base, 0))
+ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base,
+ 0)))
+ == REFERENCE_TYPE))
+ base = TREE_OPERAND (base, 0);
if (base != decl)
break;
if (scp)
/* For functions with body versioning will make a copy of arguments.
For functions with no body we need to do it here. */
if (!gimple_has_body_p (fndecl))
- DECL_ARGUMENTS (new_decl) = copy_list (DECL_ARGUMENTS (fndecl));
+ {
+ tree arg;
+
+ DECL_ARGUMENTS (new_decl) = copy_list (DECL_ARGUMENTS (fndecl));
+ for (arg = DECL_ARGUMENTS (new_decl); arg; arg = DECL_CHAIN (arg))
+ DECL_CONTEXT (arg) = new_decl;
+ }
/* We are going to modify attributes list and therefore should
make own copy. */
if (dump_file)
fprintf (dump_file, "Dropping flag_strict_aliasing on %s:%i\n",
to->name (), to->order);
- build_optimization_node (&opts);
DECL_FUNCTION_SPECIFIC_OPTIMIZATION (to->decl)
= build_optimization_node (&opts);
}
extern const unsigned char mode_2xwider[NUM_MACHINE_MODES];
#define GET_MODE_2XWIDER_MODE(MODE) ((machine_mode) mode_2xwider[MODE])
+/* Get the complex mode from the component mode. */
+extern const unsigned char mode_complex[NUM_MACHINE_MODES];
+#define GET_MODE_COMPLEX_MODE(MODE) ((machine_mode) mode_complex[MODE])
+
/* Return the mode for data of a given size SIZE and mode class CLASS.
If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE.
The value is BLKmode if no other mode is found. */
(ne (bit_and:c (bit_not @0) @1) integer_zerop)
(if (INTEGRAL_TYPE_P (TREE_TYPE (@1))
&& TYPE_PRECISION (TREE_TYPE (@1)) == 1)
- (lt @0 @1)))
+ (if (TYPE_UNSIGNED (TREE_TYPE (@1)))
+ (lt @0 @1)
+ (gt @0 @1))))
(simplify
(ne (bit_ior:c (bit_not @0) @1) integer_zerop)
(if (INTEGRAL_TYPE_P (TREE_TYPE (@1))
&& TYPE_PRECISION (TREE_TYPE (@1)) == 1)
- (le @0 @1)))
+ (if (TYPE_UNSIGNED (TREE_TYPE (@1)))
+ (le @0 @1)
+ (ge @0 @1))))
/* ~~x -> x */
(simplify
if (new_var == NULL_TREE)
new_var = maybe_lookup_decl_in_outer_ctx (var, ctx);
x = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED);
- x = build_call_expr_loc (clause_loc, x, 2, new_var,
- omp_clause_aligned_alignment (c));
+ tree alarg = omp_clause_aligned_alignment (c);
+ alarg = fold_convert_loc (clause_loc, size_type_node, alarg);
+ x = build_call_expr_loc (clause_loc, x, 2, new_var, alarg);
x = fold_convert_loc (clause_loc, TREE_TYPE (new_var), x);
x = build2 (MODIFY_EXPR, TREE_TYPE (new_var), new_var, x);
gimplify_and_add (x, ilist);
t = maybe_lookup_decl_in_outer_ctx (var, ctx);
t = build_fold_addr_expr_loc (clause_loc, t);
t2 = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED);
- t = build_call_expr_loc (clause_loc, t2, 2, t,
- omp_clause_aligned_alignment (c));
+ tree alarg = omp_clause_aligned_alignment (c);
+ alarg = fold_convert_loc (clause_loc, size_type_node, alarg);
+ t = build_call_expr_loc (clause_loc, t2, 2, t, alarg);
t = fold_convert_loc (clause_loc, ptype, t);
x = create_tmp_var (ptype);
t = build2 (MODIFY_EXPR, ptype, x, t);
to specific options. We want to do the reverse: to find all the ways
that a user could validly spell an option.
- Given valid OPT_TEXT (with a leading dash), add it and all of its valid
- variant spellings to CANDIDATES, each without a leading dash.
+ Given valid OPT_TEXT (with a leading dash) for OPTION, add it and all
+ of its valid variant spellings to CANDIDATES, each without a leading
+ dash.
For example, given "-Wabi-tag", the following are added to CANDIDATES:
"Wabi-tag"
void
add_misspelling_candidates (auto_vec<char *> *candidates,
+ const struct cl_option *option,
const char *opt_text)
{
gcc_assert (candidates);
+ gcc_assert (option);
gcc_assert (opt_text);
candidates->safe_push (xstrdup (opt_text + 1));
for (unsigned i = 0; i < ARRAY_SIZE (option_map); i++)
const char *new_prefix = option_map[i].new_prefix;
size_t new_prefix_len = strlen (new_prefix);
+ if (option->cl_reject_negative && option_map[i].negated)
+ continue;
+
if (strncmp (opt_text, new_prefix, new_prefix_len) == 0)
{
char *alternative = concat (opt0 + 1, opt_text + new_prefix_len,
} sanitizer_opts[];
extern void add_misspelling_candidates (auto_vec<char *> *candidates,
+ const struct cl_option *option,
const char *base_option);
#endif
case COMPLEX_TYPE:
TYPE_UNSIGNED (type) = TYPE_UNSIGNED (TREE_TYPE (type));
SET_TYPE_MODE (type,
- mode_for_size (2 * TYPE_PRECISION (TREE_TYPE (type)),
- (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
- ? MODE_COMPLEX_FLOAT : MODE_COMPLEX_INT),
- 0));
+ GET_MODE_COMPLEX_MODE (TYPE_MODE (TREE_TYPE (type))));
+
TYPE_SIZE (type) = bitsize_int (GET_MODE_BITSIZE (TYPE_MODE (type)));
TYPE_SIZE_UNIT (type) = size_int (GET_MODE_SIZE (TYPE_MODE (type)));
break;
+2016-07-09 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk:
+ PR fortran/71783
+ * gfortran.dg/dependency_46.f90: New test.
+
+2016-07-08 Cesar Philippidis <cesar@codesourcery.com>
+
+ Backport from trunk:
+ 2016-07-08 Cesar Philippidis <cesar@codesourcery.com>
+
+ * gfortran.dg/goacc/pr71704.f90: New test.
+
+2016-07-08 Martin Liska <mliska@suse.cz>
+
+ Backported from mainline
+ 2016-07-08 Martin Liska <mliska@suse.cz>
+
+ * gcc.dg/torture/pr71606.c: New test.
+
+2016-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ Back port from the trunk
+ 2016-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ * gcc.target/aarch64/simd/vminmaxnm_1.c: New.
+
+2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from trunk
+ 2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/71806
+ * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Add -mfloat128 option.
+
+2016-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from the trunk
+ 2016-07-01 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/71720
+ * gcc.target/powerpc/pr71720.c: New test.
+
+2016-07-07 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from mainline r237885
+ 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * gcc.target/powerpc/dfp/dfp.exp: New dejagnu test script.
+ * gcc.target/powerpc/dfp/dtstsfi-0.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-1.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-10.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-11.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-12.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-13.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-14.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-15.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-16.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-17.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-18.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-19.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-2.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-20.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-21.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-22.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-23.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-24.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-25.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-26.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-27.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-28.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-29.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-3.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-30.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-31.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-32.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-33.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-34.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-35.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-36.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-37.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-38.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-39.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-4.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-40.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-41.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-42.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-43.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-44.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-45.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-46.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-47.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-48.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-49.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-5.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-50.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-51.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-52.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-53.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-54.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-55.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-56.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-57.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-58.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-59.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-6.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-60.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-61.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-62.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-63.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-64.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-65.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-66.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-67.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-68.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-69.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-7.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-70.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-71.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-72.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-73.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-74.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-75.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-76.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-77.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-78.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-79.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-8.c: New test.
+ * gcc.target/powerpc/dfp/dtstsfi-9.c: New test.
+
+2016-07-07 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2016-06-13 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/64516
+ * gcc.dg/align-3.c: New testcase.
+
+2016-07-07 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2016-05-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71264
+ * gcc.dg/vect/pr71264.c: New testcase.
+
+ 2016-06-07 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/71423
+ * gcc.dg/torture/pr71423.c: New testcase.
+
+ 2016-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71521
+ * gcc.dg/tree-ssa/vrp101.c: New testcase.
+
+ 2016-06-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71452
+ * gcc.dg/torture/pr71452.c: New testcase.
+
+ 2016-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/71522
+ * gcc.dg/torture/pr71522.c: New testcase.
+
+2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ Backport from mainline
+ 2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ PR target/50739
+ * gcc.target/avr/pr50739.c: New test.
+
+2016-07-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ Backport from mainline
+ 2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * gcc.dg/const-float128-ped.c: Require __float128 effective
+ target and options.
+ * gcc.dg/const-float128.c: Likewise.
+ * gcc.dg/torture/float128-cmp-invalid.c: Require
+ __float128 and base_quadfloat_support effective targets, and
+ __float128 options.
+ * gcc.dg/torture/float128-div-underflow.c: Likewise.
+ * gcc.dg/torture/float128-extend-nan.c: Likewise.
+ * gcc.dg/torture/fp-int-convert-float128-timode-2.c: Likewise.
+ * gcc.dg/torture/fp-int-convert-float128-timode-3.c: Likewise.
+ * gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise.
+ * lib/target-supports.exp (check_effective_target___float128):
+ New.
+ (add_options_for___float128): New.
+ (check_effective_target_base_quadword_support): New.
+
+2016-07-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/71739
+ * g++.dg/cpp0x/pr71739.C: New test.
+
+2016-07-04 Segher Boessenkool <segher@kernel.crashing.org>
+
+ Backport from mainline
+ 2016-06-27 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/71670
+ * gcc.target/powerpc/pr71670.c: New testcase.
+
+2016-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-07-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/71687
+ * gfortran.dg/gomp/pr71687.f90: New test.
+
+ 2016-06-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/71704
+ * gfortran.dg/gomp/pr71704.f90: New test.
+
+ PR fortran/71705
+ * gfortran.dg/gomp/pr71705.f90: New test.
+
+ 2016-06-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/71685
+ * gcc.dg/pr71685.c: New test.
+
+ 2016-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71626
+ * gcc.c-torture/execute/pr71626-1.c: New test.
+ * gcc.c-torture/execute/pr71626-2.c: New test.
+
+ 2016-06-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/71559
+ * gcc.target/i386/sse2-pr71559.c: New test.
+ * gcc.target/i386/avx-pr71559.c: New test.
+ * gcc.target/i386/avx512f-pr71559.c: New test.
+
+2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r237659
+ 2016-06-21 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * gcc.target/powerpc/darn-0.c: Add dejagnu directives to disable
+ test if effective-target is not powerpc_p9vector_ok, or if a -mcpu
+ override other than -mcpu=power9 command-line option is specified,
+ or if the target operating system is aix.
+ * gcc.target/powerpc/darn-1.c: Likewise.
+ * gcc.target/powerpc/darn-2.c: Likewise.
+ * gcc.target/powerpc/vslv-0.c: Add dejagnu directives to disable
+ test if effective-target is not powerpc_p9vector_ok or if the
+ target operating system is aix.
+ * gcc.target/powerpc/vslv-1.c: Likewise.
+ * gcc.target/powerpc/vsrv-0.c: Likewise.
+ * gcc.target/powerpc/vsrv-1.c: Likewise.
+
+2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ Backport from trunk
+ 2016-06-27 Peter Bergner <bergner@vnet.ibm.com>
+
+ PR target/71656
+ * gcc.target/powerpc/pr71656-1.c: New test.
+ * gcc.target/powerpc/pr71656-2.c: New test.
+
+2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ Backport from mainline
+ 2016-06-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * gcc.target/powerpc/abs128-1.c: New.
+ * gcc.target/powerpc/copysign128-1.c: New.
+ * gcc.target/powerpc/inf128-1.c: New.
+ * gcc.target/powerpc/nan128-1.c: New.
+
+ Backport from mainline
+ 2016-06-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * gcc.target/powerpc/abs128-1.c: Require VSX.
+ * gcc.target/powerpc/copysign128-1.c: Likewise.
+ * gcc.target/powerpc/inf128-1.c: Likewise.
+ * gcc.target/powerpc/nan128-1.c: Likewise.
+
+2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ Backport from trunk
+ 2016-07-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ PR target/71698
+ * gcc.target/powerpc/pr71698.c: New test.
+
+2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r236992
+ 2016-06-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * gcc.target/powerpc/vslv-0.c: New test.
+ * gcc.target/powerpc/vslv-1.c: New test.
+ * gcc.target/powerpc/vsrv-0.c: New test.
+ * gcc.target/powerpc/vsrv-1.c: New test.
+
+2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ Backport from trunk r237390
+ 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
+ Backport from trunk r237646
+ 2016-06-20 Kelvin Nilsen <kelvin@gcc.gnu.org>
+
+ * gcc.target/powerpc/vadsdu-0.c: New test.
+ * gcc.target/powerpc/vadsdu-1.c: New test.
+ * gcc.target/powerpc/vadsdu-2.c: New test.
+ * gcc.target/powerpc/vadsdu-3.c: New test.
+ * gcc.target/powerpc/vadsdu-4.c: New test.
+ * gcc.target/powerpc/vadsdu-5.c: New test.
+ * gcc.target/powerpc/vadsdub-1.c: New test.
+ * gcc.target/powerpc/vadsdub-2.c: New test.
+ * gcc.target/powerpc/vadsduh-1.c: New test.
+ * gcc.target/powerpc/vadsduh-2.c: New test.
+ * gcc.target/powerpc/vadsduw-1.c: New test.
+ * gcc.target/powerpc/vadsduw-2.c: New test.
+
+2016-06-30 David Malcolm <dmalcolm@redhat.com>
+
+ Backport from trunk r237880.
+ 2016-06-30 David Malcolm <dmalcolm@redhat.com>
+
+ PR driver/71651
+ * gcc.dg/spellcheck-options-12.c: New test case.
+
+2016-06-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71693
+ * gcc.c-torture/compile/pr71693.c: New test.
+
+2016-06-29 Cesar Philippidis <cesar@codesourcery.com>
+
+ Back port from trunk
+ 2016-06-29 Cesar Philippidis <cesar@codesourcery.com>
+
+ * gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics.
+ * gfortran.dg/goacc/asyncwait-3.f95: Likewise.
+ * gfortran.dg/goacc/asyncwait-4.f95: Add test coverage.
+
+2016-06-27 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/70673
+ * gfortran.dg/pr70673.f90: New test.
+
+2016-06-27 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Back port from trunk
+ 2016-05-02 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * gcc.target/powerpc/float128-complex-1.c: New tests for complex
+ __float128.
+ * gcc.target/powerpc/float128-complex-2.c: Likewise.
+
+2016-06-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/71647
+ * gcc.target/i386/pr71647.c: New test.
+
+2016-06-22 Eric Botcazou <ebotcazou@adacore.com>
+
+ * gcc.dg/guality/param-5.c: New test.
+
+2016-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/71588
+ * gcc.dg/pr71558.c: New test.
+
+ Backported from mainline
+ 2016-06-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/71581
+ * gcc.dg/pr71581.c: New test.
+
+ 2016-06-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/71528
+ * g++.dg/opt/pr71528.C: New test.
+
+2016-06-20 Ilya Enkovich <ilya.enkovich@intel.com>
+
+ Backport from mainline r237484.
+ 2016-06-15 Ilya Enkovich <ilya.enkovich@intel.com>
+
+ PR middle-end/71529
+ * gcc.target/i386/pr71529.C: New test.
+
+2016-06-20 Georg-Johann Lay <avr@gjlay.de>
+ Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+
+ Backport from 2016-06-20 trunk r237589, r236558.
+
+ PR target/71103
+ * gcc.target/avr/pr71103.c: New test.
+ * gcc.target/avr/torture/pr71103-2.c: New test.
+
+2016-06-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ Backport from mainline
+ 2016-06-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+ * gcc.target/powerpc/vsx-elemrev-2.c: Change effective target
+ requirements, and disable for AIX for now.
+ * gcc.target/powerpc/vsx-elemrev-4.c: Likewise.
+
+2016-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/71554
+ * gcc.c-torture/execute/pr71554.c: New test.
+
2016-06-14 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/70572
--- /dev/null
+// PR c++/71739
+// { dg-do compile { target c++11 } }
+
+template <int N> struct alignas(N) A;
+template <int N> struct alignas(N) A {};
# error "__cpp_attributes != 200809"
#endif
-#ifndef __cpp_rvalue_reference
-# error "__cpp_rvalue_reference"
-#elif __cpp_rvalue_reference != 200610
-# error "__cpp_rvalue_reference != 200610"
+#ifndef __cpp_rvalue_references
+# error "__cpp_rvalue_references"
+#elif __cpp_rvalue_references != 200610
+# error "__cpp_rvalue_references != 200610"
#endif
#ifndef __cpp_variadic_templates
# error "__cpp_attributes != 200809"
#endif
-#ifndef __cpp_rvalue_reference
-# error "__cpp_rvalue_reference"
-#elif __cpp_rvalue_reference != 200610
-# error "__cpp_rvalue_reference != 200610"
+#ifndef __cpp_rvalue_references
+# error "__cpp_rvalue_references"
+#elif __cpp_rvalue_references != 200610
+# error "__cpp_rvalue_references != 200610"
#endif
#ifndef __cpp_variadic_templates
# error "__cpp_attributes" // { dg-error "error" }
#endif
-#ifndef __cpp_rvalue_reference
-# error "__cpp_rvalue_reference" // { dg-error "error" }
+#ifndef __cpp_rvalue_references
+# error "__cpp_rvalue_references" // { dg-error "error" }
#endif
#ifndef __cpp_variadic_templates
# error "__cpp_attributes != 200809"
#endif
-#ifndef __cpp_rvalue_reference
-# error "__cpp_rvalue_reference"
-#elif __cpp_rvalue_reference != 200610
-# error "__cpp_rvalue_reference != 200610"
+#ifndef __cpp_rvalue_references
+# error "__cpp_rvalue_references"
+#elif __cpp_rvalue_references != 200610
+# error "__cpp_rvalue_references != 200610"
#endif
#ifndef __cpp_variadic_templates
--- /dev/null
+// PR c++/71528
+// { dg-do run }
+// { dg-options "-O2" }
+
+extern int &x;
+int y;
+
+int &
+foo ()
+{
+ return y;
+}
+
+int &x = foo ();
+
+int
+main ()
+{
+ if (&x != &y)
+ __builtin_abort ();
+}
+
+extern int &x;
--- /dev/null
+// { dg-do run }
+
+int main()
+{
+ bool b;
+ *(char *)&b = 123;
+ if (*(char *)&b != 123)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* PR middle-end/71693 */
+
+unsigned short v;
+
+void
+foo (int x)
+{
+ v = ((((unsigned short) (0x0001 | (x & 0x0070) | 0x0100) & 0x00ffU) << 8)
+ | (((unsigned short) (0x0001 | (x & 0x0070) | 0x0100) >> 8) & 0x00ffU));
+}
--- /dev/null
+/* PR target/71554 */
+
+int v;
+
+__attribute__ ((noinline, noclone)) void
+bar (void)
+{
+ v++;
+}
+
+__attribute__ ((noinline, noclone))
+void
+foo (unsigned int x)
+{
+ signed int y = ((-__INT_MAX__ - 1) / 2);
+ signed int r;
+ if (__builtin_mul_overflow (x, y, &r))
+ bar ();
+}
+
+int
+main ()
+{
+ foo (2);
+ if (v)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* PR middle-end/71626 */
+
+typedef __INTPTR_TYPE__ V __attribute__((__vector_size__(sizeof (__INTPTR_TYPE__))));
+
+__attribute__((noinline, noclone)) V
+foo ()
+{
+ V v = { (__INTPTR_TYPE__) foo };
+ return v;
+}
+
+int
+main ()
+{
+ V v = foo ();
+ if (v[0] != (__INTPTR_TYPE__) foo)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* PR middle-end/71626 */
+/* { dg-additional-options "-fpic" { target fpic } } */
+
+#include "pr71626-1.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-rtl-expand" } */
+
+typedef struct { char a[2]; } __attribute__((__packed__)) TU2;
+unsigned short get16_unaligned(const void *p) {
+ unsigned short v;
+ *(TU2 *)(void *)(&v) = *(const TU2 *)p;
+ return v;
+}
+
+/* { dg-final { scan-rtl-dump "MEM\[^\n\r\]*A8\\\]" "expand" } } */
/* Test 'q' suffix with -pedantic on __float128 type constants. */
-/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-do compile } */
+/* { dg-require-effective-target __float128 } */
/* { dg-options "-pedantic" } */
+/* { dg-add-options __float128 } */
__float128 a = 123.456789q; /* { dg-warning "non-standard suffix on floating constant" } */
/* Test 'q' and 'Q' suffixes on __float128 type constants. */
-/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-do compile } */
+/* { dg-require-effective-target __float128 } */
/* { dg-options "" } */
+/* { dg-add-options __float128 } */
__float128 a = 123.456789q;
__float128 b = 123.456789Q;
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-g" } */
+/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
+
+typedef __UINTPTR_TYPE__ uintptr_t;
+
+typedef struct { uintptr_t pa; uintptr_t pb; } fatp_t
+ __attribute__ ((aligned (2 * __alignof__ (uintptr_t))));
+
+__attribute__((noinline, noclone)) void
+clear_stack (void)
+{
+ char a[128 * 1024 + 128];
+
+ __builtin_memset (a + 128 * 1024, 0, 128);
+}
+
+__attribute__((noinline, noclone)) void
+foo (fatp_t str, int count)
+{
+ char a[128 * 1024];
+
+ if (count > 0)
+ foo (str, count - 1);
+ clear_stack ();
+ count--; /* BREAK */
+}
+
+int
+main (void)
+{
+ fatp_t ptr = { 31415927, 27182818 };
+ foo (ptr, 1);
+ return 0;
+}
+
+/* { dg-final { gdb-test 26 "str.pa" "31415927" } } */
+/* { dg-final { gdb-test 26 "str.pb" "27182818" } } */
--- /dev/null
+/* PR tree-optimization/71588 */
+
+/* strcpy must not be pure, but make sure we don't ICE even when
+ it is declared incorrectly. */
+char *strcpy (char *, const char *) __attribute__ ((__pure__));
+__SIZE_TYPE__ strlen (const char *);
+void *malloc (__SIZE_TYPE__);
+
+char a[20];
+
+char *
+foo (void)
+{
+ __SIZE_TYPE__ b = strlen (a);
+ char *c = malloc (b);
+ return strcpy (c, a);
+}
--- /dev/null
+/* PR middle-end/71581 */
+/* { dg-do compile } */
+/* { dg-options "-Wuninitialized" } */
+
+_Complex float
+f1 (void)
+{
+ float x;
+ return x; /* { dg-warning "is used uninitialized in this function" } */
+}
+
+_Complex double
+f2 (void)
+{
+ double x;
+ return x; /* { dg-warning "is used uninitialized in this function" } */
+}
+
+_Complex int
+f3 (void)
+{
+ int x;
+ return x; /* { dg-warning "is used uninitialized in this function" } */
+}
--- /dev/null
+/* PR c/71685 */
+/* { dg-do compile } */
+/* { dg-options "-std=gnu11" } */
+
+extern struct S v, s;
+struct S { int t; int p[]; } v = { 4, 0 };
--- /dev/null
+/* Verify that we don't include -Wno- variants for options marked
+ with RejectNegative when considering hints for misspelled options
+ (PR driver/71651). */
+
+/* { dg-do compile } */
+/* { dg-options "-fno-stack-protector-explicit" } */
+/* { dg-error "unrecognized command line option .-fno-stack-protector-explicit.; did you mean .-fstack-protector-explicit.." "" { target *-*-* } 0 } */
/* Test for "invalid" exceptions from __float128 comparisons. */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
/* { dg-options "" } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-require-effective-target fenv_exceptions } */
+/* { dg-add-options __float128 } */
#include <fenv.h>
#include <stdlib.h>
/* Test for spurious underflow from __float128 division. */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
/* { dg-options "" } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-require-effective-target fenv_exceptions } */
+/* { dg-add-options __float128 } */
#include <fenv.h>
#include <stdlib.h>
/* Test extensions to __float128 quiet signaling NaNs. */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
/* { dg-options "-fsignaling-nans" } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-require-effective-target fenv_exceptions } */
+/* { dg-add-options __float128 } */
#include <fenv.h>
#include <float.h>
/* Test floating-point conversions. __float128 type with TImode: bug
53317. */
/* Origin: Joseph Myers <joseph@codesourcery.com> */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-require-effective-target int128 } */
/* { dg-options "" } */
+/* { dg-add-options __float128 } */
extern void abort (void);
extern void exit (int);
/* Test for correct rounding of conversions from __int128 to
__float128. */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-require-effective-target int128 } */
/* { dg-options "-frounding-math" } */
+/* { dg-add-options __float128 } */
#include <fenv.h>
#include <stdlib.h>
/* Test floating-point conversions. __float128 type with TImode. */
/* Origin: Joseph Myers <joseph@codesourcery.com> */
-/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */
+/* { dg-do run } */
+/* { dg-require-effective-target __float128 } */
+/* { dg-require-effective-target base_quadfloat_support } */
/* { dg-options "" } */
+/* { dg-add-options __float128 } */
#include "fp-int-convert.h"
--- /dev/null
+/* { dg-do run } */
+
+struct S1
+{
+ int f1:1;
+};
+
+volatile struct S1 b = { 0 };
+
+int
+main ()
+{
+ char c = b.f1;
+ b.f1 = 1;
+
+ if (b.f1 > -1 || c)
+ __builtin_abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+
+int main()
+{
+ _Bool b;
+ *(char *)&b = 123;
+ if (*(char *)&b != 123)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+
+#if __SIZEOF_LONG_DOUBLE__ == 16
+#define STR "AAAAAAAAAAAAAAA"
+#elif __SIZEOF_LONG_DOUBLE__ == 12
+#define STR "AAAAAAAAAAA"
+#elif __SIZEOF_LONG_DOUBLE__ == 8
+#define STR "AAAAAAA"
+#elif __SIZEOF_LONG_DOUBLE__ == 4
+#define STR "AAA"
+#else
+#define STR "A"
+#endif
+
+int main()
+{
+ long double d;
+ char s[sizeof d];
+
+ __builtin_memcpy(&d, STR, sizeof d);
+ __builtin_memcpy(&s, &d, sizeof s);
+
+ if (__builtin_strncmp (s, STR, sizeof s) != 0)
+ __builtin_abort ();
+
+ return 0;
+}
--- /dev/null
+_Complex a;
+void fn1 ();
+
+int main () {
+ fn1 (a);
+ return 0;
+}
+
+void fn1 (__complex__ long double p1) {
+ __imag__ p1 = 6.0L;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+int x = 1;
+
+int main ()
+{
+ int t = (1/(1>=x))>>1;
+ if (t != 0) __builtin_abort();
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump "<bb 2>:\[\n\r \]*return 0;" "optimized" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target vect_int } */
+
+typedef unsigned char uint8_t;
+typedef uint8_t footype __attribute__((vector_size(4)));
+
+void test(uint8_t *ptr, uint8_t *mask)
+{
+ footype mv;
+ __builtin_memcpy(&mv, mask, sizeof(mv));
+ for (unsigned i = 0; i < 16; i += 4)
+ {
+ footype temp;
+ __builtin_memcpy(&temp, &ptr[i], sizeof(temp));
+ temp ^= mv;
+ __builtin_memcpy(&ptr[i], &temp, sizeof(temp));
+ }
+}
+
+/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */
--- /dev/null
+/* Test the `v[min|max]nm{q}_f*' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+#define CHECK(T, N, R, E) \
+ {\
+ int i = 0;\
+ for (; i < N; i++)\
+ if (* (T *) &R[i] != * (T *) &E[i])\
+ abort ();\
+ }
+
+int
+main (int argc, char **argv)
+{
+ float32x2_t f32x2_input1 = vdup_n_f32 (-1.0);
+ float32x2_t f32x2_input2 = vdup_n_f32 (0.0);
+ float32x2_t f32x2_exp_minnm = vdup_n_f32 (-1.0);
+ float32x2_t f32x2_exp_maxnm = vdup_n_f32 (0.0);
+ float32x2_t f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2);
+ float32x2_t f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2);
+
+ CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+ CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+
+ f32x2_input1 = vdup_n_f32 (__builtin_nanf (""));
+ f32x2_input2 = vdup_n_f32 (1.0);
+ f32x2_exp_minnm = vdup_n_f32 (1.0);
+ f32x2_exp_maxnm = vdup_n_f32 (1.0);
+ f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2);
+ f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2);
+
+ CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm);
+ CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm);
+
+ float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0);
+ float32x4_t f32x4_input2 = vdupq_n_f32 (77.0);
+ float32x4_t f32x4_exp_minnm = vdupq_n_f32 (-1024.0);
+ float32x4_t f32x4_exp_maxnm = vdupq_n_f32 (77.0);
+ float32x4_t f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2);
+ float32x4_t f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2);
+
+ CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+ CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+
+ f32x4_input1 = vdupq_n_f32 (-__builtin_nanf (""));
+ f32x4_input2 = vdupq_n_f32 (-1.0);
+ f32x4_exp_minnm = vdupq_n_f32 (-1.0);
+ f32x4_exp_maxnm = vdupq_n_f32 (-1.0);
+ f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2);
+ f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2);
+
+ CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm);
+ CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm);
+
+ float64x2_t f64x2_input1 = vdupq_n_f64 (1.23);
+ float64x2_t f64x2_input2 = vdupq_n_f64 (4.56);
+ float64x2_t f64x2_exp_minnm = vdupq_n_f64 (1.23);
+ float64x2_t f64x2_exp_maxnm = vdupq_n_f64 (4.56);
+ float64x2_t f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2);
+ float64x2_t f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2);
+
+ CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm);
+ CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm);
+
+ f64x2_input1 = vdupq_n_f64 (-__builtin_nan (""));
+ f64x2_input2 = vdupq_n_f64 (1.0);
+ f64x2_exp_minnm = vdupq_n_f64 (1.0);
+ f64x2_exp_maxnm = vdupq_n_f64 (1.0);
+ f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2);
+ f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2);
+
+ CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm);
+ CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm);
+
+ return 0;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-fmerge-all-constants" } */
+
+char *ca = "123";
+
+const char a[] __attribute__((__progmem__))= "a";
+const char b[] __attribute__((__progmem__))= "b";
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+struct ResponseStruct{
+ unsigned char responseLength;
+ char *response;
+};
+
+static char response[5];
+struct ResponseStruct something(){
+ struct ResponseStruct returnValue;
+ returnValue.responseLength = 5;
+ returnValue.response = response;
+ return returnValue;
+}
+
--- /dev/null
+/* Use -g0 so that this test case doesn't just fail because
+ of PR52472. */
+
+/* { dg-do compile } */
+/* { dg-options "-std=gnu99 -g0" } */
+
+struct S12
+{
+ char c;
+ const char *p;
+};
+
+struct S12f
+{
+ char c;
+ struct S12f (*f)(void);
+};
+
+struct S12labl
+{
+ char c;
+ void **labl;
+};
+
+struct S121
+{
+ char c;
+ const char *p;
+ char d;
+};
+
+const char str[5] = "abcd";
+
+struct S12 test_S12_0 (void)
+{
+ struct S12 s;
+ s.c = 'A';
+ s.p = str;
+ return s;
+}
+
+struct S12 test_S12_4 (void)
+{
+ struct S12 s;
+ s.c = 'A';
+ s.p = str + 4;
+ return s;
+}
+
+struct S12f test_S12f (void)
+{
+ struct S12f s;
+ s.c = 'A';
+ s.f = test_S12f;
+ return s;
+}
+
+struct S121 test_S121 (void)
+{
+ struct S121 s;
+ s.c = 'c';
+ s.p = str + 4;
+ s.d = 'd';
+ return s;
+}
+
+extern void use_S12lab (struct S12labl*);
+
+struct S12labl test_S12lab (void)
+{
+ struct S12labl s;
+labl:;
+ s.c = 'A';
+ s.labl = &&labl;
+ return s;
+}
+
+#ifdef __MEMX
+
+struct S13
+{
+ char c;
+ const __memx char *p;
+};
+
+const __memx char str_x[] = "abcd";
+
+struct S13 test_S13_0 (void)
+{
+ struct S13 s;
+ s.c = 'A';
+ s.p = str_x;
+ return s;
+}
+
+struct S13 test_S13_4a (void)
+{
+ struct S13 s;
+ s.c = 'A';
+ s.p = str_x + 4;
+ return s;
+}
+
+#ifdef __FLASH1
+
+const __flash1 char str_1[] = "abcd";
+
+struct S13 test_13_4b (void)
+{
+ struct S13 s;
+ s.c = 'A';
+ s.p = str_1 + 4;
+ return s;
+}
+
+#endif /* have __flash1 */
+#endif /* have __memx */
+
--- /dev/null
+/* PR target/71559 */
+/* { dg-do run { target avx } } */
+/* { dg-options "-O2 -ftree-vectorize -mavx" } */
+
+#include "avx-check.h"
+#define PR71559_TEST avx_test
+
+#include "sse2-pr71559.c"
--- /dev/null
+/* PR target/71559 */
+/* { dg-do run { target avx512f } } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512f" } */
+
+#include "avx512f-check.h"
+#define PR71559_TEST avx512f_test
+
+#include "sse2-pr71559.c"
--- /dev/null
+/* PR71529 */
+/* { dg-do compile { target { ! x32 } } } */
+/* { dg-options "-fcheck-pointer-bounds -mmpx -O2" } */
+
+class c1
+{
+ public:
+ virtual ~c1 ();
+};
+
+class c2
+{
+ public:
+ virtual ~c2 ();
+};
+
+class c3 : c1, c2 { };
+
+int main (int, char **)
+{
+ c3 obj;
+}
--- /dev/null
+/* PR tree-optimization/71647 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fopenmp-simd -mavx -mno-avx512f -fdump-tree-vect-details" } */
+
+void
+foo (double *a, double *b)
+{
+ int i;
+#pragma omp simd aligned(a,b:4*sizeof(double))
+ for (i = 0; i < 32768; i++)
+ a[i] += b[i];
+}
+
+void
+bar (double *a, double *b)
+{
+ int i;
+#pragma omp simd aligned(a,b:32)
+ for (i = 0; i < 32768; i++)
+ a[i] += b[i];
+}
+
+void
+baz (double *a, double *b)
+{
+ int i;
+#pragma omp simd aligned(a,b:32L)
+ for (i = 0; i < 32768; i++)
+ a[i] += b[i];
+}
+
+/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */
--- /dev/null
+/* PR target/71559 */
+/* { dg-do run { target sse2 } } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+#ifndef PR71559_TEST
+#include "sse2-check.h"
+#define PR71559_TEST sse2_test
+#endif
+
+#define N 16
+float a[N] = { 5.0f, -3.0f, 1.0f, __builtin_nanf (""), 9.0f, 7.0f, -3.0f, -9.0f,
+ -3.0f, -5.0f, -9.0f, __builtin_nanf (""), 0.5f, -0.5f, 0.0f, 0.0f };
+float b[N] = { -5.0f, 3.0f, 1.0f, 7.0f, 8.0f, 8.0f, -3.0f, __builtin_nanf (""),
+ -4.0f, -4.0f, -9.0f, __builtin_nanf (""), 0.0f, 0.0f, 0.0f, __builtin_nanf ("") };
+int c[N], d[N];
+
+#define FN(name, op) \
+void \
+name (void) \
+{ \
+ int i; \
+ for (i = 0; i < N; i++) \
+ c[i] = (op || d[i] > 37) ? 5 : 32; \
+}
+FN (eq, a[i] == b[i])
+FN (ne, a[i] != b[i])
+FN (gt, a[i] > b[i])
+FN (ge, a[i] >= b[i])
+FN (lt, a[i] < b[i])
+FN (le, a[i] <= b[i])
+FN (unle, !__builtin_isgreater (a[i], b[i]))
+FN (unlt, !__builtin_isgreaterequal (a[i], b[i]))
+FN (unge, !__builtin_isless (a[i], b[i]))
+FN (ungt, !__builtin_islessequal (a[i], b[i]))
+FN (uneq, !__builtin_islessgreater (a[i], b[i]))
+FN (ordered, !__builtin_isunordered (a[i], b[i]))
+FN (unordered, __builtin_isunordered (a[i], b[i]))
+
+#define TEST(name, GT, LT, EQ, UO) \
+ name (); \
+ for (i = 0; i < N; i++) \
+ { \
+ int v; \
+ switch (i % 4) \
+ { \
+ case 0: v = GT ? 5 : 32; break; \
+ case 1: v = LT ? 5 : 32; break; \
+ case 2: v = EQ ? 5 : 32; break; \
+ case 3: v = UO ? 5 : 32; break; \
+ } \
+ if (c[i] != v) \
+ __builtin_abort (); \
+ }
+
+void
+PR71559_TEST (void)
+{
+ int i;
+ asm volatile ("" : : "g" (a), "g" (b), "g" (c), "g" (d) : "memory");
+ TEST (eq, 0, 0, 1, 0)
+ TEST (ne, 1, 1, 0, 1)
+ TEST (gt, 1, 0, 0, 0)
+ TEST (ge, 1, 0, 1, 0)
+ TEST (lt, 0, 1, 0, 0)
+ TEST (le, 0, 1, 1, 0)
+ TEST (unle, 0, 1, 1, 1)
+ TEST (unlt, 0, 1, 0, 1)
+ TEST (unge, 1, 0, 1, 1)
+ TEST (ungt, 1, 0, 0, 1)
+ TEST (uneq, 0, 0, 1, 1)
+ TEST (ordered, 1, 1, 1, 0)
+ TEST (unordered, 0, 0, 0, 1)
+}
--- /dev/null
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
+/* { dg-options "-mfloat128 -mvsx" } */
+
+void abort ();
+
+typedef unsigned long long int uint64_t;
+
+typedef union
+{
+ __float128 value;
+
+ struct
+ {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ unsigned negative:1;
+ unsigned exponent:15;
+ unsigned quiet_nan:1;
+ uint64_t mant_high:47;
+ uint64_t mant_low:64;
+#else
+ uint64_t mant_low:64;
+ uint64_t mant_high:47;
+ unsigned quiet_nan:1;
+ unsigned exponent:15;
+ unsigned negative:1;
+#endif
+ } nan;
+
+} ieee854_float128;
+
+int
+main (int argc, int *argv[])
+{
+ ieee854_float128 x, z;
+
+ x.nan.negative = 1;
+ x.nan.exponent = 0x22;
+ x.nan.quiet_nan = 0;
+ x.nan.mant_high = 0x1234;
+ x.nan.mant_low = 0xabcdef;
+
+ z.value = __builtin_fabsq (x.value);
+
+ if (z.nan.negative != 0
+ || z.nan.exponent != 0x22
+ || z.nan.quiet_nan != 0
+ || z.nan.mant_high != 0x1234
+ || z.nan.mant_low != 0xabcdef)
+ abort ();
+
+ z.value = __builtin_fabsq (z.value);
+
+ if (z.nan.negative != 0
+ || z.nan.exponent != 0x22
+ || z.nan.quiet_nan != 0
+ || z.nan.mant_high != 0x1234
+ || z.nan.mant_low != 0xabcdef)
+ abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
+/* { dg-options "-mfloat128 -mvsx" } */
+
+void abort ();
+
+typedef unsigned long long int uint64_t;
+
+typedef union
+{
+ __float128 value;
+
+ struct
+ {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ unsigned negative:1;
+ unsigned exponent:15;
+ unsigned quiet_nan:1;
+ uint64_t mant_high:47;
+ uint64_t mant_low:64;
+#else
+ uint64_t mant_low:64;
+ uint64_t mant_high:47;
+ unsigned quiet_nan:1;
+ unsigned exponent:15;
+ unsigned negative:1;
+#endif
+ } nan;
+
+} ieee854_float128;
+
+int
+main (int argc, int *argv[])
+{
+ ieee854_float128 x, y, z;
+
+ x.nan.negative = 0;
+ x.nan.exponent = 0x22;
+ x.nan.quiet_nan = 0;
+ x.nan.mant_high = 0x1234;
+ x.nan.mant_low = 0xabcdef;
+
+ y.nan.negative = 1;
+ y.nan.exponent = 0;
+ y.nan.quiet_nan = 0;
+ y.nan.mant_high = 0;
+ y.nan.mant_low = 0;
+
+ z.value = __builtin_copysignq (x.value, y.value);
+
+ if (z.nan.negative != 1
+ || z.nan.exponent != 0x22
+ || z.nan.quiet_nan != 0
+ || z.nan.mant_high != 0x1234
+ || z.nan.mant_low != 0xabcdef)
+ abort ();
+
+ return 0;
+}
/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mcpu=power9" } */
/* This test should succeed on both 32- and 64-bit configurations. */
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target lp64 } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target lp64 } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
--- /dev/null
+# Copyright (C) 2014-2016 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# Exit immediately if this isn't a PowerPC target.
+if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then {
+ return
+}
+
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+load_lib torture-options.exp
+
+# Initialize.
+dg-init
+
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c*]] "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_dd (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_lt_dd (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_td (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_lt_td (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_gt (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_gt (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_lt (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_dd (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_gt_dd (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_td (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_gt_td (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_gt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_eq (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_eq (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_dd (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_eq_dd (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_td (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_eq_td (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_eq_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_ov (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_ov (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_dd (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p)
+{
+ _Decimal64 source = *p;
+
+ if (__builtin_dfp_dtstsfi_ov_dd (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfi" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal64 *p, unsigned int significance)
+{
+ _Decimal64 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_td (5, source);
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power8" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
+
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_ov_td (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_ov_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p)
+{
+ _Decimal128 source = *p;
+
+ if (__builtin_dfp_dtstsfi_lt (63, source))
+ return 3;
+ else
+ return 5;
+}
+
+/* { dg-final { scan-assembler "dtstsfiq" } } */
+
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+int doTestBCDSignificance (_Decimal128 *p, unsigned int significance)
+{
+ _Decimal128 source = *p;
+
+ return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_float128_sw_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-O2 -mcpu=power7 -mfloat128" } */
+
+#ifndef NO_FLOAT
+typedef _Complex float float_complex;
+extern float_complex cfloat1 (void);
+extern float_complex cfloat2 (void);
+
+#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP)
+#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP)
+#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2)
+
+#else
+#define FLOAT_ARG(NAME, OP)
+#define FLOAT_PTR(NAME, OP)
+#define FLOAT_CALL()
+#endif
+
+#ifndef NO_DOUBLE
+typedef _Complex double double_complex;
+extern double_complex cdouble1 (void);
+extern double_complex cdouble2 (void);
+
+#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP)
+#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP)
+#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2)
+
+#else
+#define DOUBLE_ARG(NAME, OP)
+#define DOUBLE_PTR(NAME, OP)
+#define DOUBLE_CALL()
+#endif
+
+#ifndef NO_FLOAT128
+#ifdef __VSX__
+typedef _Complex float __attribute__((mode(KC))) float128_complex;
+#else
+typedef _Complex float __attribute__((mode(TC))) float128_complex;
+#endif
+
+extern float128_complex cfloat128_1 (void);
+extern float128_complex cfloat128_2 (void);
+
+#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP)
+#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP)
+#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2)
+
+#else
+#define FLOAT128_ARG(NAME, OP)
+#define FLOAT128_PTR(NAME, OP)
+#define FLOAT128_CALL()
+#endif
+
+#ifndef NO_LDOUBLE
+typedef _Complex long double ldouble_complex;
+extern ldouble_complex cldouble1 (void);
+extern ldouble_complex cldouble2 (void);
+
+#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP)
+#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP)
+#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2)
+
+#else
+#define LDOUBLE_ARG(NAME, OP)
+#define LDOUBLE_PTR(NAME, OP)
+#define LDOUBLE_CALL()
+#endif
+
+
+#define ARG_OP(SUFFIX, TYPE, NAME, OP) \
+TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \
+{ \
+ return a OP b; \
+}
+
+#define PTR_OP(SUFFIX, TYPE, NAME, OP) \
+void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \
+{ \
+ *p = *a OP *b; \
+}
+
+#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \
+TYPE call_ ## SUFFIX (void) \
+{ \
+ TYPE value1 = FUNC1 (); \
+ TYPE value2 = FUNC2 (); \
+ return value1 + value2; \
+}
+
+#ifndef NO_ARG
+#ifndef NO_ADD
+FLOAT_ARG (add, +)
+DOUBLE_ARG (add, +)
+FLOAT128_ARG (add, +)
+LDOUBLE_ARG (add, +)
+#endif
+
+#ifndef NO_SUB
+FLOAT_ARG (sub, -)
+DOUBLE_ARG (sub, -)
+FLOAT128_ARG (sub, -)
+LDOUBLE_ARG (sub, -)
+#endif
+
+#ifndef NO_MUL
+FLOAT_ARG (mul, *)
+DOUBLE_ARG (mul, *)
+FLOAT128_ARG (mul, *)
+LDOUBLE_ARG (mul, *)
+#endif
+
+#ifndef NO_DIV
+FLOAT_ARG (div, /)
+DOUBLE_ARG (div, /)
+FLOAT128_ARG (div, /)
+LDOUBLE_ARG (div, /)
+#endif
+#endif
+
+#ifndef NO_PTR
+#ifndef NO_ADD
+FLOAT_PTR (add, +)
+DOUBLE_PTR (add, +)
+FLOAT128_PTR (add, +)
+LDOUBLE_PTR (add, +)
+#endif
+
+#ifndef NO_SUB
+FLOAT_PTR (sub, -)
+DOUBLE_PTR (sub, -)
+FLOAT128_PTR (sub, -)
+LDOUBLE_PTR (sub, -)
+#endif
+
+#ifndef NO_MUL
+FLOAT_PTR (mul, *)
+DOUBLE_PTR (mul, *)
+FLOAT128_PTR (mul, *)
+LDOUBLE_PTR (mul, *)
+#endif
+
+#ifndef NO_DIV
+FLOAT_PTR (div, /)
+DOUBLE_PTR (div, /)
+FLOAT128_PTR (div, /)
+LDOUBLE_PTR (div, /)
+#endif
+#endif
+
+#ifndef NO_CALL
+FLOAT_CALL ()
+DOUBLE_CALL ()
+FLOAT128_CALL ()
+LDOUBLE_CALL ()
+#endif
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-O2 -mcpu=power9 -mfloat128 -mfloat128-hardware" } */
+
+#ifndef NO_FLOAT
+typedef _Complex float float_complex;
+extern float_complex cfloat1 (void);
+extern float_complex cfloat2 (void);
+
+#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP)
+#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP)
+#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2)
+
+#else
+#define FLOAT_ARG(NAME, OP)
+#define FLOAT_PTR(NAME, OP)
+#define FLOAT_CALL()
+#endif
+
+#ifndef NO_DOUBLE
+typedef _Complex double double_complex;
+extern double_complex cdouble1 (void);
+extern double_complex cdouble2 (void);
+
+#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP)
+#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP)
+#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2)
+
+#else
+#define DOUBLE_ARG(NAME, OP)
+#define DOUBLE_PTR(NAME, OP)
+#define DOUBLE_CALL()
+#endif
+
+#ifndef NO_FLOAT128
+#ifdef __VSX__
+typedef _Complex float __attribute__((mode(KC))) float128_complex;
+#else
+typedef _Complex float __attribute__((mode(TC))) float128_complex;
+#endif
+
+extern float128_complex cfloat128_1 (void);
+extern float128_complex cfloat128_2 (void);
+
+#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP)
+#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP)
+#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2)
+
+#else
+#define FLOAT128_ARG(NAME, OP)
+#define FLOAT128_PTR(NAME, OP)
+#define FLOAT128_CALL()
+#endif
+
+#ifndef NO_LDOUBLE
+typedef _Complex long double ldouble_complex;
+extern ldouble_complex cldouble1 (void);
+extern ldouble_complex cldouble2 (void);
+
+#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP)
+#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP)
+#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2)
+
+#else
+#define LDOUBLE_ARG(NAME, OP)
+#define LDOUBLE_PTR(NAME, OP)
+#define LDOUBLE_CALL()
+#endif
+
+
+#define ARG_OP(SUFFIX, TYPE, NAME, OP) \
+TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \
+{ \
+ return a OP b; \
+}
+
+#define PTR_OP(SUFFIX, TYPE, NAME, OP) \
+void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \
+{ \
+ *p = *a OP *b; \
+}
+
+#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \
+TYPE call_ ## SUFFIX (void) \
+{ \
+ TYPE value1 = FUNC1 (); \
+ TYPE value2 = FUNC2 (); \
+ return value1 + value2; \
+}
+
+#ifndef NO_ARG
+#ifndef NO_ADD
+FLOAT_ARG (add, +)
+DOUBLE_ARG (add, +)
+FLOAT128_ARG (add, +)
+LDOUBLE_ARG (add, +)
+#endif
+
+#ifndef NO_SUB
+FLOAT_ARG (sub, -)
+DOUBLE_ARG (sub, -)
+FLOAT128_ARG (sub, -)
+LDOUBLE_ARG (sub, -)
+#endif
+
+#ifndef NO_MUL
+FLOAT_ARG (mul, *)
+DOUBLE_ARG (mul, *)
+FLOAT128_ARG (mul, *)
+LDOUBLE_ARG (mul, *)
+#endif
+
+#ifndef NO_DIV
+FLOAT_ARG (div, /)
+DOUBLE_ARG (div, /)
+FLOAT128_ARG (div, /)
+LDOUBLE_ARG (div, /)
+#endif
+#endif
+
+#ifndef NO_PTR
+#ifndef NO_ADD
+FLOAT_PTR (add, +)
+DOUBLE_PTR (add, +)
+FLOAT128_PTR (add, +)
+LDOUBLE_PTR (add, +)
+#endif
+
+#ifndef NO_SUB
+FLOAT_PTR (sub, -)
+DOUBLE_PTR (sub, -)
+FLOAT128_PTR (sub, -)
+LDOUBLE_PTR (sub, -)
+#endif
+
+#ifndef NO_MUL
+FLOAT_PTR (mul, *)
+DOUBLE_PTR (mul, *)
+FLOAT128_PTR (mul, *)
+LDOUBLE_PTR (mul, *)
+#endif
+
+#ifndef NO_DIV
+FLOAT_PTR (div, /)
+DOUBLE_PTR (div, /)
+FLOAT128_PTR (div, /)
+LDOUBLE_PTR (div, /)
+#endif
+#endif
+
+#ifndef NO_CALL
+FLOAT_CALL ()
+DOUBLE_CALL ()
+FLOAT128_CALL ()
+LDOUBLE_CALL ()
+#endif
+
+/* { dg-final { scan-assembler "xsaddqp" } } */
+/* { dg-final { scan-assembler "xssubqp" } } */
--- /dev/null
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
+/* { dg-options "-mfloat128 -mvsx" } */
+
+void abort ();
+
+typedef unsigned long long int uint64_t;
+
+typedef union
+{
+ __float128 value;
+
+ struct
+ {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ unsigned negative:1;
+ unsigned exponent:15;
+ unsigned quiet_nan:1;
+ uint64_t mant_high:47;
+ uint64_t mant_low:64;
+#else
+ uint64_t mant_low:64;
+ uint64_t mant_high:47;
+ unsigned quiet_nan:1;
+ unsigned exponent:15;
+ unsigned negative:1;
+#endif
+ } nan;
+
+} ieee854_float128;
+
+int
+main (int argc, int *argv[])
+{
+ ieee854_float128 y;
+
+ y.value = __builtin_infq ();
+
+ if (y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 0
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 0)
+ abort ();
+
+ y.value = __builtin_huge_valq ();
+
+ if (y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 0
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 0)
+ abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
+/* { dg-options "-mfloat128 -mvsx" } */
+
+#include <stdio.h>
+
+void abort ();
+
+typedef unsigned long long int uint64_t;
+
+typedef union
+{
+ __float128 value;
+
+ struct
+ {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ unsigned negative:1;
+ unsigned exponent:15;
+ unsigned quiet_nan:1;
+ uint64_t mant_high:47;
+ uint64_t mant_low:64;
+#else
+ uint64_t mant_low:64;
+ uint64_t mant_high:47;
+ unsigned quiet_nan:1;
+ unsigned exponent:15;
+ unsigned negative:1;
+#endif
+ } nan;
+
+} ieee854_float128;
+
+int
+main (int argc, int *argv[])
+{
+ ieee854_float128 y;
+
+ y.value = __builtin_nanq ("1");
+
+ if (y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 1
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 1)
+ abort ();
+
+ y.value = __builtin_nanq ("0x2ab3c");
+
+ if (y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 1
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 0x2ab3c)
+ abort ();
+
+ y.value = __builtin_nansq ("1");
+
+ if (
+ y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 0
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 1
+ )
+ abort ();
+
+ y.value = __builtin_nansq ("0x2ab3c");
+
+ if (y.nan.negative != 0
+ || y.nan.exponent != 0x7fff
+ || y.nan.quiet_nan != 0
+ || y.nan.mant_high != 0
+ || y.nan.mant_low != 0x2ab3c)
+ abort ();
+
+ return 0;
+}
/* { dg-do compile { target { powerpc64le-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O3" } */
+/* { dg-options "-mcpu=power9 -O3 -mfloat128" } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-final { scan-assembler "lxvx" } } */
/* { dg-final { scan-assembler "stxvx" } } */
--- /dev/null
+/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */
+
+typedef __attribute__((altivec(vector__))) int type_t;
+type_t
+func (type_t *src)
+{
+ asm volatile ("# force the base reg on the load below to be spilled"
+ : /* no outputs */
+ : /* no inputs */
+ : "r0", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
+ return src[1];
+}
+
--- /dev/null
+/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */
+
+typedef double vec[3];
+struct vec_t
+{
+ vec x;
+ vec y;
+};
+int a, j, k, l, m, n, o, p, q;
+double b, i;
+vec c;
+double h[6];
+void func1 (vec);
+
+void
+func2 (double *b)
+{
+ for (; k; k--)
+ for (; j <= k;)
+ for (; m <= q; m++)
+ for (; n <= k; n++)
+ for (; o <= l; o++)
+ {
+ j = p + m + n + o;
+ h[j] = i;
+ }
+}
+
+void
+func3 (void)
+{
+ struct vec_t d;
+ func1 (d.y);
+ func2 (&b);
+ for (; a;)
+ {
+ double *e = d.y, *g;
+ double f;
+ c[0] = g[0] + f * e[0];
+ c[1] = g[1] + f * e[1];
+ func1 (c);
+ }
+}
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O1" } */
+
+volatile int a;
+int b;
+void fn1(void) { b + (long)b || a; }
--- /dev/null
+/* Test for a reload ICE arising from trying to direct move a TDmode value. */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target dfp } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */
+
+extern void testvad128 (int n, ...);
+void
+testitd128 (_Decimal128 g01d128)
+{
+ testvad128 (1, g01d128);
+}
--- /dev/null
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */
+
+vector float
+splat_v4sf (float f)
+{
+ return (vector float) { f, f, f, f };
+}
+
+/* { dg-final { scan-assembler "xscvdpspn " } } */
+/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned int
+doAbsoluteDifferenceUnsignedInt (__vector unsigned int *p,
+ __vector unsigned int *q)
+{
+ __vector unsigned int source_1, source_2;
+ __vector unsigned int result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = __builtin_vec_vadu (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduw" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned int
+doAbsoluteDifferenceUnsignedIntMacro (__vector unsigned int *p,
+ __vector unsigned int *q)
+{
+ __vector unsigned int result, source_1, source_2;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = vec_absd (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduw" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned short
+doAbsoluteDifferenceUnsignedShort (__vector unsigned short *p,
+ __vector unsigned short *q)
+{
+ __vector unsigned short source_1, source_2;
+ __vector unsigned short result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = __builtin_vec_vadu (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduh" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned short
+doAbsoluteDifferenceUnsignedShortMacro (__vector unsigned short *p,
+ __vector unsigned short *q)
+{
+ __vector unsigned short result, source_1, source_2;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = vec_absd (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduh" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned char
+doAbsoluteDifferenceUnsignedChar (__vector unsigned char *p,
+ __vector unsigned char *q)
+{
+ __vector unsigned char source_1, source_2;
+ __vector unsigned char result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = __builtin_vec_vadu (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsdub" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned char
+doAbsoluteDifferenceUnsignedCharMacro (__vector unsigned char *p,
+ __vector unsigned char *q)
+{
+ __vector unsigned char result, source_1, source_2;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = vec_absd (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsdub" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned char
+doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
+ __vector unsigned char *q)
+{
+ __vector unsigned char source_1, source_2;
+ __vector unsigned char uc_result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ uc_result = __builtin_vec_vadub (source_1, source_2);
+ return uc_result;
+}
+
+/* { dg-final { scan-assembler "vabsdub" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned char
+doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
+ __vector unsigned char *q)
+{
+ __vector unsigned char source_1, source_2;
+ __vector unsigned char uc_result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ uc_result = vec_absdb (source_1, source_2);
+ return uc_result;
+}
+
+/* { dg-final { scan-assembler "vabsdub" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned short
+doAbsoluteDifferenceUnsigned (__vector unsigned short *p,
+ __vector unsigned short *q)
+{
+ __vector unsigned short source_1, source_2;
+ __vector unsigned short us_result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ us_result = __builtin_vec_vaduh (source_1, source_2);
+ return us_result;
+}
+
+/* { dg-final { scan-assembler "vabsduh" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned short
+doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p,
+ __vector unsigned short *q)
+{
+ __vector unsigned short result, source_1, source_2;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = vec_absdh (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduh" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned int
+doAbsoluteDifferenceUnsigned (__vector unsigned int *p,
+ __vector unsigned int *q)
+{
+ __vector unsigned int source_1, source_2;
+ __vector unsigned int ui_result;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ ui_result = __builtin_vec_vaduw (source_1, source_2);
+ return ui_result;
+}
+
+/* { dg-final { scan-assembler "vabsduw" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
+#include <altivec.h>
+
+__vector unsigned int
+doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p,
+ __vector unsigned int *q)
+{
+ __vector unsigned int result, source_1, source_2;
+
+ source_1 = *p;
+ source_2 = *q;
+
+ result = vec_absdw (source_1, source_2);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vabsduw" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+__vector unsigned char
+doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
+{
+ __vector unsigned char result, input, shift_distance;
+ result = __builtin_vec_vslv (input, shift_distance);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vslv" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+__vector unsigned char
+doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
+{
+ __vector unsigned char result, input, shift_distance;
+ result = vec_slv (input, shift_distance);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vslv" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+__vector unsigned char
+doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
+{
+ __vector unsigned char result, input, shift_distance;
+ result = __builtin_vec_vsrv (input, shift_distance);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vsrv" } } */
--- /dev/null
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
+__vector unsigned char
+doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
+{
+ __vector unsigned char result, input, shift_distance;
+ result = vec_srv (input, shift_distance);
+ return result;
+}
+
+/* { dg-final { scan-assembler "vsrv" } } */
/* { dg-do compile { target { powerpc64le*-*-* } } } */
/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O0" } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
/* { dg-final { scan-assembler-times "lxvd2x" 6 } } */
/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */
/* { dg-final { scan-assembler-times "lxvh8x" 4 } } */
/* { dg-do compile { target { powerpc64-*-* } } } */
/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O0" } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
/* { dg-final { scan-assembler-times "lxvx" 40 } } */
/* { dg-final { scan-assembler-times "stxvx" 40 } } */
--- /dev/null
+! { dg-do compile }
+! PR 71783 - this used to ICE due to a missing charlen for the temporary.
+! Test case by Toon Moene.
+
+SUBROUTINE prtdata(ilen)
+ INTEGER :: ilen
+ character(len=ilen), allocatable :: cline(:)
+ allocate(cline(2))
+ cline(1) = 'a'
+ cline(2) = cline(1)
+END SUBROUTINE prtdata
end do
!$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" }
+ !$acc parallel copyin (a(1:N)) copy (b(1:N)) waitasync ! { dg-error "Unclassifiable OpenACC directive" }
+ do i = 1, N
+ b(i) = a(i)
+ end do
+ !$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" }
+
+ !$acc parallel copyin (a(1:N)) copy (b(1:N)) asyncwait ! { dg-error "Unclassifiable OpenACC directive" }
+ do i = 1, N
+ b(i) = a(i)
+ end do
+ !$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" }
+
!$acc parallel copyin (a(1:N)) copy (b(1:N)) wait
do i = 1, N
b(i) = a(i)
a(:) = 3.0
b(:) = 0.0
- !$acc wait (1 2) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (1 2) ! { dg-error "Syntax error in OpenACC expression list at" }
- !$acc wait (1,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (1,) ! { dg-error "Syntax error in OpenACC expression list at" }
- !$acc wait (,1) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (,1) ! { dg-error "Syntax error in OpenACC expression list at" }
- !$acc wait (1, 2, ) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (1, 2, ) ! { dg-error "Syntax error in OpenACC expression list at" }
- !$acc wait (1, 2, ,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (1, 2, ,) ! { dg-error "Syntax error in OpenACC expression list at" }
- !$acc wait (1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait (1 ! { dg-error "Syntax error in OpenACC expression list at" }
!$acc wait (1, *) ! { dg-error "Invalid argument to \\\$\\\!ACC WAIT" }
!$acc wait (1.0) ! { dg-error "WAIT clause at \\\(1\\\) requires a scalar INTEGER expression" }
- !$acc wait 1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait 1 ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait N ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait N ! { dg-error "Unclassifiable OpenACC directive" }
!$acc wait (1)
end program asyncwait
a(:) = 3.0
b(:) = 0.0
- !$acc wait async (1 2) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1 2) ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (1,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1,) ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (,1) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (,1) ! { dg-error "Invalid character in name" }
- !$acc wait async (1, 2, ) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1, 2, ) ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (1, 2, ,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1, 2, ,) ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1 ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (1, *) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1, *) ! { dg-error "Unclassifiable OpenACC directive" }
- !$acc wait async (1, a) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async (1, a) ! { dg-error "Unclassifiable OpenACC directive" }
!$acc wait async (a) ! { dg-error "ASYNC clause at \\\(1\\\) requires a scalar INTEGER expression" }
!$acc wait async (1.0) ! { dg-error "ASYNC clause at \\\(1\\\) requires a scalar INTEGER expression" }
- !$acc wait async 1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" }
+ !$acc wait async 1 ! { dg-error "Unclassifiable OpenACC directive" }
+
+ !$acc waitasync ! { dg-error "Unclassifiable OpenACC directive" }
+
+ !$acc wait,async ! { dg-error "Unclassifiable OpenACC directive" }
end program asyncwait
--- /dev/null
+! PR fortran/71704
+! { dg-do compile }
+
+real function f1 ()
+!$acc routine (f1)
+ f1 = 1
+end
+
+real function f2 (a)
+ integer a
+ !$acc enter data copyin(a)
+ f2 = 1
+end
+
+real function f3 (a)
+ integer a
+!$acc enter data copyin(a)
+ f3 = 1
+end
+
+real function f4 ()
+!$acc wait
+ f4 = 1
+end
+
+real function f5 (a)
+ integer a
+!$acc update device(a)
+ f5 = 1
+end
+
+real function f6 ()
+!$acc parallel
+!$acc end parallel
+ f6 = 1
+end
+
+real function f7 ()
+!$acc kernels
+!$acc end kernels
+ f7 = 1
+end
+
+real function f8 ()
+!$acc data
+!$acc end data
+ f8 = 1
+end
+
+real function f9 ()
+!$acc host_data
+!$acc end host_data
+ f8 = 1
+end
+
+real function f10 (a)
+ integer a
+!$acc declare present (a)
+ f8 = 1
+end
--- /dev/null
+! PR fortran/71687
+! { dg-do compile }
+! { dg-additional-options "-fstack-arrays -O2" }
+
+subroutine s (n, x)
+ integer :: n
+ real :: x(n)
+!$omp parallel
+ x(1:n) = x(n:1:-1)
+!$omp end parallel
+end
--- /dev/null
+! PR fortran/71704
+! { dg-do compile }
+
+real function f0 ()
+!$omp declare simd (f0)
+ f0 = 1
+end
+
+real function f1 ()
+!$omp declare target (f1)
+ f1 = 1
+end
+
+real function f2 ()
+!$omp declare reduction (foo : integer : omp_out = omp_out + omp_in) &
+!$omp & initializer (omp_priv = 0)
+ f2 = 1
+end
+
+real function f3 ()
+ real, save :: t
+!$omp threadprivate (t)
+ f3 = 1
+end
+
+real function f4 ()
+!$omp taskwait
+ f4 = 1
+end
+
+real function f5 ()
+!$omp barrier
+ f5 = 1
+end
+
+real function f6 ()
+!$omp parallel
+!$omp end parallel
+ f6 = 1
+end
+
+real function f7 ()
+!$omp single
+!$omp end single
+ f7 = 1
+end
+
+real function f8 ()
+!$omp critical
+!$omp end critical
+ f8 = 1
+end
+
+real function f9 ()
+!$omp critical
+!$omp end critical
+ f9 = 1
+end
--- /dev/null
+! PR fortran/71705
+! { dg-do compile }
+
+ real :: x
+ x = 0.0
+ !$omp target update to(x)
+end
--- /dev/null
+! { dg-do run }
+!
+! Test the fix for PR70673
+!
+! Contributed by David Kinniburgh <davidgkinniburgh@yahoo.co.uk>
+!
+module m
+contains
+ subroutine s(inp)
+ character(*), intent(in) :: inp
+ character(:), allocatable :: a
+ a = a ! This used to ICE.
+ a = inp
+ a = a ! This used to ICE too
+ if ((len (a) .ne. 5) .or. (a .ne. "hello")) call abort
+ a = a(2:3) ! Make sure that temporary creation is not broken.
+ if ((len (a) .ne. 2) .or. (a .ne. "el")) call abort
+ deallocate (a)
+ a = a ! This would ICE too.
+ end subroutine s
+end module m
+
+ use m
+ call s("hello")
+end
float dummy = 1.0q;
} "$opts"]
}
+
+# Return 1 if the target supports __float128,
+# 0 otherwise.
+
+proc check_effective_target___float128 { } {
+ if { [istarget powerpc*-*-*] } {
+ return [check_ppc_float128_sw_available]
+ }
+ if { [istarget ia64-*-*]
+ || [istarget i?86-*-*]
+ || [istarget x86_64-*-*] } {
+ return 1
+ }
+ return 0
+}
+
+proc add_options_for___float128 { flags } {
+ if { [istarget powerpc*-*-*] } {
+ return "$flags -mfloat128 -mvsx"
+ }
+ return "$flags"
+}
+
+# Return 1 if the target supports any special run-time requirements
+# for __float128 or _Float128,
+# 0 otherwise.
+
+proc check_effective_target_base_quadfloat_support { } {
+ if { [istarget powerpc*-*-*] } {
+ return [check_vsx_hw_available]
+ }
+ return 1
+}
+
# Return 1 if the target supports compiling fixed-point,
# 0 otherwise.
}
}
+/* Return true if STMT is a call to a builtin function with the right
+ arguments and attributes that should be considered for optimization
+ by this pass. */
+
+static bool
+valid_builtin_call (gimple *stmt)
+{
+ if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
+ return false;
+
+ tree callee = gimple_call_fndecl (stmt);
+ switch (DECL_FUNCTION_CODE (callee))
+ {
+ case BUILT_IN_MEMCMP:
+ case BUILT_IN_STRCHR:
+ case BUILT_IN_STRCHR_CHKP:
+ case BUILT_IN_STRLEN:
+ case BUILT_IN_STRLEN_CHKP:
+ /* The above functions should be pure. Punt if they aren't. */
+ if (gimple_vdef (stmt) || gimple_vuse (stmt) == NULL_TREE)
+ return false;
+ break;
+
+ case BUILT_IN_CALLOC:
+ case BUILT_IN_MALLOC:
+ case BUILT_IN_MEMCPY:
+ case BUILT_IN_MEMCPY_CHK:
+ case BUILT_IN_MEMCPY_CHKP:
+ case BUILT_IN_MEMCPY_CHK_CHKP:
+ case BUILT_IN_MEMPCPY:
+ case BUILT_IN_MEMPCPY_CHK:
+ case BUILT_IN_MEMPCPY_CHKP:
+ case BUILT_IN_MEMPCPY_CHK_CHKP:
+ case BUILT_IN_MEMSET:
+ case BUILT_IN_STPCPY:
+ case BUILT_IN_STPCPY_CHK:
+ case BUILT_IN_STPCPY_CHKP:
+ case BUILT_IN_STPCPY_CHK_CHKP:
+ case BUILT_IN_STRCAT:
+ case BUILT_IN_STRCAT_CHK:
+ case BUILT_IN_STRCAT_CHKP:
+ case BUILT_IN_STRCAT_CHK_CHKP:
+ case BUILT_IN_STRCPY:
+ case BUILT_IN_STRCPY_CHK:
+ case BUILT_IN_STRCPY_CHKP:
+ case BUILT_IN_STRCPY_CHK_CHKP:
+ /* The above functions should be neither const nor pure. Punt if they
+ aren't. */
+ if (gimple_vdef (stmt) == NULL_TREE || gimple_vuse (stmt) == NULL_TREE)
+ return false;
+ break;
+
+ default:
+ break;
+ }
+
+ return true;
+}
+
/* If the last .MEM setter statement before STMT is
memcpy (x, y, strlen (y) + 1), the only .MEM use of it is STMT
and STMT is known to overwrite x[strlen (x)], adjust the last memcpy to
return;
}
- if (!gimple_call_builtin_p (last.stmt, BUILT_IN_NORMAL))
+ if (!valid_builtin_call (last.stmt))
return;
callee = gimple_call_fndecl (last.stmt);
if (!stmt1 || !is_gimple_call (stmt1))
return true;
tree callee1 = gimple_call_fndecl (stmt1);
- if (!gimple_call_builtin_p (stmt1, BUILT_IN_NORMAL))
+ if (!valid_builtin_call (stmt1))
return true;
enum built_in_function code1 = DECL_FUNCTION_CODE (callee1);
tree size = gimple_call_arg (stmt2, 2);
if (is_gimple_call (stmt))
{
tree callee = gimple_call_fndecl (stmt);
- if (gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
+ if (valid_builtin_call (stmt))
switch (DECL_FUNCTION_CODE (callee))
{
case BUILT_IN_STRLEN:
if (!has_undefined_value_p (t))
return;
+ /* Anonymous SSA_NAMEs shouldn't be uninitialized, but ssa_undefined_value_p
+ can return true if the def stmt of anonymous SSA_NAME is COMPLEX_EXPR
+ created for conversion from scalar to complex. Use the underlying var of
+ the COMPLEX_EXPRs real part in that case. See PR71581. */
+ if (expr == NULL_TREE
+ && var == NULL_TREE
+ && SSA_NAME_VAR (t) == NULL_TREE
+ && is_gimple_assign (SSA_NAME_DEF_STMT (t))
+ && gimple_assign_rhs_code (SSA_NAME_DEF_STMT (t)) == COMPLEX_EXPR)
+ {
+ tree v = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (t));
+ if (TREE_CODE (v) == SSA_NAME
+ && has_undefined_value_p (v)
+ && zerop (gimple_assign_rhs2 (SSA_NAME_DEF_STMT (t))))
+ {
+ expr = SSA_NAME_VAR (v);
+ var = expr;
+ }
+ }
+
+ if (expr == NULL_TREE)
+ return;
+
/* TREE_NO_WARNING either means we already warned, or the front end
wishes to suppress the warning. */
if ((context
tree decl = TREE_OPERAND (TREE_OPERAND (lhs, 0), 0);
if (DECL_P (decl)
&& DECL_SIZE (decl) == TYPE_SIZE (TREE_TYPE (lhs))
+ /* If the dynamic type of the decl has larger precision than
+ the decl itself we can't use the decls type for SSA rewriting. */
+ && ((! INTEGRAL_TYPE_P (TREE_TYPE (decl))
+ || compare_tree_int (DECL_SIZE (decl),
+ TYPE_PRECISION (TREE_TYPE (decl))) == 0)
+ || (INTEGRAL_TYPE_P (TREE_TYPE (lhs))
+ && (TYPE_PRECISION (TREE_TYPE (decl))
+ >= TYPE_PRECISION (TREE_TYPE (lhs)))))
+ /* Make sure we are not re-writing non-float copying into float
+ copying as that can incur normalization. */
+ && (! FLOAT_TYPE_P (TREE_TYPE (decl))
+ || types_compatible_p (TREE_TYPE (lhs), TREE_TYPE (decl)))
&& (TREE_THIS_VOLATILE (decl) == TREE_THIS_VOLATILE (lhs)))
return false;
}
gimple *init_stmt;
tree new_temp;
- if (TREE_CODE (type) == VECTOR_TYPE
- && TREE_CODE (TREE_TYPE (val)) != VECTOR_TYPE)
+ /* We abuse this function to push sth to a SSA name with initial 'val'. */
+ if (! useless_type_conversion_p (type, TREE_TYPE (val)))
{
- if (!types_compatible_p (TREE_TYPE (type), TREE_TYPE (val)))
+ gcc_assert (TREE_CODE (type) == VECTOR_TYPE);
+ if (! types_compatible_p (TREE_TYPE (type), TREE_TYPE (val)))
{
/* Scalar boolean value should be transformed into
all zeros or all ones value before building a vector. */
else
{
new_temp = make_ssa_name (TREE_TYPE (type));
- init_stmt = gimple_build_assign (new_temp, NOP_EXPR, val);
+ if (! INTEGRAL_TYPE_P (TREE_TYPE (val)))
+ init_stmt = gimple_build_assign (new_temp,
+ fold_build1 (VIEW_CONVERT_EXPR,
+ TREE_TYPE (type),
+ val));
+ else
+ init_stmt = gimple_build_assign (new_temp, NOP_EXPR, val);
vect_init_vector_1 (stmt, init_stmt, gsi);
val = new_temp;
}
and divisor are available. */
if (vr1.type == VR_RANGE
&& !symbolic_range_p (&vr0)
- && !symbolic_range_p (&vr1))
+ && !symbolic_range_p (&vr1)
+ && compare_values (vr1.max, zero) != 0)
min = int_const_binop (code, vr0.min, vr1.max);
else
min = zero;
&& TREE_CODE (TREE_VALUE (attr2)) == TREE_LIST)
{
/* Handle attribute format. */
- if (is_attribute_p ("format", TREE_PURPOSE (attr1)))
+ if (is_attribute_p ("format", get_attribute_name (attr1)))
{
attr1 = TREE_VALUE (attr1);
attr2 = TREE_VALUE (attr2);
+2016-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-07-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/71717
+ * testsuite/libgomp.fortran/associate3.f90: New test.
+
+2016-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2016-06-17 Jakub Jelinek <jakub@redhat.com>
+
+ * testsuite/libgomp.c++/target-21.C: New test.
+
+ 2016-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ * testsuite/libgomp.c++/target-20.C: New test.
+
2016-06-10 Thomas Schwinge <thomas@codesourcery.com>
PR middle-end/71373
--- /dev/null
+extern "C" void abort ();
+struct S { int a, b, c, d; };
+
+void
+foo (S &s)
+{
+ int err;
+ #pragma omp target map (s.b, s.d) map (from: err)
+ {
+ err = s.b != 21 || s.d != 24;
+ s.b++; s.d++;
+ }
+ if (err || s.b != 22 || s.d != 25)
+ abort ();
+ #pragma omp target data map (s.b, s.d)
+ {
+ #pragma omp target map (alloc: s.b, s.d) map (from: err)
+ {
+ err = s.b != 22 || s.d != 25;
+ s.b++; s.d++;
+ }
+ }
+ if (err || s.b != 23 || s.d != 26)
+ abort ();
+ #pragma omp target data map (s)
+ {
+ #pragma omp target map (alloc: s.b, s.d) map (from: err)
+ {
+ err = s.b != 23 || s.d != 26;
+ s.b++; s.d++;
+ }
+ }
+ if (err || s.b != 24 || s.d != 27)
+ abort ();
+}
+
+template <typename T, typename U>
+void
+bar (S &s, T &t, U u)
+{
+ int err;
+ #pragma omp target map (s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
+ {
+ err = s.b != 21 || s.d != 24 || t.b != 73 || t.d != 82 || u.b != 31 || u.d != 37;
+ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
+ }
+ if (err || s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38)
+ abort ();
+ #pragma omp target data map (s.b, s.d, t.b, t.d, u.b, u.d)
+ {
+ #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
+ {
+ err = s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38;
+ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
+ }
+ }
+ if (err || s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39)
+ abort ();
+ #pragma omp target data map (s, t, u)
+ {
+ #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
+ {
+ err = s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39;
+ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
+ }
+ }
+ if (err || s.b != 24 || s.d != 27 || t.b != 76 || t.d != 85 || u.b != 34 || u.d != 40)
+ abort ();
+}
+
+int
+main ()
+{
+ S s = { 1, 21, 2, 24 };
+ foo (s);
+ S s2 = { 3, 21, 4, 24 };
+ S t = { 5, 73, 6, 82 };
+ S u = { 7, 31, 8, 37 };
+ bar <S, S &> (s2, t, u);
+}
--- /dev/null
+extern "C" void abort ();
+struct T { char t[270]; };
+struct S { int (&x)[10]; int *&y; T t; int &z; S (); ~S (); };
+
+template <int N>
+void
+foo (S s)
+{
+ int err;
+ #pragma omp target map (s.x[0:N], s.y[0:N]) map (s.t.t[16:3]) map (from: err)
+ {
+ err = s.x[2] != 28 || s.y[2] != 37 || s.t.t[17] != 81;
+ s.x[2]++;
+ s.y[2]++;
+ s.t.t[17]++;
+ }
+ if (err || s.x[2] != 29 || s.y[2] != 38 || s.t.t[17] != 82)
+ abort ();
+}
+
+template <int N>
+void
+bar (S s)
+{
+ int err;
+ #pragma omp target map (s.x, s.z)map(from:err)
+ {
+ err = s.x[2] != 29 || s.z != 6;
+ s.x[2]++;
+ s.z++;
+ }
+ if (err || s.x[2] != 30 || s.z != 7)
+ abort ();
+}
+
+template <int N>
+void
+foo2 (S &s)
+{
+ int err;
+ #pragma omp target map (s.x[N:10], s.y[N:10]) map (from: err) map (s.t.t[N+16:N+3])
+ {
+ err = s.x[2] != 30 || s.y[2] != 38 || s.t.t[17] != 81;
+ s.x[2]++;
+ s.y[2]++;
+ s.t.t[17]++;
+ }
+ if (err || s.x[2] != 31 || s.y[2] != 39 || s.t.t[17] != 82)
+ abort ();
+}
+
+template <int N>
+void
+bar2 (S &s)
+{
+ int err;
+ #pragma omp target map (s.x, s.z)map(from:err)
+ {
+ err = s.x[2] != 31 || s.z != 7;
+ s.x[2]++;
+ s.z++;
+ }
+ if (err || s.x[2] != 32 || s.z != 8)
+ abort ();
+}
+
+template <typename U>
+void
+foo3 (U s)
+{
+ int err;
+ #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3])
+ {
+ err = s.x[2] != 32 || s.y[2] != 39 || s.t.t[17] != 82;
+ s.x[2]++;
+ s.y[2]++;
+ s.t.t[17]++;
+ }
+ if (err || s.x[2] != 33 || s.y[2] != 40 || s.t.t[17] != 83)
+ abort ();
+}
+
+template <typename U>
+void
+bar3 (U s)
+{
+ int err;
+ #pragma omp target map (s.x, s.z)map(from:err)
+ {
+ err = s.x[2] != 33 || s.z != 8;
+ s.x[2]++;
+ s.z++;
+ }
+ if (err || s.x[2] != 34 || s.z != 9)
+ abort ();
+}
+
+template <typename U>
+void
+foo4 (U &s)
+{
+ int err;
+ #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3])
+ {
+ err = s.x[2] != 34 || s.y[2] != 40 || s.t.t[17] != 82;
+ s.x[2]++;
+ s.y[2]++;
+ s.t.t[17]++;
+ }
+ if (err || s.x[2] != 35 || s.y[2] != 41 || s.t.t[17] != 83)
+ abort ();
+}
+
+template <typename U>
+void
+bar4 (U &s)
+{
+ int err;
+ #pragma omp target map (s.x, s.z)map(from:err)
+ {
+ err = s.x[2] != 35 || s.z != 9;
+ s.x[2]++;
+ s.z++;
+ }
+ if (err || s.x[2] != 36 || s.z != 10)
+ abort ();
+}
+
+int xt[10] = { 1, 2, 28, 3, 4, 5, 6, 7, 8, 9 };
+int yt[10] = { 1, 2, 37, 3, 4, 5, 6, 7, 8, 9 };
+int *yp = yt;
+int zt = 6;
+
+S::S () : x (xt), y (yp), z (zt)
+{
+}
+
+S::~S ()
+{
+}
+
+int
+main ()
+{
+ S s;
+ s.t.t[16] = 5;
+ s.t.t[17] = 81;
+ s.t.t[18] = 9;
+ foo <10> (s);
+ if (s.t.t[17] != 81)
+ abort ();
+ bar <7> (s);
+ foo2 <0> (s);
+ if (s.t.t[17] != 82)
+ abort ();
+ bar2 <21> (s);
+ foo3 <S> (s);
+ if (s.t.t[17] != 82)
+ abort ();
+ bar3 <S> (s);
+ foo4 <S> (s);
+ if (s.t.t[17] != 83)
+ abort ();
+ bar4 <S> (s);
+ s.x[2] -= 4;
+ s.y[2] -= 2;
+ s.z -= 2;
+ s.t.t[17]--;
+ foo3 <S &> (s);
+ if (s.t.t[17] != 83)
+ abort ();
+ bar3 <S &> (s);
+}
--- /dev/null
+! PR fortran/71717
+! { dg-do run }
+
+ type t
+ real, allocatable :: f(:)
+ end type
+ type (t) :: v
+ integer :: i, j
+ allocate (v%f(4))
+ v%f = 19.
+ i = 5
+ associate (u => v, k => i)
+ !$omp parallel do
+ do j = 1, 4
+ u%f(j) = 21.
+ if (j.eq.1) k = 7
+ end do
+ end associate
+ if (any (v%f(:).ne.21.) .or. i.ne.7) call abort
+end
+2016-07-06 Ville Voutilainen <ville.voutilainen@gmail.com>
+
+ Implement LWG 2451, optional<T> should 'forward' T's
+ implicit conversions.
+ * include/experimental/optional (__is_optional_impl, __is_optional):
+ New.
+ (optional()): Make constexpr and default.
+ (optional(_Up&&), optional(const optional<_Up>&),
+ optional(optional<_Up>&& __t): New.
+ (operator=(_Up&&)): Constrain.
+ (operator=(const optional<_Up>&), operator=(optional<_Up>&&)): New.
+ * testsuite/experimental/optional/cons/value.cc:
+ Add tests for the functionality added by LWG 2451.
+ * testsuite/experimental/optional/cons/value_neg.cc: New.
+
+2016-07-05 Ville Voutilainen <ville.voutilainen@gmail.com>
+
+ Implement LWG 2509,
+ any_cast doesn't work with rvalue reference targets and cannot
+ move with a value target.
+ * include/experimental/any (any(_ValueType&&)): Constrain and
+ add an overload that doesn't forward.
+ (any_cast(any&&)): Constrain and add an overload that moves.
+ * testsuite/experimental/any/misc/any_cast.cc: Add tests for
+ the functionality added by LWG 2509.
+
+2016-07-04 Ville Voutilainen <ville.voutilainen@gmail.com>
+
+ PR libstdc++/71313
+ * src/filesystem/ops.cc (remove_all(const path&, error_code&)):
+ Call remove_all for children of a directory.
+ * testsuite/experimental/filesystem/operations/create_directories.cc:
+ Adjust.
+
+2016-06-17 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/71545
+ * include/bits/stl_algobase.h (lower_bound, lexicographical_compare):
+ Remove irreflexive checks.
+ * include/bits/stl_algo.h (lower_bound, upper_bound, equal_range,
+ binary_search): Likewise.
+ * testsuite/25_algorithms/equal_range/partitioned.cc: New test.
+ * testsuite/25_algorithms/lexicographical_compare/71545.cc: New test.
+ * testsuite/25_algorithms/lower_bound/partitioned.cc: New test.
+ * testsuite/25_algorithms/upper_bound/partitioned.cc: New test.
+ * testsuite/util/testsuite_iterators.h (__gnu_test::test_container):
+ Add constructor from array.
+
2016-05-26 Jonathan Wakely <jwakely@redhat.com>
Backport from mainline
typename iterator_traits<_ForwardIterator>::value_type, _Tp>)
__glibcxx_requires_partitioned_lower_pred(__first, __last,
__val, __comp);
- __glibcxx_requires_irreflexive_pred2(__first, __last, __comp);
return std::__lower_bound(__first, __last, __val,
__gnu_cxx::__ops::__iter_comp_val(__comp));
__glibcxx_function_requires(_LessThanOpConcept<
_Tp, typename iterator_traits<_ForwardIterator>::value_type>)
__glibcxx_requires_partitioned_upper(__first, __last, __val);
- __glibcxx_requires_irreflexive2(__first, __last);
return std::__upper_bound(__first, __last, __val,
__gnu_cxx::__ops::__val_less_iter());
_Tp, typename iterator_traits<_ForwardIterator>::value_type>)
__glibcxx_requires_partitioned_upper_pred(__first, __last,
__val, __comp);
- __glibcxx_requires_irreflexive_pred2(__first, __last, __comp);
return std::__upper_bound(__first, __last, __val,
__gnu_cxx::__ops::__val_comp_iter(__comp));
_Tp, typename iterator_traits<_ForwardIterator>::value_type>)
__glibcxx_requires_partitioned_lower(__first, __last, __val);
__glibcxx_requires_partitioned_upper(__first, __last, __val);
- __glibcxx_requires_irreflexive2(__first, __last);
return std::__equal_range(__first, __last, __val,
__gnu_cxx::__ops::__iter_less_val(),
__val, __comp);
__glibcxx_requires_partitioned_upper_pred(__first, __last,
__val, __comp);
- __glibcxx_requires_irreflexive_pred2(__first, __last, __comp);
return std::__equal_range(__first, __last, __val,
__gnu_cxx::__ops::__iter_comp_val(__comp),
_Tp, typename iterator_traits<_ForwardIterator>::value_type>)
__glibcxx_requires_partitioned_lower(__first, __last, __val);
__glibcxx_requires_partitioned_upper(__first, __last, __val);
- __glibcxx_requires_irreflexive2(__first, __last);
_ForwardIterator __i
= std::__lower_bound(__first, __last, __val,
__val, __comp);
__glibcxx_requires_partitioned_upper_pred(__first, __last,
__val, __comp);
- __glibcxx_requires_irreflexive_pred2(__first, __last, __comp);
_ForwardIterator __i
= std::__lower_bound(__first, __last, __val,
__glibcxx_function_requires(_LessThanOpConcept<
typename iterator_traits<_ForwardIterator>::value_type, _Tp>)
__glibcxx_requires_partitioned_lower(__first, __last, __val);
- __glibcxx_requires_irreflexive2(__first, __last);
return std::__lower_bound(__first, __last, __val,
__gnu_cxx::__ops::__iter_less_val());
__glibcxx_function_requires(_LessThanOpConcept<_ValueType1, _ValueType2>)
__glibcxx_function_requires(_LessThanOpConcept<_ValueType2, _ValueType1>)
__glibcxx_requires_valid_range(__first1, __last1);
- __glibcxx_requires_irreflexive2(__first1, __last1);
__glibcxx_requires_valid_range(__first2, __last2);
- __glibcxx_requires_irreflexive2(__first2, __last2);
return std::__lexicographical_compare_aux(std::__niter_base(__first1),
std::__niter_base(__last1),
__glibcxx_function_requires(_InputIteratorConcept<_II1>)
__glibcxx_function_requires(_InputIteratorConcept<_II2>)
__glibcxx_requires_valid_range(__first1, __last1);
- __glibcxx_requires_irreflexive_pred2(__first1, __last1, __comp);
__glibcxx_requires_valid_range(__first2, __last2);
- __glibcxx_requires_irreflexive_pred2(__first2, __last2, __comp);
return std::__lexicographical_compare_impl
(__first1, __last1, __first2, __last2,
/// Construct with a copy of @p __value as the contained object.
template <typename _ValueType, typename _Tp = _Decay<_ValueType>,
- typename _Mgr = _Manager<_Tp>>
+ typename _Mgr = _Manager<_Tp>,
+ typename enable_if<is_constructible<_Tp, _ValueType&&>::value,
+ bool>::type = true>
any(_ValueType&& __value)
: _M_manager(&_Mgr::_S_manage)
{
"The contained object must be CopyConstructible");
}
+ /// Construct with a copy of @p __value as the contained object.
+ template <typename _ValueType, typename _Tp = _Decay<_ValueType>,
+ typename _Mgr = _Manager<_Tp>,
+ typename enable_if<!is_constructible<_Tp, _ValueType&&>::value,
+ bool>::type = false>
+ any(_ValueType&& __value)
+ : _M_manager(&_Mgr::_S_manage)
+ {
+ _Mgr::_S_create(_M_storage, __value);
+ static_assert(is_copy_constructible<_Tp>::value,
+ "The contained object must be CopyConstructible");
+ }
+
/// Destructor, calls @c clear()
~any() { clear(); }
__throw_bad_any_cast();
}
- template<typename _ValueType>
+ template<typename _ValueType,
+ typename enable_if<!is_move_constructible<_ValueType>::value
+ || is_lvalue_reference<_ValueType>::value,
+ bool>::type = true>
inline _ValueType any_cast(any&& __any)
{
static_assert(any::__is_valid_cast<_ValueType>(),
return *__p;
__throw_bad_any_cast();
}
+
+ template<typename _ValueType,
+ typename enable_if<is_move_constructible<_ValueType>::value
+ && !is_lvalue_reference<_ValueType>::value,
+ bool>::type = false>
+ inline _ValueType any_cast(any&& __any)
+ {
+ static_assert(any::__is_valid_cast<_ValueType>(),
+ "Template argument must be a reference or CopyConstructible type");
+ auto __p = any_cast<remove_reference_t<_ValueType>>(&__any);
+ if (__p)
+ return std::move(*__p);
+ __throw_bad_any_cast();
+ }
// @}
template<typename _Tp>
bool _M_engaged = false;
};
+ template<typename _Tp>
+ class optional;
+
+ template<typename>
+ struct __is_optional_impl : false_type
+ { };
+
+ template<typename _Tp>
+ struct __is_optional_impl<optional<_Tp>> : true_type
+ { };
+
+ template<typename _Tp>
+ struct __is_optional
+ : public __is_optional_impl<std::remove_cv_t<std::remove_reference_t<_Tp>>>
+ { };
+
+
/**
* @brief Class template for optional values.
*/
// _Optional_base has the responsibility for construction.
using _Base::_Base;
+ constexpr optional() = default;
+ // Converting constructors for engaged optionals.
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ is_constructible<_Tp, _Up&&>,
+ is_convertible<_Up&&, _Tp>
+ >::value, bool> = true>
+ constexpr optional(_Up&& __t)
+ : _Base(_Tp(std::forward<_Up>(__t))) { }
+
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ is_constructible<_Tp, _Up&&>,
+ __not_<is_convertible<_Up&&, _Tp>>
+ >::value, bool> = false>
+ explicit constexpr optional(_Up&& __t)
+ : _Base(_Tp(std::forward<_Up>(__t))) { }
+
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ __not_<is_constructible<
+ _Tp, const optional<_Up>&>>,
+ __not_<is_convertible<
+ const optional<_Up>&, _Tp>>,
+ is_constructible<_Tp, const _Up&>,
+ is_convertible<const _Up&, _Tp>
+ >::value, bool> = true>
+ constexpr optional(const optional<_Up>& __t)
+ : _Base(__t ? optional<_Tp>(*__t) : optional<_Tp>()) { }
+
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ __not_<is_constructible<
+ _Tp, const optional<_Up>&>>,
+ __not_<is_convertible<
+ const optional<_Up>&, _Tp>>,
+ is_constructible<_Tp, const _Up&>,
+ __not_<is_convertible<const _Up&, _Tp>>
+ >::value, bool> = false>
+ explicit constexpr optional(const optional<_Up>& __t)
+ : _Base(__t ? optional<_Tp>(*__t) : optional<_Tp>()) { }
+
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ __not_<is_constructible<
+ _Tp, optional<_Up>&&>>,
+ __not_<is_convertible<
+ optional<_Up>&&, _Tp>>,
+ is_constructible<_Tp, _Up&&>,
+ is_convertible<_Up&&, _Tp>
+ >::value, bool> = true>
+ constexpr optional(optional<_Up>&& __t)
+ : _Base(__t ? optional<_Tp>(std::move(*__t)) : optional<_Tp>()) { }
+
+ template <typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>,
+ __not_<is_constructible<
+ _Tp, optional<_Up>&&>>,
+ __not_<is_convertible<
+ optional<_Up>&&, _Tp>>,
+ is_constructible<_Tp, _Up&&>,
+ __not_<is_convertible<_Up&&, _Tp>>
+ >::value, bool> = false>
+ explicit constexpr optional(optional<_Up>&& __t)
+ : _Base(__t ? optional<_Tp>(std::move(*__t)) : optional<_Tp>()) { }
+
// [X.Y.4.3] (partly) Assignment.
optional&
operator=(nullopt_t) noexcept
return *this;
}
- template<typename _Up>
- enable_if_t<is_same<_Tp, decay_t<_Up>>::value, optional&>
+ template<typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Up, nullopt_t>>,
+ __not_<__is_optional<_Up>>>::value,
+ bool> = true>
+ optional&
operator=(_Up&& __u)
{
static_assert(__and_<is_constructible<_Tp, _Up>,
return *this;
}
+ template<typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>>::value,
+ bool> = true>
+ optional&
+ operator=(const optional<_Up>& __u)
+ {
+ static_assert(__and_<is_constructible<_Tp, _Up>,
+ is_assignable<_Tp&, _Up>>(),
+ "Cannot assign to value type from argument");
+
+ if (__u)
+ {
+ if (this->_M_is_engaged())
+ this->_M_get() = *__u;
+ else
+ this->_M_construct(*__u);
+ }
+ else
+ {
+ this->_M_reset();
+ }
+ return *this;
+ }
+
+ template<typename _Up,
+ enable_if_t<__and_<
+ __not_<is_same<_Tp, _Up>>>::value,
+ bool> = true>
+ optional&
+ operator=(optional<_Up>&& __u)
+ {
+ static_assert(__and_<is_constructible<_Tp, _Up>,
+ is_assignable<_Tp&, _Up>>(),
+ "Cannot assign to value type from argument");
+
+ if (__u)
+ {
+ if (this->_M_is_engaged())
+ this->_M_get() = std::move(*__u);
+ else
+ this->_M_construct(std::move(*__u));
+ }
+ else
+ {
+ this->_M_reset();
+ }
+
+ return *this;
+ }
+
template<typename... _Args>
void
emplace(_Args&&... __args)
uintmax_t count = 0;
if (ec.value() == 0 && fs.type() == file_type::directory)
for (directory_iterator d(p, ec), end; ec.value() == 0 && d != end; ++d)
- count += fs::remove(d->path(), ec);
+ count += fs::remove_all(d->path(), ec);
if (ec.value())
return -1;
return fs::remove(p, ec) ? ++count : -1; // fs:remove() calls ec.clear()
--- /dev/null
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" }
+
+#include <algorithm>
+#include <functional>
+#include <testsuite_iterators.h>
+#include <testsuite_hooks.h>
+
+using __gnu_test::test_container;
+using __gnu_test::forward_iterator_wrapper;
+
+struct X
+{
+ int val;
+
+ bool odd() const { return val % 2; }
+
+ // Partitioned so that all odd values come before even values:
+ bool operator<(const X& x) const { return this->odd() && !x.odd(); }
+};
+
+void
+test01()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test with range that is partitioned, but not sorted.
+ X seq[] = { 1, 3, 5, 7, 1, 6, 4 };
+ test_container<X, forward_iterator_wrapper> c(seq);
+
+ auto b1 = std::binary_search(c.begin(), c.end(), X{2});
+ VERIFY( b1 );
+ auto b2 = std::binary_search(c.begin(), c.end(), X{2}, std::less<X>{});
+ VERIFY( b2 );
+
+ auto b3 = std::binary_search(c.begin(), c.end(), X{9});
+ VERIFY( b3 );
+ auto b4 = std::binary_search(c.begin(), c.end(), X{9}, std::less<X>{});
+ VERIFY( b4 );
+
+ auto b5 = std::binary_search(seq, seq+5, X{2});
+ VERIFY( !b5 );
+ auto b6 = std::binary_search(seq, seq+5, X{2}, std::less<X>{});
+ VERIFY( !b6 );
+}
+
+int
+main()
+{
+ test01();
+}
--- /dev/null
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" }
+
+#include <algorithm>
+#include <functional>
+#include <testsuite_iterators.h>
+#include <testsuite_hooks.h>
+
+using __gnu_test::test_container;
+using __gnu_test::forward_iterator_wrapper;
+
+struct X
+{
+ int val;
+
+ bool odd() const { return val % 2; }
+
+ // Partitioned so that all odd values come before even values:
+ bool operator<(const X& x) const { return this->odd() && !x.odd(); }
+};
+
+void
+test01()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test with range that is partitioned, but not sorted.
+ X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 };
+ test_container<X, forward_iterator_wrapper> c(seq);
+
+ auto part1 = std::equal_range(c.begin(), c.end(), X{2});
+ VERIFY( part1.first != c.end() && part1.second == c.end() );
+ VERIFY( part1.first->val == 6 );
+ auto part2 = std::equal_range(c.begin(), c.end(), X{2}, std::less<X>{});
+ VERIFY( part2.first != c.end() && part1.second == c.end() );
+ VERIFY( part2.first->val == 6 );
+
+ auto part3 = std::equal_range(c.begin(), c.end(), X{9});
+ VERIFY( part3.first == c.begin() && part3.second != c.end() );
+ VERIFY( part3.second->val == 6 );
+ auto part4 = std::equal_range(c.begin(), c.end(), X{9}, std::less<X>{});
+ VERIFY( part4.first == c.begin() && part4.second != c.end() );
+ VERIFY( part4.second->val == 6 );
+}
+
+int
+main()
+{
+ test01();
+}
--- /dev/null
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" }
+// { dg-do link }
+
+#include <algorithm>
+
+struct X { };
+
+bool operator<(X, int) { return true; }
+bool operator<(int, X) { return false; }
+
+bool operator<(X, X); // undefined (PR libstdc++/71545)
+
+int main()
+{
+ X x[1];
+ int i[1];
+ std::lexicographical_compare(x, x+1, i, i+1);
+}
--- /dev/null
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" }
+
+#include <algorithm>
+#include <functional>
+#include <testsuite_iterators.h>
+#include <testsuite_hooks.h>
+
+using __gnu_test::test_container;
+using __gnu_test::forward_iterator_wrapper;
+
+struct X
+{
+ int val;
+
+ bool odd() const { return val % 2; }
+
+ // Partitioned so that all odd values come before even values:
+ bool operator<(const X& x) const { return this->odd() && !x.odd(); }
+};
+
+void
+test01()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test with range that is partitioned, but not sorted.
+ X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 };
+ test_container<X, forward_iterator_wrapper> c(seq);
+
+ auto part1 = std::lower_bound(c.begin(), c.end(), X{2});
+ VERIFY( part1 != c.end() );
+ VERIFY( part1->val == 6 );
+ auto part2 = std::lower_bound(c.begin(), c.end(), X{2}, std::less<X>{});
+ VERIFY( part2 != c.end() );
+ VERIFY( part2->val == 6 );
+
+ auto part3 = std::lower_bound(c.begin(), c.end(), X{9});
+ VERIFY( part3 != c.end() );
+ VERIFY( part3->val == 1 );
+ auto part4 = std::lower_bound(c.begin(), c.end(), X{9}, std::less<X>{});
+ VERIFY( part4 != c.end() );
+ VERIFY( part4->val == 1 );
+}
+
+struct Y
+{
+ double val;
+
+ // Not irreflexive, so not a strict weak order.
+ bool operator<(const Y& y) const { return val < int(y.val); }
+};
+
+void
+test02()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test that Debug Mode checks don't fire (libstdc++/71545)
+
+ Y seq[] = { -0.1, 1.2, 5.0, 5.2, 5.1, 5.9, 5.5, 6.0 };
+ test_container<Y, forward_iterator_wrapper> c(seq);
+
+ auto part1 = std::lower_bound(c.begin(), c.end(), Y{5.5});
+ VERIFY( part1 != c.end() );
+ VERIFY( part1->val == 5.0 );
+ auto part2 = std::lower_bound(c.begin(), c.end(), Y{5.5}, std::less<Y>{});
+ VERIFY( part2 != c.end() );
+ VERIFY( part2->val == 5.0 );
+
+ auto part3 = std::lower_bound(c.begin(), c.end(), Y{1.0});
+ VERIFY( part3 != c.end() );
+ VERIFY( part3->val == 1.2 );
+ auto part4 = std::lower_bound(c.begin(), c.end(), Y{1.0}, std::less<Y>{});
+ VERIFY( part4 != c.end() );
+ VERIFY( part4->val == 1.2 );
+}
+
+int
+main()
+{
+ test01();
+ test02();
+}
--- /dev/null
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" }
+
+#include <algorithm>
+#include <functional>
+#include <testsuite_iterators.h>
+#include <testsuite_hooks.h>
+
+using __gnu_test::test_container;
+using __gnu_test::forward_iterator_wrapper;
+
+struct X
+{
+ int val;
+
+ bool odd() const { return val % 2; }
+
+ // Partitioned so that all odd values come before even values:
+ bool operator<(const X& x) const { return this->odd() && !x.odd(); }
+};
+
+void
+test01()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test with range that is partitioned, but not sorted.
+ X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 };
+ test_container<X, forward_iterator_wrapper> c(seq);
+
+ auto part1 = std::upper_bound(c.begin(), c.end(), X{2});
+ VERIFY( part1 == c.end() );
+ auto part2 = std::upper_bound(c.begin(), c.end(), X{2}, std::less<X>{});
+ VERIFY( part2 == c.end() );
+
+ auto part3 = std::upper_bound(c.begin(), c.end(), X{9});
+ VERIFY( part3 != c.end() );
+ VERIFY( part3->val == 6 );
+ auto part4 = std::upper_bound(c.begin(), c.end(), X{9}, std::less<X>{});
+ VERIFY( part3 != c.end() );
+ VERIFY( part4->val == 6 );
+}
+
+struct Y
+{
+ double val;
+
+ // Not irreflexive, so not a strict weak order.
+ bool operator<(const Y& y) const { return val < (int)y.val; }
+};
+
+void
+test02()
+{
+ bool test __attribute((unused)) = true;
+
+ // Test that Debug Mode checks don't fire (libstdc++/71545)
+
+ Y seq[] = { -0.1, 1.2, 5.0, 5.2, 5.1, 5.9, 5.5, 6.0 };
+ test_container<Y, forward_iterator_wrapper> c(seq);
+
+ auto part1 = std::upper_bound(c.begin(), c.end(), Y{5.5});
+ VERIFY( part1 != c.end() );
+ VERIFY( part1->val == 6.0 );
+ auto part2 = std::upper_bound(c.begin(), c.end(), Y{5.5}, std::less<Y>{});
+ VERIFY( part2 != c.end() );
+ VERIFY( part2->val == 6.0 );
+
+ auto part3 = std::upper_bound(c.begin(), c.end(), Y{1.0});
+ VERIFY( part3 != c.end() );
+ VERIFY( part3->val == 5.0 );
+ auto part4 = std::upper_bound(c.begin(), c.end(), Y{1.0}, std::less<Y>{});
+ VERIFY( part4 != c.end() );
+ VERIFY( part4->val == 5.0 );
+}
+
+int
+main()
+{
+ test01();
+ test02();
+}
}
}
+static int move_count = 0;
+
+void test03()
+{
+ struct MoveEnabled
+ {
+ MoveEnabled(MoveEnabled&&)
+ {
+ ++move_count;
+ }
+ MoveEnabled() = default;
+ MoveEnabled(const MoveEnabled&) = default;
+ };
+ MoveEnabled m;
+ MoveEnabled m2 = any_cast<MoveEnabled>(any(m));
+ VERIFY(move_count == 1);
+ MoveEnabled&& m3 = any_cast<MoveEnabled&&>(any(m));
+ VERIFY(move_count == 1);
+ struct MoveDeleted
+ {
+ MoveDeleted(MoveDeleted&&) = delete;
+ MoveDeleted() = default;
+ MoveDeleted(const MoveDeleted&) = default;
+ };
+ MoveDeleted md;
+ MoveDeleted&& md2 = any_cast<MoveDeleted>(any(std::move(md)));
+ MoveDeleted&& md3 = any_cast<MoveDeleted&&>(any(std::move(md)));
+}
+
int main()
{
test01();
test02();
+ test03();
}
using std::experimental::any_cast;
const any y(1);
- any_cast<int&>(y); // { dg-error "qualifiers" "" { target { *-*-* } } 353 }
+ any_cast<int&>(y); // { dg-error "qualifiers" "" { target { *-*-* } } 368 }
}
VERIFY( b );
VERIFY( is_directory(p/"./d4/../d5") );
- remove_all(p, ec);
+ std::uintmax_t count = remove_all(p, ec);
+ VERIFY( count == 6 );
}
int
#include <testsuite_hooks.h>
#include <vector>
+#include <string>
struct tracker
{
VERIFY( result == caught );
}
+
+ {
+ std::experimental::optional<std::string> os = "foo";
+ struct X
+ {
+ explicit X(int) {}
+ X& operator=(int) {return *this;}
+ };
+ std::experimental::optional<X> ox{42};
+ std::experimental::optional<int> oi{42};
+ std::experimental::optional<X> ox2{oi};
+ std::experimental::optional<std::string> os2;
+ os2 = "foo";
+ std::experimental::optional<X> ox3;
+ ox3 = 42;
+ std::experimental::optional<X> ox4;
+ ox4 = oi;
+ }
}
--- /dev/null
+// { dg-options "-std=gnu++14" }
+// { dg-do compile }
+
+// Copyright (C) 2013-2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a moved_to of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+#include <experimental/optional>
+#include <testsuite_hooks.h>
+
+#include <string>
+#include <memory>
+
+int main()
+{
+ {
+ struct X
+ {
+ explicit X(int) {}
+ };
+ std::experimental::optional<X> ox{42};
+ std::experimental::optional<X> ox2 = 42; // { dg-error "conversion" }
+ std::experimental::optional<std::unique_ptr<int>> oup{new int};
+ std::experimental::optional<std::unique_ptr<int>> oup2 = new int; // { dg-error "conversion" }
+ }
+}
test_container(T* _first, T* _last):bounds(_first, _last)
{ }
+#if __cplusplus >= 201103L
+ template<std::size_t N>
+ explicit
+ test_container(T (&arr)[N]) : test_container(arr, arr+N)
+ { }
+#endif
+
ItType<T>
it(int pos)
{
projects / platform / upstream / linaro-gcc.git / commitdiff