drm/i915: Disable atomics in L3 for gen9

Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
the machine stops responding milliseconds after receipt of the reset
request [GDRT]. By disabling the cached atomics, the hang do not occur
and we presume the GPU would reset normally for similar hangs.

Sadly this is a shotgun approach, but since the impact is critical it is
better to err on the safe side and work back from there.

Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlesktrand.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125220152.24070-1-chris@chris-wilson.co.uk
Cc: stable@vger.kernel.org
(cherry picked from commit b267c7ae0ad5b437b068f46919b17f85000154b4)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3fdcd5f..ec366cf 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1834,6 +1834,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_write_or(wal,
                            GEN8_L3SQCREG4,
                            GEN8_LQSC_FLUSH_COHERENT_LINES);
+
+               /* Disable atomics in L3 to prevent unrecoverable hangs */
+               wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
+                                GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+               wa_write_clr_set(wal, GEN8_L3SQCREG4,
+                                GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+               wa_write_clr_set(wal, GEN9_SCRATCH1,
+                                EVICTION_PERF_FIX_ENABLE, 0);
        }
 
        if (IS_HASWELL(i915)) {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 598abd2..7146cd0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8225,6 +8225,7 @@ enum {
 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE                (1 << 6)
 #define  GEN8_LQSC_RO_PERF_DIS                 (1 << 27)
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES                (1 << 21)
+#define  GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0                           _MMIO(0x7300)
@@ -12107,6 +12108,12 @@ enum skl_power_gate {
 #define __GEN11_VCS2_MOCS0     0x10000
 #define GEN11_MFX2_MOCS(i)     _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
 
+#define GEN9_SCRATCH_LNCF1             _MMIO(0xb008)
+#define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
+
+#define GEN9_SCRATCH1                  _MMIO(0xb11c)
+#define   EVICTION_PERF_FIX_ENABLE     REG_BIT(8)
+
 #define GEN10_SCRATCH_LNCF2            _MMIO(0xb0a0)
 #define   PMFLUSHDONE_LNICRSDROP       (1 << 20)
 #define   PMFLUSH_GAPL3UNBLOCK         (1 << 21)