drm/amd/pm: populate Arcturus PCIE link state

Populate current link speed, width and clock domain frequency.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 35640c8b638a19a72cce6a184a2b5042866706a3..89632ee88ae24e6b404e697109e84aad627162e0 100644 (file)
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2060,9 +2060,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
        } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
                if (asic_type < CHIP_VEGA20)
                        *states = ATTR_STATE_UNSUPPORTED;
-       } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
-               if (asic_type == CHIP_ARCTURUS)
-                       *states = ATTR_STATE_UNSUPPORTED;
        } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
                *states = ATTR_STATE_UNSUPPORTED;
                if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index fc376281e629a024b831d425869dc8b9bac80153..d96048e9823765710aff52148a5b02753c312450 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -717,6 +717,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
        struct smu_11_0_dpm_table *single_dpm_table;
        struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
        struct smu_11_0_dpm_context *dpm_context = NULL;
+       uint32_t gen_speed, lane_width;
 
        if (amdgpu_ras_intr_triggered())
                return snprintf(buf, PAGE_SIZE, "unavailable\n");
@@ -820,6 +821,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                                now) ? "*" : ""));
                break;
 
+       case SMU_PCIE:
+               gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
+               lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
+               size += sprintf(buf + size, "0: %s %s %dMhz *\n",
+                               (gen_speed == 0) ? "2.5GT/s," :
+                               (gen_speed == 1) ? "5.0GT/s," :
+                               (gen_speed == 2) ? "8.0GT/s," :
+                               (gen_speed == 3) ? "16.0GT/s," : "",
+                               (lane_width == 1) ? "x1" :
+                               (lane_width == 2) ? "x2" :
+                               (lane_width == 3) ? "x4" :
+                               (lane_width == 4) ? "x8" :
+                               (lane_width == 5) ? "x12" :
+                               (lane_width == 6) ? "x16" : "",
+                               smu->smu_table.boot_values.lclk / 100);
+               break;
+
        default:
                break;
        }