MAINTAINERS: generify the Microchip RISC-V entry name
authorConor Dooley <conor.dooley@microchip.com>
Wed, 9 Nov 2022 21:22:18 +0000 (21:22 +0000)
committerArnd Bergmann <arnd@arndb.de>
Tue, 15 Nov 2022 15:48:02 +0000 (16:48 +0100)
These drivers work on our other FPGAs, for example the non-SoC PolarFire
connected to an FU-540 via chiplink. Make the entry a wee bit more
generic to match. While at it, remove the / from the heading so that it
matches other, neighbouring RISC-V entries.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221109212219.1598355-3-conor@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
MAINTAINERS

index f411c4f..c718a8b 100644 (file)
@@ -17725,7 +17725,7 @@ F:      arch/riscv/
 N:     riscv
 K:     riscv
 
-RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
+RISC-V MICROCHIP FPGA SUPPORT
 M:     Conor Dooley <conor.dooley@microchip.com>
 M:     Daire McNamara <daire.mcnamara@microchip.com>
 L:     linux-riscv@lists.infradead.org