writel(flags, cec_dev->cec_reg + AO_CECB_INTR_CLR);
}
+/* max length = 14+1 */
+#define OSD_NAME_DEV 1
+const uint8_t dev_osd_name[1][16] = {
+ {1, 0x43, 0x68, 0x72, 0x6f, 0x6d, 0x65, 0x63, 0x61, 0x73, 0x74},
+};
+
+const uint8_t dev_vendor_id[1][3] = {
+ {0, 0, 0},
+};
+
+static bool cec_message_op(unsigned char *msg, unsigned char len)
+{
+ int i, j;
+
+ if (((msg[0] & 0xf0) >> 4) == cec_dev->cec_info.log_addr) {
+ CEC_ERR("bad iniator with self:%s", msg_log_buf);
+ return false;
+ }
+ switch (msg[1]) {
+ case 0x47:
+ /* OSD name */
+ if (len > 16)
+ break;
+ for (j = 0; j < OSD_NAME_DEV; j++) {
+ for (i = 2; i < len; i++) {
+ if (msg[i] != dev_osd_name[j][i-1])
+ break;
+ }
+ if (i == len) {
+ cec_set_dev_info(dev_osd_name[j][0]);
+ CEC_INFO("specific dev:%d", dev_osd_name[j][0]);
+ }
+ }
+ break;
+ case 0x87:
+ /* verdor ID */
+ break;
+ default:
+ break;
+ }
+ return true;
+}
+
static int cecb_pick_msg(unsigned char *msg, unsigned char *out_len)
{
int i, size;
/* clr CEC lock bit */
hdmirx_cec_write(DWC_CEC_LOCK, 0);
CEC_INFO("%s", msg_log_buf);
- if (((msg[0] & 0xf0) >> 4) == cec_dev->cec_info.log_addr) {
- *out_len = 0;
- CEC_ERR("bad iniator with self:%s", msg_log_buf);
- } else
+ if (cec_message_op(msg, len))
*out_len = len;
+ else
+ *out_len = 0;
pin_status = 1;
return 0;
}
-#define CEC_DRIVER_VERSION "Ver 2019/1/14\n"
+#define CEC_DRIVER_VERSION "Ver 2019/1/28\n"
#define CEC_FRAME_DELAY msecs_to_jiffies(400)
#define CEC_DEV_NAME "cec"
extern void hdmirx_wr_dwc(uint16_t addr, uint32_t data);
extern unsigned int rd_reg_hhi(unsigned int offset);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
-
+extern int cec_set_dev_info(uint8_t dev_idx);
+int __attribute__((weak))cec_set_dev_info(uint8_t dev_idx);
#else
static inline unsigned long hdmirx_rd_top(unsigned long addr)
{
*
*
*/
-#define RX_VER1 "ver.2019/01/08"
+#define RX_VER1 "ver.2019/01/28"
/*
*
*
extern bool downstream_repeat_support;
extern void rx_tasklet_handler(unsigned long arg);
extern void skip_frame(unsigned int cnt);
-
+extern int cec_set_dev_info(uint8_t dev_idx);
/* reg */
static bool phy_fast_switching;
static bool phy_fsm_enhancement = true;
/*unsigned int last_clk_rate;*/
-
static uint32_t modet_clk = 24000;
-
+int hdcp_enc_mode;
/* top_irq_en bit[16:13] hdcp_sts */
int top_intr_maskn_value = 1;
bool hdcp_enable = 1;
/* 1: force OESS */
/* 2: force EESS */
/* 3: auto mode,check CTL[3:0]=d9/d8 during WOO */
- data32 |= (0 << 2);
+ data32 |= (hdcp_enc_mode << 2);
data32 |= (0 << 0);
hdmirx_wr_dwc(DWC_HDMI_MODE_RECOVER, data32);
extern unsigned int hdmirx_data_port;
extern unsigned int hdmirx_ctrl_port;
extern int acr_mode;
+extern int hdcp_enc_mode;
extern int force_clk_rate;
extern int auto_aclk_mute;
extern int aud_avmute_en;
static int hdcp_none_wait_max = 100;
static int esd_phy_rst_cnt;
static int esd_phy_rst_max;
+static int cec_dev_info;
struct rx_s rx;
void hdmirx_init_params(void)
rx_pr("esm_hpd-1\n");
}
+int cec_set_dev_info(uint8_t dev_idx)
+{
+ cec_dev_info |= 1 << dev_idx;
+
+ if (dev_idx == 1)
+ hdcp_enc_mode = 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(cec_set_dev_info);
+
/*
*func: irq tasklet
*param: flag:
return pr_var(find_best_eq, index);
if (set_pr_var(tmpbuf, eq_try_cnt, value, &index, ret))
return pr_var(eq_try_cnt, index);
+ if (set_pr_var(tmpbuf, hdcp_enc_mode, value, &index, ret))
+ return pr_var(hdcp_enc_mode, index);
return 0;
}
pr_var(phy_retry_times, i++);
pr_var(find_best_eq, i++);
pr_var(eq_try_cnt, i++);
+ pr_var(hdcp_enc_mode, i++);
}
void skip_frame(unsigned int cnt)