drm/amd/display: Update swizzle mode enums
authorAlvin Lee <Alvin.Lee2@amd.com>
Fri, 30 Jul 2021 20:55:06 +0000 (16:55 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Sep 2021 20:55:10 +0000 (16:55 -0400)
[Why]
Swizzle mode enum for DC_SW_VAR_R_X was existing,
but not mapped correctly.

[How]
Update mapping and conversion for DC_SW_VAR_R_X.

Reviewed-by: XiangBing Foo <XiangBing.Foo@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

index 0159700..7bab883 100644 (file)
@@ -1856,7 +1856,9 @@ static void swizzle_to_dml_params(
        case DC_SW_VAR_D_X:
                *sw_mode = dm_sw_var_d_x;
                break;
-
+       case DC_SW_VAR_R_X:
+               *sw_mode = dm_sw_var_r_x;
+               break;
        default:
                ASSERT(0); /* Not supported */
                break;
index 1051ca1..edb9f75 100644 (file)
@@ -80,11 +80,11 @@ enum dm_swizzle_mode {
        dm_sw_SPARE_13 = 24,
        dm_sw_64kb_s_x = 25,
        dm_sw_64kb_d_x = 26,
-       dm_sw_SPARE_14 = 27,
+       dm_sw_64kb_r_x = 27,
        dm_sw_SPARE_15 = 28,
        dm_sw_var_s_x = 29,
        dm_sw_var_d_x = 30,
-       dm_sw_64kb_r_x,
+       dm_sw_var_r_x = 31,
        dm_sw_gfx7_2d_thin_l_vp,
        dm_sw_gfx7_2d_thin_gl,
 };