Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86/apic changes from Ingo Molnar:
 "Main changes:

   - Multiple MSI support added to the APIC, PCI and AHCI code - acked
     by all relevant maintainers, by Alexander Gordeev.

     The advantage is that multiple AHCI ports can have multiple MSI
     irqs assigned, and can thus spread to multiple CPUs.

     [ Drivers can make use of this new facility via the
       pci_enable_msi_block_auto() method ]

   - x86 IOAPIC code from interrupt remapping cleanups from Joerg
     Roedel:

     These patches move all interrupt remapping specific checks out of
     the x86 core code and replaces the respective call-sites with
     function pointers.  As a result the interrupt remapping code is
     better abstraced from x86 core interrupt handling code.

   - Various smaller improvements, fixes and cleanups."

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  x86/intel/irq_remapping: Clean up x2apic opt-out security warning mess
  x86, kvm: Fix intialization warnings in kvm.c
  x86, irq: Move irq_remapped out of x86 core code
  x86, io_apic: Introduce eoi_ioapic_pin call-back
  x86, msi: Introduce x86_msi.compose_msi_msg call-back
  x86, irq: Introduce setup_remapped_irq()
  x86, irq: Move irq_remapped() check into free_remapped_irq
  x86, io-apic: Remove !irq_remapped() check from __target_IO_APIC_irq()
  x86, io-apic: Move CONFIG_IRQ_REMAP code out of x86 core
  x86, irq: Add data structure to keep AMD specific irq remapping information
  x86, irq: Move irq_remapping_enabled declaration to iommu code
  x86, io_apic: Remove irq_remapping_enabled check in setup_timer_IRQ0_pin
  x86, io_apic: Move irq_remapping_enabled checks out of check_timer()
  x86, io_apic: Convert setup_ioapic_entry to function pointer
  x86, io_apic: Introduce set_affinity function pointer
  x86, msi: Use IRQ remapping specific setup_msi_irqs routine
  x86, hpet: Introduce x86_msi_ops.setup_hpet_msi
  x86, io_apic: Introduce x86_io_apic_ops.print_entries for debugging
  x86, io_apic: Introduce x86_io_apic_ops.disable()
  x86, apic: Mask IO-APIC and PIC unconditionally on LAPIC resume
  ...

diff --combined arch/x86/xen/enlighten.c
index e014092,8b4c56d..39928d1
--- 1/arch/x86/xen/enlighten.c
--- 2/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@@ -1517,51 -1517,72 +1517,51 @@@ asmlinkage void __init xen_start_kernel
  #endif
  }
  
 -#ifdef CONFIG_XEN_PVHVM
 -#define HVM_SHARED_INFO_ADDR 0xFE700000UL
 -static struct shared_info *xen_hvm_shared_info;
 -static unsigned long xen_hvm_sip_phys;
 -static int xen_major, xen_minor;
 -
 -static void xen_hvm_connect_shared_info(unsigned long pfn)
 +void __ref xen_hvm_init_shared_info(void)
  {
 +      int cpu;
        struct xen_add_to_physmap xatp;
 +      static struct shared_info *shared_info_page = 0;
  
 +      if (!shared_info_page)
 +              shared_info_page = (struct shared_info *)
 +                      extend_brk(PAGE_SIZE, PAGE_SIZE);
        xatp.domid = DOMID_SELF;
        xatp.idx = 0;
        xatp.space = XENMAPSPACE_shared_info;
 -      xatp.gpfn = pfn;
 +      xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
                BUG();
  
 -}
 -static void __init xen_hvm_set_shared_info(struct shared_info *sip)
 -{
 -      int cpu;
 -
 -      HYPERVISOR_shared_info = sip;
 +      HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
  
        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
         * page, we use it in the event channel upcall and in some pvclock
         * related functions. We don't need the vcpu_info placement
         * optimizations because we don't use any pv_mmu or pv_irq op on
 -       * HVM. */
 -      for_each_online_cpu(cpu)
 +       * HVM.
 +       * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
 +       * online but xen_hvm_init_shared_info is run at resume time too and
 +       * in that case multiple vcpus might be online. */
 +      for_each_online_cpu(cpu) {
                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 -}
 -
 -/* Reconnect the shared_info pfn to a (new) mfn */
 -void xen_hvm_resume_shared_info(void)
 -{
 -      xen_hvm_connect_shared_info(xen_hvm_sip_phys >> PAGE_SHIFT);
 -}
 -
 -/* Xen tools prior to Xen 4 do not provide a E820_Reserved area for guest usage.
 - * On these old tools the shared info page will be placed in E820_Ram.
 - * Xen 4 provides a E820_Reserved area at 0xFC000000, and this code expects
 - * that nothing is mapped up to HVM_SHARED_INFO_ADDR.
 - * Xen 4.3+ provides an explicit 1MB area at HVM_SHARED_INFO_ADDR which is used
 - * here for the shared info page. */
 -static void __init xen_hvm_init_shared_info(void)
 -{
 -      if (xen_major < 4) {
 -              xen_hvm_shared_info = extend_brk(PAGE_SIZE, PAGE_SIZE);
 -              xen_hvm_sip_phys = __pa(xen_hvm_shared_info);
 -      } else {
 -              xen_hvm_sip_phys = HVM_SHARED_INFO_ADDR;
 -              set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_hvm_sip_phys);
 -              xen_hvm_shared_info =
 -              (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
        }
 -      xen_hvm_connect_shared_info(xen_hvm_sip_phys >> PAGE_SHIFT);
 -      xen_hvm_set_shared_info(xen_hvm_shared_info);
  }
  
 +#ifdef CONFIG_XEN_PVHVM
  static void __init init_hvm_pv_info(void)
  {
 -      uint32_t ecx, edx, pages, msr, base;
 +      int major, minor;
 +      uint32_t eax, ebx, ecx, edx, pages, msr, base;
        u64 pfn;
  
        base = xen_cpuid_base();
 +      cpuid(base + 1, &eax, &ebx, &ecx, &edx);
 +
 +      major = eax >> 16;
 +      minor = eax & 0xffff;
 +      printk(KERN_INFO "Xen version %d.%d.\n", major, minor);
 +
        cpuid(base + 2, &pages, &msr, &ecx, &edx);
  
        pfn = __pa(hypercall_page);
@@@ -1612,12 -1633,22 +1612,12 @@@ static void __init xen_hvm_guest_init(v
  
  static bool __init xen_hvm_platform(void)
  {
 -      uint32_t eax, ebx, ecx, edx, base;
 -
        if (xen_pv_domain())
                return false;
  
 -      base = xen_cpuid_base();
 -      if (!base)
 +      if (!xen_cpuid_base())
                return false;
  
 -      cpuid(base + 1, &eax, &ebx, &ecx, &edx);
 -
 -      xen_major = eax >> 16;
 -      xen_minor = eax & 0xffff;
 -
 -      printk(KERN_INFO "Xen version %d.%d.\n", xen_major, xen_minor);
 -
        return true;
  }
  
@@@ -1637,6 -1668,7 +1637,7 @@@ const struct hypervisor_x86 x86_hyper_x
        .name                   = "Xen HVM",
        .detect                 = xen_hvm_platform,
        .init_platform          = xen_hvm_guest_init,
+       .x2apic_available       = xen_x2apic_para_available,
  };
  EXPORT_SYMBOL(x86_hyper_xen_hvm);
  #endif

diff --combined drivers/iommu/intel-iommu.c
index eca2801,64ae948..43d5c8b
--- 1/drivers/iommu/intel-iommu.c
--- 2/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@@ -46,6 -46,8 +46,8 @@@
  #include <asm/cacheflush.h>
  #include <asm/iommu.h>
  
+ #include "irq_remapping.h"
+ 
  #define ROOT_SIZE             VTD_PAGE_SIZE
  #define CONTEXT_SIZE          VTD_PAGE_SIZE
  
@@@ -4234,21 -4236,6 +4236,21 @@@ static struct iommu_ops intel_iommu_op
        .pgsize_bitmap  = INTEL_IOMMU_PGSIZES,
  };
  
 +static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
 +{
 +      /* G4x/GM45 integrated gfx dmar support is totally busted. */
 +      printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
 +      dmar_map_gfx = 0;
 +}
 +
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
 +
  static void quirk_iommu_rwbf(struct pci_dev *dev)
  {
        /*
@@@ -4257,6 -4244,12 +4259,6 @@@
         */
        printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
        rwbf_quirk = 1;
 -
 -      /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
 -      if (dev->revision == 0x07) {
 -              printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
 -              dmar_map_gfx = 0;
 -      }
  }
  
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);