clk: renesas: r8a779a0: Add VSPX clock support
authorKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Wed, 16 Dec 2020 15:19:31 +0000 (15:19 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 28 Dec 2020 09:45:17 +0000 (10:45 +0100)
Add clocks for the VSPX.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-4-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a779a0-cpg-mssr.c

index 2ce3150..d7825ad 100644 (file)
@@ -192,6 +192,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("vin37",        829,    R8A779A0_CLK_S1D1),
        DEF_MOD("vspd0",        830,    R8A779A0_CLK_S3D1),
        DEF_MOD("vspd1",        831,    R8A779A0_CLK_S3D1),
+       DEF_MOD("vspx0",        1028,   R8A779A0_CLK_S1D1),
+       DEF_MOD("vspx1",        1029,   R8A779A0_CLK_S1D1),
+       DEF_MOD("vspx2",        1030,   R8A779A0_CLK_S1D1),
+       DEF_MOD("vspx3",        1031,   R8A779A0_CLK_S1D1),
 };
 
 static spinlock_t cpg_lock;