+2017-09-25 Richard Sandiford <richard.sandifird@linaro.org>
+
+ * target.def (vec_perm_const_ok): Change sel parameter to
+ vec_perm_indices.
+ * optabs-query.c (can_vec_perm_p): Update accordingly.
+ * doc/tm.texi: Regenerate.
+ * config/aarch64/aarch64.c (expand_vec_perm_d): Change perm to
+ auto_vec_perm_indices and remove separate nelt field.
+ (aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_zip)
+ (aarch64_evpc_ext, aarch64_evpc_rev, aarch64_evpc_dup)
+ (aarch64_evpc_tbl, aarch64_expand_vec_perm_const_1)
+ (aarch64_expand_vec_perm_const): Update accordingly.
+ (aarch64_vectorize_vec_perm_const_ok): Likewise. Change sel
+ to vec_perm_indices.
+ * config/arm/arm.c (expand_vec_perm_d): Change perm to
+ auto_vec_perm_indices and remove separate nelt field.
+ (arm_evpc_neon_vuzp, arm_evpc_neon_vzip, arm_evpc_neon_vrev)
+ (arm_evpc_neon_vtrn, arm_evpc_neon_vext, arm_evpc_neon_vtbl)
+ (arm_expand_vec_perm_const_1, arm_expand_vec_perm_const): Update
+ accordingly.
+ (arm_vectorize_vec_perm_const_ok): Likewise. Change sel
+ to vec_perm_indices.
+ * config/i386/i386.c (ix86_vectorize_vec_perm_const_ok): Change
+ sel to vec_perm_indices.
+ * config/ia64/ia64.c (ia64_vectorize_vec_perm_const_ok): Likewise.
+ * config/mips/mips.c (mips_vectorize_vec_perm_const_ok): Likewise.
+ * config/powerpcspe/powerpcspe.c (rs6000_vectorize_vec_perm_const_ok):
+ Likewise.
+ * config/rs6000/rs6000.c (rs6000_vectorize_vec_perm_const_ok):
+ Likewise.
+
2017-09-25 Pierre-Marie de Rodat <derodat@adacore.com>
PR debug/82155
static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
static void aarch64_override_options_after_change (void);
static bool aarch64_vector_mode_supported_p (machine_mode);
-static bool aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel);
+static bool aarch64_vectorize_vec_perm_const_ok (machine_mode,
+ vec_perm_indices);
static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool);
static bool aarch64_builtin_support_vector_misalignment (machine_mode mode,
const_tree type,
struct expand_vec_perm_d
{
rtx target, op0, op1;
- unsigned char perm[MAX_VECT_LEN];
+ auto_vec_perm_indices perm;
machine_mode vmode;
- unsigned char nelt;
bool one_vector_p;
bool testing_p;
};
static bool
aarch64_evpc_trn (struct expand_vec_perm_d *d)
{
- unsigned int i, odd, mask, nelt = d->nelt;
+ unsigned int i, odd, mask, nelt = d->perm.length ();
rtx out, in0, in1, x;
rtx (*gen) (rtx, rtx, rtx);
machine_mode vmode = d->vmode;
static bool
aarch64_evpc_uzp (struct expand_vec_perm_d *d)
{
- unsigned int i, odd, mask, nelt = d->nelt;
+ unsigned int i, odd, mask, nelt = d->perm.length ();
rtx out, in0, in1, x;
rtx (*gen) (rtx, rtx, rtx);
machine_mode vmode = d->vmode;
static bool
aarch64_evpc_zip (struct expand_vec_perm_d *d)
{
- unsigned int i, high, mask, nelt = d->nelt;
+ unsigned int i, high, mask, nelt = d->perm.length ();
rtx out, in0, in1, x;
rtx (*gen) (rtx, rtx, rtx);
machine_mode vmode = d->vmode;
static bool
aarch64_evpc_ext (struct expand_vec_perm_d *d)
{
- unsigned int i, nelt = d->nelt;
+ unsigned int i, nelt = d->perm.length ();
rtx (*gen) (rtx, rtx, rtx, rtx);
rtx offset;
static bool
aarch64_evpc_rev (struct expand_vec_perm_d *d)
{
- unsigned int i, j, diff, nelt = d->nelt;
+ unsigned int i, j, diff, nelt = d->perm.length ();
rtx (*gen) (rtx, rtx);
if (!d->one_vector_p)
rtx out = d->target;
rtx in0;
machine_mode vmode = d->vmode;
- unsigned int i, elt, nelt = d->nelt;
+ unsigned int i, elt, nelt = d->perm.length ();
rtx lane;
elt = d->perm[0];
{
rtx rperm[MAX_VECT_LEN], sel;
machine_mode vmode = d->vmode;
- unsigned int i, nelt = d->nelt;
+ unsigned int i, nelt = d->perm.length ();
if (d->testing_p)
return true;
/* The pattern matching functions above are written to look for a small
number to begin the sequence (0, 1, N/2). If we begin with an index
from the second operand, we can swap the operands. */
- if (d->perm[0] >= d->nelt)
+ unsigned int nelt = d->perm.length ();
+ if (d->perm[0] >= nelt)
{
- unsigned i, nelt = d->nelt;
-
gcc_assert (nelt == (nelt & -nelt));
- for (i = 0; i < nelt; ++i)
+ for (unsigned int i = 0; i < nelt; ++i)
d->perm[i] ^= nelt; /* Keep the same index, but in the other vector. */
std::swap (d->op0, d->op1);
d.vmode = GET_MODE (target);
gcc_assert (VECTOR_MODE_P (d.vmode));
- d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
d.testing_p = false;
+ nelt = GET_MODE_NUNITS (d.vmode);
+ d.perm.reserve (nelt);
for (i = which = 0; i < nelt; ++i)
{
rtx e = XVECEXP (sel, 0, i);
int ei = INTVAL (e) & (2 * nelt - 1);
which |= (ei < nelt ? 1 : 2);
- d.perm[i] = ei;
+ d.perm.quick_push (ei);
}
switch (which)
}
static bool
-aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
struct expand_vec_perm_d d;
unsigned int i, nelt, which;
bool ret;
d.vmode = vmode;
- d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
d.testing_p = true;
- memcpy (d.perm, sel, nelt);
+ d.perm.safe_splice (sel);
/* Calculate whether all elements are in one vector. */
+ nelt = sel.length ();
for (i = which = 0; i < nelt; ++i)
{
unsigned char e = d.perm[i];
static int arm_cortex_m_branch_cost (bool, bool);
static int arm_cortex_m7_branch_cost (bool, bool);
-static bool arm_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel);
+static bool arm_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices);
static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*);
struct expand_vec_perm_d
{
rtx target, op0, op1;
- unsigned char perm[MAX_VECT_LEN];
+ auto_vec_perm_indices perm;
machine_mode vmode;
- unsigned char nelt;
bool one_vector_p;
bool testing_p;
};
static bool
arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
{
- unsigned int i, odd, mask, nelt = d->nelt;
+ unsigned int i, odd, mask, nelt = d->perm.length ();
rtx out0, out1, in0, in1;
rtx (*gen)(rtx, rtx, rtx, rtx);
int first_elem;
/* arm_expand_vec_perm_const_1 () helpfully swaps the operands for the
big endian pattern on 64 bit vectors, so we correct for that. */
swap_nelt = BYTES_BIG_ENDIAN && !d->one_vector_p
- && GET_MODE_SIZE (d->vmode) == 8 ? d->nelt : 0;
+ && GET_MODE_SIZE (d->vmode) == 8 ? nelt : 0;
first_elem = d->perm[neon_endian_lane_map (d->vmode, 0)] ^ swap_nelt;
static bool
arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
{
- unsigned int i, high, mask, nelt = d->nelt;
+ unsigned int i, high, mask, nelt = d->perm.length ();
rtx out0, out1, in0, in1;
rtx (*gen)(rtx, rtx, rtx, rtx);
int first_elem;
static bool
arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
{
- unsigned int i, j, diff, nelt = d->nelt;
+ unsigned int i, j, diff, nelt = d->perm.length ();
rtx (*gen)(rtx, rtx);
if (!d->one_vector_p)
static bool
arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
{
- unsigned int i, odd, mask, nelt = d->nelt;
+ unsigned int i, odd, mask, nelt = d->perm.length ();
rtx out0, out1, in0, in1;
rtx (*gen)(rtx, rtx, rtx, rtx);
static bool
arm_evpc_neon_vext (struct expand_vec_perm_d *d)
{
- unsigned int i, nelt = d->nelt;
+ unsigned int i, nelt = d->perm.length ();
rtx (*gen) (rtx, rtx, rtx, rtx);
rtx offset;
{
rtx rperm[MAX_VECT_LEN], sel;
machine_mode vmode = d->vmode;
- unsigned int i, nelt = d->nelt;
+ unsigned int i, nelt = d->perm.length ();
/* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
numbering of elements for big-endian, we must reverse the order. */
/* The pattern matching functions above are written to look for a small
number to begin the sequence (0, 1, N/2). If we begin with an index
from the second operand, we can swap the operands. */
- if (d->perm[0] >= d->nelt)
+ unsigned int nelt = d->perm.length ();
+ if (d->perm[0] >= nelt)
{
- unsigned i, nelt = d->nelt;
-
- for (i = 0; i < nelt; ++i)
+ for (unsigned int i = 0; i < nelt; ++i)
d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
std::swap (d->op0, d->op1);
d.vmode = GET_MODE (target);
gcc_assert (VECTOR_MODE_P (d.vmode));
- d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
d.testing_p = false;
+ nelt = GET_MODE_NUNITS (d.vmode);
+ d.perm.reserve (nelt);
for (i = which = 0; i < nelt; ++i)
{
rtx e = XVECEXP (sel, 0, i);
int ei = INTVAL (e) & (2 * nelt - 1);
which |= (ei < nelt ? 1 : 2);
- d.perm[i] = ei;
+ d.perm.quick_push (ei);
}
switch (which)
/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
static bool
-arm_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+arm_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
struct expand_vec_perm_d d;
unsigned int i, nelt, which;
bool ret;
d.vmode = vmode;
- d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
d.testing_p = true;
- memcpy (d.perm, sel, nelt);
+ d.perm.safe_splice (sel);
/* Categorize the set of elements in the selector. */
+ nelt = GET_MODE_NUNITS (d.vmode);
for (i = which = 0; i < nelt; ++i)
{
unsigned char e = d.perm[i];
/* Implement targetm.vectorize.vec_perm_const_ok. */
static bool
-ix86_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+ix86_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
struct expand_vec_perm_d d;
unsigned int i, nelt, which;
/* Extract the values from the vector CST into the permutation
array in D. */
- memcpy (d.perm, sel, nelt);
for (i = which = 0; i < nelt; ++i)
{
- unsigned char e = d.perm[i];
+ unsigned char e = sel[i];
gcc_assert (e < 2 * nelt);
+ d.perm[i] = e;
which |= (e < nelt ? 1 : 2);
}
static section * ia64_hpux_function_section (tree, enum node_frequency,
bool, bool);
-static bool ia64_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel);
+static bool ia64_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices);
static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode);
static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode);
/* Implement targetm.vectorize.vec_perm_const_ok. */
static bool
-ia64_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+ia64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
struct expand_vec_perm_d d;
unsigned int i, nelt, which;
/* Extract the values from the vector CST into the permutation
array in D. */
- memcpy (d.perm, sel, nelt);
for (i = which = 0; i < nelt; ++i)
{
- unsigned char e = d.perm[i];
+ unsigned char e = sel[i];
+ d.perm[i] = e;
gcc_assert (e < 2 * nelt);
which |= (e < nelt ? 1 : 2);
}
/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
static bool
-mips_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+mips_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
struct expand_vec_perm_d d;
unsigned int i, nelt, which;
d.vmode = vmode;
d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
d.testing_p = true;
- memcpy (d.perm, sel, nelt);
/* Categorize the set of elements in the selector. */
for (i = which = 0; i < nelt; ++i)
{
- unsigned char e = d.perm[i];
+ unsigned char e = sel[i];
+ d.perm[i] = e;
gcc_assert (e < 2 * nelt);
which |= (e < nelt ? 1 : 2);
}
/* Test whether a constant permutation is supported. */
static bool
-rs6000_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
/* AltiVec (and thus VSX) can handle arbitrary permutations. */
if (TARGET_ALTIVEC)
/* Test whether a constant permutation is supported. */
static bool
-rs6000_vectorize_vec_perm_const_ok (machine_mode vmode,
- const unsigned char *sel)
+rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel)
{
/* AltiVec (and thus VSX) can handle arbitrary permutations. */
if (TARGET_ALTIVEC)
Return true if vector alignment is reachable (by peeling N iterations) for the given scalar type @var{type}. @var{is_packed} is false if the scalar access using @var{type} is known to be naturally aligned.
@end deftypefn
-@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST_OK (machine_mode, const unsigned char *@var{sel})
+@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST_OK (machine_mode, @var{vec_perm_indices})
Return true if a vector created for @code{vec_perm_const} is valid.
@end deftypefn
if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing
&& (sel == NULL
|| targetm.vectorize.vec_perm_const_ok == NULL
- || targetm.vectorize.vec_perm_const_ok (mode, &(*sel)[0])))
+ || targetm.vectorize.vec_perm_const_ok (mode, *sel)))
return true;
}
DEFHOOK
(vec_perm_const_ok,
"Return true if a vector created for @code{vec_perm_const} is valid.",
- bool, (machine_mode, const unsigned char *sel),
+ bool, (machine_mode, vec_perm_indices),
NULL)
/* Return true if the target supports misaligned store/load of a
projects / platform / upstream / gcc.git / commitdiff