arm64: dts: juno: add GPU subsystem

Since we now have bindings for Mali Midgard GPUs, let's use them to
describe Juno's GPU subsystem, if only because we can. Juno sports a
Mali-T624 integrated behind an MMU-400 (as a gesture towards
virtualisation), in their own dedicated power domain with DVFS
controlled by the SCP.

CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
index 47bc1ac..018f3ae 100644 (file)
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
@@ -24,6 +24,10 @@ properties:
           - const: arm,mali-t820
       - items:
           - enum:
+             - arm,juno-mali
+          - const: arm,mali-t624
+      - items:
+          - enum:
              - rockchip,rk3288-mali
           - const: arm,mali-t760
       - items:
@@ -39,7 +43,6 @@ properties:
              - samsung,exynos5433-mali
           - const: arm,mali-t760
 
-          # "arm,mali-t624"
           # "arm,mali-t628"
           # "arm,mali-t830"
           # "arm,mali-t880"

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 26a039a..9e3e8ce 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -35,6 +35,18 @@
                clock-names = "apb_pclk";
        };
 
+       smmu_gpu: iommu@2b400000 {
+               compatible = "arm,mmu-400", "arm,smmu-v1";
+               reg = <0x0 0x2b400000 0x0 0x10000>;
+               interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               #global-interrupts = <1>;
+               power-domains = <&scpi_devpd 1>;
+               dma-coherent;
+               status = "disabled";
+       };
+
        smmu_pcie: iommu@2b500000 {
                compatible = "arm,mmu-401", "arm,smmu-v1";
                reg = <0x0 0x2b500000 0x0 0x10000>;
@@ -487,6 +499,21 @@
                };
        };
 
+       gpu: gpu@2d000000 {
+               compatible = "arm,juno-mali", "arm,mali-t624";
+               reg = <0 0x2d000000 0 0x10000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "gpu", "job", "mmu";
+               clocks = <&scpi_dvfs 2>;
+               power-domains = <&scpi_devpd 1>;
+               dma-coherent;
+               /* The SMMU is only really of interest to bare-metal hypervisors */
+               /* iommus = <&smmu_gpu 0>; */
+               status = "disabled";
+       };
+
        sram: sram@2e000000 {
                compatible = "arm,juno-sram-ns", "mmio-sram";
                reg = <0x0 0x2e000000 0x0 0x8000>;