lpc32xx: cpu: add support for soft reset

Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).

To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index f757474..bee9318 100644 (file)
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -20,12 +20,23 @@ void reset_cpu(ulong addr)
        /* Enable watchdog clock */
        setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
 
-       /* Reset pulse length is 13005 peripheral clock frames */
-       writel(13000, &wdt->pulse);
+       /* To be compatible with the original U-Boot code:
+        * addr: - 0: perform hard reset.
+        *       - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
+       if (addr == 0) {
+               /* Reset pulse length is 13005 peripheral clock frames */
+               writel(13000, &wdt->pulse);
 
-       /* Force WDOG_RESET2 and RESOUT_N signal active */
-       writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
-              &wdt->mctrl);
+               /* Force WDOG_RESET2 and RESOUT_N signal active */
+               writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
+                      | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
+       } else {
+               /* Force match output active */
+               writel(0x01, &wdt->emr);
+
+               /* Internal reset on match output (no pulse on "RESOUT_N") */
+               writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
+       }
 
        while (1)
                /* NOP */;