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clk: ingenic: Fix incorrect data for the i2s clock
author
Paul Cercueil
<paul@crapouillou.net>
Wed, 27 Jun 2018 12:14:58 +0000
(14:14 +0200)
committer
Stephen Boyd
<sboyd@kernel.org>
Fri, 6 Jul 2018 18:47:27 +0000
(11:47 -0700)
The register field for configuring the divider for the i2s clock
occupies the bits [8-0], which means 9 bits and not 8.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4740-cgu.c
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diff --git
a/drivers/clk/ingenic/jz4740-cgu.c
b/drivers/clk/ingenic/jz4740-cgu.c
index
32fcc75
..
bc073dd
100644
(file)
--- a/
drivers/clk/ingenic/jz4740-cgu.c
+++ b/
drivers/clk/ingenic/jz4740-cgu.c
@@
-134,7
+134,7
@@
static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 31, 1 },
- .div = { CGU_REG_I2SCDR, 0, 1,
8
, -1, -1, -1 },
+ .div = { CGU_REG_I2SCDR, 0, 1,
9
, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 6 },
},