drivers/hwmon/adcxx.c: fix for single-channel ADCs

While testing an ADC121S021 in an embedded board with a S3C2142 SoC (ARM
core), I have found that the 'adcxx' driver does not handle correctly
single channel ADCs from this chip family.  For single channel chips you
must only issue one read transfer for correct measurement.

Signed-off-by: Jose Miguel Goncalves <jose.goncalves@inov.pt>
Cc: Marc Pignat <marc.pignat@hevs.ch>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/drivers/hwmon/adcxx.c b/drivers/hwmon/adcxx.c
index 5e9e095..74d9c51 100644 (file)
--- a/drivers/hwmon/adcxx.c
+++ b/drivers/hwmon/adcxx.c
@@ -62,18 +62,23 @@ static ssize_t adcxx_read(struct device *dev,
        struct spi_device *spi = to_spi_device(dev);
        struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
        struct adcxx *adc = dev_get_drvdata(&spi->dev);
-       u8 tx_buf[2] = { attr->index << 3 }; /* other bits are don't care */
+       u8 tx_buf[2];
        u8 rx_buf[2];
        int status;
-       int value;
+       u32 value;
 
        if (mutex_lock_interruptible(&adc->lock))
                return -ERESTARTSYS;
 
-       status = spi_write_then_read(spi, tx_buf, sizeof(tx_buf),
-                                       rx_buf, sizeof(rx_buf));
+       if (adc->channels == 1) {
+               status = spi_read(spi, rx_buf, sizeof(rx_buf));
+       } else {
+               tx_buf[0] = attr->index << 3; /* other bits are don't care */
+               status = spi_write_then_read(spi, tx_buf, sizeof(tx_buf),
+                                               rx_buf, sizeof(rx_buf));
+       }
        if (status < 0) {
-               dev_warn(dev, "spi_write_then_read failed with status %d\n",
+               dev_warn(dev, "SPI synch. transfer failed with status %d\n",
                                status);
                goto out;
        }