mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG

Add support for:
 GD5F1GQ4RExxG
 GD5F2GQ4{U,R}ExxG

These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
and capacity.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com

diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index da77ab20296eac09b40f9f0f5455bc59bf2eed7e..85a61d3d846737c4a33c74ad377921d5b6ef256a 100644 (file)
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -333,6 +333,36 @@ static const struct spinand_info gigadevice_spinand_table[] = {
                     SPINAND_HAS_QE_BIT,
                     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
                                     gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F1GQ4RExxG",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+                    NAND_ECCREQ(8, 512),
+                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+                                             &write_cache_variants,
+                                             &update_cache_variants),
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F2GQ4UExxG",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+                    NAND_ECCREQ(8, 512),
+                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+                                             &write_cache_variants,
+                                             &update_cache_variants),
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F2GQ4RExxG",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+                    NAND_ECCREQ(8, 512),
+                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+                                             &write_cache_variants,
+                                             &update_cache_variants),
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
        SPINAND_INFO("GD5F1GQ4UFxxG",
                     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
                     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),