CLK: HSDK: CGU: add support for 148.5MHz clock

Add support for 148.5MHz clock for HDMI PLL

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af5..b4f8852 100644 (file)
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 
 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
        { 27000000,   0, 0,  0, 0, 1 },
+       { 148500000,  0, 21, 3, 0, 0 },
        { 297000000,  0, 21, 2, 0, 0 },
        { 540000000,  0, 19, 1, 0, 0 },
        { 594000000,  0, 21, 1, 0, 0 },