}
}
#ifdef DEBUG_EXEC
- if ((loglevel & CPU_LOG_TB_CPU)) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
/* restore flags in standard format */
regs_to_env();
#if defined(TARGET_I386)
#if defined (HARD_DEBUG_PPC_IO)
#define PPC_IO_DPRINTF(fmt, args...) \
do { \
- if (loglevel & CPU_LOG_IOPORT) { \
+ if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
qemu_log("%s: " fmt, __func__ , ##args); \
} else { \
printf("%s : " fmt, __func__ , ##args); \
}
#if defined ALPHA_DEBUG_DISAS
log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, ctx.pc - pc_start, 1);
qemu_log("\n");
*gen_opc_ptr = INDEX_op_end;
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
unsigned int insn_len = 2;
int i;
- if (unlikely(loglevel & CPU_LOG_TB_OP))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
dc->cpustate_changed = 0;
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log(
"srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
"pid=%x usp=%x\n"
#ifdef DEBUG_DISAS
#if !DISAS_CRIS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
log_target_disas(pc_start, dc->pc - pc_start, 0);
qemu_log("\nisize=%d osize=%zd\n",
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
void do_interrupt(int intno, int is_int, int error_code,
target_ulong next_eip, int is_hw)
{
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
if ((env->cr[0] & CR0_PE_MASK)) {
static int count;
qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
target_ulong next_eip, tval;
int rex_w, rex_r;
- if (unlikely(loglevel & CPU_LOG_TB_OP))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(pc_start);
s->pc = pc_start;
prefixes = 0;
#ifdef DEBUG_DISAS
log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
int disas_flags;
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
{
int cc_op;
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_OP) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
int i;
qemu_log("RESTORE:\n");
for(i = 0;i <= pc_pos; i++) {
*gen_opc_ptr = INDEX_op_end;
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("----------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, dc->pc - pc_start, 0);
old = env->CP0_Status;
env->CP0_Status = (env->CP0_Status & ~mask) | val;
compute_hflags(env);
- if (loglevel & CPU_LOG_EXEC)
+ if (qemu_loglevel_mask(CPU_LOG_EXEC))
do_mtc0_status_debug(old, val);
cpu_mips_update_irq(env);
}
static void debug_pre_eret (void)
{
- if (loglevel & CPU_LOG_EXEC) {
+ if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
if (env->CP0_Status & (1 << CP0St_ERL))
static void debug_post_eret (void)
{
- if (loglevel & CPU_LOG_EXEC) {
+ if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
if (env->CP0_Status & (1 << CP0St_ERL))
}
#ifdef DEBUG_DISAS
LOG_DISAS("\n");
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
#if defined(DEBUG_DISAS)
qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
int flags;
flags = env->bfd_mach;
flags |= ctx.le_mode << 16;
}
}
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname;
switch (env->exception_index) {
case 0x0e0:
#ifdef SH4_DEBUG_DISAS
qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
#endif
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
log_target_disas(pc_start, ctx.pc - pc_start, 0);
qemu_log("\n");
int intno = env->exception_index;
#ifdef DEBUG_PCALL
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
int cwp, intno = env->exception_index;
#ifdef DEBUG_PCALL
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
{
unsigned int insn, opc, rs1, rs2, rd;
- if (unlikely(loglevel & CPU_LOG_TB_OP))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
insn = ldl_code(dc->pc);
opc = GET_FIELD(insn, 0, 1);
tb->icount = num_insns;
}
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
const TCGArg *args;
#ifdef DEBUG_DISAS
- if (unlikely(loglevel & CPU_LOG_TB_OP)) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
qemu_log("OP:\n");
tcg_dump_ops(s, logfile);
qemu_log("\n");
#endif
#ifdef DEBUG_DISAS
- if (unlikely(loglevel & CPU_LOG_TB_OP_OPT)) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
qemu_log("OP after la:\n");
tcg_dump_ops(s, logfile);
qemu_log("\n");
#endif
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_OUT_ASM) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
qemu_log("OUT: [size=%d]\n", *gen_code_size_ptr);
log_disas(tb->tc_ptr, *gen_code_size_ptr);
qemu_log("\n");