phy: qcom-qmp: move PCS V3 registers to separate headers

Move PCS V3 registers to the separate headers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-15-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
new file mode 100644 (file)
index 0000000..a45bd30
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
+#define QCOM_PHY_QMP_PCS_MISC_V3_H_
+
+/* Only for QMP V3 PHY - PCS_MISC registers */
+#define QPHY_V3_PCS_MISC_CLAMP_ENABLE                  0x0c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2              0x2c
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1      0x44
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2                0x54
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4                0x5c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5                0x60
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
new file mode 100644 (file)
index 0000000..0b023df
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V3_H_
+#define QCOM_PHY_QMP_PCS_V3_H_
+
+/* Only for QMP V3 PHY - PCS registers */
+#define QPHY_V3_PCS_POWER_DOWN_CONTROL                 0x004
+#define QPHY_V3_PCS_TXMGN_V0                           0x00c
+#define QPHY_V3_PCS_TXMGN_V1                           0x010
+#define QPHY_V3_PCS_TXMGN_V2                           0x014
+#define QPHY_V3_PCS_TXMGN_V3                           0x018
+#define QPHY_V3_PCS_TXMGN_V4                           0x01c
+#define QPHY_V3_PCS_TXMGN_LS                           0x020
+#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL               0x02c
+#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL               0x034
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0                   0x024
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0                 0x028
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1                   0x02c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1                 0x030
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2                   0x034
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2                 0x038
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3                   0x03c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3                 0x040
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4                   0x044
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4                 0x048
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS                   0x04c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS                 0x050
+#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE              0x054
+#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL                 0x058
+#define QPHY_V3_PCS_RATE_SLEW_CNTRL                    0x05c
+#define QPHY_V3_PCS_POWER_STATE_CONFIG1                        0x060
+#define QPHY_V3_PCS_POWER_STATE_CONFIG2                        0x064
+#define QPHY_V3_PCS_POWER_STATE_CONFIG4                        0x06c
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L               0x070
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H               0x074
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L                 0x078
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H                 0x07c
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1                        0x080
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2                        0x084
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3                        0x088
+#define QPHY_V3_PCS_TSYNC_RSYNC_TIME                   0x08c
+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK                0x0a0
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK          0x0a4
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME              0x0a8
+#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK            0x0b0
+#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME             0x0b8
+#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME              0x0bc
+#define QPHY_V3_PCS_FLL_CNTRL1                         0x0c4
+#define QPHY_V3_PCS_FLL_CNTRL2                         0x0c8
+#define QPHY_V3_PCS_FLL_CNT_VAL_L                      0x0cc
+#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL                  0x0d0
+#define QPHY_V3_PCS_FLL_MAN_CODE                       0x0d4
+#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL                 0x134
+#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME                        0x138
+#define QPHY_V3_PCS_RX_SIGDET_CTRL1                    0x13c
+#define QPHY_V3_PCS_RX_SIGDET_CTRL2                    0x140
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB      0x1a8
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS                   0x1ac
+#define QPHY_V3_PCS_SIGDET_CNTRL                       0x1b0
+#define QPHY_V3_PCS_TX_MID_TERM_CTRL1                  0x1bc
+#define QPHY_V3_PCS_MULTI_LANE_CTRL1                   0x1c4
+#define QPHY_V3_PCS_RX_SIGDET_LVL                      0x1d8
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB    0x1dc
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB    0x1e0
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1                 0x20c
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2                 0x210
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1bb57d1..1290c62 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -22,6 +22,9 @@
 
 #include "phy-qcom-qmp-pcs-v2.h"
 
+#include "phy-qcom-qmp-pcs-v3.h"
+#include "phy-qcom-qmp-pcs-misc-v3.h"
+
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00
 #define QPHY_V3_DP_COM_SW_RESET                                0x04
@@ -46,76 +49,6 @@
 # define DP_PHY_TXn_TX_DRV_LVL_MASK                    0x001f
 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN                  0x0020
 
-/* Only for QMP V3 PHY - PCS registers */
-#define QPHY_V3_PCS_POWER_DOWN_CONTROL                 0x004
-#define QPHY_V3_PCS_TXMGN_V0                           0x00c
-#define QPHY_V3_PCS_TXMGN_V1                           0x010
-#define QPHY_V3_PCS_TXMGN_V2                           0x014
-#define QPHY_V3_PCS_TXMGN_V3                           0x018
-#define QPHY_V3_PCS_TXMGN_V4                           0x01c
-#define QPHY_V3_PCS_TXMGN_LS                           0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL               0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL               0x034
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0                   0x024
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0                 0x028
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1                   0x02c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1                 0x030
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2                   0x034
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2                 0x038
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3                   0x03c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3                 0x040
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4                   0x044
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4                 0x048
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS                   0x04c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS                 0x050
-#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE              0x054
-#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL                 0x058
-#define QPHY_V3_PCS_RATE_SLEW_CNTRL                    0x05c
-#define QPHY_V3_PCS_POWER_STATE_CONFIG1                        0x060
-#define QPHY_V3_PCS_POWER_STATE_CONFIG2                        0x064
-#define QPHY_V3_PCS_POWER_STATE_CONFIG4                        0x06c
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L               0x070
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H               0x074
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L                 0x078
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H                 0x07c
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1                        0x080
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2                        0x084
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3                        0x088
-#define QPHY_V3_PCS_TSYNC_RSYNC_TIME                   0x08c
-#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK                0x0a0
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK          0x0a4
-#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME              0x0a8
-#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK            0x0b0
-#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME             0x0b8
-#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME              0x0bc
-#define QPHY_V3_PCS_FLL_CNTRL1                         0x0c4
-#define QPHY_V3_PCS_FLL_CNTRL2                         0x0c8
-#define QPHY_V3_PCS_FLL_CNT_VAL_L                      0x0cc
-#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL                  0x0d0
-#define QPHY_V3_PCS_FLL_MAN_CODE                       0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL                 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME                        0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1                    0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2                    0x140
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB      0x1a8
-#define QPHY_V3_PCS_OSC_DTCT_ACTIONS                   0x1ac
-#define QPHY_V3_PCS_SIGDET_CNTRL                       0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1                  0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1                   0x1c4
-#define QPHY_V3_PCS_RX_SIGDET_LVL                      0x1d8
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB    0x1dc
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB    0x1e0
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1                 0x20c
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2                 0x210
-
-/* Only for QMP V3 PHY - PCS_MISC registers */
-#define QPHY_V3_PCS_MISC_CLAMP_ENABLE                  0x0c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2              0x2c
-#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1      0x44
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2                0x54
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4                0x5c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5                0x60
-
 /* QMP PHY - DP PHY registers */
 #define QSERDES_DP_PHY_REVISION_ID0                    0x000
 #define QSERDES_DP_PHY_REVISION_ID1                    0x004