[AArch64] [Obvious] Correct pattern target requirement

Had mistakenly used a target macro that was not defined and not the
relevant one instead of the macro that should be used.

TARGET_ARMV8_6 is not defined, and also not the macro we want to check.
Instead check TARGET_F64MM.

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
	the correct target macro.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 993986a..1b71f75 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>
 
+       * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
+       correct target macro.
+
+2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>
+
        * config/aarch64/aarch64-protos.h
        (aarch64_sve_ld1ro_operand_p): New.
        * config/aarch64/aarch64-sve-builtins-base.cc

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 59b1192..2532902 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2502,7 +2502,7 @@
           (match_operand:OI 1 "aarch64_sve_ld1ro_operand_<Vesize>"
                               "UO<Vesize>")]
          UNSPEC_LD1RO))]
-  "TARGET_SVE && TARGET_ARMV8_6"
+  "TARGET_SVE && TARGET_F64MM"
   {
     operands[1] = gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0));
     return "ld1ro<Vesize>\t%0.<Vetype>, %2/z, %1";