MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7671437..f113b91 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -26,6 +26,8 @@ config TARGET_MALTA
        select DM
        select DM_SERIAL
        select DYNAMIC_IO_PORT_BASE
+       select MIPS_CM
+       select MIPS_L2_CACHE
        select OF_CONTROL
        select OF_ISA_BUS
        select SUPPORTS_BIG_ENDIAN

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 3d48cdc..6df4d9f 100644 (file)
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -28,12 +28,6 @@
 
        .globl  lowlevel_init
 lowlevel_init:
-       /* disable any L2 cache for now */
-       sync
-       mfc0    t0, CP0_CONFIG, 2
-       ori     t0, t0, 0x1 << 12
-       mtc0    t0, CP0_CONFIG, 2
-
        /* detect the core card */
        PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
        lw      t0, 0(t0)