MIPS: OCTEON: add fixed-link nodes to in-kernel device tree

Currently OCTEON ethernet falls back to phyless operation on
boards where we have no known PHY address or a fixed-link node.
Add fixed-link support for boards that need it, so we can clean up
the platform code and ethernet driver from some legacy code.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org

diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
index 0fa3dd1..1c50cca 100644 (file)
--- a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
@@ -180,10 +180,18 @@
                                ethernet@0 {
                                        phy-handle = <&phy2>;
                                        cavium,alt-phy-handle = <&phy100>;
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
                                };
                                ethernet@1 {
                                        phy-handle = <&phy3>;
                                        cavium,alt-phy-handle = <&phy101>;
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
                                };
                                ethernet@2 {
                                        phy-handle = <&phy4>;

diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 1f9ba60..b407375 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -458,6 +458,23 @@ static bool __init octeon_has_88e1145(void)
               !OCTEON_IS_MODEL(OCTEON_CN56XX);
 }
 
+static bool __init octeon_has_fixed_link(int ipd_port)
+{
+       switch (cvmx_sysinfo_get()->board_type) {
+       case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+       case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+       case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+       case CVMX_BOARD_TYPE_CUST_NB5:
+       case CVMX_BOARD_TYPE_EBH3100:
+               /* Port 1 on these boards is always gigabit. */
+               return ipd_port == 1;
+       case CVMX_BOARD_TYPE_BBGW_REF:
+               /* Ports 0 and 1 connect to the switch. */
+               return ipd_port == 0 || ipd_port == 1;
+       }
+       return false;
+}
+
 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
 {
        const __be32 *phy_handle;
@@ -592,6 +609,7 @@ static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
        int eth;
        int phy_addr;
        int ipd_port;
+       int fixed_link;
 
        snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
        eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
@@ -609,6 +627,12 @@ static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
 
        phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
        octeon_fdt_set_phy(eth, phy_addr);
+
+       fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link");
+       if (fixed_link < 0)
+               WARN_ON(octeon_has_fixed_link(ipd_port));
+       else if (!octeon_has_fixed_link(ipd_port))
+               fdt_nop_node(initial_boot_params, fixed_link);
 }
 
 static void __init octeon_fdt_pip_iface(int pip, int idx)