drm/i915: Avoid PPS HW/SW state mismatch due to rounding

We store a SW state of the t11_t12 timing in 100usec units but have to
program it in 100msec as required by HW. The rounding used during
programming means there will be a mismatch between the SW and HW states
of this value triggering a "PPS state mismatch" error. Avoid this by
storing the already rounded-up value in the SW state.

Note that we still calculate panel_power_cycle_delay with the finer
100usec granularity to avoid any needless waits using that version of
the delay.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103903
Cc: joks <joks@linux.pl>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171129175137.2889-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dd0b3a0..c603d4c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5355,6 +5355,12 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
         */
        final->t8 = 1;
        final->t9 = 1;
+
+       /*
+        * HW has only a 100msec granularity for t11_t12 so round it up
+        * accordingly.
+        */
+       final->t11_t12 = roundup(final->t11_t12, 100 * 10);
 }
 
 static void