aarch64: Force TImode values into even registers

The LSE CASP instruction requires values to be placed in even
register pairs.  A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.

	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
	16-byte modes held in GP registers to use an even regno.

From-SVN: r265661

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bec7124..1587a51 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
 
+       * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
+       16-byte modes held in GP registers to use an even regno.
+
        * config/aarch64/aarch64.c (aarch64_emit_bic): Remove.
        (aarch64_atomic_ldop_supported_p): Remove.
        (aarch64_gen_atomic_ldop): Remove.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e646cce..9813a9d 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1452,10 +1452,14 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
   if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
     return mode == Pmode;
 
-  if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16))
-    return true;
-
-  if (FP_REGNUM_P (regno))
+  if (GP_REGNUM_P (regno))
+    {
+      if (known_le (GET_MODE_SIZE (mode), 8))
+       return true;
+      else if (known_le (GET_MODE_SIZE (mode), 16))
+       return (regno & 1) == 0;
+    }
+  else if (FP_REGNUM_P (regno))
     {
       if (vec_flags & VEC_STRUCT)
        return end_hard_regno (mode, regno) - 1 <= V31_REGNUM;