drm/amd/display: [FW Promotion] Release 0.0.75

- Add reserved bits for future feature development
- Fix issue with mismatch with type const
- Replaced problematic code with old memcpy and casted problematic
  pointers to unsigned char pointers

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index df43082..8b0b4d8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef _DMUB_CMD_H_
-#define _DMUB_CMD_H_
+#ifndef DMUB_CMD_H
+#define DMUB_CMD_H
 
 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
 #include "dmub_fw_types.h"
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xc761b9efd
+#define DMUB_FW_VERSION_GIT_HASH 0x2d2f6f51e
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 73
+#define DMUB_FW_VERSION_REVISION 75
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -1448,10 +1448,6 @@ struct dmub_cmd_psr_set_level_data {
         * Currently the support is only for 0 or 1
         */
        uint8_t panel_inst;
-       /**
-        * Explicit padding to 4 byte boundary.
-        */
-       uint8_t pad3[4];
 };
 
 /**
@@ -2474,16 +2470,14 @@ static inline bool dmub_rb_full(struct dmub_rb *rb)
 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
                                      const union dmub_rb_cmd *cmd)
 {
-       uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t);
-       const uint64_t *src = (const uint64_t *)cmd;
-       uint8_t i;
+       uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
+       const uint8_t *src = (const uint8_t *)cmd;
 
        if (dmub_rb_full(rb))
                return false;
 
        // copying data
-       for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
-               *dst++ = *src++;
+       dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
 
        rb->wrpt += DMUB_RB_CMD_SIZE;
 
@@ -2590,18 +2584,16 @@ static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
  * @return false otherwise
  */
 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
-                                union dmub_rb_out_cmd  *cmd)
+                                union dmub_rb_out_cmd *cmd)
 {
-       const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
-       uint64_t *dst = (uint64_t *)cmd;
-       uint8_t i;
+       const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr;
+       uint8_t *dst = (uint8_t *)cmd;
 
        if (dmub_rb_empty(rb))
                return false;
 
        // copying data
-       for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
-               *dst++ = *src++;
+       dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
 
        return true;
 }
@@ -2641,11 +2633,9 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
        uint32_t wptr = rb->wrpt;
 
        while (rptr != wptr) {
-               uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t);
-               uint8_t i;
+               const uint8_t *data = (const uint8_t *)rb->base_address + rptr;
 
-               for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
-                       *data++;
+               dmub_memcpy(buf, data, DMUB_RB_CMD_SIZE);
 
                rptr += DMUB_RB_CMD_SIZE;
                if (rptr >= rb->capacity)