drm/radeon/kms: refactor atombios power state fetching
authorAlex Deucher <alexdeucher@gmail.com>
Mon, 22 Nov 2010 22:56:34 +0000 (17:56 -0500)
committerDave Airlie <airlied@redhat.com>
Mon, 22 Nov 2010 23:23:31 +0000 (09:23 +1000)
The function was getting too large.  Rework it to share
more state better handle new power table formats.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/radeon_atombios.c

index 4d37b2d..7056e20 100644 (file)
@@ -1763,495 +1763,504 @@ static const char *pp_lib_thermal_controller_names[] = {
        "RV6xx",
        "RV770",
        "adt7473",
+       "NONE",
        "External GPIO",
        "Evergreen",
        "adt7473 with internal",
-
 };
 
 union power_info {
        struct _ATOM_POWERPLAY_INFO info;
        struct _ATOM_POWERPLAY_INFO_V2 info_2;
        struct _ATOM_POWERPLAY_INFO_V3 info_3;
-       struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
+       struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 };
 
-void radeon_atombios_get_power_modes(struct radeon_device *rdev)
+union pplib_clock_info {
+       struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
+       struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
+       struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
+};
+
+union pplib_power_state {
+       struct _ATOM_PPLIB_STATE v1;
+       struct _ATOM_PPLIB_STATE_V2 v2;
+};
+
+static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
+                                                int state_index,
+                                                u32 misc, u32 misc2)
+{
+       rdev->pm.power_state[state_index].misc = misc;
+       rdev->pm.power_state[state_index].misc2 = misc2;
+       /* order matters! */
+       if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_POWERSAVE;
+       if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BATTERY;
+       if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BATTERY;
+       if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BALANCED;
+       if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_PERFORMANCE;
+               rdev->pm.power_state[state_index].flags &=
+                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+       }
+       if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BALANCED;
+       if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_DEFAULT;
+               rdev->pm.default_power_state_index = state_index;
+               rdev->pm.power_state[state_index].default_clock_mode =
+                       &rdev->pm.power_state[state_index].clock_info[0];
+       } else if (state_index == 0) {
+               rdev->pm.power_state[state_index].clock_info[0].flags |=
+                       RADEON_PM_MODE_NO_DISPLAY;
+       }
+}
+
+static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
 {
        struct radeon_mode_info *mode_info = &rdev->mode_info;
+       u32 misc, misc2 = 0;
+       int num_modes = 0, i;
+       int state_index = 0;
+       struct radeon_i2c_bus_rec i2c_bus;
+       union power_info *power_info;
        int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
-       u16 data_offset;
+        u16 data_offset;
        u8 frev, crev;
-       u32 misc, misc2 = 0, sclk, mclk;
-       union power_info *power_info;
-       struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
-       struct _ATOM_PPLIB_STATE *power_state;
-       int num_modes = 0, i, j;
-       int state_index = 0, mode_index = 0;
-       struct radeon_i2c_bus_rec i2c_bus;
-
-       rdev->pm.default_power_state_index = -1;
 
-       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
-                                  &frev, &crev, &data_offset)) {
-               power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
-               if (frev < 4) {
-                       /* add the i2c bus for thermal/fan chip */
-                       if (power_info->info.ucOverdriveThermalController > 0) {
-                               DRM_INFO("Possible %s thermal controller at 0x%02x\n",
-                                        thermal_controller_names[power_info->info.ucOverdriveThermalController],
-                                        power_info->info.ucOverdriveControllerAddress >> 1);
-                               i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
-                               rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
-                               if (rdev->pm.i2c_bus) {
-                                       struct i2c_board_info info = { };
-                                       const char *name = thermal_controller_names[power_info->info.
-                                                                                   ucOverdriveThermalController];
-                                       info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
-                                       strlcpy(info.type, name, sizeof(info.type));
-                                       i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
-                               }
+       if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset))
+               return state_index;
+       power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
+
+       /* add the i2c bus for thermal/fan chip */
+       if (power_info->info.ucOverdriveThermalController > 0) {
+               DRM_INFO("Possible %s thermal controller at 0x%02x\n",
+                        thermal_controller_names[power_info->info.ucOverdriveThermalController],
+                        power_info->info.ucOverdriveControllerAddress >> 1);
+               i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
+               rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
+               if (rdev->pm.i2c_bus) {
+                       struct i2c_board_info info = { };
+                       const char *name = thermal_controller_names[power_info->info.
+                                                                   ucOverdriveThermalController];
+                       info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
+                       strlcpy(info.type, name, sizeof(info.type));
+                       i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
+               }
+       }
+       num_modes = power_info->info.ucNumOfPowerModeEntries;
+       if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
+               num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
+       /* last mode is usually default, array is low to high */
+       for (i = 0; i < num_modes; i++) {
+               rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
+               switch (frev) {
+               case 1:
+                       rdev->pm.power_state[state_index].num_clock_modes = 1;
+                       rdev->pm.power_state[state_index].clock_info[0].mclk =
+                               le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
+                       rdev->pm.power_state[state_index].clock_info[0].sclk =
+                               le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
+                       /* skip invalid modes */
+                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
+                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
+                               continue;
+                       rdev->pm.power_state[state_index].pcie_lanes =
+                               power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
+                       misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
+                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_GPIO;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
+                                       radeon_lookup_gpio(rdev,
+                                                          power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
+                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               true;
+                               else
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               false;
+                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_VDDC;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
+                                       power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
                        }
-                       num_modes = power_info->info.ucNumOfPowerModeEntries;
-                       if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
-                               num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
-                       /* last mode is usually default, array is low to high */
-                       for (i = 0; i < num_modes; i++) {
-                               rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
-                               switch (frev) {
-                               case 1:
-                                       rdev->pm.power_state[state_index].num_clock_modes = 1;
-                                       rdev->pm.power_state[state_index].clock_info[0].mclk =
-                                               le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
-                                       rdev->pm.power_state[state_index].clock_info[0].sclk =
-                                               le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
-                                       /* skip invalid modes */
-                                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
-                                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
-                                               continue;
-                                       rdev->pm.power_state[state_index].pcie_lanes =
-                                               power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
-                                       misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
-                                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
-                                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_GPIO;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
-                                                       radeon_lookup_gpio(rdev,
-                                                       power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
-                                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               true;
-                                               else
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               false;
-                                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_VDDC;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
-                                                       power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
-                                       }
-                                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       rdev->pm.power_state[state_index].misc = misc;
-                                       /* order matters! */
-                                       if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_POWERSAVE;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                       if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_PERFORMANCE;
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       }
-                                       if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_DEFAULT;
-                                               rdev->pm.default_power_state_index = state_index;
-                                               rdev->pm.power_state[state_index].default_clock_mode =
-                                                       &rdev->pm.power_state[state_index].clock_info[0];
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       } else if (state_index == 0) {
-                                               rdev->pm.power_state[state_index].clock_info[0].flags |=
-                                                       RADEON_PM_MODE_NO_DISPLAY;
-                                       }
-                                       state_index++;
-                                       break;
-                               case 2:
-                                       rdev->pm.power_state[state_index].num_clock_modes = 1;
-                                       rdev->pm.power_state[state_index].clock_info[0].mclk =
-                                               le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
-                                       rdev->pm.power_state[state_index].clock_info[0].sclk =
-                                               le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
-                                       /* skip invalid modes */
-                                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
-                                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
-                                               continue;
-                                       rdev->pm.power_state[state_index].pcie_lanes =
-                                               power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
-                                       misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
-                                       misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
-                                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
-                                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_GPIO;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
-                                                       radeon_lookup_gpio(rdev,
-                                                       power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
-                                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               true;
-                                               else
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               false;
-                                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_VDDC;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
-                                                       power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
-                                       }
-                                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       rdev->pm.power_state[state_index].misc = misc;
-                                       rdev->pm.power_state[state_index].misc2 = misc2;
-                                       /* order matters! */
-                                       if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_POWERSAVE;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                       if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_PERFORMANCE;
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       }
-                                       if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                       if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_DEFAULT;
-                                               rdev->pm.default_power_state_index = state_index;
-                                               rdev->pm.power_state[state_index].default_clock_mode =
-                                                       &rdev->pm.power_state[state_index].clock_info[0];
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       } else if (state_index == 0) {
-                                               rdev->pm.power_state[state_index].clock_info[0].flags |=
-                                                       RADEON_PM_MODE_NO_DISPLAY;
-                                       }
-                                       state_index++;
-                                       break;
-                               case 3:
-                                       rdev->pm.power_state[state_index].num_clock_modes = 1;
-                                       rdev->pm.power_state[state_index].clock_info[0].mclk =
-                                               le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
-                                       rdev->pm.power_state[state_index].clock_info[0].sclk =
-                                               le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
-                                       /* skip invalid modes */
-                                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
-                                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
-                                               continue;
-                                       rdev->pm.power_state[state_index].pcie_lanes =
-                                               power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
-                                       misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
-                                       misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
-                                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
-                                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_GPIO;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
-                                                       radeon_lookup_gpio(rdev,
-                                                       power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
-                                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               true;
-                                               else
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
-                                                               false;
-                                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
-                                                       VOLTAGE_VDDC;
-                                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
-                                                       power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
-                                               if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
-                                                               true;
-                                                       rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
-                                                       power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
-                                               }
-                                       }
-                                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       rdev->pm.power_state[state_index].misc = misc;
-                                       rdev->pm.power_state[state_index].misc2 = misc2;
-                                       /* order matters! */
-                                       if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_POWERSAVE;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                       if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                       if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_PERFORMANCE;
-                                               rdev->pm.power_state[state_index].flags &=
-                                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       }
-                                       if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                       if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_DEFAULT;
-                                               rdev->pm.default_power_state_index = state_index;
-                                               rdev->pm.power_state[state_index].default_clock_mode =
-                                                       &rdev->pm.power_state[state_index].clock_info[0];
-                                       } else if (state_index == 0) {
-                                               rdev->pm.power_state[state_index].clock_info[0].flags |=
-                                                       RADEON_PM_MODE_NO_DISPLAY;
-                                       }
-                                       state_index++;
-                                       break;
-                               }
+                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+                       radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
+                       state_index++;
+                       break;
+               case 2:
+                       rdev->pm.power_state[state_index].num_clock_modes = 1;
+                       rdev->pm.power_state[state_index].clock_info[0].mclk =
+                               le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
+                       rdev->pm.power_state[state_index].clock_info[0].sclk =
+                               le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
+                       /* skip invalid modes */
+                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
+                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
+                               continue;
+                       rdev->pm.power_state[state_index].pcie_lanes =
+                               power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
+                       misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
+                       misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
+                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_GPIO;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
+                                       radeon_lookup_gpio(rdev,
+                                                          power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
+                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               true;
+                               else
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               false;
+                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_VDDC;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
+                                       power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
                        }
-                       /* last mode is usually default */
-                       if (rdev->pm.default_power_state_index == -1) {
-                               rdev->pm.power_state[state_index - 1].type =
-                                       POWER_STATE_TYPE_DEFAULT;
-                               rdev->pm.default_power_state_index = state_index - 1;
-                               rdev->pm.power_state[state_index - 1].default_clock_mode =
-                                       &rdev->pm.power_state[state_index - 1].clock_info[0];
-                               rdev->pm.power_state[state_index].flags &=
-                                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                               rdev->pm.power_state[state_index].misc = 0;
-                               rdev->pm.power_state[state_index].misc2 = 0;
+                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+                       radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
+                       state_index++;
+                       break;
+               case 3:
+                       rdev->pm.power_state[state_index].num_clock_modes = 1;
+                       rdev->pm.power_state[state_index].clock_info[0].mclk =
+                               le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
+                       rdev->pm.power_state[state_index].clock_info[0].sclk =
+                               le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
+                       /* skip invalid modes */
+                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
+                           (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
+                               continue;
+                       rdev->pm.power_state[state_index].pcie_lanes =
+                               power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
+                       misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
+                       misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
+                       if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+                           (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_GPIO;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
+                                       radeon_lookup_gpio(rdev,
+                                                          power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
+                               if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               true;
+                               else
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
+                                               false;
+                       } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.type =
+                                       VOLTAGE_VDDC;
+                               rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
+                                       power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
+                               if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
+                                               true;
+                                       rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
+                                               power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
+                               }
                        }
+                       rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+                       radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
+                       state_index++;
+                       break;
+               }
+       }
+       /* last mode is usually default */
+       if (rdev->pm.default_power_state_index == -1) {
+               rdev->pm.power_state[state_index - 1].type =
+                       POWER_STATE_TYPE_DEFAULT;
+               rdev->pm.default_power_state_index = state_index - 1;
+               rdev->pm.power_state[state_index - 1].default_clock_mode =
+                       &rdev->pm.power_state[state_index - 1].clock_info[0];
+               rdev->pm.power_state[state_index].flags &=
+                       ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+               rdev->pm.power_state[state_index].misc = 0;
+               rdev->pm.power_state[state_index].misc2 = 0;
+       }
+       return state_index;
+}
+
+static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
+                                                        ATOM_PPLIB_THERMALCONTROLLER *controller)
+{
+       struct radeon_i2c_bus_rec i2c_bus;
+
+       /* add the i2c bus for thermal/fan chip */
+       if (controller->ucType > 0) {
+               if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
+                       DRM_INFO("Internal thermal controller %s fan control\n",
+                                (controller->ucFanParameters &
+                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                       rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
+               } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
+                       DRM_INFO("Internal thermal controller %s fan control\n",
+                                (controller->ucFanParameters &
+                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                       rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
+               } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
+                       DRM_INFO("Internal thermal controller %s fan control\n",
+                                (controller->ucFanParameters &
+                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                       rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
+               } else if ((controller->ucType ==
+                           ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
+                          (controller->ucType ==
+                           ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
+                       DRM_INFO("Special thermal controller config\n");
                } else {
-                       int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-                       uint8_t fw_frev, fw_crev;
-                       uint16_t fw_data_offset, vddc = 0;
-                       union firmware_info *firmware_info;
-                       ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
-
-                       if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
-                                                  &fw_frev, &fw_crev, &fw_data_offset)) {
-                               firmware_info =
-                                       (union firmware_info *)(mode_info->atom_context->bios +
-                                                               fw_data_offset);
-                               vddc = firmware_info->info_14.usBootUpVDDCVoltage;
+                       DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
+                                pp_lib_thermal_controller_names[controller->ucType],
+                                controller->ucI2cAddress >> 1,
+                                (controller->ucFanParameters &
+                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
+                       i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
+                       rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
+                       if (rdev->pm.i2c_bus) {
+                               struct i2c_board_info info = { };
+                               const char *name = pp_lib_thermal_controller_names[controller->ucType];
+                               info.addr = controller->ucI2cAddress >> 1;
+                               strlcpy(info.type, name, sizeof(info.type));
+                               i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
                        }
+               }
+       }
+}
 
-                       /* add the i2c bus for thermal/fan chip */
-                       if (controller->ucType > 0) {
-                               if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
-                                       DRM_INFO("Internal thermal controller %s fan control\n",
-                                                (controller->ucFanParameters &
-                                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
-                                       rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
-                               } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
-                                       DRM_INFO("Internal thermal controller %s fan control\n",
-                                                (controller->ucFanParameters &
-                                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
-                                       rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
-                               } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
-                                       DRM_INFO("Internal thermal controller %s fan control\n",
-                                                (controller->ucFanParameters &
-                                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
-                                       rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
-                               } else if ((controller->ucType ==
-                                           ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
-                                          (controller->ucType ==
-                                           ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
-                                       DRM_INFO("Special thermal controller config\n");
-                               } else {
-                                       DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
-                                                pp_lib_thermal_controller_names[controller->ucType],
-                                                controller->ucI2cAddress >> 1,
-                                                (controller->ucFanParameters &
-                                                 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
-                                       i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
-                                       rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
-                                       if (rdev->pm.i2c_bus) {
-                                               struct i2c_board_info info = { };
-                                               const char *name = pp_lib_thermal_controller_names[controller->ucType];
-                                               info.addr = controller->ucI2cAddress >> 1;
-                                               strlcpy(info.type, name, sizeof(info.type));
-                                               i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
-                                       }
+static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
+{
+       struct radeon_mode_info *mode_info = &rdev->mode_info;
+       int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
+       u8 frev, crev;
+       u16 data_offset;
+       union firmware_info *firmware_info;
+       u16 vddc = 0;
 
-                               }
-                       }
-                       /* first mode is usually default, followed by low to high */
-                       for (i = 0; i < power_info->info_4.ucNumStates; i++) {
-                               mode_index = 0;
-                               power_state = (struct _ATOM_PPLIB_STATE *)
-                                       (mode_info->atom_context->bios +
-                                        data_offset +
-                                        le16_to_cpu(power_info->info_4.usStateArrayOffset) +
-                                        i * power_info->info_4.ucStateEntrySize);
-                               non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
-                                       (mode_info->atom_context->bios +
-                                        data_offset +
-                                        le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
-                                        (power_state->ucNonClockStateIndex *
-                                         power_info->info_4.ucNonClockSize));
-                               for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
-                                       if (rdev->flags & RADEON_IS_IGP) {
-                                               struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
-                                                       (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
-                                                       (mode_info->atom_context->bios +
-                                                        data_offset +
-                                                        le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
-                                                        (power_state->ucClockStateIndices[j] *
-                                                         power_info->info_4.ucClockInfoSize));
-                                               sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
-                                               sclk |= clock_info->ucLowEngineClockHigh << 16;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
-                                               /* skip invalid modes */
-                                               if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
-                                                       continue;
-                                               /* voltage works differently on IGPs */
-                                               mode_index++;
-                                       } else if (ASIC_IS_DCE4(rdev)) {
-                                               struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
-                                                       (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
-                                                       (mode_info->atom_context->bios +
-                                                        data_offset +
-                                                        le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
-                                                        (power_state->ucClockStateIndices[j] *
-                                                         power_info->info_4.ucClockInfoSize));
-                                               sclk = le16_to_cpu(clock_info->usEngineClockLow);
-                                               sclk |= clock_info->ucEngineClockHigh << 16;
-                                               mclk = le16_to_cpu(clock_info->usMemoryClockLow);
-                                               mclk |= clock_info->ucMemoryClockHigh << 16;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
-                                               /* skip invalid modes */
-                                               if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
-                                                   (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
-                                                       continue;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
-                                                       VOLTAGE_SW;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
-                                                       clock_info->usVDDC;
-                                               /* XXX usVDDCI */
-                                               mode_index++;
-                                       } else {
-                                               struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
-                                                       (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
-                                                       (mode_info->atom_context->bios +
-                                                        data_offset +
-                                                        le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
-                                                        (power_state->ucClockStateIndices[j] *
-                                                         power_info->info_4.ucClockInfoSize));
-                                               sclk = le16_to_cpu(clock_info->usEngineClockLow);
-                                               sclk |= clock_info->ucEngineClockHigh << 16;
-                                               mclk = le16_to_cpu(clock_info->usMemoryClockLow);
-                                               mclk |= clock_info->ucMemoryClockHigh << 16;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
-                                               /* skip invalid modes */
-                                               if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
-                                                   (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
-                                                       continue;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
-                                                       VOLTAGE_SW;
-                                               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
-                                                       clock_info->usVDDC;
-                                               mode_index++;
-                                       }
-                               }
-                               rdev->pm.power_state[state_index].num_clock_modes = mode_index;
-                               if (mode_index) {
-                                       misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
-                                       misc2 = le16_to_cpu(non_clock_info->usClassification);
-                                       rdev->pm.power_state[state_index].misc = misc;
-                                       rdev->pm.power_state[state_index].misc2 = misc2;
-                                       rdev->pm.power_state[state_index].pcie_lanes =
-                                               ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
-                                               ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
-                                       switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
-                                       case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BATTERY;
-                                               break;
-                                       case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_BALANCED;
-                                               break;
-                                       case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_PERFORMANCE;
-                                               break;
-                                       case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
-                                               if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
-                                                       rdev->pm.power_state[state_index].type =
-                                                               POWER_STATE_TYPE_PERFORMANCE;
-                                               break;
-                                       }
-                                       rdev->pm.power_state[state_index].flags = 0;
-                                       if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
-                                               rdev->pm.power_state[state_index].flags |=
-                                                       RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
-                                       if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
-                                               rdev->pm.power_state[state_index].type =
-                                                       POWER_STATE_TYPE_DEFAULT;
-                                               rdev->pm.default_power_state_index = state_index;
-                                               rdev->pm.power_state[state_index].default_clock_mode =
-                                                       &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
-                                               /* patch the table values with the default slck/mclk from firmware info */
-                                               for (j = 0; j < mode_index; j++) {
-                                                       rdev->pm.power_state[state_index].clock_info[j].mclk =
-                                                               rdev->clock.default_mclk;
-                                                       rdev->pm.power_state[state_index].clock_info[j].sclk =
-                                                               rdev->clock.default_sclk;
-                                                       if (vddc)
-                                                               rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
-                                                                       vddc;
-                                               }
-                                       }
-                                       state_index++;
-                               }
-                       }
-                       /* if multiple clock modes, mark the lowest as no display */
-                       for (i = 0; i < state_index; i++) {
-                               if (rdev->pm.power_state[i].num_clock_modes > 1)
-                                       rdev->pm.power_state[i].clock_info[0].flags |=
-                                               RADEON_PM_MODE_NO_DISPLAY;
-                       }
-                       /* first mode is usually default */
-                       if (rdev->pm.default_power_state_index == -1) {
-                               rdev->pm.power_state[0].type =
-                                       POWER_STATE_TYPE_DEFAULT;
-                               rdev->pm.default_power_state_index = 0;
-                               rdev->pm.power_state[0].default_clock_mode =
-                                       &rdev->pm.power_state[0].clock_info[0];
-                       }
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               firmware_info =
+                       (union firmware_info *)(mode_info->atom_context->bios +
+                                               data_offset);
+               vddc = firmware_info->info_14.usBootUpVDDCVoltage;
+       }
+
+       return vddc;
+}
+
+static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
+                                                      int state_index, int mode_index,
+                                                      struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
+{
+       int j;
+       u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
+       u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
+       u16 vddc = radeon_atombios_get_default_vddc(rdev);
+
+       rdev->pm.power_state[state_index].misc = misc;
+       rdev->pm.power_state[state_index].misc2 = misc2;
+       rdev->pm.power_state[state_index].pcie_lanes =
+               ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
+                ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
+       switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
+       case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BATTERY;
+               break;
+       case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_BALANCED;
+               break;
+       case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_PERFORMANCE;
+               break;
+       case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
+               if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
+                       rdev->pm.power_state[state_index].type =
+                               POWER_STATE_TYPE_PERFORMANCE;
+               break;
+       }
+       rdev->pm.power_state[state_index].flags = 0;
+       if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
+               rdev->pm.power_state[state_index].flags |=
+                       RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
+       if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
+               rdev->pm.power_state[state_index].type =
+                       POWER_STATE_TYPE_DEFAULT;
+               rdev->pm.default_power_state_index = state_index;
+               rdev->pm.power_state[state_index].default_clock_mode =
+                       &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
+               /* patch the table values with the default slck/mclk from firmware info */
+               for (j = 0; j < mode_index; j++) {
+                       rdev->pm.power_state[state_index].clock_info[j].mclk =
+                               rdev->clock.default_mclk;
+                       rdev->pm.power_state[state_index].clock_info[j].sclk =
+                               rdev->clock.default_sclk;
+                       if (vddc)
+                               rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+                                       vddc;
+               }
+       }
+}
+
+static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
+                                                  int state_index, int mode_index,
+                                                  union pplib_clock_info *clock_info)
+{
+       u32 sclk, mclk;
+
+       if (rdev->flags & RADEON_IS_IGP) {
+               sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
+               sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
+               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
+       } else if (ASIC_IS_DCE4(rdev)) {
+               sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
+               sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
+               mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
+               mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
+               rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
+               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
+               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
+                       VOLTAGE_SW;
+               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
+                       clock_info->evergreen.usVDDC;
+       } else {
+               sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
+               sclk |= clock_info->r600.ucEngineClockHigh << 16;
+               mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
+               mclk |= clock_info->r600.ucMemoryClockHigh << 16;
+               rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
+               rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
+               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
+                       VOLTAGE_SW;
+               rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
+                       clock_info->r600.usVDDC;
+       }
+
+       if (rdev->flags & RADEON_IS_IGP) {
+               /* skip invalid modes */
+               if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
+                       return false;
+       } else {
+               /* skip invalid modes */
+               if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
+                   (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
+                       return false;
+       }
+       return true;
+}
+
+static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
+{
+       struct radeon_mode_info *mode_info = &rdev->mode_info;
+       struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
+       union pplib_power_state *power_state;
+       int i, j;
+       int state_index = 0, mode_index = 0;
+       union pplib_clock_info *clock_info;
+       bool valid;
+       union power_info *power_info;
+       int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
+        u16 data_offset;
+       u8 frev, crev;
+
+       if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset))
+               return state_index;
+       power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
+
+       radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
+       /* first mode is usually default, followed by low to high */
+       for (i = 0; i < power_info->pplib.ucNumStates; i++) {
+               mode_index = 0;
+               power_state = (union pplib_power_state *)
+                       (mode_info->atom_context->bios + data_offset +
+                        le16_to_cpu(power_info->pplib.usStateArrayOffset) +
+                        i * power_info->pplib.ucStateEntrySize);
+               non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
+                       (mode_info->atom_context->bios + data_offset +
+                        le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
+                        (power_state->v1.ucNonClockStateIndex *
+                         power_info->pplib.ucNonClockSize));
+               for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
+                       clock_info = (union pplib_clock_info *)
+                               (mode_info->atom_context->bios + data_offset +
+                                le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
+                                (power_state->v1.ucClockStateIndices[j] *
+                                 power_info->pplib.ucClockInfoSize));
+                       valid = radeon_atombios_parse_pplib_clock_info(rdev,
+                                                                      state_index, mode_index,
+                                                                      clock_info);
+                       if (valid)
+                               mode_index++;
+               }
+               rdev->pm.power_state[state_index].num_clock_modes = mode_index;
+               if (mode_index) {
+                       radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
+                                                                  non_clock_info);
+                       state_index++;
+               }
+       }
+       /* if multiple clock modes, mark the lowest as no display */
+       for (i = 0; i < state_index; i++) {
+               if (rdev->pm.power_state[i].num_clock_modes > 1)
+                       rdev->pm.power_state[i].clock_info[0].flags |=
+                               RADEON_PM_MODE_NO_DISPLAY;
+       }
+       /* first mode is usually default */
+       if (rdev->pm.default_power_state_index == -1) {
+               rdev->pm.power_state[0].type =
+                       POWER_STATE_TYPE_DEFAULT;
+               rdev->pm.default_power_state_index = 0;
+               rdev->pm.power_state[0].default_clock_mode =
+                       &rdev->pm.power_state[0].clock_info[0];
+       }
+       return state_index;
+}
+
+void radeon_atombios_get_power_modes(struct radeon_device *rdev)
+{
+       struct radeon_mode_info *mode_info = &rdev->mode_info;
+       int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
+       u16 data_offset;
+       u8 frev, crev;
+       int state_index = 0;
+
+       rdev->pm.default_power_state_index = -1;
+
+       if (atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               switch (frev) {
+               case 1:
+               case 2:
+               case 3:
+                       state_index = radeon_atombios_parse_power_table_1_3(rdev);
+                       break;
+               case 4:
+               case 5:
+                       state_index = radeon_atombios_parse_power_table_4_5(rdev);
+                       break;
+               default:
+                       break;
                }
        } else {
                /* add the default mode */