ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiers
authorCristian Ciocaltea <cristian.ciocaltea@gmail.com>
Fri, 28 Aug 2020 13:53:17 +0000 (16:53 +0300)
committerManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tue, 22 Sep 2020 07:15:52 +0000 (12:45 +0530)
The PPI interrupts for cortex-a9 were incorrectly specified, fix them.

Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
arch/arm/boot/dts/owl-s500.dtsi

index 5ceb6cc..1dbe4e8 100644 (file)
                global_timer: timer@b0020200 {
                        compatible = "arm,cortex-a9-global-timer";
                        reg = <0xb0020200 0x100>;
-                       interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+                       interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
                        status = "disabled";
                };
 
                twd_timer: timer@b0020600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xb0020600 0x20>;
-                       interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
                        status = "disabled";
                };
 
                twd_wdt: wdt@b0020620 {
                        compatible = "arm,cortex-a9-twd-wdt";
                        reg = <0xb0020620 0xe0>;
-                       interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+                       interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
                        status = "disabled";
                };