/errlog
/reloc_off
+/include/generated/
+/lib/asm-offsets.s
+
# stgit generated dirs
patches-*
.stgit-edit.txt
E: guillaume.alexandre@gespac.ch
D: Add PCIPPC6 configuration
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA & NETPHONE board support, ARTOS support.
E: aheppel@sysgo.de
D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
-N: August Hoeraendl
-E: august.hoerandl@gmx.at
-D: Support for the logodl board (PXA2xx)
-
N: Josh Huber
E: huber@alum.wpi.edu
D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
E: thomas@corelatus.se
D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
-N: Marc Leeman
-E: marc.leeman@barco.com
-D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
-W: www.barco.com
-
N: The LEOX team
E: team@leox.org
D: Support for LEOX boards, DS164x RTC
N: Robert Schwebel
E: r.schwebel@pengutronix.de
-D: Support for csb226, logodl and innokom boards (PXA2xx)
+D: Support for csb226 and innokom boards (PXA2xx)
N: Aaron Sells
E: sellsa@embeddedplanet.com
IVMS8_256 MPC860
LANTEC MPC850
LWMON MPC823
- NC650 MPC852
R360MPI MPC823
RMU MPC850
RRvision MPC823
c2mon MPC855
hermes MPC860
lwmon MPC823
- pcu_e MPC855
CU824 MPC8240
Sandpoint8240 MPC8240
dlvision PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
+ io PPC405EP
+ iocon PPC405EP
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>
ipek01 MPC5200
- CCM MPC855
-
PN62 MPC8240
IPHASE4539 MPC8260
SCM MPC8260
PPChameleonEVB PPC405EP
-Reinhard Meyer <r.meyer@emk-elektronik.de>
+Tirumala Marri <tmarri@apm.com>
+
+ bluestone APM821XX
+
+Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 MPC860T
TOP5200 MPC5200
+ TOP9000 ARM926EJS (AT91SAM9xxx SoC)
Tolunay Orkun <torkun@nextio.com>
sbc8240 MPC8240
sbc405 PPC405GP
+Sergei Poselenov <sposelenov@emcraft.com>
+
+ a4m072 MPC5200
+
Sudhakar Rajashekhara <sudhakar.raj@ti.com>
da850evm ARM926EJS (DA850/OMAP-L138)
Heiko Schocher <hs@denx.de>
+ charon MPC5200
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
Peter Tyser <ptyser@xes-inc.com>
- XPEDITE1000 PPC440GX
- XPEDITE5170 MPC8640
- XPEDITE5200 MPC8548
- XPEDITE5370 MPC8572
+ xpedite1000 PPC440GX
+ xpedite5170 MPC8640
+ xpedite5200 MPC8548
+ xpedite5370 MPC8572
+ xpedite5500 P2020
David Updegraff <dave@cray.com>
RPXClassic MPC8xx
RPXlite MPC8xx
- ERIC PPC4xx
-
MOUSSE MPC824x
RPXsuper MPC8260
Stefano Babic <sbabic@denx.de>
+ ea20 davinci
polaris xscale
trizepsiv xscale
mx51evk i.MX51
+ vision2 i.MX51
+
+Enric Balletbo i Serra <eballetbo@iseebcn.com>
+
+ igep0020 ARM ARMV7 (OMAP3xx SoC)
+ igep0030 ARM ARMV7 (OMAP3xx SoC)
Dirk Behme <dirk.behme@gmail.com>
omap5912osk ARM926EJS
+Andreas Bießmann <andreas.devel@gmail.com>
+
+ at91rm9200ek at91rm9200
+
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
a320evb FA526 (ARM920T-like) (a320 SoC)
+Eric Cooper <ecc@cmu.edu>
+
+ dockstar ARM926EJS (Kirkwood SoC)
+
George G. Davis <gdavis@mvista.com>
assabet SA1100
modnet50 ARM720T (NET+50)
+Kristoffer Ericson <kristoffer.ericson@gmail.com>
+
+ jornada SA1110
+
Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
Konstantin Kletschke <kletschke@synertronixx.de>
scb9328 ARM920T
-Simon Kagstrom <simon.kagstrom@netinsight.net>
-
- openrd_base ARM926EJS (Kirkwood SoC)
-
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
cm4116 ks8695p
cm4148 ks8695p
+Marek Vasut <marek.vasut@gmail.com>
+
+ balloon3 xscale
+ colibri_pxa270 xscale
+ palmld xscale
+ palmtc xscale
+ vpac270 xscale
+ zipitz2 xscale
+
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
SFFSDR ARM926EJS
+Matt Waddel <matt.waddel@linaro.org>
+
+ ca9x4_ct_vxp ARM ARMV7 (Quad Core)
+
Prafulla Wadaskar <prafulla@marvell.com>
+ aspenite ARM926EJS (ARMADA100 88AP168 SoC)
mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
+ openrd_base ARM926EJS (Kirkwood SoC)
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
lart SA1100
dnp1110 SA1110
+Syed Mohammed Khasim <sm.khasim@gmail.com>
+Sughosh Ganu <urwithsughosh@gmail.com>
+
+ hawkboard ARM926EJS (OMAP-L138)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
BF526-EZBRD BF526
BF527-EZKIT BF527
BF527-EZKIT-V2 BF527
+ BF527-SDP BF527
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-PNAV BF537
BF537-srv1 BF537
Wojtek Skulski <skulski@pas.rochester.edu>
+Wojtek Skulski <info@skutek.com>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
Benjamin Matthews <mben12@gmail.com>
- BLACKSTAMP BF532
+ BlackStamp BF533
+ BlackVME BF561
I-SYST Micromodule <support@i-syst.com>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
IP04 BF532
+Peter Meerwald <devel@bct-electronic.com>
+
+ bct-brettl2 BF536
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
#!/bin/bash
+# Tool mainly for U-Boot Quality Assurance: build one or more board
+# configurations with minimal verbosity, showing only warnings and
+# errors.
+#
+# There are several ways to select which boards to build.
+#
+# Traditionally, architecture names (like "powerpc"), CPU family names
+# (like "mpc83xx") or board names can be specified on the command
+# line; without any arguments, MAKEALL defaults to building all Power
+# Architecture systems (i. e. same as for "MAKEALL powerpc").
+#
+# With the introduction of the board.cfg file, it has become possible
+# to provide additional selections. We use standard command line
+# options for this:
+#
+# -a or --arch : Select architecture
+# -c or --cpu : Select CPU family
+# -s or --soc : Select SoC type
+# -v or --vendor: Select board vendor
+#
+# Selections by these options are logically ANDed; if the same option
+# is used repeatedly, such selections are ORed. So "-v FOO -v BAR"
+# will select all configurations where the vendor is either FOO or
+# BAR. Any additional arguments specified on the command line are
+# always build additionally.
+#
+# Examples:
+#
+# - build all Power Architecture boards:
+#
+# MAKEALL -a powerpc
+# or
+# MAKEALL --arch powerpc
+# or
+# MAKEALL powerpc
+#
+# - build all PowerPC boards manufactured by vendor "esd":
+#
+# MAKEALL -a powerpc -v esd
+#
+# - build all PowerPC boards manufactured either by "keymile" or
+# "siemens":
+#
+# MAKEALL -a powerpc -v keymile -v siemens
+#
+# - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards:
+#
+# MAKEALL -c mpc83xx -v freescale 4xx
+#
+#########################################################################
+
+SHORT_OPTS="a:c:v:s:"
+LONG_OPTS="arch:,cpu:,vendor:,soc:"
+
+# Option processing based on util-linux-2.13/getopt-parse.bash
+
+# Note that we use `"$@"' to let each command-line parameter expand to a
+# separate word. The quotes around `$@' are essential!
+# We need TEMP as the `eval set --' would nuke the return value of
+# getopt.
+TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \
+ -n 'MAKEALL' -- "$@"`
+
+if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi
+
+# Note the quotes around `$TEMP': they are essential!
+eval set -- "$TEMP"
+
+SELECTED=''
+
+while true ; do
+ case "$1" in
+ -a|--arch)
+ # echo "Option ARCH: argument \`$2'"
+ if [ "$opt_a" ] ; then
+ opt_a="${opt_a%)} || \$2 == \"$2\")"
+ else
+ opt_a="(\$2 == \"$2\")"
+ fi
+ SELECTED='y'
+ shift 2 ;;
+ -c|--cpu)
+ # echo "Option CPU: argument \`$2'"
+ if [ "$opt_c" ] ; then
+ opt_c="${opt_c%)} || \$3 == \"$2\")"
+ else
+ opt_c="(\$3 == \"$2\")"
+ fi
+ SELECTED='y'
+ shift 2 ;;
+ -s|--soc)
+ # echo "Option SoC: argument \`$2'"
+ if [ "$opt_s" ] ; then
+ opt_s="${opt_s%)} || \$6 == \"$2\")"
+ else
+ opt_s="(\$6 == \"$2\")"
+ fi
+ SELECTED='y'
+ shift 2 ;;
+ -v|--vendor)
+ # echo "Option VENDOR: argument \`$2'"
+ if [ "$opt_v" ] ; then
+ opt_v="${opt_v%)} || \$5 == \"$2\")"
+ else
+ opt_v="(\$5 == \"$2\")"
+ fi
+ SELECTED='y'
+ shift 2 ;;
+ --)
+ shift ; break ;;
+ *)
+ echo "Internal error!" >&2 ; exit 1 ;;
+ esac
+done
+# echo "Remaining arguments:"
+# for arg do echo '--> '"\`$arg'" ; done
+
+FILTER="\$1 !~ /^#/"
+[ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
+[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
+[ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
+[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+
+if [ "$SELECTED" ] ; then
+ SELECTED=$(awk '('"$FILTER"') { print $1 }' boards.cfg)
+
+ # Make sure some boards from boards.cfg are actually found
+ if [ -z "$SELECTED" ] ; then
+ echo "Error: No boards selected, invalid arguments"
+ exit 1
+ fi
+fi
+
+#########################################################################
+
# Print statistics when we exit
trap exit 1 2 3 15
trap print_stats 0
}
boards_by_arch() { boards_by_field 2 "$@" ; }
boards_by_cpu() { boards_by_field 3 "$@" ; }
+boards_by_soc() { boards_by_field 6 "$@" ; }
#########################################################################
## MPC5xx Systems
## MPC5xxx Systems
#########################################################################
-LIST_5xxx="$(boards_by_cpu mpc5xxx)
- digsy_mtc \
- EVAL5200 \
- fo300 \
- galaxy5200 \
- icecube_5200 \
- lite5200b \
- mcc200 \
- MVBC_P \
- MVSMR \
- pcm030 \
- PM520 \
- TB5200 \
- Total5200 \
- Total5200_Rev2 \
- TQM5200 \
- TQM5200_B \
- TQM5200S \
-"
+LIST_5xxx="$(boards_by_cpu mpc5xxx)"
#########################################################################
## MPC512x Systems
#########################################################################
-LIST_512x="$(boards_by_cpu mpc512x)
- mpc5121ads \
-"
+LIST_512x="$(boards_by_cpu mpc512x)"
#########################################################################
## MPC8xx Systems
#########################################################################
-LIST_8xx="$(boards_by_cpu mpc8xx)
- Adder87x \
- AdderII \
- ADS860 \
- FADS823 \
- FADS850SAR \
- FADS860T \
- FPS850L \
- GEN860T \
- GEN860T_SC \
- ICU862_100MHz \
- IVML24 \
- IVML24_128 \
- IVML24_256 \
- IVMS8 \
- IVMS8_128 \
- IVMS8_256 \
- MBX \
- MBX860T \
- MPC86xADS \
- MPC885ADS \
- NETPHONE \
- NETTA \
- NETTA2 \
- NETTA_ISDN \
- NETVIA \
- NETVIA_V2 \
- RPXlite_DW \
- SPD823TS \
- SXNI855T \
- TK885D \
- TQM823L \
- TQM823L_LCD \
- TQM850L \
- TQM855L \
- TQM860L \
- TQM885D \
- v37 \
-"
+LIST_8xx="$(boards_by_cpu mpc8xx)"
#########################################################################
## PPC4xx Systems
#########################################################################
-LIST_4xx="$(boards_by_cpu ppc4xx)
- acadia_nand \
- arches \
- bamboo_nand \
- canyonlands \
- canyonlands_nand \
- CPCI405 \
- CPCI4052 \
- CPCI405AB \
- CPCI405DT \
- devconcenter \
- fx12mm \
- glacier \
- haleakala \
- haleakala_nand \
- hcu4 \
- hcu5 \
- intip \
- kilauea \
- kilauea_nand \
- mcu25 \
- MIP405T \
- ml507 \
- ml507_flash \
- OCRTC \
- ORSG \
- PPChameleonEVB \
- rainier \
- sequoia \
- sequoia_nand \
- v5fx30teval \
- v5fx30teval_flash \
- W7OLMC \
- W7OLMG \
- walnut \
- xilinx-ppc440-generic \
- xilinx-ppc440-generic_flash \
- yellowstone \
- yosemite \
-"
+LIST_4xx="$(boards_by_cpu ppc4xx)"
#########################################################################
## MPC8220 Systems
## MPC824x Systems
#########################################################################
-LIST_824x="$(boards_by_cpu mpc824x)
- CPC45 \
- eXalion \
- IDS8247 \
- linkstation_HGLAN \
- Sandpoint8240 \
- Sandpoint8245 \
-"
+LIST_824x="$(boards_by_cpu mpc824x)"
#########################################################################
## MPC8260 Systems (includes 8250, 8255 etc.)
#########################################################################
-LIST_8260="$(boards_by_cpu mpc8260)
- cogent_mpc8260 \
- CPU86 \
- CPU87 \
- ep8248 \
- ISPAN \
- MPC8260ADS \
- MPC8272ADS \
- PM826 \
- PM828 \
- Rattler8248 \
- TQM8260_AC \
- TQM8260_AD \
- TQM8260_AE \
-"
+LIST_8260="$(boards_by_cpu mpc8260)"
#########################################################################
## MPC83xx Systems (includes 8349, etc.)
#########################################################################
-LIST_83xx="$(boards_by_cpu mpc83xx)
- caddy2 \
- MPC8313ERDB_33 \
- MPC8313ERDB_NAND_66 \
- MPC8315ERDB \
- MPC8315ERDB_NAND \
- MPC832XEMDS \
- MPC832XEMDS_ATM \
- MPC8349ITX \
- MPC8349ITXGP \
- MPC8360EMDS \
- MPC8360EMDS_ATM \
- MPC8360ERDK_33 \
- MPC8360ERDK_66 \
- MPC837XEMDS \
- sbc8349 \
- SIMPC8313_LP \
- vme8349 \
-"
-
+LIST_83xx="$(boards_by_cpu mpc83xx)"
#########################################################################
## MPC85xx Systems (includes 8540, 8560 etc.)
#########################################################################
-LIST_85xx="$(boards_by_cpu mpc85xx)
- MPC8536DS \
- MPC8536DS_NAND \
- MPC8536DS_SDCARD \
- MPC8536DS_SPIFLASH \
- MPC8536DS_36BIT \
- MPC8540EVAL \
- MPC8541CDS \
- MPC8548CDS \
- MPC8555CDS \
- MPC8569MDS \
- MPC8569MDS_ATM \
- MPC8569MDS_NAND \
- MPC8572DS \
- MPC8572DS_36BIT \
- P2020DS \
- P2020DS_36BIT \
- P1011RDB \
- P1011RDB_NAND \
- P1011RDB_SDCARD \
- P1011RDB_SPIFLASH \
- P1020RDB \
- P1020RDB_NAND \
- P1020RDB_SDCARD \
- P1020RDB_SPIFLASH \
- P2010RDB \
- P2010RDB_NAND \
- P2010RDB_SDCARD \
- P2010RDB_SPIFLASH \
- P2020RDB \
- P2020RDB_NAND \
- P2020RDB_SDCARD \
- P2020RDB_SPIFLASH \
- sbc8540 \
- sbc8548 \
- sbc8548_PCI_33 \
- sbc8548_PCI_66 \
- sbc8548_PCI_33_PCIE \
- sbc8548_PCI_66_PCIE \
- sbc8560 \
- stxssa \
- TQM8540 \
- TQM8541 \
- TQM8548 \
- TQM8548_AG \
- TQM8548_BE \
- TQM8555 \
- TQM8560 \
-"
+LIST_85xx="$(boards_by_cpu mpc85xx)"
#########################################################################
## MPC86xx Systems
#########################################################################
-LIST_86xx="$(boards_by_cpu mpc86xx)
- MPC8641HPCN_36BIT \
- MPC8641HPCN \
-"
+LIST_86xx="$(boards_by_cpu mpc86xx)"
#########################################################################
## 74xx/7xx Systems
#########################################################################
-LIST_74xx=" \
- DB64360 \
- DB64460 \
- EVB64260 \
- mpc7448hpc2 \
- P3G4 \
- p3m7448 \
- PCIPPC2 \
- PCIPPC6 \
- ZUMA \
-"
-
-LIST_7xx=" \
- BAB7xx \
- CPCI750 \
- ELPPC \
- p3m750 \
- ppmc7xx \
-"
+LIST_74xx_7xx="$(boards_by_cpu 74xx_7xx)"
#########################################################################
## PowerPC groups
${LIST_85xx} \
${LIST_86xx} \
${LIST_4xx} \
- ${LIST_74xx} \
- ${LIST_7xx} \
+ ${LIST_74xx_7xx}\
"
# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
ap926ejs \
ap946es \
ap966 \
+ aspenite \
cp920t \
cp922_XA10 \
cp926ejs \
#########################################################################
LIST_ARMV7=" \
am3517_evm \
+ ca9x4_ct_vxp \
devkit8000 \
+ igep0020 \
+ igep0030 \
mx51evk \
omap3_beagle \
omap3_overo \
## AT91 Systems
#########################################################################
-LIST_at91=" \
- afeb9260 \
- at91cap9adk \
- at91rm9200dk \
- at91rm9200ek \
+LIST_at91="$(boards_by_soc at91)\
+ $(boards_by_soc at91rm9200)\
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9g20ek \
at91sam9m10g45ek \
at91sam9rlek \
- cmc_pu2 \
CPUAT91 \
CPU9260 \
CPU9G20 \
- csb637 \
- eb_cpux9k2 \
- kb9202 \
- meesc \
- mp2usb \
- m501sk \
- otc570 \
- pm9261 \
- pm9263 \
pm9g45 \
SBC35_A9G20 \
TNY_A9260 \
## Xscale Systems
#########################################################################
-LIST_pxa="$(boards_by_cpu pxa)
- polaris \
- trizepsiv \
- vpac270_nor \
- vpac270_onenand \
-"
+LIST_pxa="$(boards_by_cpu pxa)"
LIST_ixp="$(boards_by_cpu ixp)
pdnb3 \
## i386 Systems
#########################################################################
-LIST_x86="$(boards_by_arch i386)
- sc520_eNET \
-"
+LIST_x86="$(boards_by_arch i386)"
#########################################################################
## Nios-II Systems
## Blackfin Systems
#########################################################################
-LIST_blackfin="$(boards_by_arch blackfin)
- bf527-ezkit-v2
-"
+LIST_blackfin="$(boards_by_arch blackfin)"
#########################################################################
## SH Systems
#########################################################################
-LIST_sh2=" \
- rsk7203 \
-"
-LIST_sh3=" \
- mpr2 \
- ms7720se \
-"
-
-LIST_sh4=" \
- ms7750se \
- ms7722se \
- MigoR \
- r7780mp \
- r2dplus \
- sh7763rdp \
- sh7785lcr \
- ap325rxa \
- espt \
-"
+LIST_sh2="$(boards_by_cpu sh2)"
+LIST_sh3="$(boards_by_cpu sh3)"
+LIST_sh4="$(boards_by_cpu sh4)"
-LIST_sh=" \
- ${LIST_sh2} \
- ${LIST_sh3} \
- ${LIST_sh4} \
-"
+LIST_sh="$(boards_by_arch sh)"
#########################################################################
## SPARC Systems
#-----------------------------------------------------------------------
-#----- for now, just run PowerPC by default -----
+# Build target groups selected by options, plus any command line args
+set -- ${SELECTED} "$@"
+# run PowerPC by default
[ $# = 0 ] && set -- powerpc
-
build_targets "$@"
#
VERSION = 2010
-PATCHLEVEL = 09
+PATCHLEVEL = 12
SUBLEVEL =
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
OBJS := $(addprefix $(obj),$(OBJS))
-LIBS = lib/libgeneric.a
-LIBS += lib/lzma/liblzma.a
-LIBS += lib/lzo/liblzo.a
+LIBS = lib/libgeneric.o
+LIBS += lib/lzma/liblzma.o
+LIBS += lib/lzo/liblzo.o
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
- "board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
-LIBS += $(CPUDIR)/lib$(CPU).a
+ "board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
+LIBS += $(CPUDIR)/lib$(CPU).o
ifdef SOC
-LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).a
+LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).o
endif
ifeq ($(CPU),ixp)
-LIBS += arch/arm/cpu/ixp/npe/libnpe.a
+LIBS += arch/arm/cpu/ixp/npe/libnpe.o
endif
-LIBS += arch/$(ARCH)/lib/lib$(ARCH).a
-LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
- fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a \
- fs/ubifs/libubifs.a
-LIBS += net/libnet.a
-LIBS += disk/libdisk.a
-LIBS += drivers/bios_emulator/libatibiosemu.a
-LIBS += drivers/block/libblock.a
-LIBS += drivers/dma/libdma.a
-LIBS += drivers/fpga/libfpga.a
-LIBS += drivers/gpio/libgpio.a
-LIBS += drivers/hwmon/libhwmon.a
-LIBS += drivers/i2c/libi2c.a
-LIBS += drivers/input/libinput.a
-LIBS += drivers/misc/libmisc.a
-LIBS += drivers/mmc/libmmc.a
-LIBS += drivers/mtd/libmtd.a
-LIBS += drivers/mtd/nand/libnand.a
-LIBS += drivers/mtd/onenand/libonenand.a
-LIBS += drivers/mtd/ubi/libubi.a
-LIBS += drivers/mtd/spi/libspi_flash.a
-LIBS += drivers/net/libnet.a
-LIBS += drivers/net/phy/libphy.a
-LIBS += drivers/pci/libpci.a
-LIBS += drivers/pcmcia/libpcmcia.a
-LIBS += drivers/power/libpower.a
-LIBS += drivers/spi/libspi.a
+LIBS += arch/$(ARCH)/lib/lib$(ARCH).o
+LIBS += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
+ fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \
+ fs/ubifs/libubifs.o
+LIBS += net/libnet.o
+LIBS += disk/libdisk.o
+LIBS += drivers/bios_emulator/libatibiosemu.o
+LIBS += drivers/block/libblock.o
+LIBS += drivers/dma/libdma.o
+LIBS += drivers/fpga/libfpga.o
+LIBS += drivers/gpio/libgpio.o
+LIBS += drivers/hwmon/libhwmon.o
+LIBS += drivers/i2c/libi2c.o
+LIBS += drivers/input/libinput.o
+LIBS += drivers/misc/libmisc.o
+LIBS += drivers/mmc/libmmc.o
+LIBS += drivers/mtd/libmtd.o
+LIBS += drivers/mtd/nand/libnand.o
+LIBS += drivers/mtd/onenand/libonenand.o
+LIBS += drivers/mtd/ubi/libubi.o
+LIBS += drivers/mtd/spi/libspi_flash.o
+LIBS += drivers/net/libnet.o
+LIBS += drivers/net/phy/libphy.o
+LIBS += drivers/pci/libpci.o
+LIBS += drivers/pcmcia/libpcmcia.o
+LIBS += drivers/power/libpower.o
+LIBS += drivers/spi/libspi.o
ifeq ($(CPU),mpc83xx)
-LIBS += drivers/qe/qe.a
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
+LIBS += drivers/qe/libqe.o
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc85xx)
-LIBS += drivers/qe/qe.a
-LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
+LIBS += drivers/qe/libqe.o
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
ifeq ($(CPU),mpc86xx)
-LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
endif
-LIBS += drivers/rtc/librtc.a
-LIBS += drivers/serial/libserial.a
-LIBS += drivers/twserial/libtws.a
-LIBS += drivers/usb/gadget/libusb_gadget.a
-LIBS += drivers/usb/host/libusb_host.a
-LIBS += drivers/usb/musb/libusb_musb.a
-LIBS += drivers/usb/phy/libusb_phy.a
-LIBS += drivers/video/libvideo.a
-LIBS += drivers/watchdog/libwatchdog.a
-LIBS += common/libcommon.a
-LIBS += lib/libfdt/libfdt.a
-LIBS += api/libapi.a
-LIBS += post/libpost.a
+LIBS += drivers/rtc/librtc.o
+LIBS += drivers/serial/libserial.o
+LIBS += drivers/twserial/libtws.o
+LIBS += drivers/usb/gadget/libusb_gadget.o
+LIBS += drivers/usb/host/libusb_host.o
+LIBS += drivers/usb/musb/libusb_musb.o
+LIBS += drivers/usb/phy/libusb_phy.o
+LIBS += drivers/video/libvideo.o
+LIBS += drivers/watchdog/libwatchdog.o
+LIBS += common/libcommon.o
+LIBS += lib/libfdt/libfdt.o
+LIBS += api/libapi.o
+LIBS += post/libpost.o
ifeq ($(SOC),omap3)
-LIBS += $(CPUDIR)/omap-common/libomap-common.a
+LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),omap4)
-LIBS += $(CPUDIR)/omap-common/libomap-common.a
+LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),s5pc1xx)
-LIBS += $(CPUDIR)/s5p-common/libs5p-common.a
+LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
ifeq ($(SOC),s5pc2xx)
-LIBS += $(CPUDIR)/s5p-common/libs5p-common.a
+LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
-LIBS := $(addprefix $(obj),$(LIBS))
+LIBS := $(addprefix $(obj),$(sort $(LIBS)))
.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
-LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
# Add GCC lib
ifdef USE_PRIVATE_LIBGCC
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = -L $(OBJTREE)/arch/$(ARCH)/lib -lgcc
+PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o
else
PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
endif
#########################################################################
#########################################################################
+ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
+BOARD_SIZE_CHECK = \
+ @actual=`wc -c $@ | awk '{print $$1}'`; \
+ limit=$(CONFIG_BOARD_SIZE_LIMIT); \
+ if test $$actual -gt $$limit; then \
+ echo "$@ exceeds file size limit:"; \
+ echo " limit: $$limit bytes"; \
+ echo " actual: $$actual bytes"; \
+ echo " excess: $$((actual - limit)) bytes"; \
+ exit 1; \
+ fi
+else
+BOARD_SIZE_CHECK =
+endif
+
# Always append ALL so that arch config.mk's can add custom ones
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) $(U_BOOT_MMC)
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr: $(obj)u-boot
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
+ $(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
$(obj)u-boot.img: $(obj)u-boot.bin
$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
- -a $(TEXT_BASE) -e 0 \
+ -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \
- -e $(TEXT_BASE) -d $< $@
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
- $(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
- -a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@
+ $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
-$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+$(obj)u-boot: depend \
+ $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
smap=`$(call SYSTEM_MAP,u-boot) | \
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
-depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
+ $(obj)include/autoconf.mk \
+ $(obj)include/generated/generic-asm-offsets.h
for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
$(MAKE) -C $$dir _depend ; done
sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
mv $@.tmp $@
+$(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \
+ $(obj)lib/asm-offsets.s
+ @$(XECHO) Generating $@
+ tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
+
+$(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \
+ $(src)lib/asm-offsets.c
+ @mkdir -p $(obj)lib
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $(src)lib/asm-offsets.c -c -S
+
#########################################################################
else # !config.mk
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-#========================================================================
-# PowerPC
-#========================================================================
-
-#########################################################################
-## MPC5xxx Systems
-#########################################################################
-
-digsy_mtc_config \
-digsy_mtc_LOWBOOT_config \
-digsy_mtc_RAMBOOT_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/digsy_mtc
- @ >$(obj)include/config.h
- @[ -z "$(findstring LOWBOOT_,$@)" ] || \
- echo "TEXT_BASE = 0xFF000000" >$(obj)board/digsy_mtc/config.tmp
- @[ -z "$(findstring RAMBOOT_,$@)" ] || \
- echo "TEXT_BASE = 0x00100000" >$(obj)board/digsy_mtc/config.tmp
- @$(MKCONFIG) -n $@ -a digsy_mtc powerpc mpc5xxx digsy_mtc
-
-galaxy5200_LOWBOOT_config \
-galaxy5200_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a galaxy5200 powerpc mpc5xxx galaxy5200
-
-Lite5200_config \
-Lite5200_LOWBOOT_config \
-Lite5200_LOWBOOT08_config \
-icecube_5200_config \
-icecube_5200_LOWBOOT_config \
-icecube_5200_LOWBOOT08_config \
-icecube_5200_DDR_config \
-icecube_5200_DDR_LOWBOOT_config \
-icecube_5200_DDR_LOWBOOT08_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/icecube
- @[ -z "$(findstring LOWBOOT_,$@)" ] || \
- if [ "$(findstring DDR,$@)" ] ; \
- then echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \
- else echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
- fi
- @[ -z "$(findstring LOWBOOT08,$@)" ] || \
- echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp
- @[ -z "$(findstring DDR,$@)" ] || \
- echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a IceCube powerpc mpc5xxx icecube
-
-lite5200b_config \
-lite5200b_PM_config \
-lite5200b_LOWBOOT_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/icecube
- @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
- @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
- @[ -z "$(findstring _PM_,$@)" ] || \
- echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h
- @[ -z "$(findstring LOWBOOT_,$@)" ] || \
- echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp
- @$(MKCONFIG) -n $@ -a IceCube powerpc mpc5xxx icecube
-
-mcc200_config \
-mcc200_SDRAM_config \
-mcc200_highboot_config \
-mcc200_COM12_config \
-mcc200_COM12_SDRAM_config \
-mcc200_COM12_highboot_config \
-mcc200_COM12_highboot_SDRAM_config \
-mcc200_highboot_SDRAM_config \
-prs200_config \
-prs200_DDR_config \
-prs200_highboot_config \
-prs200_highboot_DDR_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/mcc200
- @[ -z "$(findstring highboot,$@)" ] || \
- echo "TEXT_BASE = 0xFFF00000" >$(obj)board/mcc200/config.tmp
- @[ -n "$(findstring _SDRAM,$@)" ] || \
- if [ -n "$(findstring prs200,$@)" ]; \
- then \
- if [ -z "$(findstring _DDR,$@)" ];\
- then \
- echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h ;\
- fi; \
- fi
- @[ -z "$(findstring _SDRAM,$@)" ] || \
- echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h
- @[ -z "$(findstring COM12,$@)" ] || \
- echo "#define CONFIG_CONSOLE_COM12" >>$(obj)include/config.h
- @[ -z "$(findstring prs200,$@)" ] || \
- echo "#define CONFIG_PRS200" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a mcc200 powerpc mpc5xxx mcc200
-
-MVBC_P_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/mvbc_p
- @ >$(obj)include/config.h
- @[ -z "$(findstring MVBC_P,$@)" ] || \
- echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a $@ powerpc mpc5xxx mvbc_p matrix_vision
-
-MVSMR_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/matrix_vision/mvsmr
- @$(MKCONFIG) $@ powerpc mpc5xxx mvsmr matrix_vision
-
-pcm030_config \
-pcm030_LOWBOOT_config: unconfig
- @mkdir -p $(obj)include $(obj)board/phytec/pcm030
- @ >$(obj)include/config.h
- @[ -z "$(findstring LOWBOOT_,$@)" ] || \
- echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp
- @$(MKCONFIG) -n $@ -a pcm030 powerpc mpc5xxx pcm030 phytec
-
-PM520_config \
-PM520_DDR_config \
-PM520_ROMBOOT_config \
-PM520_ROMBOOT_DDR_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring DDR,$@)" ] || \
- echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
- @[ -z "$(findstring ROMBOOT,$@)" ] || \
- echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a PM520 powerpc mpc5xxx pm520
-
-TB5200_B_config \
-TB5200_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _B,$@)" ] || \
- echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a TB5200 powerpc mpc5xxx tqm5200 tqc
-
-MINI5200_config \
-EVAL5200_config \
-TOP5200_config: unconfig
- @mkdir -p $(obj)include
- @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a TOP5200 powerpc mpc5xxx top5200 emk
-
-Total5200_config \
-Total5200_lowboot_config \
-Total5200_Rev2_config \
-Total5200_Rev2_lowboot_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/total5200
- @[ -n "$(findstring Rev,$@)" ] || \
- echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h
- @[ -z "$(findstring Rev2_,$@)" ] || \
- echo "#define CONFIG_TOTAL5200_REV 2" >>$(obj)include/config.h
- @[ -z "$(findstring lowboot_,$@)" ] || \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/total5200/config.tmp
- @$(MKCONFIG) -n $@ -a Total5200 powerpc mpc5xxx total5200
-
-cam5200_config \
-cam5200_niosflash_config \
-fo300_config \
-MiniFAP_config \
-TQM5200S_config \
-TQM5200S_HIGHBOOT_config \
-TQM5200_B_config \
-TQM5200_B_HIGHBOOT_config \
-TQM5200_config \
-TQM5200_STK100_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/tqc/tqm5200
- @[ -z "$(findstring cam5200,$@)" ] || \
- { echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \
- echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
- echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
- }
- @[ -z "$(findstring niosflash,$@)" ] || \
- echo "#define CONFIG_CAM5200_NIOSFLASH" >>$(obj)include/config.h
- @[ -z "$(findstring fo300,$@)" ] || \
- echo "#define CONFIG_FO300" >>$(obj)include/config.h
- @[ -z "$(findstring MiniFAP,$@)" ] || \
- echo "#define CONFIG_MINIFAP" >>$(obj)include/config.h
- @[ -z "$(findstring STK100,$@)" ] || \
- echo "#define CONFIG_STK52XX_REV100" >>$(obj)include/config.h
- @[ -z "$(findstring TQM5200_B,$@)" ] || \
- echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h
- @[ -z "$(findstring TQM5200S,$@)" ] || \
- { echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
- echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
- }
- @[ -z "$(findstring HIGHBOOT,$@)" ] || \
- echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp
- @$(MKCONFIG) -n $@ -a TQM5200 powerpc mpc5xxx tqm5200 tqc
-
-#########################################################################
-## MPC512x Systems
-#########################################################################
-
-mpc5121ads_config \
-mpc5121ads_rev2_config \
- : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring rev2,$@)" ] ; then \
- echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \
- fi
- @$(MKCONFIG) -n $@ -a mpc5121ads powerpc mpc512x mpc5121ads freescale
-
-#########################################################################
-## MPC8xx Systems
-#########################################################################
-
-Adder87x_config \
-AdderII_config \
-AdderUSB_config \
-Adder_config \
- : unconfig
- @mkdir -p $(obj)include
- $(if $(findstring AdderII,$@), \
- @echo "#define CONFIG_MPC852T" > $(obj)include/config.h)
- @$(MKCONFIG) -n $@ -a Adder powerpc mpc8xx adder
-
-ADS860_config \
-FADS823_config \
-FADS850SAR_config \
-MPC86xADS_config \
-MPC885ADS_config \
-FADS860T_config: unconfig
- @$(MKCONFIG) -n $@ $@ powerpc mpc8xx fads
-
-GEN860T_SC_config \
-GEN860T_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _SC,$@)" ] || \
- echo "#define CONFIG_SC" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a GEN860T powerpc mpc8xx gen860t
-
-ICU862_100MHz_config \
-ICU862_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _100MHz,$@)" ] || \
- echo "#define CONFIG_100MHz" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a ICU862 powerpc mpc8xx icu862
-
-IVML24_256_config \
-IVML24_128_config \
-IVML24_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring IVML24_config,$@)" ] || \
- echo "#define CONFIG_IVML24_16M" >>$(obj)include/config.h
- @[ -z "$(findstring IVML24_128_config,$@)" ] || \
- echo "#define CONFIG_IVML24_32M" >>$(obj)include/config.h
- @[ -z "$(findstring IVML24_256_config,$@)" ] || \
- echo "#define CONFIG_IVML24_64M" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a IVML24 powerpc mpc8xx ivm
-
-IVMS8_256_config \
-IVMS8_128_config \
-IVMS8_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring IVMS8_config,$@)" ] || \
- echo "#define CONFIG_IVMS8_16M" >>$(obj)include/config.h
- @[ -z "$(findstring IVMS8_128_config,$@)" ] || \
- echo "#define CONFIG_IVMS8_32M" >>$(obj)include/config.h
- @[ -z "$(findstring IVMS8_256_config,$@)" ] || \
- echo "#define CONFIG_IVMS8_64M" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a IVMS8 powerpc mpc8xx ivm
-
-MBX_config \
-MBX860T_config: unconfig
- @$(MKCONFIG) -n $@ $@ powerpc mpc8xx mbx8xx
-
-NETVIA_V2_config \
-NETVIA_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring NETVIA_config,$@)" ] || \
- echo "#define CONFIG_NETVIA_VERSION 1" >>$(obj)include/config.h
- @[ -z "$(findstring NETVIA_V2_config,$@)" ] || \
- echo "#define CONFIG_NETVIA_VERSION 2" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a NETVIA powerpc mpc8xx netvia
-
-NETPHONE_V2_config \
-NETPHONE_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring NETPHONE_config,$@)" ] || \
- echo "#define CONFIG_NETPHONE_VERSION 1" >>$(obj)include/config.h
- @[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
- echo "#define CONFIG_NETPHONE_VERSION 2" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a NETPHONE powerpc mpc8xx netphone
-
-NETTA_ISDN_6412_SWAPHOOK_config \
-NETTA_ISDN_SWAPHOOK_config \
-NETTA_6412_SWAPHOOK_config \
-NETTA_SWAPHOOK_config \
-NETTA_ISDN_6412_config \
-NETTA_ISDN_config \
-NETTA_6412_config \
-NETTA_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring ISDN_,$@)" ] || \
- echo "#define CONFIG_NETTA_ISDN 1" >>$(obj)include/config.h
- @[ -n "$(findstring ISDN_,$@)" ] || \
- echo "#undef CONFIG_NETTA_ISDN" >>$(obj)include/config.h
- @[ -z "$(findstring 6412_,$@)" ] || \
- echo "#define CONFIG_NETTA_6412 1" >>$(obj)include/config.h
- @[ -n "$(findstring 6412_,$@)" ] || \
- echo "#undef CONFIG_NETTA_6412" >>$(obj)include/config.h
- @[ -z "$(findstring SWAPHOOK_,$@)" ] || \
- echo "#define CONFIG_NETTA_SWAPHOOK 1" >>$(obj)include/config.h
- @[ -n "$(findstring SWAPHOOK_,$@)" ] || \
- echo "#undef CONFIG_NETTA_SWAPHOOK" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a NETTA powerpc mpc8xx netta
-
-NETTA2_V2_config \
-NETTA2_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring NETTA2_config,$@)" ] || \
- echo "#define CONFIG_NETTA2_VERSION 1" >>$(obj)include/config.h
- @[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
- echo "#define CONFIG_NETTA2_VERSION 2" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a NETTA2 powerpc mpc8xx netta2
-
-NC650_Rev1_config \
-NC650_Rev2_config \
-CP850_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring CP850,$@)" ] || \
- { echo "#define CONFIG_CP850 1" >>$(obj)include/config.h ; \
- echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
- }
- @[ -z "$(findstring Rev1,$@)" ] || \
- { echo "#define CONFIG_IDS852_REV1 1" >>$(obj)include/config.h ; \
- }
- @[ -z "$(findstring Rev2,$@)" ] || \
- { echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
- }
- @$(MKCONFIG) -n $@ -a NC650 powerpc mpc8xx nc650
-
-RPXlite_DW_64_config \
-RPXlite_DW_LCD_config \
-RPXlite_DW_64_LCD_config \
-RPXlite_DW_NVRAM_config \
-RPXlite_DW_NVRAM_64_config \
-RPXlite_DW_NVRAM_LCD_config \
-RPXlite_DW_NVRAM_64_LCD_config \
-RPXlite_DW_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _64,$@)" ] || \
- echo "#define RPXlite_64MHz" >>$(obj)include/config.h
- @[ -z "$(findstring _LCD,$@)" ] || \
- { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
- echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
- }
- @[ -z "$(findstring _NVRAM,$@)" ] || \
- echo "#define CONFIG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a RPXlite_DW powerpc mpc8xx RPXlite_dw
-
-RRvision_LCD_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_LCD" >$(obj)include/config.h
- @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
- @$(MKCONFIG) -a RRvision powerpc mpc8xx RRvision
-
-SPD823TS_config: unconfig
- @$(MKCONFIG) $@ powerpc mpc8xx spd8xx
-
-SXNI855T_config: unconfig
- @$(MKCONFIG) $@ powerpc mpc8xx sixnet
-
-# Play some tricks for configuration selection
-# Only 855 and 860 boards may come with FEC
-# and only 823 boards may have LCD support
-xtract_8xx = $(subst _LCD,,$1)
-
-FPS850L_config \
-FPS860L_config \
-NSCU_config \
-TQM823L_config \
-TQM823L_LCD_config \
-TQM850L_config \
-TQM855L_config \
-TQM860L_config \
-TQM862L_config \
-TQM823M_config \
-TQM850M_config \
-TQM855M_config \
-TQM860M_config \
-TQM862M_config \
-TQM866M_config \
-TQM885D_config \
-TK885D_config \
-virtlab2_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _LCD,$@)" ] || \
- { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
- echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
- }
- @$(MKCONFIG) -n $@ -a $(call xtract_8xx,$@) powerpc mpc8xx tqm8xx tqc
-
-TTTech_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_LCD" >$(obj)include/config.h
- @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
- @$(MKCONFIG) -a TQM823L powerpc mpc8xx tqm8xx tqc
-
-v37_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_LCD" >$(obj)include/config.h
- @echo "#define CONFIG_SHARP_LQ084V1DG21" >>$(obj)include/config.h
- @$(MKCONFIG) $@ powerpc mpc8xx v37
-
-wtk_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_LCD" >$(obj)include/config.h
- @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h
- @$(MKCONFIG) -a TQM823L powerpc mpc8xx tqm8xx tqc
-
-#########################################################################
-## PPC4xx Systems
-#########################################################################
-
-acadia_nand_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/acadia
- @mkdir -p $(obj)nand_spl/board/amcc/acadia
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a acadia powerpc ppc4xx acadia amcc
-
-bamboo_nand_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/bamboo
- @mkdir -p $(obj)nand_spl/board/amcc/bamboo
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a bamboo powerpc ppc4xx bamboo amcc
-
-# Arches, Canyonlands & Glacier use different U-Boot images
-arches_config \
-canyonlands_config \
-glacier_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a canyonlands powerpc ppc4xx canyonlands amcc
-
-canyonlands_nand_config \
-glacier_nand_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/canyonlands
- @mkdir -p $(obj)nand_spl/board/amcc/canyonlands
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_nand_config=)) | \
- tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a canyonlands powerpc ppc4xx canyonlands amcc
-
-CATcenter_config \
-CATcenter_25_config \
-CATcenter_33_config: unconfig
- @mkdir -p $(obj)include
- @echo "/* CATcenter uses PPChameleon Model ME */" > $(obj)include/config.h
- @echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> $(obj)include/config.h
- @[ -z "$(findstring _25,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_CLK_25" >> $(obj)include/config.h
- @[ -z "$(findstring _33,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_CLK_33" >> $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a CATcenter powerpc ppc4xx PPChameleonEVB dave
-
-CPCI405_config \
-CPCI4052_config \
-CPCI405DT_config \
-CPCI405AB_config: unconfig
- @mkdir -p $(obj)board/esd/cpci405
- @$(MKCONFIG) -n $@ $@ powerpc ppc4xx cpci405 esd
-
-fx12mm_flash_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
- @mkdir -p $(obj)include $(obj)board/avnet/fx12mm
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
- > $(obj)board/avnet/fx12mm/config.tmp
- @echo "TEXT_BASE := 0xFFCB0000" \
- >> $(obj)board/avnet/fx12mm/config.tmp
- @$(MKCONFIG) fx12mm powerpc ppc4xx fx12mm avnet
-
-fx12mm_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
- @mkdir -p $(obj)include $(obj)board/avnet/fx12mm
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
- > $(obj)board/avnet/fx12mm/config.tmp
- @echo "TEXT_BASE := 0x03000000" \
- >> $(obj)board/avnet/fx12mm/config.tmp
- @$(MKCONFIG) fx12mm powerpc ppc4xx fx12mm avnet
-
-# Compact-Center(codename intip) & DevCon-Center use different U-Boot images
-intip_config \
-devconcenter_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a intip powerpc ppc4xx intip gdsys
-
-hcu4_config \
-hcu5_config \
-mcu25_config: unconfig
- @mkdir -p $(obj)board/netstal/common
- @$(MKCONFIG) $@ powerpc ppc4xx $(call lcname,$@) netstal
-
-# Kilauea & Haleakala images are identical (recognized via PVR)
-kilauea_config \
-haleakala_config: unconfig
- @$(MKCONFIG) -n $@ kilauea powerpc ppc4xx kilauea amcc
-
-kilauea_nand_config \
-haleakala_nand_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/kilauea
- @mkdir -p $(obj)nand_spl/board/amcc/kilauea
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a kilauea powerpc ppc4xx kilauea amcc
-
-MIP405T_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MIP405T" >$(obj)include/config.h
- @$(XECHO) "Enable subset config for MIP405T"
- @$(MKCONFIG) -a MIP405 powerpc ppc4xx mip405 mpl
-
-ml507_flash_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @mkdir -p $(obj)include $(obj)board/xilinx/ml507
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
- > $(obj)board/xilinx/ml507/config.tmp
- @echo "TEXT_BASE := 0xFE360000" \
- >> $(obj)board/xilinx/ml507/config.tmp
- @$(MKCONFIG) ml507 powerpc ppc4xx ml507 xilinx
-
-ml507_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @mkdir -p $(obj)include $(obj)board/xilinx/ml507
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
- > $(obj)board/xilinx/ml507/config.tmp
- @echo "TEXT_BASE := 0x04000000" \
- >> $(obj)board/xilinx/ml507/config.tmp
- @$(MKCONFIG) $@ powerpc ppc4xx ml507 xilinx
-
-OCRTC_config \
-ORSG_config: unconfig
- @$(MKCONFIG) -n $@ $@ powerpc ppc4xx ocrtc esd
-
-PPChameleonEVB_config \
-PPChameleonEVB_BA_25_config \
-PPChameleonEVB_ME_25_config \
-PPChameleonEVB_HI_25_config \
-PPChameleonEVB_BA_33_config \
-PPChameleonEVB_ME_33_config \
-PPChameleonEVB_HI_33_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring EVB_BA,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>$(obj)include/config.h
- @[ -z "$(findstring EVB_ME,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>$(obj)include/config.h
- @[ -z "$(findstring EVB_HI,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>$(obj)include/config.h
- @[ -z "$(findstring _25,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_CLK_25" >>$(obj)include/config.h
- @[ -z "$(findstring _33,$@)" ] || \
- echo "#define CONFIG_PPCHAMELEON_CLK_33" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a PPChameleonEVB powerpc ppc4xx PPChameleonEVB dave
-
-sequoia_config \
-rainier_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
-
-sequoia_nand_config \
-rainier_nand_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/sequoia
- @mkdir -p $(obj)nand_spl/board/amcc/sequoia
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
-
-sequoia_ramboot_config \
-rainier_ramboot_config: unconfig
- @mkdir -p $(obj)include $(obj)board/amcc/sequoia
- @echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
- @echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
- $(obj)board/amcc/sequoia/config.tmp
- @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
-
-v5fx30teval_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
- > $(obj)board/avnet/v5fx30teval/config.tmp
- @echo "TEXT_BASE := 0x03000000" \
- >> $(obj)board/avnet/v5fx30teval/config.tmp
- @$(MKCONFIG) $@ powerpc ppc4xx v5fx30teval avnet
-
-v5fx30teval_flash_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
- > $(obj)board/avnet/v5fx30teval/config.tmp
- @echo "TEXT_BASE := 0xFF1C0000" \
- >> $(obj)board/avnet/v5fx30teval/config.tmp
- @$(MKCONFIG) v5fx30teval powerpc ppc4xx v5fx30teval avnet
-
-W7OLMC_config \
-W7OLMG_config: unconfig
- @$(MKCONFIG) $@ powerpc ppc4xx w7o
-
-# Walnut & Sycamore images are identical (recognized via PVR)
-walnut_config \
-sycamore_config: unconfig
- @$(MKCONFIG) -n $@ walnut powerpc ppc4xx walnut amcc
-
-xilinx-ppc405-generic_flash_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
- > $(obj)board/xilinx/ppc405-generic/config.tmp
- @echo "TEXT_BASE := 0xFE360000" \
- >> $(obj)board/xilinx/ppc405-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx
-
-xilinx-ppc405-generic_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
- > $(obj)board/xilinx/ppc405-generic/config.tmp
- @echo "TEXT_BASE := 0x04000000" \
- >> $(obj)board/xilinx/ppc405-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx
-
-xilinx-ppc440-generic_flash_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
- > $(obj)board/xilinx/ppc440-generic/config.tmp
- @echo "TEXT_BASE := 0xFE360000" \
- >> $(obj)board/xilinx/ppc440-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx
-
-xilinx-ppc440-generic_config: unconfig
- @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
- @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
- > $(obj)board/xilinx/ppc440-generic/config.tmp
- @echo "TEXT_BASE := 0x04000000" \
- >> $(obj)board/xilinx/ppc440-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx
-
-yosemite_config \
-yellowstone_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
- tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a yosemite powerpc ppc4xx yosemite amcc
-
-#########################################################################
-## MPC824x Systems
-#########################################################################
-
-eXalion_config: unconfig
- @$(MKCONFIG) $(@:_config=) powerpc mpc824x eXalion
-
-CPC45_config \
-CPC45_ROMBOOT_config: unconfig
- @mkdir -p $(obj)include ; \
- if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
- echo "CONFIG_BOOT_ROM = y" >> $(obj)include/config.mk ; \
- else \
- echo "CONFIG_BOOT_ROM = n" >> $(obj)include/config.mk ; \
- fi; \
- echo "export CONFIG_BOOT_ROM" >> $(obj)include/config.mk;
- @$(MKCONFIG) -n $@ CPC45 powerpc mpc824x cpc45
-
-# HDLAN is broken ATM. Should be fixed as soon as hardware is available and as
-# time permits.
-#linkstation_HDLAN_config \
-# Remove this line when HDLAN is fixed
-linkstation_HGLAN_config: unconfig
- @mkdir -p $(obj)include
- @case $@ in \
- *HGLAN*) echo "#define CONFIG_HGLAN 1" >$(obj)include/config.h; ;; \
- *HDLAN*) echo "#define CONFIG_HLAN 1" >$(obj)include/config.h; ;; \
- esac
- @$(MKCONFIG) -n $@ -a linkstation powerpc mpc824x linkstation
-
-Sandpoint8240_config: unconfig
- @$(MKCONFIG) $@ powerpc mpc824x sandpoint
-
-Sandpoint8245_config: unconfig
- @$(MKCONFIG) $@ powerpc mpc824x sandpoint
-
-#########################################################################
-## MPC8260 Systems
-#########################################################################
-
-cogent_mpc8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) powerpc mpc8260 cogent
-
-CPU86_config \
-CPU86_ROMBOOT_config: unconfig
- @mkdir -p $(obj)include ; \
- if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
- echo "CONFIG_BOOT_ROM = y" >> $(obj)include/config.mk ; \
- else \
- echo "CONFIG_BOOT_ROM = n" >> $(obj)include/config.mk ; \
- fi; \
- echo "export CONFIG_BOOT_ROM" >> $(obj)include/config.mk;
- @$(MKCONFIG) -n $@ CPU86 powerpc mpc8260 cpu86
-
-CPU87_config \
-CPU87_ROMBOOT_config: unconfig
- @mkdir -p $(obj)include ; \
- if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
- echo "CONFIG_BOOT_ROM = y" >> $(obj)include/config.mk ; \
- else \
- echo "CONFIG_BOOT_ROM = n" >> $(obj)include/config.mk ; \
- fi; \
- echo "export CONFIG_BOOT_ROM" >> $(obj)include/config.mk;
- @$(MKCONFIG) -n $@ CPU87 powerpc mpc8260 cpu87
-
-ep8248_config \
-ep8248E_config : unconfig
- @$(MKCONFIG) -n $@ ep8248 powerpc mpc8260 ep8248
-
-ISPAN_config \
-ISPAN_REVB_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _REVB_,$@)" ] ; then \
- echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a ISPAN powerpc mpc8260 ispan
-
-MPC8260ADS_config \
-MPC8260ADS_lowboot_config \
-MPC8260ADS_33MHz_config \
-MPC8260ADS_33MHz_lowboot_config \
-MPC8260ADS_40MHz_config \
-MPC8260ADS_40MHz_lowboot_config \
-MPC8272ADS_config \
-MPC8272ADS_lowboot_config \
-PQ2FADS_config \
-PQ2FADS_lowboot_config \
-PQ2FADS-VR_config \
-PQ2FADS-VR_lowboot_config \
-PQ2FADS-ZU_config \
-PQ2FADS-ZU_lowboot_config \
-PQ2FADS-ZU_66MHz_config \
-PQ2FADS-ZU_66MHz_lowboot_config \
- : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/mpc8260ads
- $(if $(findstring PQ2FADS,$@), \
- @echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
- @echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
- $(if $(findstring MHz,$@), \
- @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
- $(if $(findstring VR,$@), \
- @echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h))
- @[ -z "$(findstring lowboot_,$@)" ] || \
- echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp
- @$(MKCONFIG) -n $@ -a MPC8260ADS powerpc mpc8260 mpc8260ads freescale
-
-muas3001_dev_config \
-muas3001_config : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/muas3001
- @if [ "$(findstring dev,$@)" ] ; then \
- echo "#define CONFIG_MUAS_DEV_BOARD" > $(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a muas3001 powerpc mpc8260 muas3001
-
-# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash
-PM825_config \
-PM825_ROMBOOT_config \
-PM825_BIGFLASH_config \
-PM825_ROMBOOT_BIGFLASH_config \
-PM826_config \
-PM826_ROMBOOT_config \
-PM826_BIGFLASH_config \
-PM826_ROMBOOT_BIGFLASH_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/pm826
- @if [ "$(findstring PM825_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >$(obj)include/config.h ; \
- else \
- >$(obj)include/config.h ; \
- fi
- @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
- echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
- echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \
- if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
- echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \
- fi; \
- else \
- if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
- $(XECHO) "... with 32 MB Flash" ; \
- echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \
- echo "TEXT_BASE = 0x40000000" >$(obj)board/pm826/config.tmp ; \
- else \
- echo "TEXT_BASE = 0xFF000000" >$(obj)board/pm826/config.tmp ; \
- fi; \
- fi
- @$(MKCONFIG) -n $@ -a PM826 powerpc mpc8260 pm826
-
-PM828_config \
-PM828_PCI_config \
-PM828_ROMBOOT_config \
-PM828_ROMBOOT_PCI_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/pm826
- @if [ "$(findstring _PCI_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- fi
- @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
- echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
- echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \
- fi
- @$(MKCONFIG) -n $@ -a PM828 powerpc mpc8260 pm828
-
-Rattler8248_config \
-Rattler_config: unconfig
- @mkdir -p $(obj)include
- $(if $(findstring 8248,$@), \
- @echo "#define CONFIG_MPC8248" > $(obj)include/config.h)
- @$(MKCONFIG) -n $@ -a Rattler powerpc mpc8260 rattler
-
-TQM8255_AA_config \
-TQM8260_AA_config \
-TQM8260_AB_config \
-TQM8260_AC_config \
-TQM8260_AD_config \
-TQM8260_AE_config \
-TQM8260_AF_config \
-TQM8260_AG_config \
-TQM8260_AH_config \
-TQM8260_AI_config \
-TQM8265_AA_config: unconfig
- @mkdir -p $(obj)include
- @case "$@" in \
- TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \
- TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \
- TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
- TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \
- TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
- TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \
- TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
- TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \
- TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \
- TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
- TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \
- esac; \
- if [ "$${CTYPE}" != "MPC8260" ] ; then \
- echo "#define CONFIG_$${CTYPE}" >>$(obj)include/config.h ; \
- fi; \
- echo "#define CONFIG_$${CFREQ}MHz" >>$(obj)include/config.h ; \
- if [ "$${CACHE}" = "yes" ] ; then \
- echo "#define CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
- else \
- echo "#undef CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
- fi; \
- if [ "$${BMODE}" = "60x" ] ; then \
- echo "#define CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
- else \
- echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a TQM8260 powerpc mpc8260 tqm8260 tqc
-
-VoVPN-GW_66MHz_config \
-VoVPN-GW_100MHz_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a VoVPN-GW powerpc mpc8260 vovpn-gw funkwerk
-
#########################################################################
## Coldfire
#########################################################################
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
fi
@$(MKCONFIG) -n $@ -a M52277EVB m68k mcf5227x m52277evb freescale
esac; \
if [ "$${FLASH}" != "16" ] ; then \
echo "#define NORFLASH_PS32BIT 1" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
else \
- echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
fi
@$(MKCONFIG) -n $@ -a M5235EVB m68k mcf523x m5235evb freescale
EB+MCF-EV123_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @echo "TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
+ @echo "CONFIG_SYS_TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
@$(MKCONFIG) -n $@ EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
EB+MCF-EV123_internal_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/BuS/EB+MCF-EV123
- @echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
+ @echo "CONFIG_SYS_TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
@$(MKCONFIG) -n $@ EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
M5329AFEE_config \
M54451EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "NOR" ] ; then \
- echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
fi; \
echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
esac; \
if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
fi; \
if [ "$${FLASH}" = "ATMEL" ] ; then \
echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
fi; \
echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -n $@ -a M5485EVB m68k mcf547x_8x m548xevb freescale
-#########################################################################
-## MPC83xx Systems
-#########################################################################
-
-MPC8313ERDB_33_config \
-MPC8313ERDB_66_config \
-MPC8313ERDB_NAND_33_config \
-MPC8313ERDB_NAND_66_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/mpc8313erdb
- @if [ "$(findstring _33_,$@)" ] ; then \
- echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _66_,$@)" ] ; then \
- echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _NAND_,$@)" ] ; then \
- echo "TEXT_BASE = 0x00100000" > $(obj)board/freescale/mpc8313erdb/config.tmp ; \
- echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
- fi ;
- @if [ "$(findstring _NAND_,$@)" ] ; then \
- echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
- fi ;
- @$(MKCONFIG) -n $@ -a MPC8313ERDB powerpc mpc83xx mpc8313erdb freescale
-
-MPC8315ERDB_NAND_config \
-MPC8315ERDB_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale
-
-MPC832XEMDS_config \
-MPC832XEMDS_HOST_33_config \
-MPC832XEMDS_HOST_66_config \
-MPC832XEMDS_SLAVE_config \
-MPC832XEMDS_ATM_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _HOST_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _SLAVE_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _33_,$@)" ] ; then \
- echo "#define PCI_33M" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _66_,$@)" ] ; then \
- echo "#define PCI_66M" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _ATM_,$@)" ] ; then \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
- fi ;
- @$(MKCONFIG) -n $@ -a MPC832XEMDS powerpc mpc83xx mpc832xemds freescale
-
-MPC8349ITX_config \
-MPC8349ITX_LOWBOOT_config \
-MPC8349ITXGP_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/freescale/mpc8349itx
- @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
- @if [ "$(findstring GP,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
- fi
- @if [ "$(findstring LOWBOOT,$@)" ] ; then \
- echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8349ITX powerpc mpc83xx mpc8349itx freescale
-
-MPC8360EMDS_config \
-MPC8360EMDS_HOST_33_config \
-MPC8360EMDS_HOST_66_config \
-MPC8360EMDS_SLAVE_config \
-MPC8360EMDS_ATM_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _HOST_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _SLAVE_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _33_,$@)" ] ; then \
- echo "#define PCI_33M" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _66_,$@)" ] ; then \
- echo "#define PCI_66M" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _ATM_,$@)" ] ; then \
- echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
- echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
- fi ;
- @$(MKCONFIG) -n $@ -a MPC8360EMDS powerpc mpc83xx mpc8360emds freescale
-
-MPC8360ERDK_33_config \
-MPC8360ERDK_66_config \
-MPC8360ERDK_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _33_,$@)" ] ; then \
- echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\
- fi ;
- @$(MKCONFIG) -n $@ -a MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale
-
-MPC837XEMDS_config \
-MPC837XEMDS_HOST_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _HOST_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
- fi ;
- @$(MKCONFIG) -n $@ -a MPC837XEMDS powerpc mpc83xx mpc837xemds freescale
-
-sbc8349_config \
-sbc8349_PCI_33_config \
-sbc8349_PCI_66_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ sbc8349 powerpc mpc83xx sbc8349
-
-SIMPC8313_LP_config \
-SIMPC8313_SP_config: unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/sheldon/simpc8313
- @if [ "$(findstring _LP_,$@)" ] ; then \
- echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _SP_,$@)" ] ; then \
- echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \
- fi ;
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @$(MKCONFIG) -n $@ -a SIMPC8313 powerpc mpc83xx simpc8313 sheldon
-
-caddy2_config \
-vme8349_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ vme8349 powerpc mpc83xx vme8349 esd
-
-#########################################################################
-## MPC85xx Systems
-#########################################################################
-
-MPC8536DS_NAND_config \
-MPC8536DS_SDCARD_config \
-MPC8536DS_SPIFLASH_config \
-MPC8536DS_36BIT_config \
-MPC8536DS_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ MPC8536DS powerpc mpc85xx mpc8536ds freescale
-
-MPC8540EVAL_config \
-MPC8540EVAL_33_config \
-MPC8540EVAL_66_config \
-MPC8540EVAL_33_slave_config \
-MPC8540EVAL_66_slave_config: unconfig
- @mkdir -p $(obj)include
- @if [ -z "$(findstring _33_,$@)" ] ; then \
- echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \
- fi ; \
- if [ "$(findstring _slave_,$@)" ] ; then \
- echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8540EVAL powerpc mpc85xx mpc8540eval
-
-MPC8541CDS_legacy_config \
-MPC8541CDS_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _legacy_,$@)" ] ; then \
- echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8541CDS powerpc mpc85xx mpc8541cds freescale
-
-MPC8548CDS_legacy_config \
-MPC8548CDS_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _legacy_,$@)" ] ; then \
- echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8548CDS powerpc mpc85xx mpc8548cds freescale
-
-MPC8555CDS_legacy_config \
-MPC8555CDS_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _legacy_,$@)" ] ; then \
- echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8555CDS powerpc mpc85xx mpc8555cds freescale
-
-MPC8569MDS_ATM_config \
-MPC8569MDS_NAND_config \
-MPC8569MDS_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ MPC8569MDS powerpc mpc85xx mpc8569mds freescale
-
-MPC8572DS_36BIT_config \
-MPC8572DS_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ MPC8572DS powerpc mpc85xx mpc8572ds freescale
-
-P2020DS_36BIT_config \
-P2020DS_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ P2020DS powerpc mpc85xx p2020ds freescale
-
-P1011RDB_config \
-P1011RDB_NAND_config \
-P1011RDB_SDCARD_config \
-P1011RDB_SPIFLASH_config \
-P1020RDB_config \
-P1020RDB_NAND_config \
-P1020RDB_SDCARD_config \
-P1020RDB_SPIFLASH_config \
-P2010RDB_config \
-P2010RDB_NAND_config \
-P2010RDB_SDCARD_config \
-P2010RDB_SPIFLASH_config \
-P2020DS_DDR2_config \
-P2020RDB_config \
-P2020RDB_NAND_config \
-P2020RDB_SDCARD_config \
-P2020RDB_SPIFLASH_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ P1_P2_RDB powerpc mpc85xx p1_p2_rdb freescale
-
-sbc8540_config \
-sbc8540_33_config \
-sbc8540_66_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ SBC8540 powerpc mpc85xx sbc8560
-
-sbc8548_config \
-sbc8548_PCI_33_config \
-sbc8548_PCI_66_config \
-sbc8548_PCI_33_PCIE_config \
-sbc8548_PCI_66_PCIE_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ sbc8548 powerpc mpc85xx sbc8548
-
-sbc8560_config \
-sbc8560_33_config \
-sbc8560_66_config: unconfig
- @$(MKCONFIG) -n $@ -t $@ sbc8560 powerpc mpc85xx sbc8560
-
-stxssa_config \
-stxssa_4M_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _4M_,$@)" ] ; then \
- echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a stxssa powerpc mpc85xx stxssa stx
-
-TQM8540_config \
-TQM8541_config \
-TQM8548_config \
-TQM8548_AG_config \
-TQM8548_BE_config \
-TQM8555_config \
-TQM8560_config: unconfig
- @mkdir -p $(obj)include
- @BTYPE=$(@:_config=); \
- CTYPE=$(subst TQM,,$(subst _AG,,$(subst _BE,,$(@:_config=)))); \
- echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
- echo "#define CONFIG_$${BTYPE}">>$(obj)include/config.h; \
- echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
- echo "#define CONFIG_BOARDNAME \"$${BTYPE}\"">>$(obj)include/config.h;
- @echo "CONFIG_$(@:_config=) = y">>$(obj)include/config.mk;
- @$(MKCONFIG) -n $@ -a TQM85xx powerpc mpc85xx tqm85xx tqc
-
-#########################################################################
-## MPC86xx Systems
-#########################################################################
-
-MPC8641HPCN_36BIT_config \
-MPC8641HPCN_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring _36BIT_,$@)" ] ; then \
- echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale
-
-#########################################################################
-## 74xx/7xx Systems
-#########################################################################
-
-EVB64260_config \
-EVB64260_750CX_config: unconfig
- @$(MKCONFIG) -n $@ EVB64260 powerpc 74xx_7xx evb64260
-
-p3m750_config \
-p3m7448_config: unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring 750_,$@)" ] ; then \
- echo "#define CONFIG_P3M750" >>$(obj)include/config.h ; \
- else \
- echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \
- fi
- @$(MKCONFIG) -n $@ -a p3mx powerpc 74xx_7xx p3mx prodrive
-
-PCIPPC2_config \
-PCIPPC6_config: unconfig
- @$(MKCONFIG) -n $@ $@ powerpc 74xx_7xx pcippc2
-
#========================================================================
# ARM
#========================================================================
@[ -z "$(findstring _bigflash,$@)" ] || \
{ echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \
echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \
- echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
}
@[ -z "$(findstring _old,$@)" ] || \
{ echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \
echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \
- echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
+ echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a trab arm arm920t trab - s3c24x0
fi
@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
-polaris_config \
-trizepsiv_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring polaris,$@)" ] ; then \
- echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
-
-vpac270_nor_config \
-vpac270_onenand_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring onenand,$@)" ] ; then \
- echo "#define CONFIG_ONENAND_U_BOOT" \
- >>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
-
#########################################################################
## ARM1136 Systems
#########################################################################
echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \
else \
echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \
- echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \
fi
@$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31
$(NIOS2_GENERIC:%=%_config) : unconfig
@$(MKCONFIG) $@ nios2 nios2 nios2-generic altera
-#========================================================================
-# Blackfin
-#========================================================================
-
-bf527-ezkit-v2_config : unconfig
- @$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
- bf527-ezkit blackfin blackfin bf527-ezkit
-
-#========================================================================
-# SH3 (SuperH)
-#========================================================================
-
-#########################################################################
-## sh2 (Renesas SuperH)
-#########################################################################
-rsk7203_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_RSK7203 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh2 rsk7203 renesas
-
-#########################################################################
-## sh3 (Renesas SuperH)
-#########################################################################
-
-mpr2_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh3 mpr2
-
-ms7720se_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh3 ms7720se
-
-#########################################################################
-## sh4 (Renesas SuperH)
-#########################################################################
-
-MigoR_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 MigoR renesas
-
-ms7750se_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 ms7750se
-
-ms7722se_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 ms7722se
-
-r2dplus_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 r2dplus renesas
-
-r7780mp_config: unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 r7780mp renesas
-
-sh7763rdp_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 sh7763rdp renesas
-
-sh7785lcr_32bit_config \
-sh7785lcr_config : unconfig
- @mkdir -p $(obj)include
- @mkdir -p $(obj)board/renesas/sh7785lcr
- @echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
- @if [ "$(findstring 32bit, $@)" ] ; then \
- echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
- echo "TEXT_BASE = 0x8ff80000" > \
- $(obj)board/renesas/sh7785lcr/config.tmp ; \
- fi
- @$(MKCONFIG) -n $@ -a sh7785lcr sh sh4 sh7785lcr renesas
-
-ap325rxa_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 ap325rxa renesas
-
-espt_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
- @$(MKCONFIG) -a $@ sh sh4 espt
-
#########################################################################
#########################################################################
$(obj)tools/mkimage $(obj)tools/mpc86x_clk \
$(obj)tools/ncb $(obj)tools/ubsha1
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
+ $(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
+ @rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+ @rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)mmc_ipl ] || find $(obj)mmc_ipl -name "*" -type l -print | xargs rm -f
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON, LANTEC,
- PCU_E, FLAGADM, TQM8260
+ FLAGADM, TQM8260
- Error Recovery:
CONFIG_PANIC_HANG
- CONFIG_SYS_MONITOR_BASE:
Physical start address of boot monitor code (set by
make config files to be same as the text base address
- (TEXT_BASE) used when linking) - same as
+ (CONFIG_SYS_TEXT_BASE) used when linking) - same as
CONFIG_SYS_FLASH_BASE when booting from flash.
- CONFIG_SYS_MONITOR_LEN:
all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
+- CONFIG_SYS_BOOT_RAMDISK_HIGH:
+ Enable initrd_high functionality. If defined then the
+ initrd_high feature is enabled and the bootm ramdisk subcommand
+ is enabled.
+
+- CONFIG_SYS_BOOT_GET_CMDLINE:
+ Enables allocating and saving kernel cmdline in space between
+ "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+- CONFIG_SYS_BOOT_GET_KBD:
+ Enables allocating and saving a kernel copy of the bd_info in
+ space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
- CONFIG_SYS_MAX_FLASH_BANKS:
Max number of Flash memory banks
- CONFIG_ENV_MAX_ENTRIES
- Maximum number of entries in the hash table that is used
- internally to store the environment settings. The default
- setting is supposed to be generous and should work in most
- cases. This setting can be used to tune behaviour; see
- lib/hashtable.c for details.
+ Maximum number of entries in the hash table that is used
+ internally to store the environment settings. The default
+ setting is supposed to be generous and should work in most
+ cases. This setting can be used to tune behaviour; see
+ lib/hashtable.c for details.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
- CONFIG_ENV_SIZE:
These two #defines specify the offset and size of the environment
- area within the first NAND device.
+ area within the first NAND device. CONFIG_ENV_OFFSET must be
+ aligned to an erase block boundary.
- - CONFIG_ENV_OFFSET_REDUND
+ - CONFIG_ENV_OFFSET_REDUND (optional):
This setting describes a second storage area of CONFIG_ENV_SIZE
- size used to hold a redundant copy of the environment data,
- so that there is a valid backup copy in case there is a
- power failure during a "saveenv" operation.
+ size used to hold a redundant copy of the environment data, so
+ that there is a valid backup copy in case there is a power failure
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+ aligned to an erase block boundary.
+
+ - CONFIG_ENV_RANGE (optional):
- Note: CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND must be aligned
- to a block boundary, and CONFIG_ENV_SIZE must be a multiple of
- the NAND devices block size.
+ Specifies the length of the region in which the environment
+ can be written. This should be a multiple of the NAND device's
+ block size. Specifying a range with more erase blocks than
+ are needed to hold CONFIG_ENV_SIZE allows bad blocks within
+ the range to be avoided.
+
+ - CONFIG_ENV_OFFSET_OOB (optional):
+
+ Enables support for dynamically retrieving the offset of the
+ environment from block zero's out-of-band data. The
+ "nand env.oob" command can be used to record this offset.
+ Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
+ using CONFIG_ENV_OFFSET_OOB.
- CONFIG_NAND_ENV_DST
area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
- (sometimes written as (CONFIG_SYS_INIT_RAM_END -
+ (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
globally (CONFIG_CMD_MEM).
- CONFIG_SKIP_LOWLEVEL_INIT
-- CONFIG_SKIP_RELOCATE_UBOOT
+ [ARM only] If this variable is defined, then certain
+ low level initializations (like setting up the memory
+ controller) are omitted and/or U-Boot does not
+ relocate itself into RAM.
- [ARM only] If these variables are defined, then
- certain low level initializations (like setting up
- the memory controller) are omitted and/or U-Boot does
- not relocate itself into RAM.
- Normally these variables MUST NOT be defined. The
- only exception is when U-Boot is loaded (to RAM) by
- some other boot loader or by a debugger which
- performs these initializations itself.
+ Normally this variable MUST NOT be defined. The only
+ exception is when U-Boot is loaded (to RAM) by some
+ other boot loader or by a debugger which performs
+ these initializations itself.
- CONFIG_PRELOADER
-
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
include $(TOPDIR)/config.mk
-LIB = $(obj)libapi.a
+LIB = $(obj)libapi.o
COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
#define DEBUG
#undef DEBUG
-/* U-Boot routines needed */
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/*****************************************************************************
*
* This is the API core.
endif
endif
-ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
-# needed for relocation
-PLATFORM_RELFLAGS += -fPIC
-endif
-
-ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
-endif
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
endif
endif
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# needed for relocation
+ifndef CONFIG_NAND_SPL
+PLATFORM_LDFLAGS += -pie
+endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS += generic.o
COBJS += timer.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h>
#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
__REG(reg) = tmp;
}
+void mx31_set_pad(enum iomux_pins pin, u32 config)
+{
+ u32 field, l, reg;
+
+ pin &= IOMUX_PADNUM_MASK;
+ reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
+ field = (pin + 2) % 3;
+
+ l = __REG(reg);
+ l &= ~(0x1ff << (field * 10));
+ l |= config << (field * 10);
+ __REG(reg) = l;
+
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _start
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-#endif
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
#ifdef CONFIG_NAND_SPL
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
+ ldr r0, _nand_boot_ofs
+ adr r1, _start
+ add pc, r0, r1
+_nand_boot_ofs
+ : .word nand_boot - _start
#else
jump_2_ram:
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
-#ifdef CONFIG_OMAP2420H4
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start /* r0 <- current position of code */
- add r0, r0, #4 /* skip reset vector */
- mov r2, #64 /* r2 <- size to copy */
- add r2, r0, r2 /* r2 <- source end address */
- mov r1, #SRAM_OFFSET0 /* build vect addr */
- mov r3, #SRAM_OFFSET1
- add r1, r1, r3
- mov r3, #SRAM_OFFSET2
- add r1, r1, r3
-next:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next /* loop until equal */
- bl cpy_clk_code /* put dpll adjust code behind vectors */
-#endif
- /* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
-#ifndef CONFIG_PRELOADER
- beq stack_setup
-#endif /* CONFIG_PRELOADER */
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-#ifdef CONFIG_PRELOADER
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-#else
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
-#endif /* CONFIG_PRELOADER */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- bne clbss_l
-#endif
-
- ldr pc, _start_armboot
-
-#ifdef CONFIG_NAND_SPL
-_start_armboot: .word nand_boot
-#else
-#ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
-#else
-_start_armboot: .word start_armboot
-#endif /* CONFIG_ONENAND_IPL */
-#endif /* CONFIG_NAND_SPL */
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
-#else
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
-#else
- ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
-#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r0, IRQ_STACK_START_IN @ get data regions start
-#else
- ldr r0, _armboot_start @ get data regions start
- sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
-#endif
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* Base codes by scsuh (sc.suh)
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#ifdef CONFIG_ENABLE_MMU
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
/*
* Below variable is very important because we use MMU in U-Boot.
_TEXT_PHY_BASE:
.word CONFIG_SYS_PHY_UBOOT_BASE
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
-
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
- sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
+ sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
b mmu_disable
.align 5
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
#ifdef CONFIG_ENABLE_MMU
enable_mmu:
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
_nand_boot: .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
-#ifdef CONFIG_S5P6442_EVT1
- ldr r0, =0xD0021800
- mcr p15, 0, r0, c12, c0, 0 @;Change Exception Vector Base Address
-
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_x, r0 @;Enable Imprecise Abort Exception
-
- nop @;Data Abort Exception will occurred
- nop
-
- mrs r0, cpsr @;Disable Imprecise Abort Exception
- orr r0, r0, #0x100
- msr cpsr_x, r0
-
- ldr r0, =0x0
- mcr p15, 0, r0, c12, c0, 0 @;Restore Exception Vector Base Address
-#endif
-
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0, cpsr
- bic r0, r0, #0x3f
- orr r0, r0, #0xd3
- msr cpsr, r0
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-cpu_init_crit:
- /*
- * When booting from NAND - it has definitely been a reset, so, no need
- * to flush caches and disable the MMU
- */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_ONENAND_IPL)
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
-
- /* Prepare to disable the MMU */
- adr r2, mmu_disable_phys
- sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
- b mmu_disable
-
- .align 5
- /* Run in a single cache-line */
-mmu_disable:
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- mov pc, r2
-mmu_disable_phys:
-
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
- /*
- * Go setup Memory and board specific bits prior to relocation.
- */
- bl lowlevel_init /* go setup pll,mux,memory */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
- /* enable domain access */
- ldr r5, =0x0000ffff
- mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
-
- /* Set the TTB register */
- ldr r0, _mmu_table_base
- ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
- ldr r2, =0xfff00000
- bic r0, r0, r2
- orr r1, r0, r1
- mcr p15, 0, r1, c2, c0, 0
-
- /* Enable the MMU */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #1 /* Set CR_M to enable MMU */
-
- /* Prepare to enable the MMU */
- adr r1, skip_hw_init
- and r1, r1, #0x3fc
- ldr r2, _TEXT_BASE
- ldr r3, =0xfff00000
- and r2, r2, r3
- orr r2, r2, r1
- b mmu_enable
-
- .align 5
- /* Run in a single cache-line */
-mmu_enable:
-
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- mov pc, r2
-skip_hw_init:
-#endif
-
- /* Set up the stack */
-stack_setup:
- ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0 /* clear */
-
-clbss_l:
- str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
-#ifndef CONFIG_NAND_SPL
- ldr pc, _start_armboot
-
-#ifdef CONFIG_ONENAND_IPL
-_start_armboot:
- .word start_oneboot
-#else
-_start_armboot:
- .word start_armboot
-#endif
-#else
- b nand_boot
-/* .word nand_boot*/
-#endif
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
#ifdef CONFIG_ENABLE_MMU
_mmu_table_base:
/* Save user registers (now in svc mode) r0-r12 */
stmia sp, {r0 - r12}
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- /* set base 2 words into abort stack */
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- /* setup our mode stack (enter in banked mode) */
- ldr r13, _armboot_start
- /* move past malloc pool */
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- /* move to reserved a couple spots for abort stack */
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
/* save caller lr in position 0 of saved stack */
str lr, [r13]
sub r13, r13, #4
/* save R0's value. */
str r0, [r13]
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- /* get data regions start */
- ldr r0, _armboot_start
- /* move past malloc pool */
- sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
- /* move past gbl and a couple spots for abort stack */
- sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o
SOBJS += lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
- . = ALIGN(4);
- .got : { *(.got) }
-
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = interrupts.o cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = flash.o mmc.o mmc_hw.o spi.o
SOBJS = $(obj)iap_entry.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
# this MUST be compiled as thumb code!
$(SOBJS):
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-y += cache.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/hardware.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0x13
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifdef CONFIG_LPC2292
- bl lowlevel_init
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
-#if TEXT_BASE
-#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
- ldr r2, =0x0 /* Relocate the exception vectors */
- cmp r1, r2 /* and associated data to address */
- ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
- stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
- ldmneia r0, {r3-r9}
- stmneia r2, {r3-r9}
- adrne r0, _start /* restore r0 */
-#endif /* !CONFIG_LPC2292 */
-#endif
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
ldr r1, =0xFFFFF000
and r0, r1, r0
- ldr r1, =(relocate-TEXT_BASE)
+ ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
add r0, r1, r0
ldr r4, =NETARM_GEN_MODULE_BASE
ldr r1, =NETARM_GEN_SW_SVC_RESETA
. = ALIGN(4);
.data : {
- *(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS += reset.o
COBJS += timer.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS += lowlevel_init.o
COBJS += reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
_MTEXT_BASE:
#undef START_FROM_MEM
#ifdef START_FROM_MEM
- .word TEXT_BASE-PHYS_FLASH_1
+ .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
#else
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
#endif
.globl lowlevel_init
#include <asm/arch/hardware.h>
#include <asm/arch/at91_st.h>
-void board_reset(void) __attribute__((__weak__));
+void __attribute__((weak)) board_reset(void)
+{
+ /* true empty function for defining weak symbol */
+}
void reset_cpu(ulong ignored)
{
serial_exit();
#endif
- if (board_reset)
- board_reset();
+ board_reset();
/* Reset the cpu by setting up the watchdog timer */
writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
#include <common.h>
-#include <asm/io.h>
-#include <asm/hardware.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-static u32 timestamp;
-static u32 lastinc;
-
int timer_init(void)
{
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
- lastinc = 0;
- timestamp = 0;
+ gd->lastinc = 0;
+ gd->tbl = 0;
return 0;
}
void set_timer(ulong t)
{
- timestamp = t;
+ gd->tbl = t;
}
void __udelay(unsigned long usec)
{
/* reset time */
at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
- lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
- timestamp = 0;
+ gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
+ gd->tbl = 0;
}
ulong get_timer_raw(void)
now = readl(&tc->tc[0].cv) & 0x0000ffff;
- if (now >= lastinc) {
+ if (now >= gd->lastinc) {
/* normal mode */
- timestamp += now - lastinc;
+ gd->tbl += now - gd->lastinc;
} else {
/* we have an overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
+ gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
}
- lastinc = now;
+ gd->lastinc = now;
- return timestamp;
+ return gd->tbl;
}
ulong get_timer_masked(void)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS += lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
_MTEXT_BASE:
#undef START_FROM_MEM
#ifdef START_FROM_MEM
- .word TEXT_BASE-PHYS_FLASH_1
+ .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
#else
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
#endif
.globl lowlevel_init
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = cpu.o led.o speed.o timer.o
SOBJS = lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS += generic.o
COBJS += speed.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS = lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USE_IRQ) += interrupts.o
COBJS-y += speed.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
ulong r, m, p, s;
if (pllreg == MPLL)
- r = readl(&clk_power->MPLLCON);
+ r = readl(&clk_power->mpllcon);
else if (pllreg == UPLL)
- r = readl(&clk_power->UPLLCON);
+ r = readl(&clk_power->upllcon);
else
hang();
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
+#if defined(CONFIG_S3C2440)
+ if (pllreg == MPLL)
+ return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
}
/* return FCLK frequency */
ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
- return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#ifdef CONFIG_S3C2440
+ switch (readl(&clk_power->clkdivn) & 0x6) {
+ default:
+ case 0:
+ return get_FCLK();
+ case 2:
+ return get_FCLK() / 2;
+ case 4:
+ return (readl(&clk_power->camdivn) & (1 << 9)) ?
+ get_FCLK() / 8 : get_FCLK() / 4;
+ case 6:
+ return (readl(&clk_power->camdivn) & (1 << 8)) ?
+ get_FCLK() / 6 : get_FCLK() / 3;
+ }
+#else
+ return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
}
/* return PCLK frequency */
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+ return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return readl(&timers->TCNTO4) & 0xffff;
+ return readl(&timers->tcnto4) & 0xffff;
}
static ulong timestamp;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- writel(0x0f00, &timers->TCFG0);
+ writel(0x0f00, &timers->tcfg0);
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
}
/* load value for 10 ms timeout */
lastdec = timer_load_val;
- writel(timer_load_val, &timers->TCNTB4);
- /* auto load, manual update of Timer 4 */
- tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
- writel(tmr, &timers->TCON);
- /* auto load, start Timer 4 */
+ writel(timer_load_val, &timers->tcntb4);
+ /* auto load, manual update of timer 4 */
+ tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->tcon);
+ /* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
- writel(tmr, &timers->TCON);
+ writel(tmr, &timers->tcon);
timestamp = 0;
return (0);
tbclk = timer_load_val * 100;
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
+ defined(CONFIG_S3C2440) || \
defined(CONFIG_VCMA9)
tbclk = CONFIG_SYS_HZ;
#else
watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- writel(0x0000, &watchdog->WTCON);
+ writel(0x0000, &watchdog->wtcon);
/* Initialize watchdog timer count register */
- writel(0x0001, &watchdog->WTCNT);
+ writel(0x0001, &watchdog->wtcnt);
/* Enable watchdog timer; assert reset at timer timeout */
- writel(0x0021, &watchdog->WTCON);
+ writel(0x0021, &watchdog->wtcon);
while (1)
/* loop forever and wait for reset to happen */;
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
- writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+ writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/*
* Enable USB host clock.
*/
- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0;
}
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+ gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
- clk_power->CLKCON |= (1 << 4);
+ clk_power->clkcon |= (1 << 4);
memset(&gohci, 0, sizeof(struct ohci));
memset(&urb_priv, 0, sizeof(struct urb_priv));
if (hc_reset(&gohci) < 0) {
hc_release_ohci(&gohci);
/* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return -1;
}
err("can't start usb-%s", gohci.slot_name);
hc_release_ohci(&gohci);
/* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return -1;
}
#ifdef DEBUG
/* call hc_release_ohci() here ? */
hc_reset(&gohci);
/* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
+ clk_power->clkcon &= ~(1 << 4);
return 0;
}
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <common.h>
#include <config.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual start code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
+ ldr r0, _nand_boot_ofs
+ mov pc, r0
-_nand_boot: .word nand_boot
+_nand_boot_ofs:
+ .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual start code
- */
-
-start_code:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0, cpsr
- bic r0, r0, #0x1f
- orr r0, r0, #0xd3
- msr cpsr, r0
-
- bl coloured_LED_init
- bl red_LED_on
-
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
- /*
- * relocate exception table
- */
- ldr r0, =_start
- ldr r1, =0x0
- mov r2, #16
-copyex:
- subs r2, r2, #1
- ldr r3, [r0], #4
- str r3, [r1], #4
- bne copyex
-#endif
-
-#ifdef CONFIG_S3C24X0
- /* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-# endif
-
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMSK
- str r1, [r0]
-# if defined(CONFIG_S3C2410)
- ldr r1, =0x3ff
- ldr r0, =INTSUBMSK
- str r1, [r0]
-# endif
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
-#endif /* CONFIG_S3C24X0 */
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE)
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- /* set base 2 words into abort stack */
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE)
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- /* reserve a couple spots in abort stack */
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
cmp r0, r1
bne clbss_l
+ bl coloured_LED_init
+ bl red_LED_on
#endif
/*
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
+ ldr r0, _nand_boot_ofs
+ mov pc, r0
-_nand_boot: .word nand_boot
+_nand_boot_ofs:
+ .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * Set up 925T mode
- */
- mov r1, #0x81 /* Set ARM925T configuration. */
- mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
-
- /*
- * turn off the watchdog, unlock/diable sequence
- */
- mov r1, #0xF5
- ldr r0, =WDTIM_MODE
- strh r1, [r0]
- mov r1, #0xA0
- strh r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =REG_IHL1_MIR
- str r1, [r0]
- ldr r0, =REG_IHL2_MIR
- str r1, [r0]
-
- /*
- * wait for dpll to lock
- */
- ldr r0, =CK_DPLL1
- mov r1, #0x10
- strh r1, [r0]
-poll1:
- ldrh r1, [r0]
- ands r1, r1, #0x01
- beq poll1
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN
-#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y = cpu.o timer.o dram.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID (1<<8)
+#define L2C_RAM_SEL (1<<4)
+
+int arch_cpu_init(void)
+{
+ u32 val;
+ struct armd1cpu_registers *cpuregs =
+ (struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+ struct armd1apb1_registers *apb1clkres =
+ (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+ struct armd1mpmu_registers *mpmu =
+ (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+ /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+ val = readl(&cpuregs->cpu_conf);
+ val = val | SET_MRVL_ID;
+ writel(val, &cpuregs->cpu_conf);
+
+ /* Enable Clocks for all hardware units */
+ writel(0xFFFFFFFF, &mpmu->acgr);
+
+ /* Turn on AIB and AIB-APB Functional clock */
+ writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+ /* ensure L2 cache is not mapped as SRAM */
+ val = readl(&cpuregs->cpu_conf);
+ val = val & ~(L2C_RAM_SEL);
+ writel(val, &cpuregs->cpu_conf);
+
+ /* Enable GPIO clock */
+ writel(APBC_APBCLK, &apb1clkres->gpio);
+
+ /*
+ * Enable Functional and APB clock at 14.7456MHz
+ * for configured UART console
+ */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+ writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+ writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+ writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+ icache_enable();
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 id;
+ struct armd1cpu_registers *cpuregs =
+ (struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+ id = readl(&cpuregs->chip_id);
+ printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+ u32 cs; /* Memory Address Map Register -CS */
+ u32 pad[3];
+};
+
+struct armd1ddr_registers {
+ u8 pad[0x100 - 0x000];
+ struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+ struct armd1ddr_registers *ddr_regs =
+ (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+ return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+ struct armd1ddr_registers *ddr_regs =
+ (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs);
+ result = (result >> 16) & 0xF;
+ if (result < 0x7) {
+ printf("Unknown DRAM Size\n");
+ return -1;
+ } else {
+ return ((0x8 << (result - 0x7)) * 1024 * 1024);
+ }
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+ gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+ u32 clk_ctrl; /* Timer clk control reg */
+ u32 match[9]; /* Timer match registers */
+ u32 count[3]; /* Timer count registers */
+ u32 status[3];
+ u32 ie[3];
+ u32 preload[3]; /* Timer preload value */
+ u32 preload_ctrl[3];
+ u32 wdt_match_en;
+ u32 wdt_match_r;
+ u32 wdt_val;
+ u32 wdt_sts;
+ u32 icr[3];
+ u32 wdt_icr;
+ u32 cer; /* Timer count enable reg */
+ u32 cmr;
+ u32 ilr[3];
+ u32 wcr;
+ u32 wfar;
+ u32 wsar;
+ u32 cvwr;
+};
+
+#define TIMER 0 /* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x) ((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 0xffffffff
+#define COUNT_RD_REQ 0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+ volatile int loop=100;
+
+ writel(COUNT_RD_REQ, &armd1timers->cvwr);
+ while (loop--);
+ return(readl(&armd1timers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ gd->tbl = read_timer();
+ gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (now >= gd->tbl) {
+ /* normal mode */
+ gd->tbu += now - gd->tbl;
+ } else {
+ /* we have an overflow ... */
+ gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ }
+ gd->tbl = now;
+
+ return gd->tbu;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+ base);
+}
+
+void set_timer(ulong t)
+{
+ gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong delayticks;
+ ulong endtime;
+
+ delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+ endtime = get_timer_masked() + delayticks;
+
+ while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+ struct armd1apb1_registers *apb1clkres =
+ (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+ /* Enable Timer clock at 3.25 MHZ */
+ writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+ /* load value into timer */
+ writel(0x0, &armd1timers->clk_ctrl);
+ /* Use Timer 0 Match Resiger 0 */
+ writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+ /* Preload value is 0 */
+ writel(0x0, &armd1timers->preload[TIMER]);
+ /* Enable match comparator 0 for Timer 0 */
+ writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+ /* Enable timer 0 */
+ writel(0x1, &armd1timers->cer);
+ /* init the gd->tbu and gd->tbl value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+#define MPMU_APRR_WDTR (1<<4)
+#define TMR_WFAR 0xbaba /* WDT Register First key */
+#define TMP_WSAR 0xeb10 /* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+ struct armd1mpmu_registers *mpmu =
+ (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+ struct armd1tmr_registers *armd1timers =
+ (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+ u32 val;
+
+ /* negate hardware reset to the WDT after system reset */
+ val = readl(&mpmu->aprr);
+ val = val | MPMU_APRR_WDTR;
+ writel(val, &mpmu->aprr);
+
+ /* reset/enable WDT clock */
+ writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+ readl(&mpmu->wdtpcr);
+ writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+ readl(&mpmu->wdtpcr);
+
+ /* clear previous WDT status */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0, &armd1timers->wdt_sts);
+
+ /* set match counter */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0xf, &armd1timers->wdt_match_r);
+
+ /* enable WDT reset */
+ writel(TMR_WFAR, &armd1timers->wfar);
+ writel(TMP_WSAR, &armd1timers->wsar);
+ writel(0x3, &armd1timers->wdt_match_en);
+
+ while(1);
+}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o
COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#else
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
+#if defined(CONFIG_AT91SAM9G20)
+ /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
+ at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
+ at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
+#endif
#endif
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
#endif
* (at your option) any later version.
*/
-#include <config.h>
+#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
-static unsigned long cpu_clk_rate_hz;
-static unsigned long main_clk_rate_hz;
-static unsigned long mck_rate_hz;
-static unsigned long plla_rate_hz;
-static unsigned long pllb_rate_hz;
-static u32 at91_pllb_usb_init;
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
unsigned long get_cpu_clk_rate(void)
{
- return cpu_clk_rate_hz;
+ return gd->cpu_clk_rate_hz;
}
unsigned long get_main_clk_rate(void)
{
- return main_clk_rate_hz;
+ return gd->main_clk_rate_hz;
}
unsigned long get_mck_clk_rate(void)
{
- return mck_rate_hz;
+ return gd->mck_rate_hz;
}
unsigned long get_plla_clk_rate(void)
{
- return plla_rate_hz;
+ return gd->plla_rate_hz;
}
unsigned long get_pllb_clk_rate(void)
{
- return pllb_rate_hz;
+ return gd->pllb_rate_hz;
}
u32 get_pllb_init(void)
{
- return at91_pllb_usb_init;
+ return gd->at91_pllb_usb_init;
}
static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
- return main_clk_rate_hz;
+ return gd->main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
- return plla_rate_hz;
+ return gd->plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
- return pllb_rate_hz;
+ return gd->pllb_rate_hz;
}
return 0;
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
- main_clk_rate_hz = main_clock;
+ gd->main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+ gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
- at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+ gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
- pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
+ gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
#endif
/*
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
- plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+ gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
- mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = mck_rate_hz;
+ gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
/* mdiv */
- mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
- mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
- cpu_clk_rate_hz = freq;
+ gd->cpu_clk_rate_hz = freq;
return 0;
}
/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
*/
#include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
+void arch_preboot_os(void)
+{
+ ulong cpiv;
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+ cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+ /*
+ * Disable PITC
+ * Add 0x1000 to current counter to stop it faster
+ * without waiting for wrapping back to 0
+ */
+ writel(cpiv + 0x1000, &pit->mr);
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
#ifdef CONFIG_BOOTCOUNT_LIMIT
/*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
+ * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
+ * This is done so we need to use only one of the four GPBR registers.
*/
void bootcount_store (ulong a)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
+ writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
+ &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
}
ulong bootcount_load (void)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+ ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
+ if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
return 0;
else
- return (*save_addr & 0x0000ffff);
+ return val & 0x0000ffff;
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
#endif
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
.type lowlevel_init,function
ldr r0, =POS1 /* r0 = POS1 compile */
ldr r2, _TEXT_BASE
sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
- sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
+ sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
sub r5, r5, #4 /* r1 = text base - current */
/* memory control configuration 1 */
#include <asm/arch/io.h>
#include <div64.h>
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
*/
-#define TIMER_LOAD_VAL 0xfffff
-static ulong timestamp;
-static ulong lastinc;
-static ulong timer_freq;
+#define TIMER_LOAD_VAL 0xfffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, timer_freq);
+ do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
- usec *= timer_freq;
+ usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
-/* nothing really to do with interrupts, just starts up a counter. */
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
- /*
- * Enable PITC Clock
- * The clock is already enabled for system controller in boot
- */
+
+ /* Enable PITC Clock */
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
- reset_timer_masked();
-
- timer_freq = get_mck_clk_rate() >> 4;
+ gd->timer_rate_hz = gd->mck_rate_hz / 16;
+ gd->tbu = gd->tbl = 0;
return 0;
}
/*
- * timer without interrupts
+ * Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
ulong now = readl(&pit->piir);
- if (now >= lastinc) /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += (now - lastinc);
- else /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- lastinc = now;
- return timestamp;
-}
-
-void reset_timer_masked(void)
-{
- /* reset time */
- at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
- /* capture current incrementer value time */
- lastinc = readl(&pit->piir);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->tbl)
+ gd->tbu++;
+ gd->tbl = now;
+ return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
+ ;
}
+/*
+ * reset_timer() and get_timer(base) are a pair of functions that are used by
+ * some timeout/sleep mechanisms in u-boot.
+ *
+ * reset_timer() marks the current time as epoch and
+ * get_timer(base) works relative to that epoch.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
void reset_timer(void)
{
- reset_timer_masked();
+ gd->timer_reset_value = get_ticks();
}
ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
}
/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
- return timer_freq;
+ return gd->timer_rate_hz;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o timer.o psc.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct davinci_timer {
u_int32_t pid12;
u_int32_t emumgt;
static struct davinci_timer * const timer =
(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
+#define TIMER_LOAD_VAL 0xffffffff
-static ulong timestamp;
-static ulong lastinc;
+#define TIM_CLK_DIV 16
int timer_init(void)
{
writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
- lastinc = 0;
- timestamp = 0;
writel(2 << 22, &timer->tcr);
+ gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+ gd->timer_reset_value = 0;
return(0);
}
void reset_timer(void)
{
- writel(0x0, &timer->tcr);
- writel(0x0, &timer->tim34);
- lastinc = 0;
- timestamp = 0;
- writel(2 << 22, &timer->tcr);
+ gd->timer_reset_value = get_ticks();
}
-static ulong get_timer_raw(void)
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
{
- ulong now = readl(&timer->tim34);
-
- if (now >= lastinc) {
- /* normal mode */
- timestamp += now - lastinc;
- } else {
- /* overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
- }
- lastinc = now;
- return timestamp;
+ unsigned long now = readl(&timer->tim34);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->tbl)
+ gd->tbu++;
+ gd->tbl = now;
+
+ return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
ulong get_timer(ulong base)
{
- return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
-}
+ unsigned long long timer_diff;
-void set_timer(ulong t)
-{
- timestamp = t;
+ timer_diff = get_ticks() - gd->timer_reset_value;
+
+ return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
}
void __udelay(unsigned long usec)
{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
+ unsigned long long endtime;
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
+ endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL;
+ endtime += get_ticks();
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return(get_timer(0));
+ while (get_ticks() < endtime)
+ ;
}
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-y = cpu.o
COBJS-y += dram.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
u8 outbuf[BUFLEN];
/*
- * in case of 88F6281/88F6192 A0,
+ * in case of 88F6281/88F6282/88F6192 A0,
* Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
- * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
- * Does not have names at this moment (no errata available)
+ * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
+ * reserved regs and does not have names at this moment
+ * (no errata available)
*/
writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
for (i = 0; i < BUFLEN; i++) {
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char *name = "Unknown";
+ char *rev;
+ u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
+ u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
- switch (readl(KW_REG_DEVICE_ID) & 0x03) {
- case 1:
- name = "88F6192_A0";
+ if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
+ printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+ return -1;
+ }
+
+ switch (revid) {
+ case 0:
+ rev = "Z0";
break;
case 2:
- name = "88F6281_A0";
+ rev = "A0";
+ break;
+ case 3:
+ rev = "A1";
break;
default:
- printf("SoC: Unsupported Kirkwood\n");
- return -1;
+ rev = "??";
+ break;
}
- printf("SoC: Kirkwood %s\n", name);
+
+ printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
*/
#include <config.h>
+#include <common.h>
#include <asm/arch/kirkwood.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
/*
result += 0x01000000;
return result;
}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+ gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = clock.o reset.o timer.o
SOBJS =
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = generic.o timer.o
MX27OBJS = reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
writel (outpadctl, &padctl->pad_fec_tdata1);
}
+
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ for (i = 0; i < 6; i++)
+ mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
#endif /* CONFIG_FEC_MXC */
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
- writel (0x00000000, ®s->wcr);
+ writew(0, ®s->wcr);
/* Write Service Sequence */
- writel (0x00005555, ®s->wsr);
- writel (0x0000AAAA, ®s->wsr);
+ writew(WSR_UNLOCK1, ®s->wsr);
+ writew(WSR_UNLOCK2, ®s->wsr);
/* Enable watchdog */
- writel (WCR_WDE, ®s->wcr);
+ writew(WCR_WDE, ®s->wcr);
while (1) ;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = generic.o reset.o timer.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
+
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ for (i = 0; i < 6; i++)
+ mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = timer.o gpio.o
SOBJS = reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = timer.o cpuinfo.o
SOBJS = reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS-y = cpu.o
COBJS-y += dram.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
}
/*
- * Window Size
+ * Compute Window Size field value from size expressed in bytes
* Used with the Base register to set the address window size and location.
* Must be programmed from LSB to MSB as sequence of ones followed by
* sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
+ * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
+ * NOTES:
+ * 1) A sizeval equal to 0x0 specifies 4 GiB.
+ * 2) A return value of 0x0 specifies 64 KiB.
*/
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
{
- int i;
- unsigned int j = 0;
- u32 val = sizeval >> 1;
-
- for (i = 0; val >= 0x10000; i++) {
- j |= (1 << i);
- val = val >> 1;
- }
- return 0x0000ffff & j;
+ /*
+ * Calculate the number of 64 KiB blocks needed minus one (rounding up).
+ * For sizeval > 0 this is equivalent to:
+ * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
+ */
+ sizeval = (sizeval - 1) >> 16;
+
+ /*
+ * Propagate 'one' bits to the right by 'oring' them.
+ * We need only treat bits 15-0.
+ */
+ sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
+ sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
+ sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
+ sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
+
+ return sizeval;
}
/*
*
* If remap function not used, remap_lo must be set as base
*
+ * NOTES:
+ *
+ * 1) in order to avoid windows with inconsistent control and base values
+ * (which could prevent access to BOOTCS and hence execution from FLASH)
+ * always disable window before writing the base value then reenable it
+ * by writing the control value.
+ *
+ * 2) in order to avoid losing access to BOOTCS when disabling window 7,
+ * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
+ * then configure windows 6 for its own target.
+ *
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
struct orion5x_win_registers *winregs =
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
- /* Window 0: PCIE MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
- ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 0, configure it for its intended target, enable it. */
+ writel(0, &winregs[0].ctrl);
writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
-
- /* Window 1: PCIE IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
- ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+ ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 1, configure it for its intended target, enable it. */
+ writel(0, &winregs[1].ctrl);
writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
-
- /* Window 2: PCI MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+ ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+/* Disable window 2, configure it for its intended target, enable it. */
+ writel(0, &winregs[2].ctrl);
+ writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
- writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
-
- /* Window 3: PCI IO address space */
+/* Disable window 3, configure it for its intended target, enable it. */
+ writel(0, &winregs[3].ctrl);
+ writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
- writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
-
- /* Window 4: DEV_CS0 address space */
+/* Disable window 4, configure it for its intended target, enable it. */
+ writel(0, &winregs[4].ctrl);
+ writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
- writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
-
- /* Window 5: DEV_CS1 address space */
+/* Disable window 5, configure it for its intended target, enable it. */
+ writel(0, &winregs[5].ctrl);
+ writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
- writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
-
- /* Window 6: DEV_CS2 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+/* Disable window 6, configure it for FLASH, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
- writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
-
- /* Window 7: BOOT Memory address space */
+/* Disable window 7, configure it for FLASH, enable it. */
+ writel(0, &winregs[7].ctrl);
+ writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
+/* Disable window 6, configure it for its intended target, enable it. */
+ writel(0, &winregs[6].ctrl);
+ writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+ ORION5X_WIN_ENABLE), &winregs[6].ctrl);
return 0;
}
writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+ /* initialize timer */
+ timer_init_r();
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
result = winregs[bank].base;
return result;
}
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
- gd->bd->bi_dram[i].size = get_ram_size(
- (volatile long *) (gd->bd->bi_dram[i].start),
- CONFIG_MAX_RAM_BANK_SIZE);
- }
- return 0;
-}
-#else
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
CONFIG_MAX_RAM_BANK_SIZE);
}
}
-#endif
cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
writel(cntmrctrl, CNTMR_CTRL_REG);
+ return 0;
+}
+void timer_init_r(void)
+{
/* init the timestamp and lastdec value */
reset_timer_masked();
-
- return 0;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS := reset.o \
timer.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <version.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
+ ldr r0, _nand_boot_ofs
+ mov pc, r0
-_nand_boot: .word nand_boot
+_nand_boot_ofs:
+ .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-#ifndef CONFIG_PRELOADER
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-#endif /* CONFIG_PRELOADER */
- sub sp, r0, #12 /* leave 3 words for abort-stack */
-#ifndef CONFIG_PRELOADER
- bic sp, r0, #7 /* 8-byte align stack for ABI compliance */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- bl coloured_LED_init
- bl red_LED_on
-#endif /* CONFIG_PRELOADER */
-
- ldr pc, _start_armboot
-
-_start_armboot:
-#if defined(CONFIG_NAND_SPL)
- .word nand_boot
-#elif defined(CONFIG_ONENAND_IPL)
- .word start_oneboot
-#else
- .word start_armboot
-#endif /* CONFIG_NAND_SPL */
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = timer.o
SOBJS = reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.balignl 16,0xdeadbeef
+_vectors_end:
/*
*************************************************************************
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- bne clbss_l
+ blo clbss_l
#endif
/*
_nand_boot: .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- bne clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot:
- .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE /* address of _start in the linked image */
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+#ifdef CONFIG_NAND_SPL
+ ldr r0, _nand_boot_ofs
+ mov pc, r0
+
+_nand_boot_ofs:
+ .word nand_boot
+#else
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-.globl reset
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* pc relative address of label */
- ldr r1, _TEXT_BASE /* linked image address of label */
- cmp r0, r1 /* test if we run from flash or RAM */
- beq stack_setup /* ifeq we are in the RAM copy */
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-_start_armboot:
- .word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START := start.o
COBJS := cpu.o
+COBJS += syslib.o
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
sinclude $(obj).depend
-#########################################################################
\ No newline at end of file
+#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o iomux.o timer.o speed.o
SOBJS = lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
return freq / (reg + 1);
}
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
default:
return 0;
}
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
default:
return 66500000;
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_MX51_HCLK_FREQ;
+ ret_val = CONFIG_SYS_MX5_HCLK;
else
ret_val = ((32768 * 1024));
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
default:
break;
}
/*
* Dump some core clockes.
*/
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll1: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll2: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll3: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll1: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll2: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll3: %dMHz\n", freq / 1000000);
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
/***************************************************/
U_BOOT_CMD(
- clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
- "display mx51 clocks\n",
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+ "display clocks\n",
""
);
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
init_l2cc
init_aips
#include <fsl_esdhc.h>
#endif
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
u32 get_cpu_rev(void)
{
- int reg;
- int system_rev;
+ int system_rev = CPU_TYPE;
+ int reg = __raw_readl(ROM_SI_REV);
- reg = __raw_readl(ROM_SI_REV);
switch (reg) {
case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
+ system_rev |= CHIP_REV_1_1;
break;
case 0x10:
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev = 0x51000 | CHIP_REV_2_5;
+ system_rev |= CHIP_REV_2_5;
else
- system_rev = 0x51000 | CHIP_REV_2_0;
+ system_rev |= CHIP_REV_2_0;
break;
case 0x20:
- system_rev = 0x51000 | CHIP_REV_3_0;
+ system_rev |= CHIP_REV_3_0;
break;
return system_rev;
default:
- system_rev = 0x51000 | CHIP_REV_1_0;
+ system_rev |= CHIP_REV_1_0;
break;
}
return system_rev;
u32 cpurev;
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
- (cpurev & 0xF0) >> 4,
- (cpurev & 0x0F) >> 4,
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}
return rc;
}
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ for (i = 0; i < 6; i++)
+ mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif
+
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
int get_clocks(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
#ifdef CONFIG_FSL_ESDHC
gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
#endif
void reset_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
- timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
+ timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return timestamp;
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
- tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
+ tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
if (!tmo)
tmo = 1;
include $(TOPDIR)/config.mk
-LIB = $(obj)libomap-common.a
+LIB = $(obj)libomap-common.o
SOBJS := reset.o
COBJS := timer.o
-COBJS += syslib.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h>
#include <asm/io.h>
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
void set_timer(ulong t)
{
- timestamp = t;
+ gd->tbl = t;
}
/* delay x useconds */
void reset_timer_masked(void)
{
/* reset time, capture current incrementer value time */
- lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
/* current tick value */
ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- if (now >= lastinc) /* normal mode (non roll) */
+ if (now >= gd->lastinc) /* normal mode (non roll) */
/* move stamp fordward with absoulte diff ticks */
- timestamp += (now - lastinc);
+ gd->tbl += (now - gd->lastinc);
else /* we have rollover of incrementer */
- timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- - lastinc) + now;
- lastinc = now;
- return timestamp;
+ gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
+ - gd->lastinc) + now;
+ gd->lastinc = now;
+ return gd->tbl;
}
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
SOBJS += cache.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <asm/arch/sys_proto.h>
#include <asm/arch/emif4.h>
+DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
*/
u32 get_sdr_cs_size(u32 cs)
{
- u32 size;
+ u32 size = 0;
/* TODO: Calculate the size based on EMIF4 configuration */
- size = CONFIG_SYS_CS0_SIZE;
+ if (cs == CS0)
+ size = CONFIG_SYS_CS0_SIZE;
return size;
}
* dram_init -
* - Sets uboots idea of sdram size
*/
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-}
-#else
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
void dram_init_banksize (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
-#endif
/*
* mem_init() -
#include <asm/arch/clocks_omap3.h>
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
extern omap3_sysinfo sysinfo;
static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
return 0;
offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+ offset = (offset & 15) << 27 | (offset & 0x30) << 17;
return offset;
}
&sdrc_actim_base1->ctrla);
writel(readl(&sdrc_actim_base0->ctrlb),
&sdrc_actim_base1->ctrlb);
+
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(readl(&sdrc_base->cs[CS0].mr),
+ &sdrc_base->cs[CS1].mr);
}
/*
* dram_init -
* - Sets uboots idea of sdram size
*/
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
- do_sdrc_init(CS1, NOT_EARLY);
- make_cs1_contiguous();
-
- size1 = get_sdr_cs_size(CS1);
- }
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-}
-#else
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
void dram_init_banksize (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
-#endif
/*
* mem_init -
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS += lowlevel_init.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Routine: s_init
* Description: Does early system init of muxing and clocks.
*/
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
- gd->bd->bi_dram[0].start = 0x80000000;
- gd->bd->bi_dram[0].size = sdram_size();
+ gd->ram_size = sdram_size();
+
return 0;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)libs5p-common.a
+LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
COBJS-y += timer.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
{
s5p_set_cpu_id();
- s5p_clock_init();
-
return 0;
}
#endif
#define TCON_TIMER4_SHIFT 20
-static unsigned long count_value;
+static unsigned long count_value = 1;
/* Internal tick units */
-static unsigned long long timestamp; /* Monotonic incrementing timer */
-static unsigned long lastdec; /* Last decremneter snapshot */
+static unsigned long long timestamp = 1; /* Monotonic incrementing timer */
+static unsigned long lastdec = 1; /* Last decremneter snapshot */
/* macro to read the 16 bit timer */
static inline struct s5p_timer *s5p_get_base_timer(void)
#include <asm/errno.h>
#include "usb-hs-otg.h"
-u32 remode_wakeup;
-u16 config_value;
+static u32 remode_wakeup;
+static u16 config_value;
int s5p_receive_done;
int s5p_usb_connected;
ep0_idle, ep0_setup, ep0_data, ep0_complete
};
-int dma_state;
+static int dma_state;
/*------------------------------------------------*/
/* EP0 state */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS = cache.o
SOBJS += reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#define CONFIG_SYS_CLK_FREQ_C110 24000000
#endif
-void (*set_mmc_clk)(int dev_index, unsigned int div);
-unsigned long (*get_lcd_clk)(void);
-unsigned long (*get_uart_clk)(int dev_index);
-unsigned long (*get_pwm_clk)(void);
-unsigned long (*get_arm_clk)(void);
-unsigned long (*get_pll_clk)(int);
-
/* s5pc110: return pll clock frequency */
static unsigned long s5pc100_get_pll_clk(int pllreg)
{
return pclk;
}
-void s5p_clock_init(void)
+unsigned long get_pll_clk(int pllreg)
{
- if (cpu_is_s5pc110()) {
- get_pll_clk = s5pc110_get_pll_clk;
- get_arm_clk = s5pc110_get_arm_clk;
- get_lcd_clk = s5pc110_get_lcd_clk;
- } else {
- get_pll_clk = s5pc100_get_pll_clk;
- get_arm_clk = s5pc100_get_arm_clk;
- get_lcd_clk = NULL;
- }
- get_uart_clk = s5pc1xx_get_uart_clk;
- get_pwm_clk = s5pc1xx_get_pwm_clk;
- set_mmc_clk = NULL;
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pll_clk(pllreg);
+ else
+ return s5pc100_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_arm_clk();
+ else
+ return s5pc100_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc1xx_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc1xx_get_uart_clk(dev_index);
+}
+
+unsigned long get_lcd_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_lcd_clk();
+ return 0;
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ /* DO NOTHING */
}
u32 irq[3];
u32 abt[3];
u32 und[3];
-} ____cacheline_aligned;
+};
static struct stack stacks[1];
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(SOC).o
SOBJS = cache.o
SOBJS += reset.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#endif
-void (*set_mmc_clk)(int dev_index, unsigned int div);
-int (*set_lcd_clk)(const unsigned int dev_index,
- const unsigned int pclk_name, const unsigned int div);
-unsigned long (*get_lcd_clk)(void);
-unsigned long (*get_uart_clk)(int dev_index);
-unsigned long (*get_pwm_clk)(void);
-unsigned long (*get_arm_clk)(void);
-unsigned long (*get_pll_clk)(int);
-
/* s5pc210: return pll clock frequency */
static unsigned long s5pc210_get_pll_clk(int pllreg)
{
writel(val, addr);
}
-void s5p_clock_init(void)
+unsigned long get_pll_clk(int pllreg)
{
- if (cpu_is_s5pc210()) {
- get_pll_clk = s5pc210_get_pll_clk;
- get_arm_clk = s5pc210_get_arm_clk;
- get_uart_clk = s5pc210_get_uart_clk;
- get_pwm_clk = s5pc210_get_pwm_clk;
- get_lcd_clk = s5pc210_get_lcd_clk;
- set_mmc_clk = s5pc210_set_mmc_clk;
- set_lcd_clk = s5pc210_set_lcd_clk;
- }
+ return s5pc210_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ return s5pc210_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc210_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc210_get_uart_clk(dev_index);
+}
+
+unsigned long get_lcd_clk(void)
+{
+ return s5pc210_get_lcd_clk();
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ s5pc210_set_mmc_clk(dev_index, div);
+}
+
+int set_lcd_clk(const unsigned int dev_index,
+ const unsigned int pclk_name, const unsigned int div)
+{
+ return s5pc210_set_lcd_clk(dev_index, pclk_name, div);
}
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _start
_start: b reset
-#if !defined(CONFIG_PRELOADER)
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
-#else
- . = _start + 64
-#endif
.global _end_vect
_end_vect:
*
*************************************************************************/
-#if !defined(CONFIG_PRELOADER)
.globl _TEXT_BASE
-#endif
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_PRELOADER)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-#if !defined(CONFIG_PRELOADER)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-#endif
-
/*
* the actual reset code
*/
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_PRELOADER)
#if (CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
-#endif /* CONFIG_PRELOADER */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
-#if !defined(CONFIG_PRELOADER)
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
-#endif
/*------------------------------------------------------------------------------*/
* after relocating the monitor code.
*
*/
-#if !defined(CONFIG_PRELOADER)
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
-#else
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: @ relocate U-Boot to RAM
- adr r0, _start @ r0 <- current position of code
- ldr r1, _TEXT_BASE @ test if we run from flash or RAM
- cmp r0, r1 @ don't reloc during debug
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 @ r2 <- size of armboot
- add r2, r0, r2 @ r2 <- source end address
-
-copy_loop: @ copy 32 bytes at a time
- ldmia r0!, {r3 - r10} @ copy from source address [r0]
- stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end addreee [r2]
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
-stack_setup:
- ldr r0, _TEXT_BASE
- /* As _TEXT_BASE is internal RAM start address don't sub it */
- add sp, r0, #128
- bic sp, sp, #7
-
- ldr pc, _start_armboot @ jump to C code
-#if defined(CONFIG_ONENAND_IPL)
-_start_armboot: .word start_oneboot
-#elif defined(CONFIG_MMC_IPL)
-_start_armboot: .word start_mmcboot
-#endif
-#endif
-
-#if !defined(CONFIG_SKIP_RELOCATE_UBOOT)
-#if !defined(CONFIG_PRELOADER)
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
- cmp r0, r6
#ifndef CONFIG_PRELOADER
- beq jump_2_ram
+ cmp r0, r6
+ beq clear_bss /* skip relocation */
#endif
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ cmp r0, #0
+ beq fixskip
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+fixskip:
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
clear_bss:
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
cmp r0, r1
bne clbss_l
#endif /* #ifndef CONFIG_PRELOADER */
-#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
-#if !defined(CONFIG_PRELOADER)
jump_2_ram:
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
+_board_init_r_ofs:
+ .word board_init_r - _start
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0, cpsr
- bic r0, r0, #0x1f
- orr r0, r0, #0xd3
- msr cpsr,r0
-
-#if (CONFIG_OMAP34XX)
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start @ r0 <- current position of code
- add r0, r0, #4 @ skip reset vector
- mov r2, #64 @ r2 <- size to copy
- add r2, r0, r2 @ r2 <- source end address
- mov r1, #SRAM_OFFSET0 @ build vect addr
- mov r3, #SRAM_OFFSET1
- add r1, r1, r3
- mov r3, #SRAM_OFFSET2
- add r1, r1, r3
-next:
- ldmia r0!, {r3 - r10} @ copy from source address [r0]
- stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end address [r2]
- bne next @ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
- /* No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
- */
- bl cpy_clk_code @ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
- /* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: @ relocate U-Boot to RAM
- adr r0, _start @ r0 <- current position of code
- ldr r1, _TEXT_BASE @ test if we run from flash or RAM
- cmp r0, r1 @ don't reloc during debug
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 @ r2 <- size of armboot
- add r2, r0, r2 @ r2 <- source end address
-
-copy_loop: @ copy 32 bytes at a time
- ldmia r0!, {r3 - r10} @ copy from source address [r0]
- stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end addreee [r2]
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 @ leave 3 words for abort-stack
- bic sp, sp, #7 @ 8-byte alignment for ABI compliance
-
- /* Clear BSS (if any). Is below tx (watch load addr - need space) */
-clear_bss:
- ldr r0, _bss_start @ find start of bss segment
- ldr r1, _bss_end @ stop here
- mov r2, #0x00000000 @ clear value
-clbss_l:
- str r2, [r0] @ clear BSS location
- cmp r0, r1 @ are we at the end yet
- add r0, r0, #4 @ increment clear index pointer
- bne clbss_l @ keep clearing till at end
-
- ldr pc, _start_armboot @ jump to C code
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*************************************************************************
*
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
-
-#if !defined(CONFIG_PRELOADER)
/*
*************************************************************************
*
@ user stack
stmia sp, {r0 - r12} @ Save user registers (now in
@ svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
-#else
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
@ stack
-#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc
@ and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack (enter
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
@ in banked mode)
-#endif
str lr, [r13] @ save caller lr in position 0
@ of saved stack
sub r13, r13, #4 @ space on current stack for
@ scratch reg.
str r0, [r13] @ save R0's value.
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r0, _armboot_start @ get data regions start
- sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
-#else
ldr r0, IRQ_STACK_START_IN @ get data regions start
@ spots for abort stack
-#endif
str lr, [r0] @ save caller lr in position 0
@ of saved stack
mrs r0, spsr @ get the spsr
bl do_fiq
#endif
-#endif /* CONFIG_PRELOADER */
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
/************************************************************
* sdelay() - simple spin loop. Will be constant time as
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libnpe.a
+LIB := $(obj)libnpe.o
LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
CFLAGS += $(LOCAL_CFLAGS)
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/ixp425.h>
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/****************************************************************************/
-/* */
-/* the actual reset code */
-/* */
-/****************************************************************************/
-
-reset:
- /* disable mmu, set big-endian */
- mov r0, #0xf8
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* disable write buffer coalescing */
- mrc p15, 0, r0, c1, c0, 1
- orr r0, r0, #1
- mcr p15, 0, r0, c1, c0, 1
- CPWAIT r0
-
- /* set EXP CS0 to the optimum timing */
- ldr r1, =CONFIG_SYS_EXP_CS0
- ldr r2, =IXP425_EXP_CS0
- str r1, [r2]
-
- /* make sure flash is visible at 0 */
-#if 0
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- orr r1, r1, #0x80000000
- str r1, [r2]
-#endif
- mov r1, #CONFIG_SYS_SDR_CONFIG
- ldr r2, =IXP425_SDR_CONFIG
- str r1, [r2]
-
- /* disable refresh cycles */
- mov r1, #0
- ldr r3, =IXP425_SDR_REFRESH
- str r1, [r3]
-
- /* send nop command */
- mov r1, #3
- ldr r4, =IXP425_SDR_IR
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* set SDRAM internal refresh val */
- ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
- str r1, [r3]
- DELAY_FOR 0x4000, r0
-
- /* send precharge-all command to close all open banks */
- mov r1, #2
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* provide 8 auto-refresh cycles */
- mov r1, #4
- mov r5, #8
-111: str r1, [r4]
- DELAY_FOR 0x100, r0
- subs r5, r5, #1
- bne 111b
-
- /* set mode register in sdram */
- mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* send normal operation command */
- mov r1, #6
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* copy */
- mov r0, #0
- mov r4, r0
- add r2, r0, #CONFIG_SYS_MONITOR_LEN
- mov r1, #0x10000000
- mov r5, r1
-
- 30:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r0, r2
- bne 30b
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* move flash to 0x50000000 */
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- bic r1, r1, #0x80000000
- str r1, [r2]
-
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- mrs r0,cpsr /* set the cpu to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
- orr r0,r0,#0x13
- msr cpsr,r0
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_board_init_r_ofs:
+ .word board_init_r - _start
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/****************************************************************************/
/* */
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o speed.o timer.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-
/*
*************************************************************************
*
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
-#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
-#define pCLKSET 0x80000420 /* clock divisor register */
-
- /* disable watchdog, set watchdog control register to
- * all zeros (default reset)
- */
- ldr r0, =pWDTCTL
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTENC register (default)
- */
- mov r1, #0xffffffff
- ldr r0, =pINTENC
- str r1, [r0]
-
- /* FCLK:HCLK:PCLK = 1:2:2 */
- /* default FCLK is 200 MHz, using 14.7456 MHz fin */
- ldr r0, =pCLKSET
- ldr r1, =0x0004ee39
-@ ldr r1, =0x0005ee39 @ 1: 2: 4
- str r1, [r0]
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- blt copy_loop /* a 'ble' here actually copies */
- /* four bytes of bss */
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- @add r0, r0, #4 /* start at first byte of bss */
- /* why inc. 4 bytes past then? */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* CPU specific code
*/
-#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
#include <command.h>
+#include <common.h>
#include <asm/arch/pxa-regs.h>
-#include <asm/system.h>
static void cache_flush(void);
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
- int gafr;
+ int val;
+
+ /* This below changes direction setting of GPIO "gpio" */
+ val = readl(GPDR(gpio));
if (gpio_mode & GPIO_MD_MASK_DIR)
- {
- GPDR(gpio) |= GPIO_bit(gpio);
- }
+ val |= GPIO_bit(gpio);
else
- {
- GPDR(gpio) &= ~GPIO_bit(gpio);
- }
- gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
- GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
+ val &= ~GPIO_bit(gpio);
+
+ writel(val, GPDR(gpio));
+
+ /* This below updates only AF of GPIO "gpio" */
+ val = readl(GAFR(gpio));
+ val &= ~(0x3 << (((gpio) & 0xf) * 2));
+ val |= fn << (((gpio) & 0xf) * 2);
+ writel(val, GAFR(gpio));
}
#endif /* CONFIG_CPU_MONAHANS */
+
+void pxa_wait_ticks(int ticks)
+{
+ writel(0, OSCR);
+ while (readl(OSCR) < ticks)
+ asm volatile("":::"memory");
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+ writel(val, addr);
+ asm volatile("":::"memory");
+ readl(addr);
+ asm volatile("":::"memory");
+}
+
+void pxa_dram_init(void)
+{
+ uint32_t tmp;
+ int i;
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+ writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+ writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ writelrb(CONFIG_SYS_MECR_VAL, MECR);
+ /* MCMEM0: Card Interface slot 0 timing */
+ writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+ /* MCMEM1: Card Interface slot 1 timing */
+ writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+
+ /* Read current MDREFR config and zero out DRI */
+ tmp = readl(MDREFR) & ~0xfff;
+ /* Add user-specified DRI */
+ tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+ /* Configure important bits */
+ tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+ tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+ /* Write MDREFR back */
+ writelrb(tmp, MDREFR);
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+ writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ writelrb(CONFIG_SYS_MDCNFG_VAL &
+ ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ pxa_wait_ticks(0x300);
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+ for (i = 9; i >= 0; i--) {
+ writel(i, 0xa0000000);
+ asm volatile("":::"memory");
+ }
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ tmp = CONFIG_SYS_MDCNFG_VAL &
+ (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+ tmp |= readl(MDCNFG);
+ writelrb(tmp, MDCNFG);
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+ /*
+ * 11) Enable APD
+ */
+
+ if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+ tmp = readl(MDREFR);
+ tmp |= MDREFR_APD;
+ writelrb(tmp, MDREFR);
+ }
+}
+
+void pxa_gpio_setup(void)
+{
+ writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+ writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+ writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+ writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+ writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+ writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+ writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+ writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+ writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+ writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+ writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+ writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+ writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+ writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+ writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+ writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+ writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+ writel(0, ICLR);
+ writel(0, ICMR);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(0, ICLR2);
+ writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+#ifndef CONFIG_CPU_MONAHANS
+ writel(CONFIG_SYS_CKEN, CKEN);
+ writel(CONFIG_SYS_CCCR, CCCR);
+ asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
+#else
+/* Set CKENA/CKENB/ACCR for MH */
+#endif
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ writel(OSCC_OON, OSCC);
+ while(!(readl(OSCC) & OSCC_OOK))
+ asm volatile("":::"memory");
+}
+
+void pxa_wakeup(void)
+{
+ uint32_t rcsr;
+
+ rcsr = readl(RCSR);
+ writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+ /* Wakeup */
+ if (rcsr & RCSR_SMR) {
+ writel(PSSR_PH, PSSR);
+ pxa_dram_init();
+ icache_disable();
+ dcache_disable();
+ asm volatile("mov pc, %0"::"r"(readl(PSSR)));
+ }
+}
+
+int arch_cpu_init(void)
+{
+ pxa_gpio_setup();
+/* pxa_wait_ticks(0x8000); */
+ pxa_wakeup();
+ pxa_interrupt_setup();
+ pxa_clock_setup();
+ return 0;
+}
/* FIXME: this file is PXA255 specific! What about other XScales? */
#include <common.h>
+#include <asm/io.h>
#ifdef CONFIG_HARD_I2C
static void i2c_reset( void )
{
- ICR &= ~ICR_IUE; /* disable unit */
- ICR |= ICR_UR; /* reset the unit */
+ writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
+ writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
udelay(100);
- ICR &= ~ICR_IUE; /* disable unit */
+ writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
#ifdef CONFIG_CPU_MONAHANS
- CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+ /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
#else /* CONFIG_CPU_MONAHANS */
- CKEN |= CKEN14_I2C; /* set the global I2C clock on */
+ /* set the global I2C clock on */
+ writel(readl(CKEN) | CKEN14_I2C, CKEN);
#endif
- ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
- ICR = I2C_ICR_INIT; /* set control register values */
- ISR = I2C_ISR_INIT; /* set clear interrupt bits */
- ICR |= ICR_IUE; /* enable unit */
+ writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
+ writel(I2C_ICR_INIT, ICR); /* set control reg values */
+ writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
+ writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
udelay(100);
}
goto transfer_error_bus_busy;
/* start transmission */
- ICR &= ~ICR_START;
- ICR &= ~ICR_STOP;
- IDBR = msg->data;
- if (msg->condition == I2C_COND_START) ICR |= ICR_START;
- if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
- if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
- if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
- ICR &= ~ICR_ALDIE;
- ICR |= ICR_TB;
+ writel(readl(ICR) & ~ICR_START, ICR);
+ writel(readl(ICR) & ~ICR_STOP, ICR);
+ writel(msg->data, IDBR);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(ICR) | ICR_START, ICR);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(ICR) | ICR_STOP, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(ICR) | ICR_ACKNAK, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+ writel(readl(ICR) & ~ICR_ALDIE, ICR);
+ writel(readl(ICR) | ICR_TB, ICR);
/* transmit register empty? */
if (!i2c_isr_set_cleared(ISR_ITE,0))
goto transfer_error_transmit_timeout;
/* clear 'transmit empty' state */
- ISR |= ISR_ITE;
+ writel(readl(ISR) | ISR_ITE, ISR);
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
goto transfer_error_bus_busy;
/* start receive */
- ICR &= ~ICR_START;
- ICR &= ~ICR_STOP;
- if (msg->condition == I2C_COND_START) ICR |= ICR_START;
- if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
- if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
- if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
- ICR &= ~ICR_ALDIE;
- ICR |= ICR_TB;
+ writel(readl(ICR) & ~ICR_START, ICR);
+ writel(readl(ICR) & ~ICR_STOP, ICR);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(ICR) | ICR_START, ICR);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(ICR) | ICR_STOP, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(ICR) | ICR_ACKNAK, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+ writel(readl(ICR) & ~ICR_ALDIE, ICR);
+ writel(readl(ICR) | ICR_TB, ICR);
/* receive register full? */
if (!i2c_isr_set_cleared(ISR_IRF,0))
goto transfer_error_receive_timeout;
- msg->data = IDBR;
+ msg->data = readl(IDBR);
/* clear 'receive empty' state */
- ISR |= ISR_IRF;
+ writel(readl(ISR) | ISR_IRF, ISR);
break;
#include <stdio_dev.h>
#include <lcd.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
/* #define DEBUG */
/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 640,
- vl_height: 480,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 0,
- vl_clor: 0,
- vl_tft: 1,
- vl_hpw: 40,
- vl_blw: 56,
- vl_elw: 56,
- vl_vpw: 20,
- vl_bfw: 8,
- vl_efw: 8,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 640,
+ .vl_height = 480,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 0,
+ .vl_clor = 0,
+ .vl_tft = 1,
+ .vl_hpw = 40,
+ .vl_blw = 56,
+ .vl_elw = 56,
+ .vl_vpw = 20,
+ .vl_bfw = 8,
+ .vl_efw = 8,
};
#endif /* CONFIG_PXA_VIDEO */
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 157,
- vl_height: 118,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 0,
- vl_hpw: 1,
- vl_blw: 3,
- vl_elw: 3,
- vl_vpw: 1,
- vl_bfw: 0,
- vl_efw: 0,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 157,
+ .vl_height = 118,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 0,
+ .vl_hpw = 1,
+ .vl_blw = 3,
+ .vl_elw = 3,
+ .vl_vpw = 1,
+ .vl_bfw = 0,
+ .vl_efw = 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 157,
- vl_height: 118,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 1,
- vl_hpw: 32,
- vl_blw: 144,
- vl_elw: 32,
- vl_vpw: 2,
- vl_bfw: 13,
- vl_efw: 30,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 157,
+ .vl_height = 118,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 32,
+ .vl_blw = 144,
+ .vl_elw = 32,
+ .vl_vpw = 2,
+ .vl_bfw = 13,
+ .vl_efw = 30,
};
#endif /* CONFIG_VOIPAC_LCD */
#define REG_LCCR3 0x0340FF20
vidinfo_t panel_info = {
- vl_col: 320,
- vl_row: 240,
- vl_width: 167,
- vl_height: 109,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 1,
- vl_splt: 0,
- vl_clor: 1,
- vl_tft: 0,
- vl_hpw: 1,
- vl_blw: 1,
- vl_elw: 1,
- vl_vpw: 7,
- vl_bfw: 0,
- vl_efw: 0,
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_width = 167,
+ .vl_height = 109,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 1,
+ .vl_splt = 0,
+ .vl_clor = 1,
+ .vl_tft = 0,
+ .vl_hpw = 1,
+ .vl_blw = 1,
+ .vl_elw = 1,
+ .vl_vpw = 7,
+ .vl_bfw = 0,
+ .vl_efw = 0,
};
#endif /* CONFIG_HITACHI_SX14 */
# define REG_LCCR3 0x03b00009
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_width: 240,
- vl_height: 320,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_LOW,
- vl_hsp: CONFIG_SYS_LOW,
- vl_vsp: CONFIG_SYS_LOW,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 1,
- vl_hpw: 4,
- vl_blw: 4,
- vl_elw: 8,
- vl_vpw: 4,
- vl_bfw: 4,
- vl_efw: 8,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_width = 240,
+ .vl_height = 320,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 4,
+ .vl_blw = 4,
+ .vl_elw = 8,
+ .vl_vpw = 4,
+ .vl_bfw = 4,
+ .vl_efw = 8,
};
#endif /* CONFIG_LMS283GF05 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_ACX517AKN
+
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x03700006
+
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 320,
+ .vl_width = 320,
+ .vl_height = 320,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 0x04,
+ .vl_blw = 0x1c,
+ .vl_elw = 0x08,
+ .vl_vpw = 0x01,
+ .vl_bfw = 0x07,
+ .vl_efw = 0x08,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LQ038J7DH53
+
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x03700004
+
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 480,
+ .vl_width = 320,
+ .vl_height = 480,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 0x04,
+ .vl_blw = 0x20,
+ .vl_elw = 0x01,
+ .vl_vpw = 0x01,
+ .vl_bfw = 0x04,
+ .vl_efw = 0x01,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LITTLETON_LCD
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f8
+# define REG_LCCR3 0x0300FF04
+
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 640,
+ .vl_width = 480,
+ .vl_height = 640,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 0,
+ .vl_clor = 0,
+ .vl_tft = 1,
+ .vl_hpw = 9,
+ .vl_blw = 8,
+ .vl_elw = 24,
+ .vl_vpw = 2,
+ .vl_bfw = 2,
+ .vl_efw = 4,
+};
+#endif /* CONFIG_LITTLETON_LCD */
+
+/*----------------------------------------------------------------------*/
+
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
{
debug("Setting GPIO for 4 bit data\n");
/* bits 58-61 */
- GPDR1 |= (0xf << 26);
- GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR1) | (0xf << 26), GPDR1);
+ writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR1_U);
/* bits 74-77 */
- GPDR2 |= (0xf << 10);
- GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR2) | (0xf << 10), GPDR2);
+ writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR2_L);
}
/* 8 bit interface */
{
debug("Setting GPIO for 8 bit data\n");
/* bits 58-65 */
- GPDR1 |= (0x3f << 26);
- GPDR2 |= (0x3);
+ writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+ writel(readl(GPDR2) | (0x3), GPDR2);
- GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
- GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
+ writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+ GAFR1_U);
+ writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
/* bits 74-77 */
- GPDR2 |= (0xf << 10);
- GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR2) | (0xf << 10), GPDR2);
+ writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR2_L);
}
/* 16 bit interface */
{
debug("Setting GPIO for 16 bit data\n");
/* bits 58-77 */
- GPDR1 |= (0x3f << 26);
- GPDR2 |= 0x00003fff;
+ writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+ writel(readl(GPDR2) | 0x00003fff, GPDR2);
- GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
- GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
+ writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+ GAFR1_U);
+ writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
}
else
{
debug("Enabling LCD controller\n");
/* Sequence from 11.7.10 */
- LCCR3 = vid->pxa.reg_lccr3;
- LCCR2 = vid->pxa.reg_lccr2;
- LCCR1 = vid->pxa.reg_lccr1;
- LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
- FDADR0 = vid->pxa.fdadr0;
- FDADR1 = vid->pxa.fdadr1;
- LCCR0 |= LCCR0_ENB;
+ writel(vid->pxa.reg_lccr3, LCCR3);
+ writel(vid->pxa.reg_lccr2, LCCR2);
+ writel(vid->pxa.reg_lccr1, LCCR1);
+ writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
+ writel(vid->pxa.fdadr0, FDADR0);
+ writel(vid->pxa.fdadr1, FDADR1);
+ writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_1_LCD;
+ writel(readl(CKENA) | CKENA_1_LCD, CKENA);
#else
- CKEN |= CKEN16_LCD;
+ writel(readl(CKEN) | CKEN16_LCD, CKEN);
#endif
- debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
- debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
- debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
- debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
- debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
- debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
+ debug("FDADR0 = 0x%08x\n", readl(FDADR0));
+ debug("FDADR1 = 0x%08x\n", readl(FDADR1));
+ debug("LCCR0 = 0x%08x\n", readl(LCCR0));
+ debug("LCCR1 = 0x%08x\n", readl(LCCR1));
+ debug("LCCR2 = 0x%08x\n", readl(LCCR2));
+ debug("LCCR3 = 0x%08x\n", readl(LCCR3));
}
static int pxafb_init (vidinfo_t *vid)
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ * Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
+/* takes care the CP15 update has taken place */
+.macro CPWAIT reg
+mrc p15,0,\reg,c2,c0,0
+mov \reg,\reg
+sub pc,pc,#4
+.endm
+
.globl _start
_start: b reset
#ifdef CONFIG_PRELOADER
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#ifndef CONFIG_PRELOADER
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
msr cpsr,r0
/*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
+ * Enable MMU to use DCache as DRAM
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
+ /* Domain access -- enable for all CPs */
+ ldr r0, =0x0000ffff
+ mcr p15, 0, r0, c3, c0, 0
+
+ /* Point TTBR to MMU table */
+ ldr r0, =mmu_table
+ adr r2, _start
+ orr r0, r2
+ mcr p15, 0, r0, c2, c0, 0
+
+/* !!! Hereby, check if the code is running from SRAM !!! */
+/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
+ * is linked to 0x0 too, so this makes things easier. */
+ cmp r2, #0x5c000000
+
+ ldreq r1, [r0]
+ orreq r1, r2
+ streq r1, [r0]
+
+ /* Kick in MMU, ICache, DCache, BTB */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #0x1b00
+ bic r0, #0x0087
+ orr r0, #0x1800
+ orr r0, #0x0005
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
+
+ /* Unlock Icache, Dcache */
+ mcr p15, 0, r0, c9, c1, 1
+ mcr p15, 0, r0, c9, c2, 1
+
+ /* Flush Icache, Dcache, BTB */
+ mcr p15, 0, r0, c7, c7, 0
+
+ /* Unlock I-TLB, D-TLB */
+ mcr p15, 0, r0, c10, c4, 1
+ mcr p15, 0, r0, c10, c8, 1
+
+ /* Flush TLB */
+ mcr p15, 0, r0, c8, c7, 0
+ /* Allocate 4096 bytes of Dcache as RAM */
+
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+
+ mov r4, #0x00
+ mov r5, #0x00
+ mov r2, #0x01
+ mcr p15, 0, r0, c9, c2, 0
+ CPWAIT r0
+
+ /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+ mov r0, #128
+ mov r1, #0xa0000000
+alloc:
+ mcr p15, 0, r1, c7, c2, 5
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ subs r0, #0x01
+ bne alloc
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ mov r2, #0x00
+ mcr p15, 0, r2, c9, c2, 0
+ CPWAIT r0
+
+ /* Jump to 0x0 ( + offset) if running from SRAM */
+ adr r0, zerojmp
+ bic r0, #0x5c000000
+ mov pc, r0
+zerojmp:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ stmfd sp!, {r0-r12}
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
+ stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
+ ldmfd sp!, {r0-r12}
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
-#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
+ blo fixloop
+#endif /* #ifndef CONFIG_PRELOADER */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
add r0, r0, #4
cmp r0, r1
bne clbss_l
-#endif
+#endif /* #ifndef CONFIG_PRELOADER */
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
#ifdef CONFIG_ONENAND_IPL
- ldr pc, _start_oneboot
+ ldr r0, _start_oneboot_ofs
+ mov pc, r0
-_start_oneboot: .word start_oneboot
+_start_oneboot_ofs
+ : .word start_oneboot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-#endif
+_board_init_r_ofs:
+ .word board_init_r - _start
+#endif /* CONFIG_ONENAND_IPL */
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+#else /* CONFIG_PRELOADER */
/****************************************************************************/
/* */
-/* the actual reset code */
+/* the actual reset code for OneNAND IPL */
/* */
/****************************************************************************/
+#ifndef CONFIG_PXA27X
+#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
+#endif
+
reset:
- mrs r0,cpsr /* set the CPU to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
+ /* Set CPU to SVC32 mode */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from RAM!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit /* we do sys-critical inits */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
-#ifndef CONFIG_PRELOADER
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-#endif
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- ble copy_loop
-#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
+ /* Point stack at the end of SRAM and leave 32 words for abort-stack */
+ ldr sp, =0x5c03ff80
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-#ifdef CONFIG_PRELOADER
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-#else
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif /* CONFIG_USE_IRQ */
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-#endif
+ /* Start OneNAND IPL */
+ ldr pc, =start_oneboot
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-#endif
-
- ldr pc, _start_armboot
-
-#ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
-#else
-_start_armboot: .word start_armboot
-#endif
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/****************************************************************************/
-/* */
-/* CPU_init_critical registers */
-/* */
-/* - setup important registers */
-/* - setup memory timing */
-/* */
-/****************************************************************************/
-/* mk@tbd: Fix this! */
-#undef RCSR
-#undef ICMR
-#undef OSMR3
-#undef OSCR
-#undef OWER
-#undef OIER
-#undef CCCR
-
-/* Interrupt-Controller base address */
-IC_BASE: .word 0x40d00000
-#define ICMR 0x04
-
-/* Reset-Controller */
-RST_BASE: .word 0x40f00030
-#define RCSR 0x00
-
-/* Operating System Timer */
-OSTIMER_BASE: .word 0x40a00000
-#define OSMR3 0x0C
-#define OSCR 0x10
-#define OWER 0x18
-#define OIER 0x1C
-
-/* Clock Manager Registers */
-#ifdef CONFIG_CPU_MONAHANS
-# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
-# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
-# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
-# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
-CC_BASE: .word 0x41300000
-#define CCCR 0x00
-cpuspeed: .word CONFIG_SYS_CPUSPEED
-#else /* !CONFIG_SYS_CPUSPEED */
-#error "You have to define CONFIG_SYS_CPUSPEED!!"
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
- /* takes care the CP15 update has taken place */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-cpu_init_crit:
-
- /* mask all IRQs */
-#ifndef CONFIG_CPU_MONAHANS
- ldr r0, IC_BASE
- mov r1, #0x00
- str r1, [r0, #ICMR]
-#else /* CONFIG_CPU_MONAHANS */
- /* Step 1 - Enable CP6 permission */
- mrc p15, 0, r1, c15, c1, 0 @ read CPAR
- orr r1, r1, #0x40
- mcr p15, 0, r1, c15, c1, 0
- CPWAIT r1
-
- /* Step 2 - Mask ICMR & ICMR2 */
- mov r1, #0
- mcr p6, 0, r1, c1, c0, 0 @ ICMR
- mcr p6, 0, r1, c7, c0, 0 @ ICMR2
-
- /* turn off all clocks but the ones we will definitly require */
- ldr r1, =CKENA
- ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
- str r2, [r1]
- ldr r1, =CKENB
- ldr r2, =(CKENB_6_IRQ)
- str r2, [r1]
-#endif /* !CONFIG_CPU_MONAHANS */
-
- /* set clock speed */
-#ifdef CONFIG_CPU_MONAHANS
- ldr r0, =ACCR
- ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
- str r1, [r0]
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
- ldr r0, CC_BASE
- ldr r1, cpuspeed
- str r1, [r0, #CCCR]
- mov r0, #2
- mcr p14, 0, r0, c6, c0, 0
-
-setspeed_done:
-
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
- /*
- * before relocating, we have to setup RAM timing
- * because memory timing is board-dependend, you will
- * find a lowlevel_init.S in your board directory.
- */
- mov ip, lr
- bl lowlevel_init
- mov lr, ip
-
- /* Memory interfaces are working. Disable MMU and enable I-cache. */
- /* mk: hmm, this is not in the monahans docs, leave it now but
- * check here if it doesn't work :-) */
-
- ldr r0, =0x2001 /* enable access to all coproc. */
- mcr p15, 0, r0, c15, c1, 0
- CPWAIT r0
-
- mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
- CPWAIT r0
-
- mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
- CPWAIT r0
-
- mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
- CPWAIT r0
-
- /* Enable the Icache */
-/*
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x1800
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT
-*/
- mov pc, lr
+#endif /* CONFIG_PRELOADER */
#ifndef CONFIG_PRELOADER
/****************************************************************************/
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_PRELOADER
/****************************************************************************/
do_hang:
ldr sp, _TEXT_BASE /* use 32 words abort stack */
bl hang /* hang and never return */
-#else /* !CONFIG_PRELOADER */
+#else
.align 5
undefined_instruction:
get_bad_stack
/* perform a watchdog timeout for a soft reset. */
/* */
/****************************************************************************/
-
- .align 5
+/* Operating System Timer */
+.align 5
.globl reset_cpu
/* FIXME: this code is PXA250 specific. How is this handled on */
/* We set OWE:WME (watchdog enable) and wait until timeout happens */
- ldr r0, OSTIMER_BASE
- ldr r1, [r0, #OWER]
+ ldr r0, =OWER
+ ldr r1, [r0]
orr r1, r1, #0x0001 /* bit0: WME */
- str r1, [r0, #OWER]
+ str r1, [r0]
/* OS timer does only wrap every 1165 seconds, so we have to set */
/* the match register as well. */
- ldr r1, [r0, #OSCR] /* read OS timer */
+ ldr r0, =OSCR
+ ldr r1, [r0] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
- str r1, [r0, #OSMR3]
+ ldr r0, =OSMR3
+ str r1, [r0]
reset_endless:
b reset_endless
+
+#ifndef CONFIG_PRELOADER
+.section .mmudata, "a"
+ .align 14
+ .globl mmu_table
+mmu_table:
+ /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+ .set __base, 0
+ .rept 0xa00
+ .word (__base << 20) | 0xc12
+ .set __base, __base + 1
+ .endr
+
+ /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
+ .word (0xa00 << 20) | 0x1c1e
+
+ .set __base, 0xa01
+ .rept 0x1000 - 0xa01
+ .word (__base << 20) | 0xc12
+ .set __base, __base + 1
+ .endr
+#endif /* CONFIG_PRELOADER */
* MA 02111-1307 USA
*/
-#include <common.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <common.h>
#include <div64.h>
#ifdef CONFIG_USE_IRQ
void reset_timer_masked (void)
{
- OSCR = 0;
+ writel(0, OSCR);
}
ulong get_timer_masked (void)
*/
unsigned long long get_ticks(void)
{
- return OSCR;
+ return readl(OSCR);
}
/*
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
- CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC);
+ writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
/* Enable USB host clock. */
- CKEN |= CKEN10_USBHOST;
+ writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
- UP2OCR = 0x3000c;
+ writel(0x3000c, UP2OCR);
#endif
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
wait_ms(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCHR |= UHCHR_FSBIR;
- while (UHCHR & UHCHR_FSBIR)
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR &= ~UHCHR_SSEP0;
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR &= ~UHCHR_SSEP2;
+ writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
- UHCHR &= ~UHCHR_SSEP1;
- UHCHR &= ~UHCHR_SSE;
+ writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR |= UHCHR_SSEP0;
+ writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR |= UHCHR_SSEP2;
+ writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
- UHCHR |= UHCHR_SSEP1;
- UHCHR |= UHCHR_SSE;
-
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
- UHCHR |= UHCHR_FHR;
- udelay(11);
- UHCHR &= ~UHCHR_FHR;
-
- UHCCOMS |= 1;
- udelay(10);
+ writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR |= UHCHR_SSEP0;
+ /* Disable USB host clock. */
+ writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+ udelay(100);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR |= UHCHR_SSEP2;
+ /* Disable USB host clock. */
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
- UHCHR |= UHCHR_SSEP1;
- UHCHR |= UHCHR_SSE;
return 0;
}
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-
/*
* Jump vector table
*/
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-/*
- now copy to sram the interrupt vector
-*/
- adr r0, real_vectors
- add r2, r0, #1024
- ldr r1, =0x0c000000
- add r1, r1, #0x08
-vector_copy_loop:
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- ble vector_copy_loop
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0x13
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
- /*
- * before relocating, we have to setup RAM timing
- * because memory timing is board-dependend, you will
- * find a lowlevel_init.S in your board directory.
- */
- bl lowlevel_init
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
-/*
- now copy to sram the interrupt vector
-*/
- adr r0, real_vectors
- add r2, r0, #1024
- ldr r1, =0x0c000000
- add r1, r1, #0x08
-vector_copy_loop:
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- ble vector_copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
+_board_init_r_ofs:
+ .word board_init_r - _start
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-
/*
*************************************************************************
*
.globl _TEXT_BASE
_TEXT_BASE:
- .word TEXT_BASE
-
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
+ .word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
-#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
- sub r0, r0, r3
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+ add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0x13
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc, _start_armboot
+_board_init_r_ofs:
+ .word board_init_r - _start
-_start_armboot: .word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
/*
*************************************************************************
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
-#else
ldr r2, IRQ_STACK_START_IN
-#endif
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
- * USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined (CONFIG_ARMADA100)
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
+#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
+#define APBC_RST (1<<2) /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE 0xB0000000
+#define ARMD1_TIMER_BASE 0xD4014000
+#define ARMD1_APBC1_BASE 0xD4015000
+#define ARMD1_APBC2_BASE 0xD4015800
+#define ARMD1_UART1_BASE 0xD4017000
+#define ARMD1_UART2_BASE 0xD4018000
+#define ARMD1_GPIO_BASE 0xD4019000
+#define ARMD1_SSP1_BASE 0xD401B000
+#define ARMD1_SSP2_BASE 0xD401C000
+#define ARMD1_MFPR_BASE 0xD401E000
+#define ARMD1_SSP3_BASE 0xD401F000
+#define ARMD1_SSP4_BASE 0xD4020000
+#define ARMD1_SSP5_BASE 0xD4021000
+#define ARMD1_UART3_BASE 0xD4026000
+#define ARMD1_MPMU_BASE 0xD4050000
+#define ARMD1_APMU_BASE 0xD4282800
+#define ARMD1_CPU_BASE 0xD4282C00
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+ u8 pad0[0x08 - 0x00];
+ u32 fccr; /*0x0008*/
+ u32 pocr; /*0x000c*/
+ u32 posr; /*0x0010*/
+ u32 succr; /*0x0014*/
+ u8 pad1[0x030 - 0x014 - 4];
+ u32 gpcr; /*0x0030*/
+ u8 pad2[0x200 - 0x030 - 4];
+ u32 wdtpcr; /*0x0200*/
+ u8 pad3[0x1000 - 0x200 - 4];
+ u32 apcr; /*0x1000*/
+ u32 apsr; /*0x1004*/
+ u8 pad4[0x1020 - 0x1004 - 4];
+ u32 aprr; /*0x1020*/
+ u32 acgr; /*0x1024*/
+ u32 arsr; /*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+ u32 uart1; /*0x000*/
+ u32 uart2; /*0x004*/
+ u32 gpio; /*0x008*/
+ u32 pwm1; /*0x00c*/
+ u32 pwm2; /*0x010*/
+ u32 pwm3; /*0x014*/
+ u32 pwm4; /*0x018*/
+ u8 pad0[0x028 - 0x018 - 4];
+ u32 rtc; /*0x028*/
+ u32 twsi0; /*0x02c*/
+ u32 kpc; /*0x030*/
+ u32 timers; /*0x034*/
+ u8 pad1[0x03c - 0x034 - 4];
+ u32 aib; /*0x03c*/
+ u32 sw_jtag; /*0x040*/
+ u32 timer1; /*0x044*/
+ u32 onewire; /*0x048*/
+ u8 pad2[0x050 - 0x048 - 4];
+ u32 asfar; /*0x050 AIB Secure First Access Reg*/
+ u32 assar; /*0x054 AIB Secure Second Access Reg*/
+ u8 pad3[0x06c - 0x054 - 4];
+ u32 twsi1; /*0x06c*/
+ u32 uart3; /*0x070*/
+ u8 pad4[0x07c - 0x070 - 4];
+ u32 timer2; /*0x07C*/
+ u8 pad5[0x084 - 0x07c - 4];
+ u32 ac97; /*0x084*/
+};
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+ u32 chip_id; /* Chip Id Reg */
+ u32 pad;
+ u32 cpu_conf; /* CPU Conf Reg */
+ u32 pad1;
+ u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
+ u32 pad2;
+ u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
+ u32 mcb_conf; /* MCB Conf Reg */
+ u32 sys_boot_ctl; /* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
--- /dev/null
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART2 */
+#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART3 */
+#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX 117
+
+#endif /* __ARMADA100_MFP_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYSCTRL_H_
+#define _SYSCTRL_H_
+
+/* System controller (SP810) register definitions */
+#define SP810_TIMER0_ENSEL (1 << 15)
+#define SP810_TIMER1_ENSEL (1 << 17)
+#define SP810_TIMER2_ENSEL (1 << 19)
+#define SP810_TIMER3_ENSEL (1 << 21)
+
+struct sysctrl {
+ u32 scctrl; /* 0x000 */
+ u32 scsysstat;
+ u32 scimctrl;
+ u32 scimstat;
+ u32 scxtalctrl;
+ u32 scpllctrl;
+ u32 scpllfctrl;
+ u32 scperctrl0;
+ u32 scperctrl1;
+ u32 scperen;
+ u32 scperdis;
+ u32 scperclken;
+ u32 scperstat;
+ u32 res1[0x006];
+ u32 scflashctrl; /* 0x04c */
+ u32 res2[0x3a4];
+ u32 scsysid0; /* 0xee0 */
+ u32 scsysid1;
+ u32 scsysid2;
+ u32 scsysid3;
+ u32 scitcr;
+ u32 scitir0;
+ u32 scitir1;
+ u32 scitor;
+ u32 sccntctrl;
+ u32 sccntdata;
+ u32 sccntstep;
+ u32 res3[0x32];
+ u32 scperiphid0; /* 0xfe0 */
+ u32 scperiphid1;
+ u32 scperiphid2;
+ u32 scperiphid3;
+ u32 scpcellid0;
+ u32 scpcellid1;
+ u32 scpcellid2;
+ u32 scpcellid3;
+};
+#endif /* _SYSCTRL_H_ */
/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#ifndef _SYSTIMER_H_
+#define _SYSTIMER_H_
-#ifndef __BOARD_FREESCALE_MX51_EVK_H__
-#define __BOARD_FREESCALE_MX51_EVK_H__
+/* AMBA timer register base address */
+#define SYSTIMER_BASE 0x10011000
-#ifndef __ASSEMBLY__
-struct io_board_ctrl {
- u16 led_ctrl; /* 0x00 */
- u16 resv1[0x03];
- u16 sb_stat; /* 0x08 */
- u16 resv2[0x03];
- u16 int_stat; /* 0x10 */
- u16 resv3[0x07];
- u16 int_rest; /* 0x20 */
- u16 resv4[0x0B];
- u16 int_mask; /* 0x38 */
- u16 resv5[0x03];
- u16 id1; /* 0x40 */
- u16 resv6[0x03];
- u16 id2; /* 0x48 */
- u16 resv7[0x03];
- u16 version; /* 0x50 */
- u16 resv8[0x03];
- u16 id3; /* 0x58 */
- u16 resv9[0x03];
- u16 sw_reset; /* 0x60 */
-};
-#endif
+#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */
+#define SYSTIMER_RELOAD 0xFFFFFFFF
+#define SYSTIMER_EN (1 << 7)
+#define SYSTIMER_32BIT (1 << 1)
-#endif
+struct systimer {
+ u32 timer0load; /* 0x00 */
+ u32 timer0value;
+ u32 timer0control;
+ u32 timer0intclr;
+ u32 timer0ris;
+ u32 timer0mis;
+ u32 timer0bgload;
+ u32 timer1load; /* 0x20 */
+ u32 timer1value;
+ u32 timer1control;
+ u32 timer1intclr;
+ u32 timer1ris;
+ u32 timer1mis;
+ u32 timer1bgload;
+};
+#endif /* _SYSTIMER_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* Watchdog timer (SP805) register base address */
+#define WDT_BASE 0x100E5000
+
+#define WDT_EN 0x2
+#define WDT_RESET_LOAD 0x0
+
+struct wdt {
+ u32 wdogload; /* 0x000 */
+ u32 wdogvalue;
+ u32 wdogcontrol;
+ u32 wdogintclr;
+ u32 wdogris;
+ u32 wdogmis;
+ u32 res1[0x2F9];
+ u32 wdoglock; /* 0xC00 */
+ u32 res2[0xBE];
+ u32 wdogitcr; /* 0xF00 */
+ u32 wdogitop;
+ u32 res3[0x35];
+ u32 wdogperiphid0; /* 0xFE0 */
+ u32 wdogperiphid1;
+ u32 wdogperiphid2;
+ u32 wdogperiphid3;
+ u32 wdogpcellid0;
+ u32 wdogpcellid1;
+ u32 wdogpcellid2;
+ u32 wdogpcellid3;
+};
+
+#endif /* _WDT_H_ */
u32 reserved2[3];
u32 hsh;
u32 hsl;
- u32 sh1l;
+ u32 sa1l;
u32 sa1h;
u32 sa2l;
u32 sa2h;
#define AT91_PMC_MCKR_PRES_64 0x00000018
#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
+#ifdef CONFIG_AT91RM9200
+#define AT91_PMC_MCKR_MDIV_1 0x00000000
+#define AT91_PMC_MCKR_MDIV_2 0x00000100
+#define AT91_PMC_MCKR_MDIV_3 0x00000200
+#define AT91_PMC_MCKR_MDIV_4 0x00000300
+#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
+#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
#define AT91_PMC_MCKR_MDIV_4 0x00000200
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
+#endif
#define AT91_PMC_MCKR_PLLADIV_1 0x00001000
#define AT91_PMC_MCKR_PLLADIV_2 0x00002000
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Shutdown Controller
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_SHDWN_H
+#define AT91_SHDWN_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_shdwn {
+ u32 cr; /* Control Rer. WO */
+ u32 mr; /* Mode Register RW 0x00000003 */
+ u32 sr; /* Status Register RO 0x00000000 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SHDW_CR_KEY 0xa5000000
+#define AT91_SHDW_CR_SHDW 0x00000001
+
+#define AT91_SHDW_MR_RTTWKEN 0x00010000
+#define AT91_SHDW_MR_CPTWK0 0x000000f0
+#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
+#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
+
+#define AT91_SHDW_SR_RTTWK 0x00010000
+#define AT91_SHDW_SR_WAKEUP0 0x00000001
+
+#endif
#define AT91_PIO_BASE 0xfffff400
#define AT91_PMC_BASE 0xfffffc00
#define AT91_RSTC_BASE 0xfffffd00
+#define AT91_SHDWN_BASE 0xfffffd10
#define AT91_RTT_BASE 0xfffffd20
#define AT91_PIT_BASE 0xfffffd30
#define AT91_WDT_BASE 0xfffffd40
#if defined(CONFIG_AT91RM9200)
#include <asm/arch-at91/at91rm9200.h>
+#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
+#define AT91_BASE_SPI1 AT91SAM9260_BASE_SPI1
#define AT91_ID_UHP AT91SAM9260_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
#define USART2_BASE AT91_USART2
#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
#define SPI0_BASE AT91_BASE_SPI
+#define SPI1_BASE AT91_BASE_SPI1
#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */
.n_pins = ARRAY_SIZE(item) \
}
+#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13
+#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0
+
+struct lpsc_resource {
+ const int lpsc_no;
+};
+
int dvevm_read_mac_address(uint8_t *buf);
-void dv_configure_mac_address(uint8_t *rom_enetaddr);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
int n_items);
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+void davinci_emac_mii_mode_sel(int mode_sel);
+#endif
+#if defined(CONFIG_SOC_DA8XX)
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items);
+#endif
#endif /* __MISC_H */
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
-void davinci_eth_set_mac_addr(const u_int8_t *addr);
typedef struct
{
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
#define DAVINCI_USB_OTG_BASE 0x01e00000
-#define DAVINCI_SPI1_BASE 0x01e12000
+#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
+ 0x01e12000 : 0x01f0e000)
#define DAVINCI_GPIO_BASE 0x01e26000
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
+#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
+#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
+#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
+#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
+#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
+#define ASYNC3 get_async3_src()
+#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
/* Boot config */
struct davinci_syscfg_regs {
dv_reg revid;
- dv_reg rsvd[71];
+ dv_reg rsvd[13];
+ dv_reg kick0;
+ dv_reg kick1;
+ dv_reg rsvd1[56];
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+static inline int cpu_is_da830(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7df) ? 1 : 0);
+}
+static inline int cpu_is_da850(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7d1) ? 1 : 0);
+}
+
+static inline int get_async3_src(void)
+{
+ return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
+ PLL1_SYSCLK2 : 2;
+}
+
#endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */
#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
+#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
#define SYSRST_CNT_1SEC_VAL (25*1000000)
#ifndef __ASSEMBLY__
#ifdef CONFIG_FEC_MXC
extern void mx25_fec_init_pins(void);
+extern void imx_get_mac_from_fuse(unsigned char *mac);
#endif
/* Clock Control Module (CCM) registers */
/* Watchdog Timer (WDOG) registers */
struct wdog_regs {
- u32 wcr; /* Control */
- u32 wsr; /* Service */
- u32 wrsr; /* Reset Status */
- u32 wicr; /* Interrupt Control */
- u32 wmcr; /* Misc Control */
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Misc Control */
};
/* IIM control registers */
u32 iim_srev;
u32 iim_prog_p;
u32 res1[0x1f5];
- u32 iim_bank_area0[0x20];
- u32 res2[0xe0];
- u32 iim_bank_area1[0x20];
- u32 res3[0xe0];
- u32 iim_bank_area2[0x20];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
};
+
+struct fuse_bank0_regs {
+ u32 fuse0_25[0x1a];
+ u32 mac_addr[6];
+};
+
#endif
/* AIPS 1 */
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
-#define WCR_WDE 0x04
-
-/* FUSE bank offsets */
-#define IIM0_MAC 0x1a
+#define WCR_WDE 0x04
+#define WSR_UNLOCK1 0x5555
+#define WSR_UNLOCK2 0xAAAA
#endif /* _IMX_REGS_H */
#ifdef CONFIG_FEC_MXC
extern void mx27_fec_init_pins(void);
+extern void imx_get_mac_from_fuse(unsigned char *mac);
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
- u32 res[0x1F0];
- u32 iim_bank_area0[0x100];
+ u32 res[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[1];
};
+
+struct fuse_bank0_regs {
+ u32 fuse0_3[5];
+ u32 mac_addr[6];
+ u32 fuse10_31[0x16];
+};
+
#endif
#define IMX_IO_BASE 0x10000000
#define IIM_ERR_SNSE (1 << 2)
#define IIM_ERR_PARITYE (1 << 1)
-/* Definitions for i.MX27 TO2 */
-#define IIM0_MAC 5
-#define IIM0_SCC_KEY 11
-#define IIM1_SUID 1
-
#endif /* _IMX_REGS_H */
u32 pdr2;
};
+/* GPIO Registers */
+struct gpio_regs {
+ u32 gpio_dr;
+ u32 gpio_dir;
+ u32 gpio_psr;
+};
+
+#define IOMUX_PADNUM_MASK 0x1ff
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+ PAD_CTL_NOLOOPBACK = 0x0 << 9,
+ PAD_CTL_LOOPBACK = 0x1 << 9,
+ PAD_CTL_PKE_NONE = 0x0 << 8,
+ PAD_CTL_PKE_ENABLE = 0x1 << 8,
+ PAD_CTL_PUE_KEEPER = 0x0 << 7,
+ PAD_CTL_PUE_PUD = 0x1 << 7,
+ PAD_CTL_100K_PD = 0x0 << 5,
+ PAD_CTL_100K_PU = 0x1 << 5,
+ PAD_CTL_47K_PU = 0x2 << 5,
+ PAD_CTL_22K_PU = 0x3 << 5,
+ PAD_CTL_HYS_CMOS = 0x0 << 4,
+ PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
+ PAD_CTL_ODE_CMOS = 0x0 << 3,
+ PAD_CTL_ODE_OpenDrain = 0x1 << 3,
+ PAD_CTL_DRV_NORMAL = 0x0 << 1,
+ PAD_CTL_DRV_HIGH = 0x1 << 1,
+ PAD_CTL_DRV_MAX = 0x2 << 1,
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
+ PAD_CTL_SRE_FAST = 0x1 << 0
+};
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+ MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
+ MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
+ MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
+ MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
+ MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
+ MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
+ MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
+ MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
+ MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
+ MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
+ MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
+ MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
+ MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
+ MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
+ MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
+ MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
+ MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
+ MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
+ MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
+ MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
+ MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
+ MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
+ MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
+ MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
+ MX31_PIN_READ = IOMUX_PIN(0xff, 24),
+ MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
+ MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
+ MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
+ MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
+ MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
+ MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
+ MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
+ MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
+ MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
+ MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
+ MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
+ MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
+ MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
+ MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
+ MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
+ MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
+ MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
+ MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
+ MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
+ MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
+ MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
+ MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
+ MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
+ MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
+ MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
+ MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
+ MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
+ MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
+ MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
+ MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
+ MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
+ MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
+ MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
+ MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
+ MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
+ MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
+ MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
+ MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
+ MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
+ MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
+ MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
+ MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
+ MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
+ MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
+ MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
+ MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
+ MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
+ MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
+ MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
+ MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
+ MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
+ MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
+ MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
+ MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
+ MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
+ MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
+ MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
+ MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
+ MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
+ MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
+ MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
+ MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
+ MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
+ MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
+ MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
+ MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
+ MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
+ MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
+ MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
+ MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
+ MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
+ MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
+ MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
+ MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
+ MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
+ MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
+ MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
+ MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
+ MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
+ MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
+ MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
+ MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
+ MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
+ MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
+ MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
+ MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
+ MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
+ MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
+ MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
+ MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
+ MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
+ MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
+ MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
+ MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
+ MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
+ MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
+ MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
+ MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
+ MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
+ MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
+ MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
+ MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
+ MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
+ MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
+ MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
+ MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
+ MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
+ MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
+ MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
+ MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
+ MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
+ MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
+ MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
+ MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
+ MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
+ MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
+ MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
+ MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
+ MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
+ MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
+ MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
+ MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
+ MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
+ MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
+ MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
+ MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
+ MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
+ MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
+ MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
+ MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
+ MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
+ MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
+ MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
+ MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
+ MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
+ MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
+ MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
+ MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
+ MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
+ MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
+ MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
+ MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
+ MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
+ MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
+ MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
+ MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
+ MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
+ MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
+ MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
+ MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
+ MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
+ MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
+ MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
+ MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
+ MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
+ MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
+ MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
+ MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
+ MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
+ MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
+ MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
+ MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
+ MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
+ MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
+ MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
+ MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
+ MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
+ MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
+ MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
+ MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
+ MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
+ MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
+ MX31_PIN_NFRB = IOMUX_PIN(16, 197),
+ MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
+ MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
+ MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
+ MX31_PIN_NFALE = IOMUX_PIN(12, 201),
+ MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
+ MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
+ MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
+ MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
+ MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
+ MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
+ MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
+ MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
+ MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
+ MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
+ MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
+ MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
+ MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
+ MX31_PIN_RW = IOMUX_PIN(0xff, 215),
+ MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
+ MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
+ MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
+ MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
+ MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
+ MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
+ MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
+ MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
+ MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
+ MX31_PIN_OE = IOMUX_PIN(0xff, 225),
+ MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
+ MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
+ MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
+ MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
+ MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
+ MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
+ MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
+ MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
+ MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
+ MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
+ MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
+ MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
+ MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
+ MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
+ MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
+ MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
+ MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
+ MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
+ MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
+ MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
+ MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
+ MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
+ MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
+ MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
+ MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
+ MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
+ MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
+ MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
+ MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
+ MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
+ MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
+ MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
+ MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
+ MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
+ MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
+ MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
+ MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
+ MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
+ MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
+ MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
+ MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
+ MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
+ MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
+ MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
+ MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
+ MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
+ MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
+ MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
+ MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
+ MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
+ MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
+ MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
+ MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
+ MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
+ MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
+ MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
+ MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
+ MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
+ MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
+ MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
+ MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
+ MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
+ MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
+ MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
+ MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
+ MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
+ MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
+ MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
+ MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
+ MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
+ MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
+ MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
+ MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
+ MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
+ MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
+ MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
+ MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
+ MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
+ MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
+ MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
+ MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
+ MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
+ MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
+ MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
+ MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
+ MX31_PIN_STX0 = IOMUX_PIN(33, 311),
+ MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
+ MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
+ MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
+ MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
+ MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
+ MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317),
+ MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318),
+ MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319),
+ MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320),
+ MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321),
+ MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322),
+ MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
+ MX31_PIN_PWMO = IOMUX_PIN(9, 324),
+ MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
+ MX31_PIN_COMPARE = IOMUX_PIN(8, 326),
+ MX31_PIN_CAPTURE = IOMUX_PIN(7, 327),
+};
+
/* Bit definitions for RCSR register in CCM */
#define CCM_RCSR_NF16B (1 << 31)
#define CCM_RCSR_NFMS (1 << 30)
/*
* GPIO
*/
-#define GPIO1_BASE 0x53FCC000
-#define GPIO2_BASE 0x53FD0000
-#define GPIO3_BASE 0x53FA4000
+#define GPIO1_BASE_ADDR 0x53FCC000
+#define GPIO2_BASE_ADDR 0x53FD0000
+#define GPIO3_BASE_ADDR 0x53FA4000
#define GPIO_DR 0x00000000 /* data register */
#define GPIO_GDIR 0x00000004 /* direction register */
#define GPIO_PSR 0x00000008 /* pad status register */
/* Register offsets based on IOMUXC_BASE */
/* 0x00 .. 0x7b */
+#define MUX_CTL_USBH2_DATA1 0x40
+#define MUX_CTL_USBH2_DIR 0x44
+#define MUX_CTL_USBH2_STP 0x45
+#define MUX_CTL_USBH2_NXT 0x46
+#define MUX_CTL_USBH2_DATA0 0x47
+#define MUX_CTL_USBH2_CLK 0x4B
#define MUX_CTL_RTS1 0x7c
#define MUX_CTL_CTS1 0x7d
#define MUX_CTL_DTR_DCE1 0x7e
#define MUX_CTL_CSPI1_MISO 0x8d
#define MUX_CTL_CSPI1_SS0 0x8e
#define MUX_CTL_CSPI1_SS1 0x8f
+#define MUX_CTL_STXD6 0x90
+#define MUX_CTL_SRXD6 0x91
+#define MUX_CTL_SCK6 0x92
+#define MUX_CTL_SFS6 0x93
+
+#define MUX_CTL_STXD3 0x9C
+#define MUX_CTL_SRXD3 0x9D
+#define MUX_CTL_SCK3 0x9E
+#define MUX_CTL_SFS3 0x9F
#define MUX_CTL_NFC_WP 0xD0
#define MUX_CTL_NFC_CE 0xD1
#define MUX_CTL_NFC_CLE 0xD7
+#define MUX_CTL_CAPTURE 0x150
+#define MUX_CTL_COMPARE 0x151
+
/*
* Helper macros for the MUX_[contact name]__[pin function] macros
*/
#define IRAM_BASE_ADDR 0x1FFFC000
#define IRAM_SIZE (16 * 1024)
+#define MX31_AIPS1_BASE_ADDR 0x43f00000
+#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+
+/* USB portsc */
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
+#define MXC_EHCI_FORCE_FS (1 << 24)
+#define MXC_EHCI_UTMI_8BIT (0 << 28)
+#define MXC_EHCI_UTMI_16BIT (1 << 28)
+#define MXC_EHCI_SERIAL (1 << 29)
+#define MXC_EHCI_MODE_UTMI (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS (1 << 30)
+#define MXC_EHCI_MODE_ULPI (2 << 30)
+#define MXC_EHCI_MODE_SERIAL (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
+#define MXC_EHCI_TTL_ENABLED (1 << 6)
+
+#define MXC_EHCI_INTERNAL_PHY (1 << 7)
+#define MXC_EHCI_IPPUE_DOWN (1 << 8)
+#define MXC_EHCI_IPPUE_UP (1 << 9)
+
#endif /* __ASM_ARCH_MX31_REGS_H */
extern u32 mx31_get_ipg_clk(void);
#define imx_get_uartclk mx31_get_ipg_clk
extern void mx31_gpio_mux(unsigned long mode);
-
-enum mx31_gpio_direction {
- MX31_GPIO_DIRECTION_IN,
- MX31_GPIO_DIRECTION_OUT,
-};
-
-#ifdef CONFIG_MX31_GPIO
-extern int mx31_gpio_direction(unsigned int gpio,
- enum mx31_gpio_direction direction);
-extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
-extern int mx31_gpio_get(unsigned int gpio);
-#else
-static inline int mx31_gpio_direction(unsigned int gpio,
- enum mx31_gpio_direction direction)
-{
- return 1;
-}
-static inline int mx31_gpio_get(unsigned int gpio)
-{
- return 1;
-}
-static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
-{
-}
-#endif
+extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+
+/* Define the bits in register CCGRx */
+#define MXC_CCM_CCGR_CG_MASK 0x3
+
+#define MXC_CCM_CCGR5_CG5_OFFSET 10
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
#ifndef __ASM_ARCH_MXC_MX51_H__
#define __ASM_ARCH_MXC_MX51_H__
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
/*
* IRAM
*/
-#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
+#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
+#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* Graphics Memory of GPU
*/
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
-#ifndef __ASSEMBLY__
+#define IMX_IIM_BASE (IIM_BASE_ADDR)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(unsigned char *mac);
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
struct clkctl {
u32 ccr;
u32 cswcr2;
};
+/* GPIO Registers */
+struct gpio_regs {
+ u32 gpio_dr;
+ u32 gpio_dir;
+ u32 gpio_psr;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr;
+ u32 srsr;
+ u32 reserved1[2];
+ u32 sisr;
+ u32 simr;
+};
+
+struct iim_regs {
+ u32 stat;
+ u32 statm;
+ u32 err;
+ u32 emask;
+ u32 fctl;
+ u32 ua;
+ u32 la;
+ u32 sdat;
+ u32 prev;
+ u32 srev;
+ u32 preg_p;
+ u32 scs0;
+ u32 scs1;
+ u32 scs2;
+ u32 scs3;
+ u32 res0[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[4];
+};
+
+struct fuse_bank1_regs {
+ u32 fuse0_8[9];
+ u32 mac_addr[6];
+ u32 fuse15_31[0x11];
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MXC_MX51_H__ */
* MA 02111-1307 USA
*/
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
+#ifndef __MACH_MX5_IOMUX_H__
+#define __MACH_MX5_IOMUX_H__
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
typedef unsigned int iomux_pin_name_t;
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif /* __MACH_MX51_IOMUX_H__ */
+#endif /* __MACH_MX5_IOMUX_H__ */
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
+#define __ASM_ARCH_MX5_MX5X_PINS_H__
#ifndef __ASSEMBLY__
MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+
+ /* The following are PADS used for drive strength */
+
+ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
+ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
+ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
+ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
+ MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
+ MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
+ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
+ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
+ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
+ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
+ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
+ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
+ MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
+ MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
+ MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
+ MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
+ MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
+ MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
+ MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
+ MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
+ MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
+ MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
+ MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
+ MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
+ MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
+ MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
+ MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
+ MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
+ MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
+ MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
+ MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
+ MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
+ MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
+ MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
+ MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
+ MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
+ MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
+ MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
+ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
+ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
+ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
};
#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
+#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
u32 get_cpu_rev(void);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+void sdelay(unsigned long);
#endif
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
#ifndef _OMAP2420_SYS_H_
#define _OMAP2420_SYS_H_
-#include <asm/arch/sizes.h>
+#include <asm/sizes.h>
/*
* 2420 specific Section
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
(MICRON_TWTR_165 << 16))
+/*
+ * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 22.5/6 = 3.75 -> 4
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 140/6 = 23.3 -> 24
+ * ACTIMB
+ * TWTR = 2
+ * TCKE = 2
+ * TXSR = 200/6 = 33.3 -> 34
+ * TXP = 1.0 + 1.1 = 2.1 -> 3
+ */
+#define NUMONYX_TDAL_165 6
+#define NUMONYX_TDPL_165 3
+#define NUMONYX_TRRD_165 2
+#define NUMONYX_TRCD_165 4
+#define NUMONYX_TRP_165 3
+#define NUMONYX_TRAS_165 7
+#define NUMONYX_TRC_165 10
+#define NUMONYX_TRFC_165 24
+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
+ (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
+ (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
+ (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
+ (NUMONYX_TDAL_165))
+
+#define NUMONYX_TWTR_165 2
+#define NUMONYX_TCKE_165 2
+#define NUMONYX_TXP_165 3
+#define NUMONYX_XSR_165 34
+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
+ (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
+ (NUMONYX_TWTR_165 << 16))
+
#ifdef CONFIG_OMAP3_INFINEON_DDR
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#endif
+#ifdef CONFIG_OMAP3_NUMONYX_DDR
+#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define DATI_CMDDIS (0x1 << 1)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
unsigned int size;
unsigned int RCA;
} mmc_card_data;
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+int omap_mmc_init(int dev_index);
+
#endif /* MMC_HOST_DEF_H */
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define DATI_CMDDIS (0x1 << 1)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
unsigned int size;
unsigned int RCA;
} mmc_card_data;
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+int omap_mmc_init(int dev_index);
+
#endif /* MMC_HOST_DEF_H */
u32 orion5x_device_id(void);
u32 orion5x_device_rev(void);
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+void timer_init_r(void);
#endif /* __ASSEMBLY__ */
#endif /* _ORION5X_CPU_H */
#include <linux/config.h>
#include <asm/mach-types.h>
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA300) || \
+ defined(CONFIG_CPU_PXA310) || \
+ defined(CONFIG_CPU_PXA320)
+#define CONFIG_CPU_MONAHANS
+#endif
+#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-
-#ifndef UBOOT_REG_FIX
-#ifndef __ASSEMBLY__
-
-#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
-
-/*
- * This __REG() version gives the same results as the one above, except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers. It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x) __REGP(io_p2v(x))
-#endif
-
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y) \
- ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
- : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
-
-# define __PREG(x) (io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __PREG(x) io_v2p(x)
-
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-# define io_p2v(PhAdd) (PhAdd)
-# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
-# define __REG_2(x) (x)
-# define __REG_3(x) (x)
-# endif
-# endif
-#endif /* UBOOT_REG_FIX */
-
#include "pxa-regs.h"
#ifndef __ASSEMBLY__
+++ /dev/null
-/*
- * arch/arm/include/asm/arch-pxa/macro.h
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_PXA_MACRO_H__
-#define __ASM_ARCH_PXA_MACRO_H__
-#ifdef __ASSEMBLY__
-
-#include <asm/macro.h>
-#include <asm/arch/pxa-regs.h>
-
-/*
- * This macro performs a 32bit write to a memory location and makes sure the
- * write operation really happened by performing a read back.
- *
- * Clobbered regs: r4, r5
- */
-.macro write32rb addr, data
- ldr r4, =\addr
- ldr r5, =\data
- str r5, [r4]
- ldr r5, [r4]
-.endm
-
-/*
- * This macro waits according to OSCR incrementation
- *
- * Clobbered regs: r4, r5, r6
- */
-.macro pxa_wait_ticks ticks
- ldr r4, =OSCR
- mov r5, #0
- str r5, [r4]
- ldr r5, =\ticks
-1:
- ldr r6, [r4]
- cmp r5, r6
- bgt 1b
-.endm
-
-/*
- * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_gpio_setup
- write32 GPSR0, CONFIG_SYS_GPSR0_VAL
- write32 GPSR1, CONFIG_SYS_GPSR1_VAL
- write32 GPSR2, CONFIG_SYS_GPSR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPSR3, CONFIG_SYS_GPSR3_VAL
-#endif
-
- write32 GPCR0, CONFIG_SYS_GPCR0_VAL
- write32 GPCR1, CONFIG_SYS_GPCR1_VAL
- write32 GPCR2, CONFIG_SYS_GPCR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPCR3, CONFIG_SYS_GPCR3_VAL
-#endif
-
- write32 GPDR0, CONFIG_SYS_GPDR0_VAL
- write32 GPDR1, CONFIG_SYS_GPDR1_VAL
- write32 GPDR2, CONFIG_SYS_GPDR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GPDR3, CONFIG_SYS_GPDR3_VAL
-#endif
-
- write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
- write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
- write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
- write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
- write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
- write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
- write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
-#endif
-
- write32 PSSR, CONFIG_SYS_PSSR_VAL
-.endm
-
-/*
- * This macro sets up the Memory controller of the PXA2xx CPU
- *
- * Clobbered regs: r3, r4, r5
- */
-.macro pxa_mem_setup
- /* This comes handy when setting MDREFR */
- ldr r3, =MEMC_BASE
-
- /*
- * 1) Initialize Asynchronous static memory controller
- */
-
- /* MSC0: nCS(0,1) */
- write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
- /* MSC1: nCS(2,3) */
- write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
- /* MSC2: nCS(4,5) */
- write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
-
- /*
- * 2) Initialize Card Interface
- */
-
- /* MECR: Memory Expansion Card Register */
- write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
- /* MCMEM0: Card Interface slot 0 timing */
- write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
- /* MCMEM1: Card Interface slot 1 timing */
- write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
-
- /*
- * 3) Configure Fly-By DMA register
- */
-
- write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
-
- /*
- * 4) Initialize Timing for Sync Memory (SDCLK0)
- */
-
- /*
- * Before accessing MDREFR we need a valid DRI field, so we set
- * this to power on defaults + DRI field.
- */
- ldr r5, [r3, #MDREFR_OFFSET]
- bic r5, r5, #0x0ff
- bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- mov r6, r4
- lsl r4, #20
- lsr r4, #20 /* Get a valid DRI field */
-
- orr r5, r5, r4 /* MDREFR user config with correct DRI */
-
- orr r5, #MDREFR_K0RUN
- orr r5, #MDREFR_SLFRSH
- bic r5, #MDREFR_APD
- bic r5, #MDREFR_E1PIN
-
- str r5, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- /*
- * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
- */
-
- /* Initialize SXCNFG register. Assert the enable bits.
- *
- * Write SXMRS to cause an MRS command to all enabled banks of
- * synchronous static memory. Note that SXLCR need not be written
- * at this time.
- */
- write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
-
- /*
- * 6) Initialize SDRAM
- */
-
- bic r6, #MDREFR_SLFRSH
- str r6, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- orr r6, #MDREFR_E1PIN
- str r6, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-
- /*
- * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
- * but not enable each SDRAM partition pair.
- */
-
- /* Fetch platform value of MDCNFG */
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- /* Disable all sdram banks */
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
- /* Write initial value of MDCNFG, w/o enabling sdram banks */
- str r4, [r3, #MDCNFG_OFFSET]
- ldr r4, [r3, #MDCNFG_OFFSET]
-
- /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
- pxa_wait_ticks 0x300
-
- /*
- * 8) Trigger a number (usually 8) refresh cycles by attempting
- * non-burst read or write accesses to disabled SDRAM, as commonly
- * specified in the power up sequence documented in SDRAM data
- * sheets. The address(es) used for this purpose must not be
- * cacheable.
- */
-
- ldr r4, =CONFIG_SYS_DRAM_BASE
-.rept 9
- str r5, [r4]
-.endr
-
- /*
- * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
- */
-
- ldr r5, =CONFIG_SYS_MDCNFG_VAL
- ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
- and r5, r5, r4
- ldr r4, [r3, #MDCNFG_OFFSET]
- orr r4, r4, r5
- str r4, [r3, #MDCNFG_OFFSET]
- ldr r4, [r3, #MDCNFG_OFFSET]
-
- /*
- * 10) Write MDMRS.
- */
-
- ldr r4, =CONFIG_SYS_MDMRS_VAL
- str r4, [r3, #MDMRS_OFFSET]
- ldr r4, [r3, #MDMRS_OFFSET]
-
- /*
- * 11) Enable APD
- */
-
- ldr r4, [r3, #MDREFR_OFFSET]
- and r6, r6, #MDREFR_APD
- orr r4, r4, r6
- str r4, [r3, #MDREFR_OFFSET]
- ldr r4, [r3, #MDREFR_OFFSET]
-.endm
-
-/*
- * This macro tests if the CPU woke up from sleep and eventually resumes
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_wakeup
- ldr r4, =RCSR
- ldr r5, [r4]
- and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r5, [r4]
- teq r5, #RCSR_SMR
-
- bne pxa_wakeup_exit
-
- ldr r4, =PSSR
- mov r5, #PSSR_PH
- str r5, [r4]
-
- ldr r4, =PSPR
- ldr pc, [r4]
-pxa_wakeup_exit:
-.endm
-
-/*
- * This macro disables all interupts on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_intr_setup
- write32 ICLR, 0
- write32 ICMR, 0
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- write32 ICLR2, 0
- write32 ICMR2, 0
-#endif
-.endm
-
-/*
- * This macro configures clock on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro pxa_clock_setup
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- write32 CKEN, CONFIG_SYS_CKEN
-
- /* Write CCCR */
- write32 CCCR, CONFIG_SYS_CCCR
-
-#ifdef CONFIG_RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- write32 OSCC, #OSCC_OON
- ldr r4, =OSCC
-
- /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
-2:
- ldr r5, [r4]
- ands r5, r5, #1
- beq 2b
-#endif
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_PXA_MACRO_H__ */
/*
* DMA Controller
*/
-#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
-#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
-#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
-#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
-#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
-#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
-#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
-#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
-#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
-#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
-#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
-#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
-#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
-#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
-#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
-#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
-#ifdef CONFIG_CPU_MONAHANS
-#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */
-#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */
-#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */
-#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */
-#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */
-#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */
-#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */
-#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */
-#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */
-#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */
-#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */
-#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */
-#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */
-#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */
-#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */
-#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_CPU_MONAHANS */
-
-#define DCSR(x) __REG2(0x40000000, (x) << 2)
+#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
+#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
+#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
+#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
+#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
+#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
+#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
+#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
+#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
+#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
+#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */
+#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */
+#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */
+#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
+#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
+#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
+#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
+#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
+#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */
+#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */
+#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */
+#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */
+#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */
+#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */
+#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */
+#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */
+#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */
+#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */
+#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
+#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
+#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define DCSR(x) (0x40000000 | ((x) << 2))
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
-#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
-
-#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15 __REG(0x4000013c) /* Reserved */
-#define DRCMR16 __REG(0x40000140) /* Reserved */
-#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23 __REG(0x4000015c) /* Reserved */
-#define DRCMR24 __REG(0x40000160) /* Reserved */
-#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29 __REG(0x40000174) /* Reserved */
-#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34 __REG(0x40000188) /* Reserved */
-#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39 __REG(0x4000019C) /* Reserved */
-
-#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
+#define DINT 0x400000f0 /* DMA Interrupt Register */
+
+#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15 0x4000013c /* Reserved */
+#define DRCMR16 0x40000140 /* Reserved */
+#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23 0x4000015c /* Reserved */
+#define DRCMR24 0x40000160 /* Reserved */
+#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29 0x40000174 /* Reserved */
+#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34 0x40000188 /* Reserved */
+#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39 0x4000019C /* Reserved */
+
+#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */
#define DRCMRRXSADR DRCMR2
#define DRCMRTXSADR DRCMR3
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
-#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
-#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
-#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
-#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
-#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
-#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
-#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
-#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
-#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
-#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
-#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
-#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
-#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
-#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
-#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
-#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
-#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
-#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
-#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
-#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
-#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
-#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
-#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
-#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
-#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
-#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
-#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
-#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
-#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
-#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
-#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
-#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
-#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
-#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
-#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
-#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
-#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
-#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
-#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
-#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
-#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
-#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
-#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
-#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
-#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
-#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
-#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
-#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
-
-#define DDADR(x) __REG2(0x40000200, (x) << 4)
-#define DSADR(x) __REG2(0x40000204, (x) << 4)
-#define DTADR(x) __REG2(0x40000208, (x) << 4)
-#define DCMD(x) __REG2(0x4000020c, (x) << 4)
+#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
+#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */
+#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */
+#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
+#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */
+#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */
+#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
+#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */
+#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */
+#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */
+#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */
+#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */
+#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */
+#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */
+#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */
+#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */
+#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */
+#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */
+#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */
+#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */
+#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */
+#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */
+#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */
+#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */
+#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */
+#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */
+#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */
+#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */
+#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */
+#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */
+#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */
+#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */
+#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */
+#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */
+#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */
+#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */
+#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */
+#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */
+#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */
+#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */
+#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */
+#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */
+#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */
+#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */
+#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */
+#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */
+#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */
+#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x) (0x40000200 | ((x) << 4))
+#define DSADR(x) (0x40000204 | ((x) << 4))
+#define DTADR(x) (0x40000208 | ((x) << 4))
+#define DCMD(x) (0x4000020c | ((x) << 4))
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
#define DDADR_STOP (1 << 0) /* Stop (read / write) */
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+/******************************************************************************/
/*
* UARTs
*/
/* Full Function UART (FFUART) */
#define FFUART FFRBR
-#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
-#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
-#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
-#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
-#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
-#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
-#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
-#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
-#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
-#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
-#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
-#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
+#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
+#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
+#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
+#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
+#define FFLCR 0x4010000C /* Line Control Register (read/write) */
+#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
+#define FFLSR 0x40100014 /* Line Status Register (read only) */
+#define FFMSR 0x40100018 /* Modem Status Register (read only) */
+#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
+#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
+#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Bluetooth UART (BTUART) */
#define BTUART BTRBR
-#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
-#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
-#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
-#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
-#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
-#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
-#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
-#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
-#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
-#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
-#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
-#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
+#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
+#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
+#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
+#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
+#define BTLCR 0x4020000C /* Line Control Register (read/write) */
+#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
+#define BTLSR 0x40200014 /* Line Status Register (read only) */
+#define BTMSR 0x40200018 /* Modem Status Register (read only) */
+#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
+#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
+#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Standard UART (STUART) */
#define STUART STRBR
-#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
-#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
-#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
-#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
-#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
-#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
-#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
-#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
-#define STMSR __REG(0x40700018) /* Reserved */
-#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
-#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
-#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
+#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
+#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
+#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
+#define STFCR 0x40700008 /* FIFO Control Register (write only) */
+#define STLCR 0x4070000C /* Line Control Register (read/write) */
+#define STMCR 0x40700010 /* Modem Control Register (read/write) */
+#define STLSR 0x40700014 /* Line Status Register (read only) */
+#define STMSR 0x40700018 /* Reserved */
+#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
+#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
+#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
-#define MCR_LOOP (1 << 4) */
+#define MCR_LOOP (1 << 4) /* */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
+/******************************************************************************/
/*
* IrSR (Infrared Selection Register)
*/
/*
* I2C registers
*/
-#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
-#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
-#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
-#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
-#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
-
-#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
-#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
-#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */
+#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */
+#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */
+#define ICR 0x40301690 /* I2C Control Register - ICR */
+#define ISR 0x40301698 /* I2C Status Register - ISR */
+#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */
+
+#ifdef CONFIG_CPU_MONAHANS
+#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */
+#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */
+#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */
+#else
+#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */
+#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */
+#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */
+#endif
/* ----- Control register bits ---------------------------------------- */
/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
* short defines because there is too much chance of namespace collision
*/
-/*#define SACR0 __REG(0x40400000) / Global Control Register */
-/*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
-/*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-/*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */
-/*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */
-/*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */
-/*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */
-
+#define SACR0 0x40400000 /* Global Control Register */
+#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */
+#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */
+#define SADIV 0x40400060 /* Audio Clock Divider Register. */
+#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */
/*
* AC97 Controller registers
*/
-#define POCR __REG(0x40500000) /* PCM Out Control Register */
+#define POCR 0x40500000 /* PCM Out Control Register */
#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define PICR __REG(0x40500004) /* PCM In Control Register */
+#define PICR 0x40500004 /* PCM In Control Register */
#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define MCCR __REG(0x40500008) /* Mic In Control Register */
+#define MCCR 0x40500008 /* Mic In Control Register */
#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define GCR __REG(0x4050000C) /* Global Control Register */
+#define GCR 0x4050000C /* Global Control Register */
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
-#define POSR __REG(0x40500010) /* PCM Out Status Register */
+#define POSR 0x40500010 /* PCM Out Status Register */
#define POSR_FIFOE (1 << 4) /* FIFO error */
-#define PISR __REG(0x40500014) /* PCM In Status Register */
+#define PISR 0x40500014 /* PCM In Status Register */
#define PISR_FIFOE (1 << 4) /* FIFO error */
-#define MCSR __REG(0x40500018) /* Mic In Status Register */
+#define MCSR 0x40500018 /* Mic In Status Register */
#define MCSR_FIFOE (1 << 4) /* FIFO error */
-#define GSR __REG(0x4050001C) /* Global Status Register */
+#define GSR 0x4050001C /* Global Status Register */
#define GSR_CDONE (1 << 19) /* Command Done */
#define GSR_SDONE (1 << 18) /* Status Done */
#define GSR_RDCS (1 << 15) /* Read Completion Status */
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
-#define CAR __REG(0x40500020) /* CODEC Access Register */
+#define CAR 0x40500020 /* CODEC Access Register */
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
-#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
-#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
+#define PCDR 0x40500040 /* PCM FIFO Data Register */
+#define MCDR 0x40500060 /* Mic-in FIFO Data Register */
-#define MOCR __REG(0x40500100) /* Modem Out Control Register */
+#define MOCR 0x40500100 /* Modem Out Control Register */
#define MOCR_FEIE (1 << 3) /* FIFO Error */
-#define MICR __REG(0x40500108) /* Modem In Control Register */
+#define MICR 0x40500108 /* Modem In Control Register */
#define MICR_FEIE (1 << 3) /* FIFO Error */
-#define MOSR __REG(0x40500110) /* Modem Out Status Register */
+#define MOSR 0x40500110 /* Modem Out Status Register */
#define MOSR_FIFOE (1 << 4) /* FIFO error */
-#define MISR __REG(0x40500118) /* Modem In Status Register */
+#define MISR 0x40500118 /* Modem In Status Register */
#define MISR_FIFOE (1 << 4) /* FIFO error */
-#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
+#define MODR 0x40500140 /* Modem FIFO Data Register */
-#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
-#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
-#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
-#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
+#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */
+#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */
+#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */
+#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */
/*
* USB Device Controller
*/
-#ifdef CONFIG_PXA27X
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define UDCCR __REG(0x40600000) /* UDC Control Register */
+#define UDCCR 0x40600000 /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */
#define UDCCR_AAISN_S 5
-#define UDCCS0 __REG(0x40600100) /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1 __REG(0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2 __REG(0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
-#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
-#define UFNRL __REG(0x40600014) /* UDC Frame Number Register Low */
-#define UBCR2 __REG(0x40600208) /* UDC Byte Count Reg 2 */
-#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
-#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
-#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
-#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
-#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
-#define UDDR0 __REG(0x40600300) /* UDC Endpoint 0 Data Register */
-#define UDDR1 __REG(0x40600304) /* UDC Endpoint 1 Data Register */
-#define UDDR2 __REG(0x40600308) /* UDC Endpoint 2 Data Register */
-#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
-#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
-#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
-#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
-#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
-#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
-#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
-#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
-#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
-#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
-#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
-#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
-#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
-
-#define UICR0 __REG(0x40600004) /* UDC Interrupt Control Register 0 */
+#define UFNRH 0x40600060 /* UDC Frame Number Register High */
+#define UFNRL 0x40600014 /* UDC Frame Number Register Low */
+#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */
+#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */
+#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */
+#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */
+#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */
+#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */
+#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */
+#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */
+#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */
+#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */
+#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */
+#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */
+#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */
+#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */
+#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */
+#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */
+#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */
+#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */
+#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */
+#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */
+#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */
+#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */
+
+#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
-#define UICR1 __REG(0x40600008) /* UDC Interrupt Control Register 1 */
+#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
-#define USIR0 __REG(0x4060000C) /* UDC Status Interrupt Register 0 */
+#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
-#define USIR1 __REG(0x40600010) /* UDC Status Interrupt Register 1 */
+#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
-#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
-#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */
+#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
-#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */
+#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
-#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCFNR 0x40600014 /* UDC Frame Number Register */
+#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
-#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
-#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
-#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
+#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
+#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
+#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
+#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */
+#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */
+#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */
+#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */
+#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */
+#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */
+#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */
+#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */
+#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */
+#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */
+#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */
+#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */
+#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */
+#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */
+#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */
+#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */
+#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */
+#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */
+#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */
+#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
+#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
-#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
+#define UDCDR0 0x40600300 /* Data Register - EP0 */
+#define UDCDRA 0x40600304 /* Data Register - EPA */
+#define UDCDRB 0x40600308 /* Data Register - EPB */
+#define UDCDRC 0x4060030C /* Data Register - EPC */
+#define UDCDRD 0x40600310 /* Data Register - EPD */
+#define UDCDRE 0x40600314 /* Data Register - EPE */
+#define UDCDRF 0x40600318 /* Data Register - EPF */
+#define UDCDRG 0x4060031C /* Data Register - EPG */
+#define UDCDRH 0x40600320 /* Data Register - EPH */
+#define UDCDRI 0x40600324 /* Data Register - EPI */
+#define UDCDRJ 0x40600328 /* Data Register - EPJ */
+#define UDCDRK 0x4060032C /* Data Register - EPK */
+#define UDCDRL 0x40600330 /* Data Register - EPL */
+#define UDCDRM 0x40600334 /* Data Register - EPM */
+#define UDCDRN 0x40600338 /* Data Register - EPN */
+#define UDCDRP 0x4060033C /* Data Register - EPP */
+#define UDCDRQ 0x40600340 /* Data Register - EPQ */
+#define UDCDRR 0x40600344 /* Data Register - EPR */
+#define UDCDRS 0x40600348 /* Data Register - EPS */
+#define UDCDRT 0x4060034C /* Data Register - EPT */
+#define UDCDRU 0x40600350 /* Data Register - EPU */
+#define UDCDRV 0x40600354 /* Data Register - EPV */
+#define UDCDRW 0x40600358 /* Data Register - EPW */
+#define UDCDRX 0x4060035C /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
-#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
+#define UDCCRA 0x40600404 /* Configuration register EPA */
+#define UDCCRB 0x40600408 /* Configuration register EPB */
+#define UDCCRC 0x4060040C /* Configuration register EPC */
+#define UDCCRD 0x40600410 /* Configuration register EPD */
+#define UDCCRE 0x40600414 /* Configuration register EPE */
+#define UDCCRF 0x40600418 /* Configuration register EPF */
+#define UDCCRG 0x4060041C /* Configuration register EPG */
+#define UDCCRH 0x40600420 /* Configuration register EPH */
+#define UDCCRI 0x40600424 /* Configuration register EPI */
+#define UDCCRJ 0x40600428 /* Configuration register EPJ */
+#define UDCCRK 0x4060042C /* Configuration register EPK */
+#define UDCCRL 0x40600430 /* Configuration register EPL */
+#define UDCCRM 0x40600434 /* Configuration register EPM */
+#define UDCCRN 0x40600438 /* Configuration register EPN */
+#define UDCCRP 0x4060043C /* Configuration register EPP */
+#define UDCCRQ 0x40600440 /* Configuration register EPQ */
+#define UDCCRR 0x40600444 /* Configuration register EPR */
+#define UDCCRS 0x40600448 /* Configuration register EPS */
+#define UDCCRT 0x4060044C /* Configuration register EPT */
+#define UDCCRU 0x40600450 /* Configuration register EPU */
+#define UDCCRV 0x40600454 /* Configuration register EPV */
+#define UDCCRW 0x40600458 /* Configuration register EPW */
+#define UDCCRX 0x4060045C /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+/******************************************************************************/
/*
* USB Host Controller
*/
#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
-#define UHCREV __REG(0x4C000000)
-#define UHCHCON __REG(0x4C000004)
-#define UHCCOMS __REG(0x4C000008)
-#define UHCINTS __REG(0x4C00000C)
-#define UHCINTE __REG(0x4C000010)
-#define UHCINTD __REG(0x4C000014)
-#define UHCHCCA __REG(0x4C000018)
-#define UHCPCED __REG(0x4C00001C)
-#define UHCCHED __REG(0x4C000020)
-#define UHCCCED __REG(0x4C000024)
-#define UHCBHED __REG(0x4C000028)
-#define UHCBCED __REG(0x4C00002C)
-#define UHCDHEAD __REG(0x4C000030)
-#define UHCFMI __REG(0x4C000034)
-#define UHCFMR __REG(0x4C000038)
-#define UHCFMN __REG(0x4C00003C)
-#define UHCPERS __REG(0x4C000040)
-#define UHCLST __REG(0x4C000044)
-#define UHCRHDA __REG(0x4C000048)
-#define UHCRHDB __REG(0x4C00004C)
-#define UHCRHS __REG(0x4C000050)
-#define UHCRHPS1 __REG(0x4C000054)
-#define UHCRHPS2 __REG(0x4C000058)
-#define UHCRHPS3 __REG(0x4C00005C)
-#define UHCSTAT __REG(0x4C000060)
-#define UHCHR __REG(0x4C000064)
-#define UHCHIE __REG(0x4C000068)
-#define UHCHIT __REG(0x4C00006C)
+#define UHCREV 0x4C000000
+#define UHCHCON 0x4C000004
+#define UHCCOMS 0x4C000008
+#define UHCINTS 0x4C00000C
+#define UHCINTE 0x4C000010
+#define UHCINTD 0x4C000014
+#define UHCHCCA 0x4C000018
+#define UHCPCED 0x4C00001C
+#define UHCCHED 0x4C000020
+#define UHCCCED 0x4C000024
+#define UHCBHED 0x4C000028
+#define UHCBCED 0x4C00002C
+#define UHCDHEAD 0x4C000030
+#define UHCFMI 0x4C000034
+#define UHCFMR 0x4C000038
+#define UHCFMN 0x4C00003C
+#define UHCPERS 0x4C000040
+#define UHCLST 0x4C000044
+#define UHCRHDA 0x4C000048
+#define UHCRHDB 0x4C00004C
+#define UHCRHS 0x4C000050
+#define UHCRHPS1 0x4C000054
+#define UHCRHPS2 0x4C000058
+#define UHCRHPS3 0x4C00005C
+#define UHCSTAT 0x4C000060
+#define UHCHR 0x4C000064
+#define UHCHIE 0x4C000068
+#define UHCHIT 0x4C00006C
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
#define UHCHIE_HBAIE (1<<8)
#define UHCHIE_RWIE (1<<7)
-#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
-#define UP2OCR __REG(0x40600020)
-#endif
+#define UP2OCR 0x40600020
#define UP2OCR_HXOE (1<<17)
#define UP2OCR_HXS (1<<16)
#define UP2OCR_CPVPE (1<<1)
#define UP2OCR_CPVEN (1<<0)
-#endif
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+/******************************************************************************/
/*
* Fast Infrared Communication Port
*/
-#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
-#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
-#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
-#define ICDR __REG(0x4080000c) /* ICP Data Register */
-#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
-#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
+#define ICCR0 0x40800000 /* ICP Control Register 0 */
+#define ICCR1 0x40800004 /* ICP Control Register 1 */
+#define ICCR2 0x40800008 /* ICP Control Register 2 */
+#define ICDR 0x4080000c /* ICP Data Register */
+#define ICSR0 0x40800014 /* ICP Status Register 0 */
+#define ICSR1 0x40800018 /* ICP Status Register 1 */
/*
* Real Time Clock
*/
-#define RCNR __REG(0x40900000) /* RTC Count Register */
-#define RTAR __REG(0x40900004) /* RTC Alarm Register */
-#define RTSR __REG(0x40900008) /* RTC Status Register */
-#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
-#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
-#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
-#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
-#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
-#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
-#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
-#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
+#define RCNR 0x40900000 /* RTC Count Register */
+#define RTAR 0x40900004 /* RTC Alarm Register */
+#define RTSR 0x40900008 /* RTC Status Register */
+#define RTTR 0x4090000C /* RTC Timer Trim Register */
+#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */
+#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */
+#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */
+#define RDCR 0x40900010 /* RTC Day Count Register. */
+#define RYCR 0x40900014 /* RTC Year Count Register. */
+#define SWCR 0x40900028 /* Stopwatch Count Register */
+#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */
#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
+/******************************************************************************/
/*
* OS Timer & Match Registers
*/
-#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */
-#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */
-#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */
-#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */
-#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
-#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
-#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
-#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
+#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */
+#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */
+#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */
+#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */
+#define OSCR 0x40A00010 /* OS Timer Counter Register */
+#define OSSR 0x40A00014 /* OS Timer Status Register */
+#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
+#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
-#ifdef CONFIG_CPU_MONAHANS
-#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */
-#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */
-#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */
-#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */
-#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */
-#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */
-#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */
-#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */
-
-#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */
-#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */
-#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */
-#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */
-#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */
-#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */
-#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */
-#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */
-
-#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */
-#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */
-#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */
-#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */
-#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */
-#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
-#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
-#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
-
-#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */
-#endif /* CONFIG_CPU_MONAHANS */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
+#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
+#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
+#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */
+#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */
+#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */
+#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */
+#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */
+
+#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */
+#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */
+#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */
+#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */
+#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */
+#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */
+#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */
+#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */
+
+#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */
+#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */
+#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */
+#define OMCR7 0x40A000CC /* OS Match Control Register 7 */
+#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */
+#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */
+#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
+#define OMCR11 0x40A000DC /* OS Match Control Register 11 */
+
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
+#define OSCR_CLK_FREQ 3250
+
+/******************************************************************************/
/*
- * Pulse Width Modulator
+ * Core Clock
*/
-#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
-#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
-#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
-#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */
+#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */
+#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA 0x4134000C /* A Clock Enable Register */
+#define CKENB 0x41340010 /* B Clock Enable Register */
+#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS (1 << 31)
+#define ACCR_SPDIS (1 << 30)
+#define ACCR_13MEND1 (1 << 27)
+#define ACCR_D0CS (1 << 26)
+#define ACCR_13MEND2 (1 << 21)
+#define ACCR_PCCE (1 << 11)
+
+#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
+#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
+#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
+#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
+#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
+#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
+#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
+#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
+#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
+#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
+#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
+#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
+#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
+#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
+#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
+
+#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
+#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
+#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
+#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
+#define CCCR 0x41300000 /* Core Clock Configuration Register */
+#define CKEN 0x41300004 /* Clock Enable Register */
+#define OSCC 0x41300008 /* Oscillator Configuration Register */
+#define CCSR 0x4130000C /* Core Clock Status Register */
+
+#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC (1 << 22) /* Memory Controler */
+#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
+
+#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_PXA27X)
+#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
+#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
+#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
+#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
+#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
+#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
+#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
+#if defined(CONFIG_PXA27X)
+#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
+#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
+#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
+#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
+#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
+#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
+#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
+#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
+
+#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_PXA27X)
+#define CCCR_L09 (0x1F)
+#define CCCR_L27 (0x1)
+#define CCCR_L32 (0x2)
+#define CCCR_L36 (0x3)
+#define CCCR_L40 (0x4)
+#define CCCR_L45 (0x5)
+
+#define CCCR_M1 (0x1 << 5)
+#define CCCR_M2 (0x2 << 5)
+#define CCCR_M4 (0x3 << 5)
-#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
-#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
-#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+#define CCCR_N10 (0x2 << 7)
+#define CCCR_N15 (0x3 << 7)
+#define CCCR_N20 (0x4 << 7)
+#define CCCR_N25 (0x5 << 7)
+#define CCCR_N30 (0x6 << 7)
+#endif
-#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
-#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
-#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+#endif /* CONFIG_CPU_MONAHANS */
+/******************************************************************************/
/*
- * Interrupt Controller
+ * Pulse Width Modulator
*/
-#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
-#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
-#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
-#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
-#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
-#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
+#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */
+#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */
-#ifdef CONFIG_CPU_MONAHANS
-#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers
- * These are the same as beneath for PXA27x: maybe can be merged if
- * GPIO Stuff is same too.
+#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */
+#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
+#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
+#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/*
+ * Interrupt Controller
*/
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-/* Missing: 2 Interrupt priority registers */
-#endif /* CONFIG_CPU_MONAHANS */
+#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */
+#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */
+#define ICLR 0x40D00008 /* Interrupt Controller Level Register */
+#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */
+#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
+#define ICCR 0x40D00014 /* Interrupt Controller Control Register */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
+#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
+#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
+#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
/*
* General Purpose I/O
*/
-#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
+#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */
-#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
+#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */
-#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
+#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */
-#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
+#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */
-#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */
-#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */
-#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
+#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
+#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_CPU_MONAHANS
-#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
-#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
-#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
-#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
-
-#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
-#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
-#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
-#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
-
-#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
-#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
-
-#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
-#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
-
-#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
-#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
-
-#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
-#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
-
-#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
-
-/* Multi-funktion Pin Registers, uncomplete, only:
- * - GPIO
- * - Data Flash DF_* pins defined.
+#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3)
+#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3)
+#endif
+
+#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3))
+#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3))
+#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3))
+#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3))
+#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3))
+#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3))
+#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
+#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
+#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
+#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
+#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
+#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
+#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
+#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
+#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \
+ ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
+#else
+#define GPLR(x) _GPLR(x)
+#define GPDR(x) _GPDR(x)
+#define GPSR(x) _GPSR(x)
+#define GPCR(x) _GPCR(x)
+#define GRER(x) _GRER(x)
+#define GFER(x) _GFER(x)
+#define GEDR(x) _GEDR(x)
+#define GAFR(x) _GAFR(x)
+#endif
+
+#define GPIO_bit(x) (1 << ((x) & 0x1f))
+
+/******************************************************************************/
+/*
+ * Multi-function Pin Registers:
*/
-#define GPIO0 __REG(0x40e10124)
-#define GPIO1 __REG(0x40e10128)
-#define GPIO2 __REG(0x40e1012c)
-#define GPIO3 __REG(0x40e10130)
-#define GPIO4 __REG(0x40e10134)
-#define nXCVREN __REG(0x40e10138)
-
-#define DF_CLE_NOE __REG(0x40e10204)
-#define DF_ALE_WE1 __REG(0x40e10208)
-
-#define DF_SCLK_E __REG(0x40e10210)
-#define nBE0 __REG(0x40e10214)
-#define nBE1 __REG(0x40e10218)
-#define DF_ALE_WE2 __REG(0x40e1021c)
-#define DF_INT_RnB __REG(0x40e10220)
-#define DF_nCS0 __REG(0x40e10224)
-#define DF_nCS1 __REG(0x40e10228)
-#define DF_nWE __REG(0x40e1022c)
-#define DF_nRE __REG(0x40e10230)
-#define nLUA __REG(0x40e10234)
-#define nLLA __REG(0x40e10238)
-#define DF_ADDR0 __REG(0x40e1023c)
-#define DF_ADDR1 __REG(0x40e10240)
-#define DF_ADDR2 __REG(0x40e10244)
-#define DF_ADDR3 __REG(0x40e10248)
-#define DF_IO0 __REG(0x40e1024c)
-#define DF_IO8 __REG(0x40e10250)
-#define DF_IO1 __REG(0x40e10254)
-#define DF_IO9 __REG(0x40e10258)
-#define DF_IO2 __REG(0x40e1025c)
-#define DF_IO10 __REG(0x40e10260)
-#define DF_IO3 __REG(0x40e10264)
-#define DF_IO11 __REG(0x40e10268)
-#define DF_IO4 __REG(0x40e1026c)
-#define DF_IO12 __REG(0x40e10270)
-#define DF_IO5 __REG(0x40e10274)
-#define DF_IO13 __REG(0x40e10278)
-#define DF_IO6 __REG(0x40e1027c)
-#define DF_IO14 __REG(0x40e10280)
-#define DF_IO7 __REG(0x40e10284)
-#define DF_IO15 __REG(0x40e10288)
-
-#define GPIO5 __REG(0x40e1028c)
-#define GPIO6 __REG(0x40e10290)
-#define GPIO7 __REG(0x40e10294)
-#define GPIO8 __REG(0x40e10298)
-#define GPIO9 __REG(0x40e1029c)
-
-#define GPIO11 __REG(0x40e102a0)
-#define GPIO12 __REG(0x40e102a4)
-#define GPIO13 __REG(0x40e102a8)
-#define GPIO14 __REG(0x40e102ac)
-#define GPIO15 __REG(0x40e102b0)
-#define GPIO16 __REG(0x40e102b4)
-#define GPIO17 __REG(0x40e102b8)
-#define GPIO18 __REG(0x40e102bc)
-#define GPIO19 __REG(0x40e102c0)
-#define GPIO20 __REG(0x40e102c4)
-#define GPIO21 __REG(0x40e102c8)
-#define GPIO22 __REG(0x40e102cc)
-#define GPIO23 __REG(0x40e102d0)
-#define GPIO24 __REG(0x40e102d4)
-#define GPIO25 __REG(0x40e102d8)
-#define GPIO26 __REG(0x40e102dc)
-
-#define GPIO27 __REG(0x40e10400)
-#define GPIO28 __REG(0x40e10404)
-#define GPIO29 __REG(0x40e10408)
-#define GPIO30 __REG(0x40e1040c)
-#define GPIO31 __REG(0x40e10410)
-#define GPIO32 __REG(0x40e10414)
-#define GPIO33 __REG(0x40e10418)
-#define GPIO34 __REG(0x40e1041c)
-#define GPIO35 __REG(0x40e10420)
-#define GPIO36 __REG(0x40e10424)
-#define GPIO37 __REG(0x40e10428)
-#define GPIO38 __REG(0x40e1042c)
-#define GPIO39 __REG(0x40e10430)
-#define GPIO40 __REG(0x40e10434)
-#define GPIO41 __REG(0x40e10438)
-#define GPIO42 __REG(0x40e1043c)
-#define GPIO43 __REG(0x40e10440)
-#define GPIO44 __REG(0x40e10444)
-#define GPIO45 __REG(0x40e10448)
-#define GPIO46 __REG(0x40e1044c)
-#define GPIO47 __REG(0x40e10450)
-#define GPIO48 __REG(0x40e10454)
-
-#define GPIO10 __REG(0x40e10458)
-
-#define GPIO49 __REG(0x40e1045c)
-#define GPIO50 __REG(0x40e10460)
-#define GPIO51 __REG(0x40e10464)
-#define GPIO52 __REG(0x40e10468)
-#define GPIO53 __REG(0x40e1046c)
-#define GPIO54 __REG(0x40e10470)
-#define GPIO55 __REG(0x40e10474)
-#define GPIO56 __REG(0x40e10478)
-#define GPIO57 __REG(0x40e1047c)
-#define GPIO58 __REG(0x40e10480)
-#define GPIO59 __REG(0x40e10484)
-#define GPIO60 __REG(0x40e10488)
-#define GPIO61 __REG(0x40e1048c)
-#define GPIO62 __REG(0x40e10490)
-
-#define GPIO6_2 __REG(0x40e10494)
-#define GPIO7_2 __REG(0x40e10498)
-#define GPIO8_2 __REG(0x40e1049c)
-#define GPIO9_2 __REG(0x40e104a0)
-#define GPIO10_2 __REG(0x40e104a4)
-#define GPIO11_2 __REG(0x40e104a8)
-#define GPIO12_2 __REG(0x40e104ac)
-#define GPIO13_2 __REG(0x40e104b0)
-
-#define GPIO63 __REG(0x40e104b4)
-#define GPIO64 __REG(0x40e104b8)
-#define GPIO65 __REG(0x40e104bc)
-#define GPIO66 __REG(0x40e104c0)
-#define GPIO67 __REG(0x40e104c4)
-#define GPIO68 __REG(0x40e104c8)
-#define GPIO69 __REG(0x40e104cc)
-#define GPIO70 __REG(0x40e104d0)
-#define GPIO71 __REG(0x40e104d4)
-#define GPIO72 __REG(0x40e104d8)
-#define GPIO73 __REG(0x40e104dc)
-
-#define GPIO14_2 __REG(0x40e104e0)
-#define GPIO15_2 __REG(0x40e104e4)
-#define GPIO16_2 __REG(0x40e104e8)
-#define GPIO17_2 __REG(0x40e104ec)
-
-#define GPIO74 __REG(0x40e104f0)
-#define GPIO75 __REG(0x40e104f4)
-#define GPIO76 __REG(0x40e104f8)
-#define GPIO77 __REG(0x40e104fc)
-#define GPIO78 __REG(0x40e10500)
-#define GPIO79 __REG(0x40e10504)
-#define GPIO80 __REG(0x40e10508)
-#define GPIO81 __REG(0x40e1050c)
-#define GPIO82 __REG(0x40e10510)
-#define GPIO83 __REG(0x40e10514)
-#define GPIO84 __REG(0x40e10518)
-#define GPIO85 __REG(0x40e1051c)
-#define GPIO86 __REG(0x40e10520)
-#define GPIO87 __REG(0x40e10524)
-#define GPIO88 __REG(0x40e10528)
-#define GPIO89 __REG(0x40e1052c)
-#define GPIO90 __REG(0x40e10530)
-#define GPIO91 __REG(0x40e10534)
-#define GPIO92 __REG(0x40e10538)
-#define GPIO93 __REG(0x40e1053c)
-#define GPIO94 __REG(0x40e10540)
-#define GPIO95 __REG(0x40e10544)
-#define GPIO96 __REG(0x40e10548)
-#define GPIO97 __REG(0x40e1054c)
-#define GPIO98 __REG(0x40e10550)
-
-#define GPIO99 __REG(0x40e10600)
-#define GPIO100 __REG(0x40e10604)
-#define GPIO101 __REG(0x40e10608)
-#define GPIO102 __REG(0x40e1060c)
-#define GPIO103 __REG(0x40e10610)
-#define GPIO104 __REG(0x40e10614)
-#define GPIO105 __REG(0x40e10618)
-#define GPIO106 __REG(0x40e1061c)
-#define GPIO107 __REG(0x40e10620)
-#define GPIO108 __REG(0x40e10624)
-#define GPIO109 __REG(0x40e10628)
-#define GPIO110 __REG(0x40e1062c)
-#define GPIO111 __REG(0x40e10630)
-#define GPIO112 __REG(0x40e10634)
-
-#define GPIO113 __REG(0x40e10638)
-#define GPIO114 __REG(0x40e1063c)
-#define GPIO115 __REG(0x40e10640)
-#define GPIO116 __REG(0x40e10644)
-#define GPIO117 __REG(0x40e10648)
-#define GPIO118 __REG(0x40e1064c)
-#define GPIO119 __REG(0x40e10650)
-#define GPIO120 __REG(0x40e10654)
-#define GPIO121 __REG(0x40e10658)
-#define GPIO122 __REG(0x40e1065c)
-#define GPIO123 __REG(0x40e10660)
-#define GPIO124 __REG(0x40e10664)
-#define GPIO125 __REG(0x40e10668)
-#define GPIO126 __REG(0x40e1066c)
-#define GPIO127 __REG(0x40e10670)
-
-#define GPIO0_2 __REG(0x40e10674)
-#define GPIO1_2 __REG(0x40e10678)
-#define GPIO2_2 __REG(0x40e1067c)
-#define GPIO3_2 __REG(0x40e10680)
-#define GPIO4_2 __REG(0x40e10684)
-#define GPIO5_2 __REG(0x40e10688)
+/* PXA320 */
+#if defined(CONFIG_CPU_PXA320)
+#define DF_IO0 0x40e1024c
+#define DF_IO1 0x40e10254
+#define DF_IO2 0x40e1025c
+#define DF_IO3 0x40e10264
+#define DF_IO4 0x40e1026c
+#define DF_IO5 0x40e10274
+#define DF_IO6 0x40e1027c
+#define DF_IO7 0x40e10284
+#define DF_IO8 0x40e10250
+#define DF_IO9 0x40e10258
+#define DF_IO10 0x40e10260
+#define DF_IO11 0x40e10268
+#define DF_IO12 0x40e10270
+#define DF_IO13 0x40e10278
+#define DF_IO14 0x40e10280
+#define DF_IO15 0x40e10288
+#define DF_CLE_nOE 0x40e10204
+#define DF_ALE_nWE1 0x40e10208
+#define DF_ALE_nWE2 0x40e1021c
+#define DF_SCLK_E 0x40e10210
+#define DF_nCS0 0x40e10224
+#define DF_nCS1 0x40e10228
+#define nBE0 0x40e10214
+#define nBE1 0x40e10218
+#define nLUA 0x40e10234
+#define nLLA 0x40e10238
+#define DF_ADDR0 0x40e1023c
+#define DF_ADDR1 0x40e10240
+#define DF_ADDR2 0x40e10244
+#define DF_ADDR3 0x40e10248
+#define DF_INT_RnB 0x40e10220
+#define DF_nCS0 0x40e10224
+#define DF_nCS1 0x40e10228
+#define DF_nWE 0x40e1022c
+#define DF_nRE 0x40e10230
+
+#define nXCVREN 0x40e10138
+
+#define GPIO0 0x40e10124
+#define GPIO1 0x40e10128
+#define GPIO2 0x40e1012c
+#define GPIO3 0x40e10130
+#define GPIO4 0x40e10134
+#define GPIO5 0x40e1028c
+#define GPIO6 0x40e10290
+#define GPIO7 0x40e10294
+#define GPIO8 0x40e10298
+#define GPIO9 0x40e1029c
+#define GPIO10 0x40e10458
+#define GPIO11 0x40e102a0
+#define GPIO12 0x40e102a4
+#define GPIO13 0x40e102a8
+#define GPIO14 0x40e102ac
+#define GPIO15 0x40e102b0
+#define GPIO16 0x40e102b4
+#define GPIO17 0x40e102b8
+#define GPIO18 0x40e102bc
+#define GPIO19 0x40e102c0
+#define GPIO20 0x40e102c4
+#define GPIO21 0x40e102c8
+#define GPIO22 0x40e102cc
+#define GPIO23 0x40e102d0
+#define GPIO24 0x40e102d4
+#define GPIO25 0x40e102d8
+#define GPIO26 0x40e102dc
+
+#define GPIO27 0x40e10400
+#define GPIO28 0x40e10404
+#define GPIO29 0x40e10408
+#define GPIO30 0x40e1040c
+#define GPIO31 0x40e10410
+#define GPIO32 0x40e10414
+#define GPIO33 0x40e10418
+#define GPIO34 0x40e1041c
+#define GPIO35 0x40e10420
+#define GPIO36 0x40e10424
+#define GPIO37 0x40e10428
+#define GPIO38 0x40e1042c
+#define GPIO39 0x40e10430
+#define GPIO40 0x40e10434
+#define GPIO41 0x40e10438
+#define GPIO42 0x40e1043c
+#define GPIO43 0x40e10440
+#define GPIO44 0x40e10444
+#define GPIO45 0x40e10448
+#define GPIO46 0x40e1044c
+#define GPIO47 0x40e10450
+#define GPIO48 0x40e10454
+#define GPIO49 0x40e1045c
+#define GPIO50 0x40e10460
+#define GPIO51 0x40e10464
+#define GPIO52 0x40e10468
+#define GPIO53 0x40e1046c
+#define GPIO54 0x40e10470
+#define GPIO55 0x40e10474
+#define GPIO56 0x40e10478
+#define GPIO57 0x40e1047c
+#define GPIO58 0x40e10480
+#define GPIO59 0x40e10484
+#define GPIO60 0x40e10488
+#define GPIO61 0x40e1048c
+#define GPIO62 0x40e10490
+
+#define GPIO6_2 0x40e10494
+#define GPIO7_2 0x40e10498
+#define GPIO8_2 0x40e1049c
+#define GPIO9_2 0x40e104a0
+#define GPIO10_2 0x40e104a4
+#define GPIO11_2 0x40e104a8
+#define GPIO12_2 0x40e104ac
+#define GPIO13_2 0x40e104b0
+
+#define GPIO63 0x40e104b4
+#define GPIO64 0x40e104b8
+#define GPIO65 0x40e104bc
+#define GPIO66 0x40e104c0
+#define GPIO67 0x40e104c4
+#define GPIO68 0x40e104c8
+#define GPIO69 0x40e104cc
+#define GPIO70 0x40e104d0
+#define GPIO71 0x40e104d4
+#define GPIO72 0x40e104d8
+#define GPIO73 0x40e104dc
+
+#define GPIO14_2 0x40e104e0
+#define GPIO15_2 0x40e104e4
+#define GPIO16_2 0x40e104e8
+#define GPIO17_2 0x40e104ec
+
+#define GPIO74 0x40e104f0
+#define GPIO75 0x40e104f4
+#define GPIO76 0x40e104f8
+#define GPIO77 0x40e104fc
+#define GPIO78 0x40e10500
+#define GPIO79 0x40e10504
+#define GPIO80 0x40e10508
+#define GPIO81 0x40e1050c
+#define GPIO82 0x40e10510
+#define GPIO83 0x40e10514
+#define GPIO84 0x40e10518
+#define GPIO85 0x40e1051c
+#define GPIO86 0x40e10520
+#define GPIO87 0x40e10524
+#define GPIO88 0x40e10528
+#define GPIO89 0x40e1052c
+#define GPIO90 0x40e10530
+#define GPIO91 0x40e10534
+#define GPIO92 0x40e10538
+#define GPIO93 0x40e1053c
+#define GPIO94 0x40e10540
+#define GPIO95 0x40e10544
+#define GPIO96 0x40e10548
+#define GPIO97 0x40e1054c
+#define GPIO98 0x40e10550
+
+#define GPIO99 0x40e10600
+#define GPIO100 0x40e10604
+#define GPIO101 0x40e10608
+#define GPIO102 0x40e1060c
+#define GPIO103 0x40e10610
+#define GPIO104 0x40e10614
+#define GPIO105 0x40e10618
+#define GPIO106 0x40e1061c
+#define GPIO107 0x40e10620
+#define GPIO108 0x40e10624
+#define GPIO109 0x40e10628
+#define GPIO110 0x40e1062c
+#define GPIO111 0x40e10630
+#define GPIO112 0x40e10634
+
+#define GPIO113 0x40e10638
+#define GPIO114 0x40e1063c
+#define GPIO115 0x40e10640
+#define GPIO116 0x40e10644
+#define GPIO117 0x40e10648
+#define GPIO118 0x40e1064c
+#define GPIO119 0x40e10650
+#define GPIO120 0x40e10654
+#define GPIO121 0x40e10658
+#define GPIO122 0x40e1065c
+#define GPIO123 0x40e10660
+#define GPIO124 0x40e10664
+#define GPIO125 0x40e10668
+#define GPIO126 0x40e1066c
+#define GPIO127 0x40e10670
+
+#define GPIO0_2 0x40e10674
+#define GPIO1_2 0x40e10678
+#define GPIO2_2 0x40e1067c
+#define GPIO3_2 0x40e10680
+#define GPIO4_2 0x40e10684
+#define GPIO5_2 0x40e10688
+
+/* PXA300 and PXA310 */
+#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
+#define DF_IO0 0x40e10220
+#define DF_IO1 0x40e10228
+#define DF_IO2 0x40e10230
+#define DF_IO3 0x40e10238
+#define DF_IO4 0x40e10258
+#define DF_IO5 0x40e10260
+#define DF_IO7 0x40e10270
+#define DF_IO6 0x40e10268
+#define DF_IO8 0x40e10224
+#define DF_IO9 0x40e1022c
+#define DF_IO10 0x40e10234
+#define DF_IO11 0x40e1023c
+#define DF_IO12 0x40e1025c
+#define DF_IO13 0x40e10264
+#define DF_IO14 0x40e1026c
+#define DF_IO15 0x40e10274
+#define DF_CLE_NOE 0x40e10240
+#define DF_ALE_nWE 0x40e1020c
+#define DF_SCLK_E 0x40e10250
+#define nCS0 0x40e100c4
+#define nCS1 0x40e100c0
+#define nBE0 0x40e10204
+#define nBE1 0x40e10208
+#define nLUA 0x40e10244
+#define nLLA 0x40e10254
+#define DF_ADDR0 0x40e10210
+#define DF_ADDR1 0x40e10214
+#define DF_ADDR2 0x40e10218
+#define DF_ADDR3 0x40e1021c
+#define DF_INT_RnB 0x40e100c8
+#define DF_nCS0 0x40e10248
+#define DF_nCS1 0x40e10278
+#define DF_nWE 0x40e100cc
+#define DF_nRE 0x40e10200
+
+#define GPIO0 0x40e100b4
+#define GPIO1 0x40e100b8
+#define GPIO2 0x40e100bc
+#define GPIO3 0x40e1027c
+#define GPIO4 0x40e10280
+
+#define GPIO5 0x40e10284
+#define GPIO6 0x40e10288
+#define GPIO7 0x40e1028c
+#define GPIO8 0x40e10290
+#define GPIO9 0x40e10294
+#define GPIO10 0x40e10298
+#define GPIO11 0x40e1029c
+#define GPIO12 0x40e102a0
+#define GPIO13 0x40e102a4
+#define GPIO14 0x40e102a8
+#define GPIO15 0x40e102ac
+#define GPIO16 0x40e102b0
+#define GPIO17 0x40e102b4
+#define GPIO18 0x40e102b8
+#define GPIO19 0x40e102bc
+#define GPIO20 0x40e102c0
+#define GPIO21 0x40e102c4
+#define GPIO22 0x40e102c8
+#define GPIO23 0x40e102cc
+#define GPIO24 0x40e102d0
+#define GPIO25 0x40e102d4
+#define GPIO26 0x40e102d8
+
+#define GPIO27 0x40e10400
+#define GPIO28 0x40e10404
+#define GPIO29 0x40e10408
+#define ULPI_STP 0x40e1040c
+#define ULPI_NXT 0x40e10410
+#define ULPI_DIR 0x40e10414
+#define GPIO30 0x40e10418
+#define GPIO31 0x40e1041c
+#define GPIO32 0x40e10420
+#define GPIO33 0x40e10424
+#define GPIO34 0x40e10428
+#define GPIO35 0x40e1042c
+#define GPIO36 0x40e10430
+#define GPIO37 0x40e10434
+#define GPIO38 0x40e10438
+#define GPIO39 0x40e1043c
+#define GPIO40 0x40e10440
+#define GPIO41 0x40e10444
+#define GPIO42 0x40e10448
+#define GPIO43 0x40e1044c
+#define GPIO44 0x40e10450
+#define GPIO45 0x40e10454
+#define GPIO46 0x40e10458
+#define GPIO47 0x40e1045c
+#define GPIO48 0x40e10460
+
+#define GPIO49 0x40e10464
+#define GPIO50 0x40e10468
+#define GPIO51 0x40e1046c
+#define GPIO52 0x40e10470
+#define GPIO53 0x40e10474
+#define GPIO54 0x40e10478
+#define GPIO55 0x40e1047c
+#define GPIO56 0x40e10480
+#define GPIO57 0x40e10484
+#define GPIO58 0x40e10488
+#define GPIO59 0x40e1048c
+#define GPIO60 0x40e10490
+#define GPIO61 0x40e10494
+#define GPIO62 0x40e10498
+#define GPIO63 0x40e1049c
+#define GPIO64 0x40e104a0
+#define GPIO65 0x40e104a4
+#define GPIO66 0x40e104a8
+#define GPIO67 0x40e104ac
+#define GPIO68 0x40e104b0
+#define GPIO69 0x40e104b4
+#define GPIO70 0x40e104b8
+#define GPIO71 0x40e104bc
+#define GPIO72 0x40e104c0
+#define GPIO73 0x40e104c4
+#define GPIO74 0x40e104c8
+#define GPIO75 0x40e104cc
+#define GPIO76 0x40e104d0
+#define GPIO77 0x40e104d4
+#define GPIO78 0x40e104d8
+#define GPIO79 0x40e104dc
+#define GPIO80 0x40e104e0
+#define GPIO81 0x40e104e4
+#define GPIO82 0x40e104e8
+#define GPIO83 0x40e104ec
+#define GPIO84 0x40e104f0
+#define GPIO85 0x40e104f4
+#define GPIO86 0x40e104f8
+#define GPIO87 0x40e104fc
+#define GPIO88 0x40e10500
+#define GPIO89 0x40e10504
+#define GPIO90 0x40e10508
+#define GPIO91 0x40e1050c
+#define GPIO92 0x40e10510
+#define GPIO93 0x40e10514
+#define GPIO94 0x40e10518
+#define GPIO95 0x40e1051c
+#define GPIO96 0x40e10520
+#define GPIO97 0x40e10524
+#define GPIO98 0x40e10528
+
+#define GPIO99 0x40e10600
+#define GPIO100 0x40e10604
+#define GPIO101 0x40e10608
+#define GPIO102 0x40e1060c
+#define GPIO103 0x40e10610
+#define GPIO104 0x40e10614
+#define GPIO105 0x40e10618
+#define GPIO106 0x40e1061c
+#define GPIO107 0x40e10620
+#define GPIO108 0x40e10624
+#define GPIO109 0x40e10628
+#define GPIO110 0x40e1062c
+#define GPIO111 0x40e10630
+#define GPIO112 0x40e10634
+
+#define GPIO113 0x40e10638
+#define GPIO114 0x40e1063c
+#define GPIO115 0x40e10640
+#define GPIO116 0x40e10644
+#define GPIO117 0x40e10648
+#define GPIO118 0x40e1064c
+#define GPIO119 0x40e10650
+#define GPIO120 0x40e10654
+#define GPIO121 0x40e10658
+#define GPIO122 0x40e1065c
+#define GPIO123 0x40e10660
+#define GPIO124 0x40e10664
+#define GPIO125 0x40e10668
+#define GPIO126 0x40e1066c
+#define GPIO127 0x40e10670
+
+#define GPIO0_2 0x40e10674
+#define GPIO1_2 0x40e10678
+#define GPIO2_2 0x40e102dc
+#define GPIO3_2 0x40e102e0
+#define GPIO4_2 0x40e102e4
+#define GPIO5_2 0x40e102e8
+#define GPIO6_2 0x40e102ec
+
+#ifndef CONFIG_CPU_PXA300 /* PXA310 only */
+#define GPIO7_2 0x40e1052c
+#define GPIO8_2 0x40e10530
+#define GPIO9_2 0x40e10534
+#define GPIO10_2 0x40e10538
+#endif
+#endif
+#ifdef CONFIG_CPU_MONAHANS
/* MFPR Bit Definitions, see 4-10, Vol. 1 */
#define PULL_SEL 0x8000
#define PULLUP_EN 0x4000
#define AF_SEL_6 0x6 /* Alternate function 6 */
#define AF_SEL_7 0x7 /* Alternate function 7 */
-
-#else /* CONFIG_CPU_MONAHANS */
-
-#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
#endif /* CONFIG_CPU_MONAHANS */
-/* More handy macros. The argument is a literal GPIO number. */
-
-#define GPIO_bit(x) (1 << ((x) & 0x1f))
-
-#ifdef CONFIG_PXA27X
-
-/* Interrupt Controller */
-
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
-#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
-#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
-#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
-#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
-#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
-#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
-#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
-#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
- ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-#else
-
-#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#endif
-
/* GPIO alternate function assignments */
#define GPIO1_RST 1 /* reset */
*/
#ifdef CONFIG_CPU_MONAHANS
-#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */
-#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */
-#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */
-#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */
-#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */
-#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */
-#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */
-#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */
-#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */
-#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */
-#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */
-#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */
-#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */
-#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */
-
-#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
-#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
-#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
-#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
-#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
-#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
-#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
-#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
-#define PCMD(x) __REG(0x40F50110 + x*4)
-#define PCMD0 __REG(0x40F50110 + 0 * 4)
-#define PCMD1 __REG(0x40F50110 + 1 * 4)
-#define PCMD2 __REG(0x40F50110 + 2 * 4)
-#define PCMD3 __REG(0x40F50110 + 3 * 4)
-#define PCMD4 __REG(0x40F50110 + 4 * 4)
-#define PCMD5 __REG(0x40F50110 + 5 * 4)
-#define PCMD6 __REG(0x40F50110 + 6 * 4)
-#define PCMD7 __REG(0x40F50110 + 7 * 4)
-#define PCMD8 __REG(0x40F50110 + 8 * 4)
-#define PCMD9 __REG(0x40F50110 + 9 * 4)
-#define PCMD10 __REG(0x40F50110 + 10 * 4)
-#define PCMD11 __REG(0x40F50110 + 11 * 4)
-#define PCMD12 __REG(0x40F50110 + 12 * 4)
-#define PCMD13 __REG(0x40F50110 + 13 * 4)
-#define PCMD14 __REG(0x40F50110 + 14 * 4)
-#define PCMD15 __REG(0x40F50110 + 15 * 4)
-#define PCMD16 __REG(0x40F50110 + 16 * 4)
-#define PCMD17 __REG(0x40F50110 + 17 * 4)
-#define PCMD18 __REG(0x40F50110 + 18 * 4)
-#define PCMD19 __REG(0x40F50110 + 19 * 4)
-#define PCMD20 __REG(0x40F50110 + 20 * 4)
-#define PCMD21 __REG(0x40F50110 + 21 * 4)
-#define PCMD22 __REG(0x40F50110 + 22 * 4)
-#define PCMD23 __REG(0x40F50110 + 23 * 4)
-#define PCMD24 __REG(0x40F50110 + 24 * 4)
-#define PCMD25 __REG(0x40F50110 + 25 * 4)
-#define PCMD26 __REG(0x40F50110 + 26 * 4)
-#define PCMD27 __REG(0x40F50110 + 27 * 4)
-#define PCMD28 __REG(0x40F50110 + 28 * 4)
-#define PCMD29 __REG(0x40F50110 + 29 * 4)
-#define PCMD30 __REG(0x40F50110 + 30 * 4)
-#define PCMD31 __REG(0x40F50110 + 31 * 4)
+#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */
+#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */
+#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */
+#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */
+#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR 0x40F50000 /* Power Manager Control Register */
+#define PSR 0x40F50004 /* Power Manager S2 Status Register */
+#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */
+#define PCFR 0x40F5000C /* Power Manager General Configuration Register */
+#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */
+#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */
+#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */
+#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */
+#define PCMD(x) (0x40F50110 + x*4)
+#define PCMD0 (0x40F50110 + 0 * 4)
+#define PCMD1 (0x40F50110 + 1 * 4)
+#define PCMD2 (0x40F50110 + 2 * 4)
+#define PCMD3 (0x40F50110 + 3 * 4)
+#define PCMD4 (0x40F50110 + 4 * 4)
+#define PCMD5 (0x40F50110 + 5 * 4)
+#define PCMD6 (0x40F50110 + 6 * 4)
+#define PCMD7 (0x40F50110 + 7 * 4)
+#define PCMD8 (0x40F50110 + 8 * 4)
+#define PCMD9 (0x40F50110 + 9 * 4)
+#define PCMD10 (0x40F50110 + 10 * 4)
+#define PCMD11 (0x40F50110 + 11 * 4)
+#define PCMD12 (0x40F50110 + 12 * 4)
+#define PCMD13 (0x40F50110 + 13 * 4)
+#define PCMD14 (0x40F50110 + 14 * 4)
+#define PCMD15 (0x40F50110 + 15 * 4)
+#define PCMD16 (0x40F50110 + 16 * 4)
+#define PCMD17 (0x40F50110 + 17 * 4)
+#define PCMD18 (0x40F50110 + 18 * 4)
+#define PCMD19 (0x40F50110 + 19 * 4)
+#define PCMD20 (0x40F50110 + 20 * 4)
+#define PCMD21 (0x40F50110 + 21 * 4)
+#define PCMD22 (0x40F50110 + 22 * 4)
+#define PCMD23 (0x40F50110 + 23 * 4)
+#define PCMD24 (0x40F50110 + 24 * 4)
+#define PCMD25 (0x40F50110 + 25 * 4)
+#define PCMD26 (0x40F50110 + 26 * 4)
+#define PCMD27 (0x40F50110 + 27 * 4)
+#define PCMD28 (0x40F50110 + 28 * 4)
+#define PCMD29 (0x40F50110 + 29 * 4)
+#define PCMD30 (0x40F50110 + 30 * 4)
+#define PCMD31 (0x40F50110 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PVCR_FVC (0x1 << 28)
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
-#define PVCR_ReadPointer (0x01f00000)
+#define PVCR_ReadPointer 0x01f00000
#define PVCR_SlaveAddress (0x7f)
#else /* ifdef CONFIG_CPU_MONAHANS */
-#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
-#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
-#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
-#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
-#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
-#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
-
-#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
-#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG(0x40F00080 + x*4)
-#define PCMD0 __REG(0x40F00080 + 0 * 4)
-#define PCMD1 __REG(0x40F00080 + 1 * 4)
-#define PCMD2 __REG(0x40F00080 + 2 * 4)
-#define PCMD3 __REG(0x40F00080 + 3 * 4)
-#define PCMD4 __REG(0x40F00080 + 4 * 4)
-#define PCMD5 __REG(0x40F00080 + 5 * 4)
-#define PCMD6 __REG(0x40F00080 + 6 * 4)
-#define PCMD7 __REG(0x40F00080 + 7 * 4)
-#define PCMD8 __REG(0x40F00080 + 8 * 4)
-#define PCMD9 __REG(0x40F00080 + 9 * 4)
-#define PCMD10 __REG(0x40F00080 + 10 * 4)
-#define PCMD11 __REG(0x40F00080 + 11 * 4)
-#define PCMD12 __REG(0x40F00080 + 12 * 4)
-#define PCMD13 __REG(0x40F00080 + 13 * 4)
-#define PCMD14 __REG(0x40F00080 + 14 * 4)
-#define PCMD15 __REG(0x40F00080 + 15 * 4)
-#define PCMD16 __REG(0x40F00080 + 16 * 4)
-#define PCMD17 __REG(0x40F00080 + 17 * 4)
-#define PCMD18 __REG(0x40F00080 + 18 * 4)
-#define PCMD19 __REG(0x40F00080 + 19 * 4)
-#define PCMD20 __REG(0x40F00080 + 20 * 4)
-#define PCMD21 __REG(0x40F00080 + 21 * 4)
-#define PCMD22 __REG(0x40F00080 + 22 * 4)
-#define PCMD23 __REG(0x40F00080 + 23 * 4)
-#define PCMD24 __REG(0x40F00080 + 24 * 4)
-#define PCMD25 __REG(0x40F00080 + 25 * 4)
-#define PCMD26 __REG(0x40F00080 + 26 * 4)
-#define PCMD27 __REG(0x40F00080 + 27 * 4)
-#define PCMD28 __REG(0x40F00080 + 28 * 4)
-#define PCMD29 __REG(0x40F00080 + 29 * 4)
-#define PCMD30 __REG(0x40F00080 + 30 * 4)
-#define PCMD31 __REG(0x40F00080 + 31 * 4)
+#define PMCR 0x40F00000 /* Power Manager Control Register */
+#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */
+#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */
+#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */
+#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR 0x40F0001C /* Power Manager General Configuration Register */
+#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR 0x40F00030 /* Reset Controller Status Register */
+
+#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */
+#define PSTR 0x40F00038 /* Power Manager Standby Config Register */
+#define PSNR 0x40F0003C /* Power Manager Sense Config Register */
+#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */
+#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */
+#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */
+#define PCMD(x) (0x40F00080 + x*4)
+#define PCMD0 (0x40F00080 + 0 * 4)
+#define PCMD1 (0x40F00080 + 1 * 4)
+#define PCMD2 (0x40F00080 + 2 * 4)
+#define PCMD3 (0x40F00080 + 3 * 4)
+#define PCMD4 (0x40F00080 + 4 * 4)
+#define PCMD5 (0x40F00080 + 5 * 4)
+#define PCMD6 (0x40F00080 + 6 * 4)
+#define PCMD7 (0x40F00080 + 7 * 4)
+#define PCMD8 (0x40F00080 + 8 * 4)
+#define PCMD9 (0x40F00080 + 9 * 4)
+#define PCMD10 (0x40F00080 + 10 * 4)
+#define PCMD11 (0x40F00080 + 11 * 4)
+#define PCMD12 (0x40F00080 + 12 * 4)
+#define PCMD13 (0x40F00080 + 13 * 4)
+#define PCMD14 (0x40F00080 + 14 * 4)
+#define PCMD15 (0x40F00080 + 15 * 4)
+#define PCMD16 (0x40F00080 + 16 * 4)
+#define PCMD17 (0x40F00080 + 17 * 4)
+#define PCMD18 (0x40F00080 + 18 * 4)
+#define PCMD19 (0x40F00080 + 19 * 4)
+#define PCMD20 (0x40F00080 + 20 * 4)
+#define PCMD21 (0x40F00080 + 21 * 4)
+#define PCMD22 (0x40F00080 + 22 * 4)
+#define PCMD23 (0x40F00080 + 23 * 4)
+#define PCMD24 (0x40F00080 + 24 * 4)
+#define PCMD25 (0x40F00080 + 25 * 4)
+#define PCMD26 (0x40F00080 + 26 * 4)
+#define PCMD27 (0x40F00080 + 27 * 4)
+#define PCMD28 (0x40F00080 + 28 * 4)
+#define PCMD29 (0x40F00080 + 29 * 4)
+#define PCMD30 (0x40F00080 + 30 * 4)
+#define PCMD31 (0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
/*
* SSP Serial Port Registers
*/
-#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
-#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
-#define SSSR __REG(0x41000008) /* SSP Status Register */
-#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
-#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+#define SSCR0 0x41000000 /* SSP Control Register 0 */
+#define SSCR1 0x41000004 /* SSP Control Register 1 */
+#define SSSR 0x41000008 /* SSP Status Register */
+#define SSITR 0x4100000C /* SSP Interrupt Test Register */
+#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
/*
* MultiMediaCard (MMC) controller
*/
-#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
-#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
-#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
-#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
-#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
-#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
-#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
-#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
-#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
-#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
-#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
-#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
-#define MMC_CMD __REG(0x41100030) /* Index of current command */
-#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
-#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
-#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
-#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
-#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
-
-/*
- * Core Clock
- */
-
-#if defined(CONFIG_CPU_MONAHANS)
-#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
-#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
-#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
-#define CKENB __REG(0x41340010) /* B Clock Enable Register */
-#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
-
-#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
-#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
-#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
-#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
-#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
-#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
-#define ACCR_XPDIS (1 << 31)
-#define ACCR_SPDIS (1 << 30)
-#define ACCR_13MEND1 (1 << 27)
-#define ACCR_D0CS (1 << 26)
-#define ACCR_13MEND2 (1 << 21)
-#define ACCR_PCCE (1 << 11)
-
-#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
-#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
-#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
-#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
-#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
-#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
-#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
-#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
-#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
-#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
-#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
-#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
-#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
-#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
-#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
-#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
-#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
-#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
-#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
-#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
-
-#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
-#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
-#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
-#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
-#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
-#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
-
-#else /* if defined CONFIG_CPU_MONAHANS */
-
-#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
-#define CKEN __REG(0x41300004) /* Clock Enable Register */
-#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
-
-#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
-#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
-#endif
-#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
-#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
-#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
-#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
-#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
-#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
-#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
-#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
-#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
-#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
-#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
-#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
-#endif
-#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
-#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
-#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
-#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
-#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
-#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
-#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
-#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
-
-#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
-
-#if !defined(CONFIG_PXA27X)
-#define CCCR_L09 (0x1F)
-#define CCCR_L27 (0x1)
-#define CCCR_L32 (0x2)
-#define CCCR_L36 (0x3)
-#define CCCR_L40 (0x4)
-#define CCCR_L45 (0x5)
-
-#define CCCR_M1 (0x1 << 5)
-#define CCCR_M2 (0x2 << 5)
-#define CCCR_M4 (0x3 << 5)
-
-#define CCCR_N10 (0x2 << 7)
-#define CCCR_N15 (0x3 << 7)
-#define CCCR_N20 (0x4 << 7)
-#define CCCR_N25 (0x5 << 7)
-#define CCCR_N30 (0x6 << 7)
-#endif
+#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */
+#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */
+#define MMC_CLKRT 0x41100008 /* MMC clock rate */
+#define MMC_SPI 0x4110000c /* SPI mode control bits */
+#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */
+#define MMC_RESTO 0x41100014 /* Expected response time out */
+#define MMC_RDTO 0x41100018 /* Expected data read time out */
+#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */
+#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */
+#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK 0x41100028 /* Interrupt Mask */
+#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */
+#define MMC_CMD 0x41100030 /* Index of current command */
+#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */
+#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */
+#define MMC_RES 0x4110003c /* Response FIFO (read only) */
+#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */
+#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */
-#endif /* CONFIG_CPU_MONAHANS */
/*
* LCD
*/
-#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
-#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
-#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
-#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
-#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
-#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
-#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
-#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
-#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
-#define TMEDCR __REG(0x44000044) /* TMED Control Register */
-
-#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
-#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
-#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
-#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
+#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */
+#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */
+#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */
+#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */
+#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
+#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
+#define LCSR0 0x44000038 /* LCD Controller Status Register */
+#define LCSR1 0x44000034 /* LCD Controller Status Register */
+#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */
+#define TMEDCR 0x44000044 /* TMED Control Register */
+
+#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */
+#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */
+#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */
+#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */
#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_BFW))
-#if 0
-#define LCCR3_PCD (0xff) /* Pixel clock divisor */
-#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
-#define LCCR3_ACB_S 8
-#endif
-
#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
#define LCCR3_API_S 16
#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
#define LCCR3_OEP (1 << 23) /* output enable polarity */
-#if 0
-#define LCCR3_BPP (7 << 24) /* bits per pixel */
-#define LCCR3_BPP_S 24
-#endif
#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
#define LCCR3_PDFOR_0 (0 << 30)
*/
#ifdef CONFIG_CPU_MONAHANS
+
+/* PXA3xx */
+
/* Static Memory Controller Registers */
-#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
-#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
-#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
-#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
-#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
-#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
-#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
-#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
-#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
-#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
-#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */
-#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */
+#define MSC0 0x4A000008 /* Static Memory Control Register 0 */
+#define MSC1 0x4A00000C /* Static Memory Control Register 1 */
+#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */
+#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */
+#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */
+#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */
+#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */
+#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */
+#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */
+#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */
+#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
+#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
/* Dynamic Memory Controller Registers */
-#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
-#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
-#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
-#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
-#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
-#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
-#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */
-#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
-#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
-#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
-#define EMPI __REG_2(0x48100090) /* EMPI Control Register */
-#define RCOMP __REG_2(0x48100100)
-#define PAD_MA __REG_2(0x48100110)
-#define PAD_MDMSB __REG_2(0x48100114)
-#define PAD_MDLSB __REG_2(0x48100118)
-#define PAD_DMEM __REG_2(0x4810011c)
-#define PAD_SDCLK __REG_2(0x48100120)
-#define PAD_SDCS __REG_2(0x48100124)
-#define PAD_SMEM __REG_2(0x48100128)
-#define PAD_SCLK __REG_2(0x4810012C)
-#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */
+#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */
+#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
+#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */
+#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */
+#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */
+#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */
+#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
+#define EMPI 0x48100090 /* EMPI Control Register */
+#define RCOMP 0x48100100
+#define PAD_MA 0x48100110
+#define PAD_MDMSB 0x48100114
+#define PAD_MDLSB 0x48100118
+#define PAD_DMEM 0x4810011c
+#define PAD_SDCLK 0x48100120
+#define PAD_SDCS 0x48100124
+#define PAD_SMEM 0x48100128
+#define PAD_SCLK 0x4810012C
+#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */
/* Some frequently used bits */
#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
/* Data Flash Controller Registers */
-#define NDCR __REG(0x43100000) /* Data Flash Control register */
-#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
-#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
-#define NDSR __REG(0x43100014) /* Data Controller Status Register */
-#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
-#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
-#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
-#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
-#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
-#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
-#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
+#define NDCR 0x43100000 /* Data Flash Control register */
+#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR 0x43100014 /* Data Controller Status Register */
+#define NDPCR 0x43100018 /* Data Controller Page Count Register */
+#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */
+#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */
+#define NDDB 0x43100040 /* Data Controller Data Buffer */
+#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */
+#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */
+#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */
#define NDCR_SPARE_EN (0x1<<31)
#define NDCR_ECC_EN (0x1<<30)
#else /* CONFIG_CPU_MONAHANS */
-#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
+/* PXA2xx */
+
+#define MEMC_BASE 0x48000000 /* Base of Memory Controller */
#define MDCNFG_OFFSET 0x0
#define MDREFR_OFFSET 0x4
#define MSC0_OFFSET 0x8
#define MCIO1_OFFSET 0x3C
#define MDMRS_OFFSET 0x40
-#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
+#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */
#define MDCNFG_DE0 0x00000001
#define MDCNFG_DE1 0x00000002
#define MDCNFG_DE2 0x00010000
#define MDCNFG_DE3 0x00020000
#define MDCNFG_DWID0 0x00000004
-#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
-#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
-#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
-#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
-#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
-#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
-#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */
+#define MSC0 0x48000008 /* Static Memory Control Register 0 */
+#define MSC1 0x4800000C /* Static Memory Control Register 1 */
+#define MSC2 0x48000010 /* Static Memory Control Register 2 */
+#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */
+#define FLYCNFG 0x48000020
+#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */
+#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */
#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */
#if defined(CONFIG_PXA27X)
-#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
+#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
-#endif /* CONFIG_CPU_MONAHANS */
-
-/* Interrupt Controller */
-
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
-/* General Purpose I/O */
-
-#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
-#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */
-#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-/* Core Clock */
-
-#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
-
-#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC (1 << 22) /* Memory Controler */
-#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
-#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
-#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
-#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
-#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
-
-/* Memory controller */
-
-#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */
+#endif /* CONFIG_PXA27X */
/* LCD registers */
-#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
-#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
-#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
-#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
-#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
-#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
-#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
-#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
-#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
-#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
-#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
-#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
-#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
-#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
-#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
-#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
-#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
-#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
-#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
-#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
-#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
-#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
-#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
-
-#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
-#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
-#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
-#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
-#define CCR __REG(0x44000090) /* Cursor Control Register */
-
-#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
-#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
+#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
+#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */
+#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
+#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
+#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */
+#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */
+#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */
+#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */
+#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */
+#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */
+#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */
+#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */
+#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */
+#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */
+#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */
+
+#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */
+#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */
+#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */
+#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */
+#define CCR 0x44000090 /* Cursor Control Register */
+
+#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */
+#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */
#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
/* Keypad controller */
-#define KPC __REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
-#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */
-#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+#define KPC 0x41500000 /* Keypad Interface Control register */
+#define KPDK 0x41500008 /* Keypad Interface Direct Key register */
+#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */
+#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */
+#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */
+#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */
#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
#define KPASMKPx_SO (0x1 << 31)
#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR __REG(0x40F00034)
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
-#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4 __REG(0x40A00080) /* */
-#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
-#define OMCR4 __REG(0x40A000C0) /* */
+#define PSLR 0x40F00034
+#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */
+#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */
+#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */
+#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4 0x40A00080 /* */
+#define OSCR4 0x40A00040 /* OS Timer Counter Register */
+#define OMCR4 0x40A000C0 /* */
#endif /* CONFIG_PXA27X */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2440.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2440 User's manual Rev x.x
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS 3
+#define S3C24X0_SPI_CHANNELS 2
+
+/* S3C2440 only supports 512 Byte HW ECC */
+#define S3C2440_ECCSIZE 512
+#define S3C2440_ECCBYTES 3
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+ S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C24X0_USB_HOST_BASE 0x49000000
+#define S3C24X0_INTERRUPT_BASE 0x4A000000
+#define S3C24X0_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C24X0_LCD_BASE 0x4D000000
+#define S3C2440_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C24X0_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C24X0_I2C_BASE 0x54000000
+#define S3C24X0_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C24X0_RTC_BASE 0x57000000
+#define S3C2440_ADC_BASE 0x58000000
+#define S3C24X0_SPI_BASE 0x59000000
+#define S3C2440_SDI_BASE 0x5A000000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+{
+ return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
+{
+ return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+{
+ return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+
+#endif /*__S3C2440_H__*/
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
- u32 BWSCON;
- u32 BANKCON[8];
- u32 REFRESH;
- u32 BANKSIZE;
- u32 MRSRB6;
- u32 MRSRB7;
+ u32 bwscon;
+ u32 bankcon[8];
+ u32 refresh;
+ u32 banksize;
+ u32 mrsrb6;
+ u32 mrsrb7;
};
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
- u32 SRCPND;
- u32 INTMOD;
- u32 INTMSK;
- u32 PRIORITY;
- u32 INTPND;
- u32 INTOFFSET;
-#ifdef CONFIG_S3C2410
- u32 SUBSRCPND;
- u32 INTSUBMSK;
+ u32 srcpnd;
+ u32 intmod;
+ u32 intmsk;
+ u32 priority;
+ u32 intpnd;
+ u32 intoffset;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 subsrcpnd;
+ u32 intsubmsk;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
- u32 DISRC;
-#ifdef CONFIG_S3C2410
- u32 DISRCC;
+ u32 disrc;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 disrcc;
#endif
- u32 DIDST;
-#ifdef CONFIG_S3C2410
- u32 DIDSTC;
+ u32 didst;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 didstc;
#endif
- u32 DCON;
- u32 DSTAT;
- u32 DCSRC;
- u32 DCDST;
- u32 DMASKTRIG;
-#ifdef CONFIG_S3C2400
+ u32 dcon;
+ u32 dstat;
+ u32 dcsrc;
+ u32 dcdst;
+ u32 dmasktrig;
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
+ || defined(CONFIG_S3C2440)
u32 res[1];
#endif
-#ifdef CONFIG_S3C2410
- u32 res[7];
-#endif
};
struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
- u32 LOCKTIME;
- u32 MPLLCON;
- u32 UPLLCON;
- u32 CLKCON;
- u32 CLKSLOW;
- u32 CLKDIVN;
+ u32 locktime;
+ u32 mpllcon;
+ u32 upllcon;
+ u32 clkcon;
+ u32 clkslow;
+ u32 clkdivn;
+#if defined(CONFIG_S3C2440)
+ u32 camdivn;
+#endif
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
- u32 LCDCON1;
- u32 LCDCON2;
- u32 LCDCON3;
- u32 LCDCON4;
- u32 LCDCON5;
- u32 LCDSADDR1;
- u32 LCDSADDR2;
- u32 LCDSADDR3;
- u32 REDLUT;
- u32 GREENLUT;
- u32 BLUELUT;
+ u32 lcdcon1;
+ u32 lcdcon2;
+ u32 lcdcon3;
+ u32 lcdcon4;
+ u32 lcdcon5;
+ u32 lcdsaddr1;
+ u32 lcdsaddr2;
+ u32 lcdsaddr3;
+ u32 redlut;
+ u32 greenlut;
+ u32 bluelut;
u32 res[8];
- u32 DITHMODE;
- u32 TPAL;
-#ifdef CONFIG_S3C2410
- u32 LCDINTPND;
- u32 LCDSRCPND;
- u32 LCDINTMSK;
- u32 LPCSEL;
+ u32 dithmode;
+ u32 tpal;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ u32 lcdintpnd;
+ u32 lcdsrcpnd;
+ u32 lcdintmsk;
+ u32 lpcsel;
#endif
};
+#ifdef CONFIG_S3C2410
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
- u32 NFCONF;
- u32 NFCMD;
- u32 NFADDR;
- u32 NFDATA;
- u32 NFSTAT;
- u32 NFECC;
+ u32 nfconf;
+ u32 nfcmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfstat;
+ u32 nfecc;
+};
+#endif
+#ifdef CONFIG_S3C2440
+/* NAND FLASH (see S3C2440 manual chapter 6) */
+struct s3c2440_nand {
+ u32 nfconf;
+ u32 nfcont;
+ u32 nfcmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfeccd0;
+ u32 nfeccd1;
+ u32 nfeccd;
+ u32 nfstat;
+ u32 nfstat0;
+ u32 nfstat1;
};
+#endif
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
- u32 ULCON;
- u32 UCON;
- u32 UFCON;
- u32 UMCON;
- u32 UTRSTAT;
- u32 UERSTAT;
- u32 UFSTAT;
- u32 UMSTAT;
+ u32 ulcon;
+ u32 ucon;
+ u32 ufcon;
+ u32 umcon;
+ u32 utrstat;
+ u32 uerstat;
+ u32 ufstat;
+ u32 umstat;
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 UTXH;
+ u8 utxh;
u8 res2[3];
- u8 URXH;
+ u8 urxh;
#else /* Little Endian */
- u8 UTXH;
+ u8 utxh;
u8 res1[3];
- u8 URXH;
+ u8 urxh;
u8 res2[3];
#endif
- u32 UBRDIV;
+ u32 ubrdiv;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
- u32 TCNTB;
- u32 TCMPB;
- u32 TCNTO;
+ u32 tcntb;
+ u32 tcmpb;
+ u32 tcnto;
};
struct s3c24x0_timers {
- u32 TCFG0;
- u32 TCFG1;
- u32 TCON;
+ u32 tcfg0;
+ u32 tcfg1;
+ u32 tcon;
struct s3c24x0_timer ch[4];
- u32 TCNTB4;
- u32 TCNTO4;
+ u32 tcntb4;
+ u32 tcnto4;
};
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
#else /* little endian */
- u8 EP_FIFO_REG;
+ u8 ep_fifo_reg;
u8 res[3];
#endif
};
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res2[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res3[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res4[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res5[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res6[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
#else /* little endian */
- u8 EP_DMA_CON;
+ u8 ep_dma_con;
u8 res1[3];
- u8 EP_DMA_UNIT;
+ u8 ep_dma_unit;
u8 res2[3];
- u8 EP_DMA_FIFO;
+ u8 ep_dma_fifo;
u8 res3[3];
- u8 EP_DMA_TTC_L;
+ u8 ep_dma_ttc_l;
u8 res4[3];
- u8 EP_DMA_TTC_M;
+ u8 ep_dma_ttc_m;
u8 res5[3];
- u8 EP_DMA_TTC_H;
+ u8 ep_dma_ttc_h;
u8 res6[3];
#endif
};
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res2[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res3[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res4[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res5[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res6[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res7[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res8[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res9[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res10[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res11[3];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res12[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res13[7];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res14[3];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res16[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
#else /* little endian */
- u8 FUNC_ADDR_REG;
+ u8 func_addr_reg;
u8 res1[3];
- u8 PWR_REG;
+ u8 pwr_reg;
u8 res2[3];
- u8 EP_INT_REG;
+ u8 ep_int_reg;
u8 res3[15];
- u8 USB_INT_REG;
+ u8 usb_int_reg;
u8 res4[3];
- u8 EP_INT_EN_REG;
+ u8 ep_int_en_reg;
u8 res5[15];
- u8 USB_INT_EN_REG;
+ u8 usb_int_en_reg;
u8 res6[3];
- u8 FRAME_NUM1_REG;
+ u8 frame_num1_reg;
u8 res7[3];
- u8 FRAME_NUM2_REG;
+ u8 frame_num2_reg;
u8 res8[3];
- u8 INDEX_REG;
+ u8 index_reg;
u8 res9[7];
- u8 MAXP_REG;
+ u8 maxp_reg;
u8 res10[7];
- u8 EP0_CSR_IN_CSR1_REG;
+ u8 ep0_csr_in_csr1_reg;
u8 res11[3];
- u8 IN_CSR2_REG;
+ u8 in_csr2_reg;
u8 res12[3];
- u8 OUT_CSR1_REG;
+ u8 out_csr1_reg;
u8 res13[7];
- u8 OUT_CSR2_REG;
+ u8 out_csr2_reg;
u8 res14[3];
- u8 OUT_FIFO_CNT1_REG;
+ u8 out_fifo_cnt1_reg;
u8 res15[3];
- u8 OUT_FIFO_CNT2_REG;
+ u8 out_fifo_cnt2_reg;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
- u32 WTCON;
- u32 WTDAT;
- u32 WTCNT;
+ u32 wtcon;
+ u32 wtdat;
+ u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
- u32 IICCON;
- u32 IICSTAT;
- u32 IICADD;
- u32 IICDS;
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
};
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
- u16 IISCON;
+ u16 iiscon;
u16 res2;
- u16 IISMOD;
+ u16 iismod;
u16 res3;
- u16 IISPSR;
+ u16 iispsr;
u16 res4;
- u16 IISFCON;
+ u16 iisfcon;
u16 res5;
- u16 IISFIFO;
+ u16 iisfifo;
#else /* little endian */
- u16 IISCON;
+ u16 iiscon;
u16 res1;
- u16 IISMOD;
+ u16 iismod;
u16 res2;
- u16 IISPSR;
+ u16 iispsr;
u16 res3;
- u16 IISFCON;
+ u16 iisfcon;
u16 res4;
- u16 IISFIFO;
+ u16 iisfifo;
u16 res5;
#endif
};
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
- u32 PACON;
- u32 PADAT;
+ u32 pacon;
+ u32 padat;
- u32 PBCON;
- u32 PBDAT;
- u32 PBUP;
+ u32 pbcon;
+ u32 pbdat;
+ u32 pbup;
- u32 PCCON;
- u32 PCDAT;
- u32 PCUP;
+ u32 pccon;
+ u32 pcdat;
+ u32 pcup;
- u32 PDCON;
- u32 PDDAT;
- u32 PDUP;
+ u32 pdcon;
+ u32 pddat;
+ u32 pdup;
- u32 PECON;
- u32 PEDAT;
- u32 PEUP;
+ u32 pecon;
+ u32 pedat;
+ u32 peup;
- u32 PFCON;
- u32 PFDAT;
- u32 PFUP;
+ u32 pfcon;
+ u32 pfdat;
+ u32 pfup;
- u32 PGCON;
- u32 PGDAT;
- u32 PGUP;
+ u32 pgcon;
+ u32 pgdat;
+ u32 pgup;
- u32 OPENCR;
+ u32 opencr;
- u32 MISCCR;
- u32 EXTINT;
+ u32 misccr;
+ u32 extint;
#endif
#ifdef CONFIG_S3C2410
- u32 GPACON;
- u32 GPADAT;
+ u32 gpacon;
+ u32 gpadat;
+ u32 res1[2];
+ u32 gpbcon;
+ u32 gpbdat;
+ u32 gpbup;
+ u32 res2;
+ u32 gpccon;
+ u32 gpcdat;
+ u32 gpcup;
+ u32 res3;
+ u32 gpdcon;
+ u32 gpddat;
+ u32 gpdup;
+ u32 res4;
+ u32 gpecon;
+ u32 gpedat;
+ u32 gpeup;
+ u32 res5;
+ u32 gpfcon;
+ u32 gpfdat;
+ u32 gpfup;
+ u32 res6;
+ u32 gpgcon;
+ u32 gpgdat;
+ u32 gpgup;
+ u32 res7;
+ u32 gphcon;
+ u32 gphdat;
+ u32 gphup;
+ u32 res8;
+
+ u32 misccr;
+ u32 dclkcon;
+ u32 extint0;
+ u32 extint1;
+ u32 extint2;
+ u32 eintflt0;
+ u32 eintflt1;
+ u32 eintflt2;
+ u32 eintflt3;
+ u32 eintmask;
+ u32 eintpend;
+ u32 gstatus0;
+ u32 gstatus1;
+ u32 gstatus2;
+ u32 gstatus3;
+ u32 gstatus4;
+#endif
+#if defined(CONFIG_S3C2440)
+ u32 gpacon;
+ u32 gpadat;
u32 res1[2];
- u32 GPBCON;
- u32 GPBDAT;
- u32 GPBUP;
+ u32 gpbcon;
+ u32 gpbdat;
+ u32 gpbup;
u32 res2;
- u32 GPCCON;
- u32 GPCDAT;
- u32 GPCUP;
+ u32 gpccon;
+ u32 gpcdat;
+ u32 gpcup;
u32 res3;
- u32 GPDCON;
- u32 GPDDAT;
- u32 GPDUP;
+ u32 gpdcon;
+ u32 gpddat;
+ u32 gpdup;
u32 res4;
- u32 GPECON;
- u32 GPEDAT;
- u32 GPEUP;
+ u32 gpecon;
+ u32 gpedat;
+ u32 gpeup;
u32 res5;
- u32 GPFCON;
- u32 GPFDAT;
- u32 GPFUP;
+ u32 gpfcon;
+ u32 gpfdat;
+ u32 gpfup;
u32 res6;
- u32 GPGCON;
- u32 GPGDAT;
- u32 GPGUP;
+ u32 gpgcon;
+ u32 gpgdat;
+ u32 gpgup;
u32 res7;
- u32 GPHCON;
- u32 GPHDAT;
- u32 GPHUP;
+ u32 gphcon;
+ u32 gphdat;
+ u32 gphup;
u32 res8;
- u32 MISCCR;
- u32 DCLKCON;
- u32 EXTINT0;
- u32 EXTINT1;
- u32 EXTINT2;
- u32 EINTFLT0;
- u32 EINTFLT1;
- u32 EINTFLT2;
- u32 EINTFLT3;
- u32 EINTMASK;
- u32 EINTPEND;
- u32 GSTATUS0;
- u32 GSTATUS1;
- u32 GSTATUS2;
- u32 GSTATUS3;
- u32 GSTATUS4;
+ u32 misccr;
+ u32 dclkcon;
+ u32 extint0;
+ u32 extint1;
+ u32 extint2;
+ u32 eintflt0;
+ u32 eintflt1;
+ u32 eintflt2;
+ u32 eintflt3;
+ u32 eintmask;
+ u32 eintpend;
+ u32 gstatus0;
+ u32 gstatus1;
+ u32 gstatus2;
+ u32 gstatus3;
+ u32 gstatus4;
+
+ u32 res9;
+ u32 dsc0;
+ u32 dsc1;
+ u32 mslcon;
+ u32 gpjcon;
+ u32 gpjdat;
+ u32 gpjup;
+ u32 res10;
#endif
};
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
- u8 RTCCON;
+ u8 rtccon;
u8 res2[3];
- u8 TICNT;
+ u8 ticnt;
u8 res3[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res4[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res5[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res6[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res7[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res8[3];
- u8 ALMMON;
+ u8 almmon;
u8 res9[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res10[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res11[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res12[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res13[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res14[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res15[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res16[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res17[3];
- u8 BCDYEAR;
+ u8 bcdyear;
#else /* little endian */
u8 res0[64];
- u8 RTCCON;
+ u8 rtccon;
u8 res1[3];
- u8 TICNT;
+ u8 ticnt;
u8 res2[11];
- u8 RTCALM;
+ u8 rtcalm;
u8 res3[3];
- u8 ALMSEC;
+ u8 almsec;
u8 res4[3];
- u8 ALMMIN;
+ u8 almmin;
u8 res5[3];
- u8 ALMHOUR;
+ u8 almhour;
u8 res6[3];
- u8 ALMDATE;
+ u8 almdate;
u8 res7[3];
- u8 ALMMON;
+ u8 almmon;
u8 res8[3];
- u8 ALMYEAR;
+ u8 almyear;
u8 res9[3];
- u8 RTCRST;
+ u8 rtcrst;
u8 res10[3];
- u8 BCDSEC;
+ u8 bcdsec;
u8 res11[3];
- u8 BCDMIN;
+ u8 bcdmin;
u8 res12[3];
- u8 BCDHOUR;
+ u8 bcdhour;
u8 res13[3];
- u8 BCDDATE;
+ u8 bcddate;
u8 res14[3];
- u8 BCDDAY;
+ u8 bcdday;
u8 res15[3];
- u8 BCDMON;
+ u8 bcdmon;
u8 res16[3];
- u8 BCDYEAR;
+ u8 bcdyear;
u8 res17[3];
#endif
};
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
- u32 ADCCON;
- u32 ADCDAT;
+ u32 adccon;
+ u32 adcdat;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
- u32 ADCCON;
- u32 ADCTSC;
- u32 ADCDLY;
- u32 ADCDAT0;
- u32 ADCDAT1;
+ u32 adccon;
+ u32 adctsc;
+ u32 adcdly;
+ u32 adcdat0;
+ u32 adcdat1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
- u8 SPCON;
+ u8 spcon;
u8 res1[3];
- u8 SPSTA;
+ u8 spsta;
u8 res2[3];
- u8 SPPIN;
+ u8 sppin;
u8 res3[3];
- u8 SPPRE;
+ u8 sppre;
u8 res4[3];
- u8 SPTDAT;
+ u8 sptdat;
u8 res5[3];
- u8 SPRDAT;
+ u8 sprdat;
u8 res6[3];
u8 res7[16];
};
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
- u8 MMCON;
+ u8 mmcon;
u8 res2[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res3[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res4[3];
- u8 MMSTA;
+ u8 mmsta;
u16 res5;
- u16 MMFSTA;
+ u16 mmfsta;
u8 res6[3];
- u8 MMPRE;
+ u8 mmpre;
u16 res7;
- u16 MMLEN;
+ u16 mmlen;
u8 res8[3];
- u8 MMCR7;
- u32 MMRSP[4];
+ u8 mmcr7;
+ u32 mmrsp[4];
u8 res9[3];
- u8 MMCMD0;
- u32 MMCMD1;
+ u8 mmcmd0;
+ u32 mmcmd1;
u16 res10;
- u16 MMCR16;
+ u16 mmcr16;
u8 res11[3];
- u8 MMDAT;
+ u8 mmdat;
#else
- u8 MMCON;
+ u8 mmcon;
u8 res1[3];
- u8 MMCRR;
+ u8 mmcrr;
u8 res2[3];
- u8 MMFCON;
+ u8 mmfcon;
u8 res3[3];
- u8 MMSTA;
+ u8 mmsta;
u8 res4[3];
- u16 MMFSTA;
+ u16 mmfsta;
u16 res5;
- u8 MMPRE;
+ u8 mmpre;
u8 res6[3];
- u16 MMLEN;
+ u16 mmlen;
u16 res7;
- u8 MMCR7;
+ u8 mmcr7;
u8 res8[3];
- u32 MMRSP[4];
- u8 MMCMD0;
+ u32 mmrsp[4];
+ u8 mmcmd0;
u8 res9[3];
- u32 MMCMD1;
- u16 MMCR16;
+ u32 mmcmd1;
+ u16 mmcr16;
u16 res10;
- u8 MMDAT;
+ u8 mmdat;
u8 res11[3];
#endif
};
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
- u32 SDICON;
- u32 SDIPRE;
- u32 SDICARG;
- u32 SDICCON;
- u32 SDICSTA;
- u32 SDIRSP0;
- u32 SDIRSP1;
- u32 SDIRSP2;
- u32 SDIRSP3;
- u32 SDIDTIMER;
- u32 SDIBSIZE;
- u32 SDIDCON;
- u32 SDIDCNT;
- u32 SDIDSTA;
- u32 SDIFSTA;
+ u32 sdicon;
+ u32 sdipre;
+ u32 sdicarg;
+ u32 sdiccon;
+ u32 sdicsta;
+ u32 sdirsp0;
+ u32 sdirsp1;
+ u32 sdirsp2;
+ u32 sdirsp3;
+ u32 sdidtimer;
+ u32 sdibsize;
+ u32 sdidcon;
+ u32 sdidcnt;
+ u32 sdidsta;
+ u32 sdifsta;
#ifdef __BIG_ENDIAN
u8 res[3];
- u8 SDIDAT;
+ u8 sdidat;
#else
- u8 SDIDAT;
+ u8 sdidat;
u8 res[3];
#endif
- u32 SDIIMSK;
+ u32 sdiimsk;
};
#endif /*__S3C24X0_H__*/
#include <asm/arch/s3c2400.h>
#elif defined CONFIG_S3C2410
#include <asm/arch/s3c2410.h>
+#elif defined CONFIG_S3C2440
+ #include <asm/arch/s3c2440.h>
#else
#error Please define the s3c24x0 cpu type
#endif
#define HPLL 3
#define VPLL 4
-void s5p_clock_init(void);
-
-extern unsigned long (*get_pll_clk)(int pllreg);
-extern unsigned long (*get_arm_clk)(void);
-extern unsigned long (*get_pwm_clk)(void);
-extern unsigned long (*get_uart_clk)(int dev_index);
-extern unsigned long (*get_lcd_clk)(void);
-extern void (*set_mmc_clk)(int dev_index, unsigned int div);
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_lcd_clk(void);
+void set_mmc_clk(int dev_index, unsigned int div);
#endif
#define HPLL 3
#define VPLL 4
-void s5p_clock_init(void);
-
-extern unsigned long (*get_pll_clk)(int pllreg);
-extern unsigned long (*get_arm_clk)(void);
-extern unsigned long (*get_pwm_clk)(void);
-extern unsigned long (*get_uart_clk)(int dev_index);
-extern unsigned long (*get_lcd_clk)(void);
-extern void (*set_mmc_clk)(int dev_index, unsigned int div);
-extern int (*set_lcd_clk)(const unsigned int dev_index,
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_lcd_clk(void);
+void set_mmc_clk(int dev_index, unsigned int div);
+int set_lcd_clk(const unsigned int dev_index,
const unsigned int pclk_name, const unsigned int div);
-
#endif
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-/* Relocation to SDRAM works on all ARM boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-#endif
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
#ifdef CONFIG_FSL_ESDHC
unsigned long sdhc_clk;
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#ifdef CONFIG_AT91FAMILY
+ /* "static data" needed by at91's clock.c */
+ unsigned long cpu_clk_rate_hz;
+ unsigned long main_clk_rate_hz;
+ unsigned long mck_rate_hz;
+ unsigned long plla_rate_hz;
+ unsigned long pllb_rate_hz;
+ unsigned long at91_pllb_usb_init;
+#endif
+#ifdef CONFIG_ARM
+ /* "static data" needed by most of timer.c on ARM platforms */
+ unsigned long timer_rate_hz;
+ unsigned long tbl;
+ unsigned long tbu;
+ unsigned long long timer_reset_value;
+ unsigned long lastinc;
+#endif
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
unsigned long mon_len; /* monitor len */
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
unsigned long tlb_addr;
#endif
-#endif
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
} gd_t;
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
/* Size defintions
* Copyright (C) ARM Limited 1998. All rights reserved.
*/
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
+#define SZ_31M 0x01F00000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define _U_BOOT_ARM_H_ 1
/* for the following variables, see start.S */
-extern ulong _bss_start; /* code + data end == BSS start */
-extern ulong _bss_end; /* BSS end */
+extern ulong _bss_start_ofs; /* BSS start relative to _start */
+extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-extern ulong _armboot_start; /* code start */
-#else
extern ulong _TEXT_BASE; /* code start */
-extern ulong _datarel_start;
-extern ulong _datarelrolocal_start;
-extern ulong _datarellocal_start;
-extern ulong _datarelro_start;
+extern ulong _datarel_start_ofs;
+extern ulong _datarelrolocal_start_ofs;
+extern ulong _datarellocal_start_ofs;
+extern ulong _datarelro_start_ofs;
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
-#endif
/* cpu/.../cpu.c */
int cpu_init(void);
/* board/.../... */
int board_init(void);
int dram_init (void);
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
void dram_init_banksize (void);
-#endif
void setup_serial_tag (struct tag **params);
void setup_revision_tag (struct tag **params);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
-LIBGCC = $(obj)libgcc.a
+LIB = $(obj)lib$(ARCH).o
+LIBGCC = $(obj)libgcc.o
GLSOBJS += _ashldi3.o
GLSOBJS += _ashrdi3.o
LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \
$(addprefix $(obj),$(GLCOBJS))
-# Always build libarm.a
+# Always build libarm.o
TARGETS := $(LIB)
# Build private libgcc only when asked for
all: $(TARGETS)
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
$(LIBGCC): $(obj).depend $(LGOBJS)
- $(AR) $(ARFLAGS) $@ $(LGOBJS)
+ $(call cmd_link_o_target, $(LGOBJS))
#########################################################################
char tmp[64]; /* long enough for environment variables */
int i = getenv_f("baudrate", tmp, sizeof (tmp));
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
gd->baudrate = (i > 0)
-#else
- gd->bd->bi_baudrate = gd->baudrate = (i > 0)
-#endif
? (int) simple_strtoul (tmp, NULL, 10)
: CONFIG_BAUDRATE;
{
printf ("\n\n%s\n\n", version_string);
debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
_TEXT_BASE,
-#else
- _armboot_start,
-#endif
- _bss_start, _bss_end);
+ _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
#ifdef CONFIG_MODEM_SUPPORT
debug ("Modem Support enabled\n");
#endif
return (0);
}
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-#ifndef CONFIG_SYS_NO_FLASH
-static void display_flash_config (ulong size)
-{
- puts ("Flash: ");
- print_size (size, "\n");
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-#endif
-
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
static int init_func_i2c (void)
{
int print_cpuinfo (void);
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_ARCH_CPU_INIT)
- arch_cpu_init, /* basic arch cpu dependent setup */
-#endif
- board_init, /* basic board dependent setup */
-#if defined(CONFIG_USE_IRQ)
- interrupt_init, /* set up exceptions */
-#endif
- timer_init, /* initialize timer */
-#ifdef CONFIG_FSL_ESDHC
- get_clocks,
-#endif
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f, /* stage 1 init of console */
- display_banner, /* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
- print_cpuinfo, /* display cpu info (and speed) */
-#endif
-#if defined(CONFIG_DISPLAY_BOARDINFO)
- checkboard, /* display board info */
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
- init_func_i2c,
-#endif
- dram_init, /* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
- arm_pci_init,
-#endif
- display_dram_config,
- NULL,
-};
-
-void start_armboot (void)
-{
- init_fnc_t **init_fnc_ptr;
- char *s;
-#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
- unsigned long addr;
-#endif
-
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
-
- memset ((void*)gd, 0, sizeof (gd_t));
- gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
- memset (gd->bd, 0, sizeof (bd_t));
-
- gd->flags |= GD_FLG_RELOC;
-
- monitor_flash_len = _bss_start - _armboot_start;
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0) {
- hang ();
- }
- }
-
- /* armboot_start is defined in the board-specific linker script */
- mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
- /* configure available FLASH banks */
- display_flash_config (flash_init ());
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#ifdef CONFIG_VFD
-# ifndef PAGE_SIZE
-# define PAGE_SIZE 4096
-# endif
- /*
- * reserve memory for VFD display (always full pages)
- */
- /* bss_end is defined in the board-specific linker script */
- addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
- vfd_setmem (addr);
- gd->fb_base = addr;
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_LCD
- /* board init may have inited fb_base */
- if (!gd->fb_base) {
-# ifndef PAGE_SIZE
-# define PAGE_SIZE 4096
-# endif
- /*
- * reserve memory for LCD display (always full pages)
- */
- /* bss_end is defined in the board-specific linker script */
- addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
- lcd_setmem (addr);
- gd->fb_base = addr;
- }
-#endif /* CONFIG_LCD */
-
-#if defined(CONFIG_CMD_NAND)
- puts ("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- onenand_init();
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
- AT91F_DataflashInit();
- dataflash_print_info();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-/*
- * MMC initialization is called before relocating env.
- * Thus It is required that operations like pin multiplexer
- * be put in board_init.
- */
- puts ("MMC: ");
- mmc_initialize (gd->bd);
-#endif
-
- /* initialize environment */
- env_relocate ();
-
-#ifdef CONFIG_VFD
- /* must do this after the framebuffer is allocated */
- drv_vfd_init();
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_SERIAL_MULTI
- serial_initialize();
-#endif
-
- /* IP Address */
- gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
- stdio_init (); /* get the devices list going. */
-
- jumptable_init ();
-
-#if defined(CONFIG_API)
- /* Initialize API */
- api_init ();
-#endif
-
- console_init_r (); /* fully init console as a device */
-
-#if defined(CONFIG_ARCH_MISC_INIT)
- /* miscellaneous arch dependent initialisations */
- arch_misc_init ();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
- /* miscellaneous platform dependent initialisations */
- misc_init_r ();
-#endif
-
- /* enable exceptions */
- enable_interrupts ();
-
- /* Perform network card initialisation if necessary */
-#ifdef CONFIG_DRIVER_TI_EMAC
- /* XXX: this needs to be moved to board init */
-extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
- if (getenv ("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- davinci_eth_set_mac_addr(enetaddr);
- }
-#endif
-
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
- /* XXX: this needs to be moved to board init */
- if (getenv ("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- smc_set_mac_addr(enetaddr);
- }
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
- /* Initialize from environment */
- if ((s = getenv ("loadaddr")) != NULL) {
- load_addr = simple_strtoul (s, NULL, 16);
- }
-#if defined(CONFIG_CMD_NET)
- if ((s = getenv ("bootfile")) != NULL) {
- copy_filename (BootFile, s, sizeof (BootFile));
- }
-#endif
-
-#ifdef BOARD_LATE_INIT
- board_late_init ();
-#endif
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-#if defined(CONFIG_NET_MULTI)
- puts ("Net: ");
-#endif
- eth_initialize(gd->bd);
-#if defined(CONFIG_RESET_PHY_R)
- debug ("Reset Ethernet PHY\n");
- reset_phy();
-#endif
-#endif
- /* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;) {
- main_loop ();
- }
-
- /* NOTREACHED - no way out of command loop except booting */
-}
-#else
void __dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
ulong addr, addr_sp;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_SP_ADDR);
+ gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset ((void*)gd, 0, sizeof (gd_t));
- gd->mon_len = _bss_end - _TEXT_BASE;
+ gd->mon_len = _bss_end_ofs;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
addr_sp -= sizeof (bd_t);
bd = (bd_t *) addr_sp;
gd->bd = bd;
-
debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
addr_sp -= sizeof (gd_t);
*
************************************************************************
*/
+
void board_init_r (gd_t *id, ulong dest_addr)
{
char *s;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
- extern void malloc_bin_reloc (void);
-#if defined(CONFIG_CMD_BMP)
- extern void bmp_reloc(void);
-#endif
-#if defined(CONFIG_CMD_I2C)
- extern void i2c_reloc(void);
-#endif
-#if defined(CONFIG_CMD_ONENAND)
- extern void onenand_reloc(void);
-#endif
-#endif
gd = id;
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
- monitor_flash_len = _bss_start - _TEXT_BASE;
+ monitor_flash_len = _bss_start_ofs;
debug ("monitor flash len: %08lX\n", monitor_flash_len);
-
- /* Workaround */
- arch_cpu_init();
-
board_init(); /* Setup chipselects */
#ifdef CONFIG_SERIAL_MULTI
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
- /*
- * We have to relocate the command table manually
- */
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#if defined(CONFIG_CMD_BMP)
- bmp_reloc();
-#endif
-#if defined(CONFIG_CMD_I2C)
- i2c_reloc();
-#endif
-#if defined(CONFIG_CMD_ONENAND)
- onenand_reloc();
-#endif
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
-
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs ();
#endif
#ifdef CONFIG_POST
post_output_backlog ();
-#ifndef CONFIG_RELOC_FIXUP_WORKS
- post_reloc ();
-#endif
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
- malloc_bin_reloc ();
-#endif
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("FLASH: ");
#endif
#ifdef CONFIG_GENERIC_MMC
- puts ("MMC: ");
- mmc_initialize (gd->bd);
+ puts("MMC: ");
+ mmc_initialize(bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
enable_interrupts ();
/* Perform network card initialisation if necessary */
-#ifdef CONFIG_DRIVER_TI_EMAC
- /* XXX: this needs to be moved to board init */
-extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
- if (getenv ("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- davinci_eth_set_mac_addr(enetaddr);
- }
-#endif
-
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv ("ethaddr")) {
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
-
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
/* NOTREACHED - no way out of command loop except booting */
}
-#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
void hang (void)
{
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+static ulong get_sp(void);
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_linux_fdt(int machid, bootm_headers_t *images);
+#endif
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp;
+
+ /*
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
+ */
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 1K to be safe */
+ sp -= 1024;
+ lmb_reserve(lmb, sp,
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+}
+
+static void announce_and_cleanup(void)
+{
+#ifdef CONFIG_TEST_BOOTTIME
+ /* Checking for boot time: It will be deleted */
+ printf("boot time: %d ms\n\n", (0xffffffff - readl(0x1005000c)) / 20 / 1000);
+#endif
+
+ printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+ cleanup_before_linux();
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
bd_t *bd = gd->bd;
char *s;
int machid = bd->bi_arch_number;
- void (*theKernel)(int zero, int arch, uint params);
+ void (*kernel_entry)(int zero, int arch, uint params);
#ifdef CONFIG_CMDLINE_TAG
char *commandline = getenv ("bootargs");
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
- theKernel = (void (*)(int, int, uint))images->ep;
-
s = getenv ("machid");
if (s) {
machid = simple_strtoul (s, NULL, 16);
show_boot_progress (15);
+#ifdef CONFIG_OF_LIBFDT
+ if (images->ft_len)
+ return bootm_linux_fdt(machid, images);
+#endif
+
+ kernel_entry = (void (*)(int, int, uint))images->ep;
+
debug ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
+ (ulong) kernel_entry);
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
defined (CONFIG_CMDLINE_TAG) || \
if (images->rd_start && images->rd_end)
setup_initrd_tag (bd, images->rd_start, images->rd_end);
#endif
- setup_end_tag (bd);
+ setup_end_tag(bd);
#endif
- /* we assume that the kernel is in place */
- printf ("\nStarting kernel ...\n\n");
+ announce_and_cleanup();
-#ifdef CONFIG_USB_DEVICE
- {
- extern void udc_disconnect (void);
- udc_disconnect ();
+ kernel_entry(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+static int fixup_memory_node(void *blob)
+{
+ bd_t *bd = gd->bd;
+ int bank;
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = bd->bi_dram[bank].start;
+ size[bank] = bd->bi_dram[bank].size;
}
-#endif
- cleanup_before_linux ();
+ return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
-#ifdef CONFIG_TEST_BOOTTIME
- /* Checking for boot time: It will be deleted */
- printf("boot time: %d ms\n\n", (0xffffffff - readl(0x1005000c)) / 20 / 1000);
-#endif
+static int bootm_linux_fdt(int machid, bootm_headers_t *images)
+{
+ ulong rd_len;
+ void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
+ ulong bootmap_base = getenv_bootm_low();
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ ulong *initrd_start = &images->initrd_start;
+ ulong *initrd_end = &images->initrd_end;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ kernel_entry = (void (*)(int, int, void *))images->ep;
- theKernel (0, machid, bd->bi_boot_params);
+ rd_len = images->rd_end - images->rd_start;
+ ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+ initrd_start, initrd_end);
+ if (ret)
+ return ret;
+
+ ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+ fdt_chosen(*of_flat_tree, 1);
+
+ fixup_memory_node(*of_flat_tree);
+
+ fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ announce_and_cleanup();
+
+ kernel_entry(0, machid, *of_flat_tree);
/* does not return */
return 1;
}
-
+#endif
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
defined (CONFIG_CMDLINE_TAG) || \
params->hdr.size = 0;
}
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
asm volatile("" : : : "memory");
}
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
static inline void dram_bank_mmu_setup(int bank)
{
u32 *page_table = (u32 *)gd->tlb_addr;
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
-#endif
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
u32 *page_table = (u32 *)gd->tlb_addr;
-#else
- static u32 __attribute__((aligned(16384))) page_table[4096];
- bd_t *bd = gd->bd;
- int j;
-#endif
int i;
u32 reg;
for (i = 0; i < 4096; i++)
page_table[i] = i << 20 | (3 << 10) | 0x12;
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
}
-#else
- /* Then, enable cacheable and bufferable for RAM only */
- for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
- for (i = bd->bi_dram[j].start >> 20;
- i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
- i++) {
- page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
- }
- }
-#endif
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
/*
* setup up stacks if necessary
*/
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
IRQ_STACK_START = gd->irq_sp - 4;
IRQ_STACK_START_IN = gd->irq_sp + 8;
-#else
- IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-#endif
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
return arch_interrupt_init();
return (old & 0x80) == 0;
}
#else
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int interrupt_init (void)
{
/*
return 0;
}
-#endif
void enable_interrupts (void)
{
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(CPU).a
+LIB := $(obj)lib$(CPU).o
START-y += start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(SOC).a
+LIB := $(obj)lib$(SOC).o
COBJS := portmux.o clk.o mmu.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
#########################################################################
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/ptrace.h>
#include <asm/sysreg.h>
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_NEEDS_MANUAL_RELOC
+
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y += memset.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
extern char * env_name_spec;
#endif
char *s;
- cmd_tbl_t *cmdtp;
bd_t *bd;
gd = new_gd;
monitor_flash_len = _edata - _text;
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE
STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
-CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
-CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
-CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE)))
PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
LDFLAGS += --gc-sections -m elf32bfin
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-ifneq (,$(CONFIG_BFIN_CPU))
+PLATFORM_CPPFLAGS += -DBFIN_CPU='"$(CONFIG_BFIN_CPU)"'
PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
-endif
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
ALL += $(obj)u-boot.ldr
endif
ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
+HOSTCFLAGS_NOPED += \
+ $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
+ | awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
else
CREATE_LDR_ENV =
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
EXTRA :=
CEXTRA := initcode.o
COBJS-y += traps.o
COBJS-$(CONFIG_HW_WATCHDOG) += watchdog.o
-ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-COBJS-y += initcode.o
-endif
-
SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
EXTRA := $(addprefix $(obj),$(EXTRA))
all: $(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
$(OBJS): $(obj)bootrom-asm-offsets.h
$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
#include <common.h>
#include <command.h>
+#include <linux/ctype.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
/* grab the [p]<port> portion */
ulong port_base;
- if (*str_pin == 'p') ++str_pin;
- switch (*str_pin) {
+ if (tolower(*str_pin) == 'p') ++str_pin;
+ switch (tolower(*str_pin)) {
#ifdef GPIO_PA0
case 'a': port_base = GPIO_PA0; break;
#endif
gpio_request(gpio, "cmd_gpio");
/* finally, let's do it: set direction and exec command */
+ ulong value;
if (sub_cmd == GPIO_INPUT) {
gpio_direction_input(gpio);
- printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin);
- return 0;
- }
-
- ulong value;
- switch (sub_cmd) {
- case GPIO_SET: value = 1; break;
- case GPIO_CLEAR: value = 0; break;
- case GPIO_TOGGLE: value = !gpio_get_value(gpio); break;
- default: goto show_usage;
+ value = gpio_get_value(gpio);
+ } else {
+ switch (sub_cmd) {
+ case GPIO_SET: value = 1; break;
+ case GPIO_CLEAR: value = 0; break;
+ case GPIO_TOGGLE: value = !gpio_get_value(gpio); break;
+ default: goto show_usage;
+ }
+ gpio_direction_output(gpio, value);
}
- gpio_direction_output(gpio, value);
printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n",
pin, *str_pin, gpio, value);
gpio_free(gpio);
- return 0;
+ return value;
}
U_BOOT_CMD(gpio, 3, 0, do_gpio,
- "set/clear/toggle gpio output pins",
- "<set|clear|toggle> <port><pin>\n"
- " - set/clear/toggle the specified pin (e.g. PF10)");
+ "input/set/clear/toggle gpio output pins",
+ "<
input|set|clear|toggle> <port><pin>\n"
+ " - input/set/clear/toggle the specified pin (e.g. PF10)");
/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
ADI_SYSCTRL_VALUES memory_settings;
- uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
+ uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
+ if (!ANOMALY_05000440)
+ actions |= SYSCTRL_PLLDIV;
if (CONFIG_HAS_VR) {
actions |= SYSCTRL_VRCTL;
if (CONFIG_VR_CTL_VAL & FREQ_MASK)
serial_putc('e');
bfrom_SysControl(actions, &memory_settings, NULL);
serial_putc('f');
+ if (ANOMALY_05000440)
+ bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
#if ANOMALY_05000432
bfin_write_SIC_IWR1(-1);
#endif
#include <asm/blackfin.h>
#include <asm/mach-common/bits/uart.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_UART_CONSOLE
#include "serial.h"
*/
void serial_setbrg(void)
{
- DECLARE_GLOBAL_DATA_PTR;
serial_set_baud(gd->baudrate);
}
#ifndef __MACH_CDEF_BLACKFIN__
#define __MACH_CDEF_BLACKFIN__
+#ifdef __ADSPBF512__
+# include "mach-bf518/BF512_cdef.h"
+#endif
+#ifdef __ADSPBF514__
+# include "mach-bf518/BF514_cdef.h"
+#endif
+#ifdef __ADSPBF516__
+# include "mach-bf518/BF516_cdef.h"
+#endif
+#ifdef __ADSPBF518__
+# include "mach-bf518/BF518_cdef.h"
+#endif
#ifdef __ADSPBF522__
# include "mach-bf527/BF522_cdef.h"
#endif
#ifdef __ADSPBF537__
# include "mach-bf537/BF537_cdef.h"
#endif
-#ifdef __ADSPBF541__
-# include "mach-bf548/BF541_cdef.h"
+#ifdef __ADSPBF538__
+# include "mach-bf538/BF538_cdef.h"
+#endif
+#ifdef __ADSPBF539__
+# include "mach-bf538/BF539_cdef.h"
#endif
#ifdef __ADSPBF542__
# include "mach-bf548/BF542_cdef.h"
#ifndef __MACH_DEF_BLACKFIN__
#define __MACH_DEF_BLACKFIN__
+#ifdef __ADSPBF512__
+# include "mach-bf518/BF512_def.h"
+# include "mach-bf518/anomaly.h"
+# include "mach-bf518/def_local.h"
+#endif
+#ifdef __ADSPBF514__
+# include "mach-bf518/BF514_def.h"
+# include "mach-bf518/anomaly.h"
+# include "mach-bf518/def_local.h"
+#endif
+#ifdef __ADSPBF516__
+# include "mach-bf518/BF516_def.h"
+# include "mach-bf518/anomaly.h"
+# include "mach-bf518/def_local.h"
+#endif
+#ifdef __ADSPBF518__
+# include "mach-bf518/BF518_def.h"
+# include "mach-bf518/anomaly.h"
+# include "mach-bf518/def_local.h"
+#endif
#ifdef __ADSPBF522__
# include "mach-bf527/BF522_def.h"
# include "mach-bf527/anomaly.h"
# include "mach-bf537/anomaly.h"
# include "mach-bf537/def_local.h"
#endif
-#ifdef __ADSPBF541__
-# include "mach-bf548/BF541_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
+#ifdef __ADSPBF538__
+# include "mach-bf538/BF538_def.h"
+# include "mach-bf538/anomaly.h"
+# include "mach-bf538/def_local.h"
+#endif
+#ifdef __ADSPBF539__
+# include "mach-bf538/BF539_def.h"
+# include "mach-bf538/anomaly.h"
+# include "mach-bf538/def_local.h"
#endif
#ifdef __ADSPBF542__
# include "mach-bf548/BF542_def.h"
#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
#define __ASM_BLACKFIN_CONFIG_POST_H__
-/* Sanity check CONFIG_BFIN_CPU */
-#ifndef CONFIG_BFIN_CPU
-# error CONFIG_BFIN_CPU: your board config needs to define this
-#endif
+/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
+#include <asm-offsets.h>
#ifndef CONFIG_BFIN_SCRATCH_REG
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
-/* Relocation to SDRAM works on all Blackfin boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#endif
-#ifndef CONFIG_SYS_GBL_DATA_SIZE
-# define CONFIG_SYS_GBL_DATA_SIZE (128)
-#endif
#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#endif
#ifndef CONFIG_STACKBASE
# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
--- /dev/null
+/*
+ * dma.h - Blackfin DMA defines/structures/etc...
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_DMA_H_
+#define _BLACKFIN_DMA_H_
+
+#include <asm/mach-common/bits/dma.h>
+
+struct dmasg_large {
+ void *next_desc_addr;
+ unsigned long start_addr;
+ unsigned short cfg;
+ unsigned short x_count;
+ short x_modify;
+ unsigned short y_count;
+ short y_modify;
+} __attribute__((packed));
+
+struct dmasg {
+ unsigned long start_addr;
+ unsigned short cfg;
+ unsigned short x_count;
+ short x_modify;
+ unsigned short y_count;
+ short y_modify;
+} __attribute__((packed));
+
+struct dma_register {
+ void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
+ unsigned long start_addr; /* DMA Start address register */
+
+ unsigned short cfg; /* DMA Configuration register */
+ unsigned short dummy1; /* DMA Configuration register */
+
+ unsigned long reserved;
+
+ unsigned short x_count; /* DMA x_count register */
+ unsigned short dummy2;
+
+ short x_modify; /* DMA x_modify register */
+ unsigned short dummy3;
+
+ unsigned short y_count; /* DMA y_count register */
+ unsigned short dummy4;
+
+ short y_modify; /* DMA y_modify register */
+ unsigned short dummy5;
+
+ void *curr_desc_ptr; /* DMA Current Descriptor Pointer
+ register */
+ unsigned long curr_addr_ptr; /* DMA Current Address Pointer
+ register */
+ unsigned short irq_status; /* DMA irq status register */
+ unsigned short dummy6;
+
+ unsigned short peripheral_map; /* DMA peripheral map register */
+ unsigned short dummy7;
+
+ unsigned short curr_x_count; /* DMA Current x-count register */
+ unsigned short dummy8;
+
+ unsigned long reserved2;
+
+ unsigned short curr_y_count; /* DMA Current y-count register */
+ unsigned short dummy9;
+
+ unsigned long reserved3;
+
+};
+
+#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
bd_t *bd;
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF512_proc__
+#define __BFIN_CDEF_ADSP_BF512_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
+#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
+#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
+#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
+#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
+#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
+#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
+#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
+#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
+#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
+#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
+#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
+#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
+#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
+#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
+#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
+#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
+#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
+#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
+#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
+#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
+#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
+#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
+#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
+#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
+#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
+#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
+#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
+#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
+#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
+#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
+#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
+#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
+#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
+#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
+#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
+#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
+#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
+#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
+#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
+#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
+#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
+#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
+#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
+#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
+#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
+#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
+#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
+#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
+#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
+#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
+#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
+#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
+#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
+#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
+#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
+#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
+#define bfin_read_PWM_CTRL() bfin_read16(PWM_CTRL)
+#define bfin_write_PWM_CTRL(val) bfin_write16(PWM_CTRL, val)
+#define bfin_read_PWM_STAT() bfin_read16(PWM_STAT)
+#define bfin_write_PWM_STAT(val) bfin_write16(PWM_STAT, val)
+#define bfin_read_PWM_TM() bfin_read16(PWM_TM)
+#define bfin_write_PWM_TM(val) bfin_write16(PWM_TM, val)
+#define bfin_read_PWM_DT() bfin_read16(PWM_DT)
+#define bfin_write_PWM_DT(val) bfin_write16(PWM_DT, val)
+#define bfin_read_PWM_GATE() bfin_read16(PWM_GATE)
+#define bfin_write_PWM_GATE(val) bfin_write16(PWM_GATE, val)
+#define bfin_read_PWM_CHA() bfin_read16(PWM_CHA)
+#define bfin_write_PWM_CHA(val) bfin_write16(PWM_CHA, val)
+#define bfin_read_PWM_CHB() bfin_read16(PWM_CHB)
+#define bfin_write_PWM_CHB(val) bfin_write16(PWM_CHB, val)
+#define bfin_read_PWM_CHC() bfin_read16(PWM_CHC)
+#define bfin_write_PWM_CHC(val) bfin_write16(PWM_CHC, val)
+#define bfin_read_PWM_SEG() bfin_read16(PWM_SEG)
+#define bfin_write_PWM_SEG(val) bfin_write16(PWM_SEG, val)
+#define bfin_read_PWM_SYNCWT() bfin_read16(PWM_SYNCWT)
+#define bfin_write_PWM_SYNCWT(val) bfin_write16(PWM_SYNCWT, val)
+#define bfin_read_PWM_CHAL() bfin_read16(PWM_CHAL)
+#define bfin_write_PWM_CHAL(val) bfin_write16(PWM_CHAL, val)
+#define bfin_read_PWM_CHBL() bfin_read16(PWM_CHBL)
+#define bfin_write_PWM_CHBL(val) bfin_write16(PWM_CHBL, val)
+#define bfin_read_PWM_CHCL() bfin_read16(PWM_CHCL)
+#define bfin_write_PWM_CHCL(val) bfin_write16(PWM_CHCL, val)
+#define bfin_read_PWM_LSI() bfin_read16(PWM_LSI)
+#define bfin_write_PWM_LSI(val) bfin_write16(PWM_LSI, val)
+#define bfin_read_PWM_STAT2() bfin_read16(PWM_STAT2)
+#define bfin_write_PWM_STAT2(val) bfin_write16(PWM_STAT2, val)
+#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
+#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
+#define bfin_read_SWRST() bfin_read16(SWRST)
+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
+#define bfin_read_SYSCR() bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF512_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF512_proc__
+#define __BFIN_DEF_ADSP_BF512_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define PLL_CTL 0xFFC00000 /* PLL Control Register */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT 0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID 0xFFC00014
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration register */
+#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
+#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
+#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
+#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
+#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
+#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */
+#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_MSR 0xFFC00418 /* Modem Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
+#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
+#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
+#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
+#define SPI1_CTL 0xFFC03400 /* SPI1 Control */
+#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */
+#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */
+#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */
+#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */
+#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */
+#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
+#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
+#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
+#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
+#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
+#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
+#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
+#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_MSR 0xFFC02018 /* Modem Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
+#define PORTF_MUX 0xFFC03210 /* Port F mux control */
+#define PORTG_MUX 0xFFC03214 /* Port G mux control */
+#define PORTH_MUX 0xFFC03218 /* Port H mux control */
+#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
+#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
+#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */
+#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
+#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */
+#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */
+#define CNT_STATUS 0xFFC03508 /* Status Register */
+#define CNT_COMMAND 0xFFC0350C /* Command Register */
+#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */
+#define CNT_COUNTER 0xFFC03514 /* Counter Register */
+#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */
+#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */
+#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */
+#define SECURE_CONTROL 0xFFC03624 /* Secure Control */
+#define SECURE_STATUS 0xFFC03628 /* Secure Status */
+#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PWM_CTRL 0xFFC03700 /* PWM Control Register */
+#define PWM_STAT 0xFFC03704 /* PWM Status Register */
+#define PWM_TM 0xFFC03708 /* PWM Period Register */
+#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */
+#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */
+#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */
+#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */
+#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */
+#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */
+#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */
+#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
+#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
+#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
+#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */
+#define PWM_STAT2 0xFFC03738 /* PWM Status Register */
+#define DMA_TC_CNT 0xFFC00B0C
+#define DMA_TC_PER 0xFFC00B10
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF512_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF514_proc__
+#define __BFIN_CDEF_ADSP_BF514_proc__
+
+#include "BF512_cdef.h"
+
+#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
+#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
+#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
+#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
+#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
+#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
+#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF514_proc__
+#define __BFIN_DEF_ADSP_BF514_proc__
+
+#include "BF512_def.h"
+
+#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
+#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
+#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
+#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
+#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
+#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
+#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
+#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
+#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
+#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
+#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
+#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
+#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
+#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
+#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
+#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
+#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
+#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
+#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
+#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
+#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
+#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
+#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
+
+#endif /* __BFIN_DEF_ADSP_BF514_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF516_proc__
+#define __BFIN_CDEF_ADSP_BF516_proc__
+
+#include "BF514_cdef.h"
+
+#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
+#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
+#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
+#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
+#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
+#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
+#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
+#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
+#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
+#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
+#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
+#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
+#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
+#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
+#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
+#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
+#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
+#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
+#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
+#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
+#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
+#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
+#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
+#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
+#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
+#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
+#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
+#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
+#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
+#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
+#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
+#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
+#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
+#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
+#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
+#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
+#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
+#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
+#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
+#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
+#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
+#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
+#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
+#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
+#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
+#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
+#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
+#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
+#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
+#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
+#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
+#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
+#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
+#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
+#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
+#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
+#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
+#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
+#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
+#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
+#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
+#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
+#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
+#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
+#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
+#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
+#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
+#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
+#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
+#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
+#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
+#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
+#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
+#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF516_proc__
+#define __BFIN_DEF_ADSP_BF516_proc__
+
+#include "BF514_def.h"
+
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+#endif /* __BFIN_DEF_ADSP_BF516_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF518_proc__
+#define __BFIN_CDEF_ADSP_BF518_proc__
+
+#include "BF516_cdef.h"
+
+#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
+#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
+#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
+#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
+#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
+#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
+#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
+#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
+#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
+#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
+#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
+#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
+#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
+#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
+#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
+#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
+#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
+#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
+#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
+#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
+#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
+#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
+#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
+#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
+#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
+#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val)
+#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
+#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val)
+#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
+#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val)
+#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
+#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val)
+#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
+#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
+#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
+#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
+#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
+#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
+#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
+#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
+#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO)
+#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val)
+#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
+#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
+#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
+#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF518_proc__
+#define __BFIN_DEF_ADSP_BF518_proc__
+
+#include "BF516_def.h"
+
+#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
+#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
+#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
+#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
+#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
+#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
+#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
+#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
+#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
+#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
+#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
+#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
+#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
+#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
+#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
+#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
+#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
+#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
+#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
+#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
+#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
+#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
+#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
+
+#endif /* __BFIN_DEF_ADSP_BF518_proc__ */
--- /dev/null
+/*
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
+ */
+
+/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
+#if __SILICON_REVISION__ < 0
+# error will not work on BF518 silicon version
+#endif
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (1)
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
+/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
+#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
+/* Preboot Cannot be Used to Alter the PLL_DIV Register */
+#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
+#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* Incorrect L1 Instruction Bank B Memory Map Location */
+#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
+/* PWM_TRIPB Signal Not Available on PG10 */
+#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
+/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
+#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (1)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000257 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000283 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000315 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (0)
+#define ANOMALY_05000357 (0)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
+#define ANOMALY_05000371 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
+#define ANOMALY_05000485 (0)
+
+#endif
--- /dev/null
+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define CONFIG_BF51x 1 /* Linux glue */
--- /dev/null
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 41
+
+#define GPIO_PF0 0
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+#define GPIO_PG0 16
+#define GPIO_PG1 17
+#define GPIO_PG2 18
+#define GPIO_PG3 19
+#define GPIO_PG4 20
+#define GPIO_PG5 21
+#define GPIO_PG6 22
+#define GPIO_PG7 23
+#define GPIO_PG8 24
+#define GPIO_PG9 25
+#define GPIO_PG10 26
+#define GPIO_PG11 27
+#define GPIO_PG12 28
+#define GPIO_PG13 29
+#define GPIO_PG14 30
+#define GPIO_PG15 31
+#define GPIO_PH0 32
+#define GPIO_PH1 33
+#define GPIO_PH2 34
+#define GPIO_PH3 35
+#define GPIO_PH4 36
+#define GPIO_PH5 37
+#define GPIO_PH6 38
+#define GPIO_PH7 39
+#define GPIO_PH8 40
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+/* EMAC MII/RMII Port Mux */
+#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+
+#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+
+#define P_MII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxD2, \
+ P_MII0_ETxD3, \
+ P_MII0_ETxEN, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_COL, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxD2, \
+ P_MII0_ERxD3, \
+ P_MII0_ERxDV, \
+ P_MII0_ERxCLK, \
+ P_MII0_ERxER, \
+ P_MII0_CRS, \
+ P_MII0_MDC, \
+ P_MII0_MDIO, 0}
+
+#define P_RMII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxEN, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxER, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_CRS, \
+ P_MII0_MDC, \
+ P_MII0_MDIO, 0}
+
+/* PPI Port Mux */
+#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+
+#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+
+#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
+
+#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
+#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
+#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
+#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
+
+/* SPORT Port Mux */
+#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+
+#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+
+/* UART Port Mux */
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
+
+/* Timer */
+#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
+#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
+
+/* DMA */
+#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
+
+/* TWI */
+#define P_TWI0_SCL (P_DONTCARE)
+#define P_TWI0_SDA (P_DONTCARE)
+
+/* PWM */
+#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+
+#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+
+#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+
+/* RSI */
+#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
+#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
+#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
+#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
+#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+
+/* PTP */
+#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+
+/* AMS */
+#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
+
+#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
+
+#endif /* _MACH_PORTMUX_H_ */
--- /dev/null
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK 0x0003
+#define PORT_x_MUX_1_MASK 0x000C
+#define PORT_x_MUX_2_MASK 0x0030
+#define PORT_x_MUX_3_MASK 0x00C0
+#define PORT_x_MUX_4_MASK 0x0300
+#define PORT_x_MUX_5_MASK 0x0C00
+#define PORT_x_MUX_6_MASK 0x3000
+#define PORT_x_MUX_7_MASK 0xC000
+
+#define PORT_x_MUX_FUNC_1 (0x0)
+#define PORT_x_MUX_FUNC_2 (0x1)
+#define PORT_x_MUX_FUNC_3 (0x2)
+#define PORT_x_MUX_FUNC_4 (0x3)
+#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
+
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+
+#endif
#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
-#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */
#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pPORTF_MUX ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */
#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define pPORTG_MUX ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */
#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define pPORTH_MUX ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */
#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define pPORTF_DRIVE ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */
#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define pPORTG_DRIVE ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */
#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define pPORTH_DRIVE ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */
#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define pPORTF_SLEW ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */
#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define pPORTG_SLEW ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */
#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define pPORTH_SLEW ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */
#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define pPORTF_HYSTERESIS ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */
#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define pPORTG_HYSTERESIS ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */
#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define pPORTH_HYSTERESIS ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */
#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define pNONGPIO_DRIVE ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */
#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define pNONGPIO_SLEW ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */
#define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW)
#define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val)
-#define pNONGPIO_HYSTERESIS ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */
#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-#define pPFCTL ((uint32_t volatile *)PFCTL)
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER)
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
#define NFC_CMD 0xFFC03744 /* NAND Command Register */
#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */
#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-#define PFCTL 0xFFE08000
-#define PFCNTR0 0xFFE08100
-#define PFCNTR1 0xFFE08104
#define DMA_TC_CNT 0xFFC00B0C
#define DMA_TC_PER 0xFFC00B10
#include "ADSP-EDN-BF52x-extended_cdef.h"
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF523_proc__
-#define __BFIN_CDEF_ADSP_BF523_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
+#include "BF522_cdef.h"
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF523_proc__
-#define __BFIN_DEF_ADSP_BF523_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-#endif /* __BFIN_DEF_ADSP_BF523_proc__ */
+#include "BF522_def.h"
#include "ADSP-EDN-BF52x-extended_cdef.h"
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#define USB_FADDR 0xFFC03800 /* Function address register */
#define USB_POWER 0xFFC03804 /* Power management register */
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF525_proc__
-#define __BFIN_CDEF_ADSP_BF525_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF525_proc__ */
+#include "BF524_cdef.h"
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF525_proc__
-#define __BFIN_DEF_ADSP_BF525_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define USB_FADDR 0xFFC03800 /* Function address register */
-#define USB_POWER 0xFFC03804 /* Power management register */
-#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03820 /* USB frame number */
-#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF525_proc__ */
+#include "BF524_def.h"
#include "ADSP-EDN-BF52x-extended_cdef.h"
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF527_proc__
-#define __BFIN_CDEF_ADSP_BF527_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF527_proc__ */
+#include "BF526_cdef.h"
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF527_proc__
-#define __BFIN_DEF_ADSP_BF527_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-#define USB_FADDR 0xFFC03800 /* Function address register */
-#define USB_POWER 0xFFC03804 /* Power management register */
-#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03820 /* USB frame number */
-#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF527_proc__ */
+#include "BF526_def.h"
/* This file should be up to date with:
* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* The CODEC Zero-Cross Detect Feature is not Functional */
+#define ANOMALY_05000487 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
#include "../mach-common/ADSP-EDN-core_cdef.h"
-#include "../mach-common/ADSP-EDN-extended_cdef.h"
-
+#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
+#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
+#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D)
+#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
+#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
+#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
+#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D)
+#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
+#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
+#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
+#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
+#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
+#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D)
+#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
+#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
+#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
+#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
+#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
+#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
+#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
+#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S)
+#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
+#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
+#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
+#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S)
+#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
+#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
+#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
+#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
+#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
+#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S)
+#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
+#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
+#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
+#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
+#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
+#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
+#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
+#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D)
+#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
+#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
+#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
+#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D)
+#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
+#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
+#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
+#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
+#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
+#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D)
+#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
+#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
+#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
+#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
+#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
+#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
+#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
+#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S)
+#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
+#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
+#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
+#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S)
+#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
+#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
+#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
+#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
+#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
+#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S)
+#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
+#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
+#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
+#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
+#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
+#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG)
+#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
+#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT)
+#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
+#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY)
+#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
+#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT)
+#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
+#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY)
+#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
+#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT)
+#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
+#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP)
+#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val)
+#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT)
+#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
+#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT)
+#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
+#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG)
+#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
+#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT)
+#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
+#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY)
+#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
+#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT)
+#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
+#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY)
+#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
+#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT)
+#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
+#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP)
+#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val)
+#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT)
+#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
+#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT)
+#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
+#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG)
+#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
+#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT)
+#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
+#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY)
+#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
+#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT)
+#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
+#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY)
+#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
+#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT)
+#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
+#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP)
+#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val)
+#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT)
+#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
+#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT)
+#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
+#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG)
+#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
+#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT)
+#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
+#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY)
+#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
+#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT)
+#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
+#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY)
+#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
+#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT)
+#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
+#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP)
+#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val)
+#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT)
+#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
+#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT)
+#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
+#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG)
+#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
+#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT)
+#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
+#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY)
+#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
+#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT)
+#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
+#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY)
+#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
+#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT)
+#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
+#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP)
+#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val)
+#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT)
+#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
+#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT)
+#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
+#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG)
+#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
+#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT)
+#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
+#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY)
+#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
+#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT)
+#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
+#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY)
+#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
+#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT)
+#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
+#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP)
+#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val)
+#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT)
+#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
+#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT)
+#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
+#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG)
+#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
+#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT)
+#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
+#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY)
+#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
+#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT)
+#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
+#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY)
+#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
+#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT)
+#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
+#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP)
+#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val)
+#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT)
+#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
+#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT)
+#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
+#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG)
+#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
+#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT)
+#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
+#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY)
+#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
+#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT)
+#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
+#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY)
+#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
+#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT)
+#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
+#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP)
+#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val)
+#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT)
+#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
+#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT)
+#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
+#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
+#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
+#define bfin_read_UART_THR() bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
+#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
+#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
+#define bfin_read_UART_IER() bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
+#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
+#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
+#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
+#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
+#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
+#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
+#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
+#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0)
+#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
+#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1)
+#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
+#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0)
+#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
+#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1)
+#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
+#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX)
+#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val)
+#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX)
+#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val)
+#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV)
+#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val)
+#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV)
+#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val)
+#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV)
+#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val)
+#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV)
+#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val)
+#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT)
+#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val)
+#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0)
+#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val)
+#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1)
+#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val)
+#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2)
+#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val)
+#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3)
+#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val)
+#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0)
+#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val)
+#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1)
+#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val)
+#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2)
+#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val)
+#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3)
+#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val)
+#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1)
+#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val)
+#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2)
+#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val)
+#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL)
+#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val)
+#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0)
+#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
+#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1)
+#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
+#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0)
+#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
+#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1)
+#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
+#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX)
+#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val)
+#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX)
+#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val)
+#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV)
+#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val)
+#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV)
+#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val)
+#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV)
+#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val)
+#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV)
+#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val)
+#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT)
+#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val)
+#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0)
+#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val)
+#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1)
+#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val)
+#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2)
+#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val)
+#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3)
+#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val)
+#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0)
+#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val)
+#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1)
+#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val)
+#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2)
+#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val)
+#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3)
+#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val)
+#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1)
+#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val)
+#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2)
+#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val)
+#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL)
+#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val)
+#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_SWRST() bfin_read16(SWRST)
+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
+#define bfin_read_SYSCR() bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
+#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
+#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
+#define bfin_read_TBUF() bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
+#define bfin_read_PFCTL() bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
+#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
+#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
+#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
+#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
+#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
+#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
+#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
+#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
+#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
+#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
+#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
+#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
+#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val)
+#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
+#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val)
+#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
+#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val)
+#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
+#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val)
+#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
+#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val)
+#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
+#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val)
+#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
+#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val)
+#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
+#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val)
+#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
+#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val)
+#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
+#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val)
+#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
+#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val)
+#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
+#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val)
+#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
+#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val)
+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
+#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
+#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */
#include "../mach-common/ADSP-EDN-core_def.h"
-#include "../mach-common/ADSP-EDN-extended_def.h"
+#define MDMAFLX0_DMACNFG_D 0xFFC00E08
+#define MDMAFLX0_XCOUNT_D 0xFFC00E10
+#define MDMAFLX0_XMODIFY_D 0xFFC00E14
+#define MDMAFLX0_YCOUNT_D 0xFFC00E18
+#define MDMAFLX0_YMODIFY_D 0xFFC00E1C
+#define MDMAFLX0_IRQSTAT_D 0xFFC00E28
+#define MDMAFLX0_PMAP_D 0xFFC00E2C
+#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30
+#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38
+#define MDMAFLX0_DMACNFG_S 0xFFC00E48
+#define MDMAFLX0_XCOUNT_S 0xFFC00E50
+#define MDMAFLX0_XMODIFY_S 0xFFC00E54
+#define MDMAFLX0_YCOUNT_S 0xFFC00E58
+#define MDMAFLX0_YMODIFY_S 0xFFC00E5C
+#define MDMAFLX0_IRQSTAT_S 0xFFC00E68
+#define MDMAFLX0_PMAP_S 0xFFC00E6C
+#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70
+#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78
+#define MDMAFLX1_DMACNFG_D 0xFFC00E88
+#define MDMAFLX1_XCOUNT_D 0xFFC00E90
+#define MDMAFLX1_XMODIFY_D 0xFFC00E94
+#define MDMAFLX1_YCOUNT_D 0xFFC00E98
+#define MDMAFLX1_YMODIFY_D 0xFFC00E9C
+#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8
+#define MDMAFLX1_PMAP_D 0xFFC00EAC
+#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0
+#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8
+#define MDMAFLX1_DMACNFG_S 0xFFC00EC8
+#define MDMAFLX1_XCOUNT_S 0xFFC00ED0
+#define MDMAFLX1_XMODIFY_S 0xFFC00ED4
+#define MDMAFLX1_YCOUNT_S 0xFFC00ED8
+#define MDMAFLX1_YMODIFY_S 0xFFC00EDC
+#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8
+#define MDMAFLX1_PMAP_S 0xFFC00EEC
+#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0
+#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8
+#define DMAFLX0_DMACNFG 0xFFC00C08
+#define DMAFLX0_XCOUNT 0xFFC00C10
+#define DMAFLX0_XMODIFY 0xFFC00C14
+#define DMAFLX0_YCOUNT 0xFFC00C18
+#define DMAFLX0_YMODIFY 0xFFC00C1C
+#define DMAFLX0_IRQSTAT 0xFFC00C28
+#define DMAFLX0_PMAP 0xFFC00C2C
+#define DMAFLX0_CURXCOUNT 0xFFC00C30
+#define DMAFLX0_CURYCOUNT 0xFFC00C38
+#define DMAFLX1_DMACNFG 0xFFC00C48
+#define DMAFLX1_XCOUNT 0xFFC00C50
+#define DMAFLX1_XMODIFY 0xFFC00C54
+#define DMAFLX1_YCOUNT 0xFFC00C58
+#define DMAFLX1_YMODIFY 0xFFC00C5C
+#define DMAFLX1_IRQSTAT 0xFFC00C68
+#define DMAFLX1_PMAP 0xFFC00C6C
+#define DMAFLX1_CURXCOUNT 0xFFC00C70
+#define DMAFLX1_CURYCOUNT 0xFFC00C78
+#define DMAFLX2_DMACNFG 0xFFC00C88
+#define DMAFLX2_XCOUNT 0xFFC00C90
+#define DMAFLX2_XMODIFY 0xFFC00C94
+#define DMAFLX2_YCOUNT 0xFFC00C98
+#define DMAFLX2_YMODIFY 0xFFC00C9C
+#define DMAFLX2_IRQSTAT 0xFFC00CA8
+#define DMAFLX2_PMAP 0xFFC00CAC
+#define DMAFLX2_CURXCOUNT 0xFFC00CB0
+#define DMAFLX2_CURYCOUNT 0xFFC00CB8
+#define DMAFLX3_DMACNFG 0xFFC00CC8
+#define DMAFLX3_XCOUNT 0xFFC00CD0
+#define DMAFLX3_XMODIFY 0xFFC00CD4
+#define DMAFLX3_YCOUNT 0xFFC00CD8
+#define DMAFLX3_YMODIFY 0xFFC00CDC
+#define DMAFLX3_IRQSTAT 0xFFC00CE8
+#define DMAFLX3_PMAP 0xFFC00CEC
+#define DMAFLX3_CURXCOUNT 0xFFC00CF0
+#define DMAFLX3_CURYCOUNT 0xFFC00CF8
+#define DMAFLX4_DMACNFG 0xFFC00D08
+#define DMAFLX4_XCOUNT 0xFFC00D10
+#define DMAFLX4_XMODIFY 0xFFC00D14
+#define DMAFLX4_YCOUNT 0xFFC00D18
+#define DMAFLX4_YMODIFY 0xFFC00D1C
+#define DMAFLX4_IRQSTAT 0xFFC00D28
+#define DMAFLX4_PMAP 0xFFC00D2C
+#define DMAFLX4_CURXCOUNT 0xFFC00D30
+#define DMAFLX4_CURYCOUNT 0xFFC00D38
+#define DMAFLX5_DMACNFG 0xFFC00D48
+#define DMAFLX5_XCOUNT 0xFFC00D50
+#define DMAFLX5_XMODIFY 0xFFC00D54
+#define DMAFLX5_YCOUNT 0xFFC00D58
+#define DMAFLX5_YMODIFY 0xFFC00D5C
+#define DMAFLX5_IRQSTAT 0xFFC00D68
+#define DMAFLX5_PMAP 0xFFC00D6C
+#define DMAFLX5_CURXCOUNT 0xFFC00D70
+#define DMAFLX5_CURYCOUNT 0xFFC00D78
+#define DMAFLX6_DMACNFG 0xFFC00D88
+#define DMAFLX6_XCOUNT 0xFFC00D90
+#define DMAFLX6_XMODIFY 0xFFC00D94
+#define DMAFLX6_YCOUNT 0xFFC00D98
+#define DMAFLX6_YMODIFY 0xFFC00D9C
+#define DMAFLX6_IRQSTAT 0xFFC00DA8
+#define DMAFLX6_PMAP 0xFFC00DAC
+#define DMAFLX6_CURXCOUNT 0xFFC00DB0
+#define DMAFLX6_CURYCOUNT 0xFFC00DB8
+#define DMAFLX7_DMACNFG 0xFFC00DC8
+#define DMAFLX7_XCOUNT 0xFFC00DD0
+#define DMAFLX7_XMODIFY 0xFFC00DD4
+#define DMAFLX7_YCOUNT 0xFFC00DD8
+#define DMAFLX7_YMODIFY 0xFFC00DDC
+#define DMAFLX7_IRQSTAT 0xFFC00DE8
+#define DMAFLX7_PMAP 0xFFC00DEC
+#define DMAFLX7_CURXCOUNT 0xFFC00DF0
+#define DMAFLX7_CURYCOUNT 0xFFC00DF8
+#define TIMER0_CONFIG 0xFFC00600
+#define TIMER0_COUNTER 0xFFC00604
+#define TIMER0_PERIOD 0xFFC00608
+#define TIMER0_WIDTH 0xFFC0060C
+#define TIMER1_CONFIG 0xFFC00610
+#define TIMER1_COUNTER 0xFFC00614
+#define TIMER1_PERIOD 0xFFC00618
+#define TIMER1_WIDTH 0xFFC0061C
+#define TIMER2_CONFIG 0xFFC00620
+#define TIMER2_COUNTER 0xFFC00624
+#define TIMER2_PERIOD 0xFFC00628
+#define TIMER2_WIDTH 0xFFC0062C
+#define TIMER_ENABLE 0xFFC00640
+#define TIMER_DISABLE 0xFFC00644
+#define TIMER_STATUS 0xFFC00648
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
+#define UART_THR 0xFFC00400 /* Transmit Holding */
+#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */
+#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */
+#define UART_IER 0xFFC00404
+#define UART_IIR 0xFFC00408
+#define UART_LCR 0xFFC0040C
+#define UART_MCR 0xFFC00410
+#define UART_LSR 0xFFC00414
+#define UART_SCR 0xFFC0041C
+#define UART_RBR 0xFFC00400 /* Receive Buffer */
+#define UART_GCTL 0xFFC00424
+#define SPT0_TX_CONFIG0 0xFFC00800
+#define SPT0_TX_CONFIG1 0xFFC00804
+#define SPT0_RX_CONFIG0 0xFFC00820
+#define SPT0_RX_CONFIG1 0xFFC00824
+#define SPT0_TX 0xFFC00810
+#define SPT0_RX 0xFFC00818
+#define SPT0_TSCLKDIV 0xFFC00808
+#define SPT0_RSCLKDIV 0xFFC00828
+#define SPT0_TFSDIV 0xFFC0080C
+#define SPT0_RFSDIV 0xFFC0082C
+#define SPT0_STAT 0xFFC00830
+#define SPT0_MTCS0 0xFFC00840
+#define SPT0_MTCS1 0xFFC00844
+#define SPT0_MTCS2 0xFFC00848
+#define SPT0_MTCS3 0xFFC0084C
+#define SPT0_MRCS0 0xFFC00850
+#define SPT0_MRCS1 0xFFC00854
+#define SPT0_MRCS2 0xFFC00858
+#define SPT0_MRCS3 0xFFC0085C
+#define SPT0_MCMC1 0xFFC00838
+#define SPT0_MCMC2 0xFFC0083C
+#define SPT0_CHNL 0xFFC00834
+#define SPT1_TX_CONFIG0 0xFFC00900
+#define SPT1_TX_CONFIG1 0xFFC00904
+#define SPT1_RX_CONFIG0 0xFFC00920
+#define SPT1_RX_CONFIG1 0xFFC00924
+#define SPT1_TX 0xFFC00910
+#define SPT1_RX 0xFFC00918
+#define SPT1_TSCLKDIV 0xFFC00908
+#define SPT1_RSCLKDIV 0xFFC00928
+#define SPT1_TFSDIV 0xFFC0090C
+#define SPT1_RFSDIV 0xFFC0092C
+#define SPT1_STAT 0xFFC00930
+#define SPT1_MTCS0 0xFFC00940
+#define SPT1_MTCS1 0xFFC00944
+#define SPT1_MTCS2 0xFFC00948
+#define SPT1_MTCS3 0xFFC0094C
+#define SPT1_MRCS0 0xFFC00950
+#define SPT1_MRCS1 0xFFC00954
+#define SPT1_MRCS2 0xFFC00958
+#define SPT1_MRCS3 0xFFC0095C
+#define SPT1_MCMC1 0xFFC00938
+#define SPT1_MCMC2 0xFFC0093C
+#define SPT1_CHNL 0xFFC00934
+#define PPI_CONTROL 0xFFC01000
+#define PPI_STATUS 0xFFC01004
+#define PPI_DELAY 0xFFC0100C
+#define PPI_COUNT 0xFFC01008
+#define PPI_FRAME 0xFFC01010
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
+#define SYSCR 0xFFC00104 /* System Configuration register */
+#define CHIPID 0xFFC00014
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT 0xFFC00300
+#define RTC_ICTL 0xFFC00304
+#define RTC_ISTAT 0xFFC00308
+#define RTC_SWCNT 0xFFC0030C
+#define RTC_ALARM 0xFFC00310
+#define RTC_PREN 0xFFC00314
+#define SPI_CTL 0xFFC00500
+#define SPI_FLG 0xFFC00504
+#define SPI_STAT 0xFFC00508
+#define SPI_TDBR 0xFFC0050C
+#define SPI_RDBR 0xFFC00510
+#define SPI_BAUD 0xFFC00514
+#define SPI_SHADOW 0xFFC00518
+#define FIO_FLAG_D 0xFFC00700
+#define FIO_FLAG_C 0xFFC00704
+#define FIO_FLAG_S 0xFFC00708
+#define FIO_FLAG_T 0xFFC0070C
+#define FIO_MASKA_D 0xFFC00710
+#define FIO_MASKA_C 0xFFC00714
+#define FIO_MASKA_S 0xFFC00718
+#define FIO_MASKA_T 0xFFC0071C
+#define FIO_MASKB_D 0xFFC00720
+#define FIO_MASKB_C 0xFFC00724
+#define FIO_MASKB_S 0xFFC00728
+#define FIO_MASKB_T 0xFFC0072C
+#define FIO_DIR 0xFFC00730
+#define FIO_POLAR 0xFFC00734
+#define FIO_EDGE 0xFFC00738
+#define FIO_BOTH 0xFFC0073C
+#define FIO_INEN 0xFFC00740
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00
+#define DMA0_START_ADDR 0xFFC00C04
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10
+#define DMA0_X_MODIFY 0xFFC00C14
+#define DMA0_Y_COUNT 0xFFC00C18
+#define DMA0_Y_MODIFY 0xFFC00C1C
+#define DMA0_CURR_DESC_PTR 0xFFC00C20
+#define DMA0_CURR_ADDR 0xFFC00C24
+#define DMA0_IRQ_STATUS 0xFFC00C28
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
+#define DMA0_CURR_X_COUNT 0xFFC00C30
+#define DMA0_CURR_Y_COUNT 0xFFC00C38
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40
+#define DMA1_START_ADDR 0xFFC00C44
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50
+#define DMA1_X_MODIFY 0xFFC00C54
+#define DMA1_Y_COUNT 0xFFC00C58
+#define DMA1_Y_MODIFY 0xFFC00C5C
+#define DMA1_CURR_DESC_PTR 0xFFC00C60
+#define DMA1_CURR_ADDR 0xFFC00C64
+#define DMA1_IRQ_STATUS 0xFFC00C68
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
+#define DMA1_CURR_X_COUNT 0xFFC00C70
+#define DMA1_CURR_Y_COUNT 0xFFC00C78
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80
+#define DMA2_START_ADDR 0xFFC00C84
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90
+#define DMA2_X_MODIFY 0xFFC00C94
+#define DMA2_Y_COUNT 0xFFC00C98
+#define DMA2_Y_MODIFY 0xFFC00C9C
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0
+#define DMA2_CURR_ADDR 0xFFC00CA4
+#define DMA2_IRQ_STATUS 0xFFC00CA8
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
+#define DMA2_CURR_X_COUNT 0xFFC00CB0
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
+#define DMA3_START_ADDR 0xFFC00CC4
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0
+#define DMA3_X_MODIFY 0xFFC00CD4
+#define DMA3_Y_COUNT 0xFFC00CD8
+#define DMA3_Y_MODIFY 0xFFC00CDC
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0
+#define DMA3_CURR_ADDR 0xFFC00CE4
+#define DMA3_IRQ_STATUS 0xFFC00CE8
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
+#define DMA3_CURR_X_COUNT 0xFFC00CF0
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00
+#define DMA4_START_ADDR 0xFFC00D04
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10
+#define DMA4_X_MODIFY 0xFFC00D14
+#define DMA4_Y_COUNT 0xFFC00D18
+#define DMA4_Y_MODIFY 0xFFC00D1C
+#define DMA4_CURR_DESC_PTR 0xFFC00D20
+#define DMA4_CURR_ADDR 0xFFC00D24
+#define DMA4_IRQ_STATUS 0xFFC00D28
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
+#define DMA4_CURR_X_COUNT 0xFFC00D30
+#define DMA4_CURR_Y_COUNT 0xFFC00D38
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40
+#define DMA5_START_ADDR 0xFFC00D44
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50
+#define DMA5_X_MODIFY 0xFFC00D54
+#define DMA5_Y_COUNT 0xFFC00D58
+#define DMA5_Y_MODIFY 0xFFC00D5C
+#define DMA5_CURR_DESC_PTR 0xFFC00D60
+#define DMA5_CURR_ADDR 0xFFC00D64
+#define DMA5_IRQ_STATUS 0xFFC00D68
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
+#define DMA5_CURR_X_COUNT 0xFFC00D70
+#define DMA5_CURR_Y_COUNT 0xFFC00D78
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80
+#define DMA6_START_ADDR 0xFFC00D84
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90
+#define DMA6_X_MODIFY 0xFFC00D94
+#define DMA6_Y_COUNT 0xFFC00D98
+#define DMA6_Y_MODIFY 0xFFC00D9C
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0
+#define DMA6_CURR_ADDR 0xFFC00DA4
+#define DMA6_IRQ_STATUS 0xFFC00DA8
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
+#define DMA6_CURR_X_COUNT 0xFFC00DB0
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
+#define DMA7_START_ADDR 0xFFC00DC4
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0
+#define DMA7_X_MODIFY 0xFFC00DD4
+#define DMA7_Y_COUNT 0xFFC00DD8
+#define DMA7_Y_MODIFY 0xFFC00DDC
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0
+#define DMA7_CURR_ADDR 0xFFC00DE4
+#define DMA7_IRQ_STATUS 0xFFC00DE8
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
+#define DMA7_CURR_X_COUNT 0xFFC00DF0
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00
+#define MDMA_D0_START_ADDR 0xFFC00E04
+#define MDMA_D0_CONFIG 0xFFC00E08
+#define MDMA_D0_X_COUNT 0xFFC00E10
+#define MDMA_D0_X_MODIFY 0xFFC00E14
+#define MDMA_D0_Y_COUNT 0xFFC00E18
+#define MDMA_D0_Y_MODIFY 0xFFC00E1C
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20
+#define MDMA_D0_CURR_ADDR 0xFFC00E24
+#define MDMA_D0_IRQ_STATUS 0xFFC00E28
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C
+#define MDMA_D0_CURR_X_COUNT 0xFFC00E30
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40
+#define MDMA_S0_START_ADDR 0xFFC00E44
+#define MDMA_S0_CONFIG 0xFFC00E48
+#define MDMA_S0_X_COUNT 0xFFC00E50
+#define MDMA_S0_X_MODIFY 0xFFC00E54
+#define MDMA_S0_Y_COUNT 0xFFC00E58
+#define MDMA_S0_Y_MODIFY 0xFFC00E5C
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60
+#define MDMA_S0_CURR_ADDR 0xFFC00E64
+#define MDMA_S0_IRQ_STATUS 0xFFC00E68
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C
+#define MDMA_S0_CURR_X_COUNT 0xFFC00E70
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80
+#define MDMA_D1_START_ADDR 0xFFC00E84
+#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00E90
+#define MDMA_D1_X_MODIFY 0xFFC00E94
+#define MDMA_D1_Y_COUNT 0xFFC00E98
+#define MDMA_D1_Y_MODIFY 0xFFC00E9C
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0
+#define MDMA_D1_CURR_ADDR 0xFFC00EA4
+#define MDMA_D1_IRQ_STATUS 0xFFC00EA8
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC
+#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0
+#define MDMA_S1_START_ADDR 0xFFC00EC4
+#define MDMA_S1_CONFIG 0xFFC00EC8
+#define MDMA_S1_X_COUNT 0xFFC00ED0
+#define MDMA_S1_X_MODIFY 0xFFC00ED4
+#define MDMA_S1_Y_COUNT 0xFFC00ED8
+#define MDMA_S1_Y_MODIFY 0xFFC00EDC
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0
+#define MDMA_S1_CURR_ADDR 0xFFC00EE4
+#define MDMA_S1_IRQ_STATUS 0xFFC00EE8
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC
+#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8
+#define EBIU_AMGCTL 0xFFC00A00
+#define EBIU_AMBCTL0 0xFFC00A04
+#define EBIU_AMBCTL1 0xFFC00A08
+#define EBIU_SDGCTL 0xFFC00A10
+#define EBIU_SDBCTL 0xFFC00A14
+#define EBIU_SDRRC 0xFFC00A18
+#define EBIU_SDSTAT 0xFFC00A1C
+#define DMA_TC_CNT 0xFFC00B0C
+#define DMA_TC_PER 0xFFC00B10
+#ifndef __BFIN_DEF_ADSP_BF533_proc__
#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+#endif
#endif /* __BFIN_DEF_ADSP_BF531_proc__ */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF532_proc__
-#define __BFIN_CDEF_ADSP_BF532_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "../mach-common/ADSP-EDN-extended_cdef.h"
-
-
-#endif /* __BFIN_CDEF_ADSP_BF532_proc__ */
+#include "BF531_cdef.h"
#ifndef __BFIN_DEF_ADSP_BF532_proc__
#define __BFIN_DEF_ADSP_BF532_proc__
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "../mach-common/ADSP-EDN-extended_def.h"
+#include "BF531_def.h"
+#ifndef __BFIN_DEF_ADSP_BF533_proc__
#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+#endif
#endif /* __BFIN_DEF_ADSP_BF532_proc__ */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF533_proc__
-#define __BFIN_CDEF_ADSP_BF533_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "../mach-common/ADSP-EDN-extended_cdef.h"
-
-
-#endif /* __BFIN_CDEF_ADSP_BF533_proc__ */
+#include "BF532_cdef.h"
#ifndef __BFIN_DEF_ADSP_BF533_proc__
#define __BFIN_DEF_ADSP_BF533_proc__
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "../mach-common/ADSP-EDN-extended_def.h"
+#include "BF532_def.h"
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
*/
/* This file should be up to date with:
- * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__
#define __BFIN_CDEF_ADSP_EDN_BF534_extended__
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
-#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */
#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pCAN_MC1 ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */
#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define pCAN_MD1 ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */
#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define pCAN_TRS1 ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */
#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define pCAN_TRR1 ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */
#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define pCAN_TA1 ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */
#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define pCAN_AA1 ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */
#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define pCAN_RMP1 ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */
#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define pCAN_RML1 ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */
#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define pCAN_MBTIF1 ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */
#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define pCAN_MBRIF1 ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive Interrupt Flag reg 1 */
#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define pCAN_MBIM1 ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */
#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define pCAN_RFH1 ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */
#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define pCAN_OPSS1 ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */
#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define pCAN_MC2 ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */
#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define pCAN_MD2 ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */
#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define pCAN_TRS2 ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */
#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define pCAN_TRR2 ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */
#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define pCAN_TA2 ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */
#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define pCAN_AA2 ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */
#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define pCAN_RMP2 ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */
#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define pCAN_RML2 ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */
#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define pCAN_MBTIF2 ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */
#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define pCAN_MBRIF2 ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive Interrupt Flag reg 2 */
#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define pCAN_MBIM2 ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */
#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define pCAN_RFH2 ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */
#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define pCAN_OPSS2 ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */
#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define pCAN_CLOCK ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */
#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define pCAN_TIMING ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */
#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define pCAN_DEBUG ((uint16_t volatile *)CAN_DEBUG) /* Config register */
#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define pCAN_STATUS ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */
#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define pCAN_CEC ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */
#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define pCAN_GIS ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */
#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define pCAN_GIM ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */
#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define pCAN_GIF ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */
#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define pCAN_CONTROL ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */
#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define pCAN_INTR ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */
#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define pCAN_VERSION ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */
#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define pCAN_MBTD ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */
#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define pCAN_EWR ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */
#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define pCAN_ESR ((uint16_t volatile *)CAN_ESR) /* Error Status Register */
#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define pCAN_UCREG ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */
#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define pCAN_UCCNT ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */
#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define pCAN_UCRC ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */
#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define pCAN_UCCNF ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */
#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define pCAN_VERSION2 ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */
#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define pCAN_AM00L ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */
#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define pCAN_AM00H ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */
#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define pCAN_AM01L ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask */
#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define pCAN_AM01H ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */
#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define pCAN_AM02L ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask */
#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define pCAN_AM02H ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */
#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define pCAN_AM03L ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask */
#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define pCAN_AM03H ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */
#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define pCAN_AM04L ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask */
#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define pCAN_AM04H ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */
#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define pCAN_AM05L ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask */
#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define pCAN_AM05H ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */
#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define pCAN_AM06L ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask */
#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define pCAN_AM06H ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */
#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define pCAN_AM07L ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask */
#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define pCAN_AM07H ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */
#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define pCAN_AM08L ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask */
#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define pCAN_AM08H ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */
#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define pCAN_AM09L ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask */
#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define pCAN_AM09H ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */
#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define pCAN_AM10L ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask */
#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define pCAN_AM10H ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */
#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define pCAN_AM11L ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask */
#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define pCAN_AM11H ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */
#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define pCAN_AM12L ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask */
#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define pCAN_AM12H ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */
#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define pCAN_AM13L ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask */
#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define pCAN_AM13H ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */
#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define pCAN_AM14L ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask */
#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define pCAN_AM14H ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */
#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define pCAN_AM15L ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask */
#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define pCAN_AM15H ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */
#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define pCAN_AM16L ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask */
#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define pCAN_AM16H ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */
#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define pCAN_AM17L ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask */
#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define pCAN_AM17H ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */
#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define pCAN_AM18L ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask */
#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define pCAN_AM18H ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */
#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define pCAN_AM19L ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask */
#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define pCAN_AM19H ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */
#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define pCAN_AM20L ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask */
#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define pCAN_AM20H ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */
#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define pCAN_AM21L ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask */
#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define pCAN_AM21H ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */
#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define pCAN_AM22L ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask */
#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define pCAN_AM22H ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */
#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define pCAN_AM23L ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask */
#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define pCAN_AM23H ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */
#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define pCAN_AM24L ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask */
#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define pCAN_AM24H ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */
#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define pCAN_AM25L ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask */
#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define pCAN_AM25H ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */
#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define pCAN_AM26L ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask */
#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define pCAN_AM26H ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */
#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define pCAN_AM27L ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask */
#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define pCAN_AM27H ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */
#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define pCAN_AM28L ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask */
#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define pCAN_AM28H ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */
#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define pCAN_AM29L ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask */
#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define pCAN_AM29H ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */
#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define pCAN_AM30L ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask */
#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define pCAN_AM30H ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */
#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define pCAN_AM31L ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask */
#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define pCAN_AM31H ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */
#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define pCAN_MB00_DATA0 ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define pCAN_MB00_DATA1 ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define pCAN_MB00_DATA2 ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define pCAN_MB00_DATA3 ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define pCAN_MB00_LENGTH ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */
#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define pCAN_MB00_TIMESTAMP ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */
#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define pCAN_MB00_ID0 ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */
#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define pCAN_MB00_ID1 ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */
#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define pCAN_MB01_DATA0 ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define pCAN_MB01_DATA1 ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define pCAN_MB01_DATA2 ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define pCAN_MB01_DATA3 ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define pCAN_MB01_LENGTH ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */
#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define pCAN_MB01_TIMESTAMP ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */
#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define pCAN_MB01_ID0 ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */
#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define pCAN_MB01_ID1 ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */
#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define pCAN_MB02_DATA0 ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define pCAN_MB02_DATA1 ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define pCAN_MB02_DATA2 ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define pCAN_MB02_DATA3 ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define pCAN_MB02_LENGTH ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register */
#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define pCAN_MB02_TIMESTAMP ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */
#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define pCAN_MB02_ID0 ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */
#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define pCAN_MB02_ID1 ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */
#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define pCAN_MB03_DATA0 ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define pCAN_MB03_DATA1 ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define pCAN_MB03_DATA2 ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define pCAN_MB03_DATA3 ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define pCAN_MB03_LENGTH ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */
#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define pCAN_MB03_TIMESTAMP ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */
#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define pCAN_MB03_ID0 ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */
#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define pCAN_MB03_ID1 ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */
#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define pCAN_MB04_DATA0 ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define pCAN_MB04_DATA1 ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define pCAN_MB04_DATA2 ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define pCAN_MB04_DATA3 ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define pCAN_MB04_LENGTH ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */
#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define pCAN_MB04_TIMESTAMP ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */
#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define pCAN_MB04_ID0 ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */
#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define pCAN_MB04_ID1 ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */
#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define pCAN_MB05_DATA0 ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define pCAN_MB05_DATA1 ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define pCAN_MB05_DATA2 ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define pCAN_MB05_DATA3 ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define pCAN_MB05_LENGTH ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */
#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define pCAN_MB05_TIMESTAMP ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */
#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define pCAN_MB05_ID0 ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */
#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define pCAN_MB05_ID1 ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */
#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define pCAN_MB06_DATA0 ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define pCAN_MB06_DATA1 ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define pCAN_MB06_DATA2 ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define pCAN_MB06_DATA3 ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define pCAN_MB06_LENGTH ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */
#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define pCAN_MB06_TIMESTAMP ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */
#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define pCAN_MB06_ID0 ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */
#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define pCAN_MB06_ID1 ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */
#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define pCAN_MB07_DATA0 ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define pCAN_MB07_DATA1 ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define pCAN_MB07_DATA2 ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define pCAN_MB07_DATA3 ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define pCAN_MB07_LENGTH ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */
#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define pCAN_MB07_TIMESTAMP ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */
#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define pCAN_MB07_ID0 ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */
#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define pCAN_MB07_ID1 ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */
#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define pCAN_MB08_DATA0 ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define pCAN_MB08_DATA1 ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define pCAN_MB08_DATA2 ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define pCAN_MB08_DATA3 ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define pCAN_MB08_LENGTH ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */
#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define pCAN_MB08_TIMESTAMP ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */
#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define pCAN_MB08_ID0 ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */
#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define pCAN_MB08_ID1 ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */
#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define pCAN_MB09_DATA0 ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define pCAN_MB09_DATA1 ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define pCAN_MB09_DATA2 ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define pCAN_MB09_DATA3 ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define pCAN_MB09_LENGTH ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */
#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define pCAN_MB09_TIMESTAMP ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */
#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define pCAN_MB09_ID0 ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */
#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define pCAN_MB09_ID1 ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */
#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define pCAN_MB10_DATA0 ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define pCAN_MB10_DATA1 ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define pCAN_MB10_DATA2 ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define pCAN_MB10_DATA3 ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define pCAN_MB10_LENGTH ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */
#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define pCAN_MB10_TIMESTAMP ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */
#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define pCAN_MB10_ID0 ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */
#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define pCAN_MB10_ID1 ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */
#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define pCAN_MB11_DATA0 ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define pCAN_MB11_DATA1 ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define pCAN_MB11_DATA2 ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define pCAN_MB11_DATA3 ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define pCAN_MB11_LENGTH ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */
#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define pCAN_MB11_TIMESTAMP ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */
#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define pCAN_MB11_ID0 ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */
#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define pCAN_MB11_ID1 ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */
#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define pCAN_MB12_DATA0 ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define pCAN_MB12_DATA1 ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define pCAN_MB12_DATA2 ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define pCAN_MB12_DATA3 ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define pCAN_MB12_LENGTH ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */
#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define pCAN_MB12_TIMESTAMP ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */
#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define pCAN_MB12_ID0 ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */
#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define pCAN_MB12_ID1 ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */
#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define pCAN_MB13_DATA0 ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define pCAN_MB13_DATA1 ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define pCAN_MB13_DATA2 ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define pCAN_MB13_DATA3 ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define pCAN_MB13_LENGTH ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */
#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define pCAN_MB13_TIMESTAMP ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */
#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define pCAN_MB13_ID0 ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */
#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define pCAN_MB13_ID1 ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */
#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define pCAN_MB14_DATA0 ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define pCAN_MB14_DATA1 ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define pCAN_MB14_DATA2 ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define pCAN_MB14_DATA3 ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define pCAN_MB14_LENGTH ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */
#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define pCAN_MB14_TIMESTAMP ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */
#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define pCAN_MB14_ID0 ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */
#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define pCAN_MB14_ID1 ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */
#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define pCAN_MB15_DATA0 ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define pCAN_MB15_DATA1 ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define pCAN_MB15_DATA2 ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define pCAN_MB15_DATA3 ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define pCAN_MB15_LENGTH ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */
#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define pCAN_MB15_TIMESTAMP ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */
#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define pCAN_MB15_ID0 ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */
#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define pCAN_MB15_ID1 ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */
#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define pCAN_MB16_DATA0 ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define pCAN_MB16_DATA1 ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define pCAN_MB16_DATA2 ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define pCAN_MB16_DATA3 ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define pCAN_MB16_LENGTH ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */
#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define pCAN_MB16_TIMESTAMP ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */
#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define pCAN_MB16_ID0 ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */
#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define pCAN_MB16_ID1 ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */
#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define pCAN_MB17_DATA0 ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define pCAN_MB17_DATA1 ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define pCAN_MB17_DATA2 ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define pCAN_MB17_DATA3 ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define pCAN_MB17_LENGTH ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */
#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define pCAN_MB17_TIMESTAMP ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */
#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define pCAN_MB17_ID0 ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */
#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define pCAN_MB17_ID1 ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */
#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define pCAN_MB18_DATA0 ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define pCAN_MB18_DATA1 ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define pCAN_MB18_DATA2 ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define pCAN_MB18_DATA3 ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define pCAN_MB18_LENGTH ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */
#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define pCAN_MB18_TIMESTAMP ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */
#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define pCAN_MB18_ID0 ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */
#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define pCAN_MB18_ID1 ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */
#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define pCAN_MB19_DATA0 ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define pCAN_MB19_DATA1 ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define pCAN_MB19_DATA2 ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define pCAN_MB19_DATA3 ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define pCAN_MB19_LENGTH ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */
#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define pCAN_MB19_TIMESTAMP ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */
#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define pCAN_MB19_ID0 ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */
#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define pCAN_MB19_ID1 ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */
#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define pCAN_MB20_DATA0 ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define pCAN_MB20_DATA1 ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define pCAN_MB20_DATA2 ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define pCAN_MB20_DATA3 ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define pCAN_MB20_LENGTH ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */
#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define pCAN_MB20_TIMESTAMP ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */
#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define pCAN_MB20_ID0 ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */
#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define pCAN_MB20_ID1 ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */
#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define pCAN_MB21_DATA0 ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define pCAN_MB21_DATA1 ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define pCAN_MB21_DATA2 ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define pCAN_MB21_DATA3 ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define pCAN_MB21_LENGTH ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */
#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define pCAN_MB21_TIMESTAMP ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */
#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define pCAN_MB21_ID0 ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */
#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define pCAN_MB21_ID1 ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */
#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define pCAN_MB22_DATA0 ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define pCAN_MB22_DATA1 ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define pCAN_MB22_DATA2 ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define pCAN_MB22_DATA3 ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define pCAN_MB22_LENGTH ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */
#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define pCAN_MB22_TIMESTAMP ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */
#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define pCAN_MB22_ID0 ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */
#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define pCAN_MB22_ID1 ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */
#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define pCAN_MB23_DATA0 ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define pCAN_MB23_DATA1 ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define pCAN_MB23_DATA2 ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define pCAN_MB23_DATA3 ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define pCAN_MB23_LENGTH ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */
#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define pCAN_MB23_TIMESTAMP ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */
#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define pCAN_MB23_ID0 ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */
#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define pCAN_MB23_ID1 ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */
#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define pCAN_MB24_DATA0 ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define pCAN_MB24_DATA1 ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define pCAN_MB24_DATA2 ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define pCAN_MB24_DATA3 ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define pCAN_MB24_LENGTH ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */
#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define pCAN_MB24_TIMESTAMP ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */
#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define pCAN_MB24_ID0 ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */
#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define pCAN_MB24_ID1 ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */
#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define pCAN_MB25_DATA0 ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define pCAN_MB25_DATA1 ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define pCAN_MB25_DATA2 ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define pCAN_MB25_DATA3 ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define pCAN_MB25_LENGTH ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */
#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define pCAN_MB25_TIMESTAMP ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */
#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define pCAN_MB25_ID0 ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */
#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define pCAN_MB25_ID1 ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */
#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define pCAN_MB26_DATA0 ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define pCAN_MB26_DATA1 ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define pCAN_MB26_DATA2 ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define pCAN_MB26_DATA3 ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define pCAN_MB26_LENGTH ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */
#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define pCAN_MB26_TIMESTAMP ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */
#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define pCAN_MB26_ID0 ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */
#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define pCAN_MB26_ID1 ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */
#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define pCAN_MB27_DATA0 ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define pCAN_MB27_DATA1 ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define pCAN_MB27_DATA2 ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define pCAN_MB27_DATA3 ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define pCAN_MB27_LENGTH ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */
#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define pCAN_MB27_TIMESTAMP ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */
#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define pCAN_MB27_ID0 ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */
#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define pCAN_MB27_ID1 ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */
#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define pCAN_MB28_DATA0 ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define pCAN_MB28_DATA1 ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define pCAN_MB28_DATA2 ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define pCAN_MB28_DATA3 ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define pCAN_MB28_LENGTH ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */
#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define pCAN_MB28_TIMESTAMP ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */
#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define pCAN_MB28_ID0 ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */
#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define pCAN_MB28_ID1 ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */
#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define pCAN_MB29_DATA0 ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define pCAN_MB29_DATA1 ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define pCAN_MB29_DATA2 ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define pCAN_MB29_DATA3 ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define pCAN_MB29_LENGTH ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */
#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define pCAN_MB29_TIMESTAMP ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */
#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define pCAN_MB29_ID0 ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */
#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define pCAN_MB29_ID1 ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */
#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define pCAN_MB30_DATA0 ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define pCAN_MB30_DATA1 ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define pCAN_MB30_DATA2 ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define pCAN_MB30_DATA3 ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define pCAN_MB30_LENGTH ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */
#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define pCAN_MB30_TIMESTAMP ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */
#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define pCAN_MB30_ID0 ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */
#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define pCAN_MB30_ID1 ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */
#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define pCAN_MB31_DATA0 ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */
#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define pCAN_MB31_DATA1 ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */
#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define pCAN_MB31_DATA2 ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */
#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define pCAN_MB31_DATA3 ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */
#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define pCAN_MB31_LENGTH ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */
#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define pCAN_MB31_TIMESTAMP ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */
#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define pCAN_MB31_ID0 ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */
#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define pCAN_MB31_ID1 ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */
#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORT_MUX ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */
#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-#define pPFCTL ((uint32_t volatile *)PFCTL)
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER)
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
#ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__
#define __BFIN_DEF_ADSP_EDN_BF534_extended__
+#include "../mach-common/ADSP-EDN-core_def.h"
+
#define PLL_CTL 0xFFC00000 /* PLL Control Register */
#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */
-#define DCPLB_FAULT_ADDR 0xFFE0000C
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008
-#define ICPLB_FAULT_ADDR 0xFFE0100C
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#define CHIPID 0xFFC00014
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-#define PFCTL 0xFFE08000
-#define PFCNTR0 0xFFE08100
-#define PFCNTR1 0xFFE08104
#define DMA_TC_CNT 0xFFC00B0C
#define DMA_TC_PER 0xFFC00B10
#include "ADSP-EDN-BF534-extended_def.h"
+#if defined(__BFIN_DEF_ADSP_BF537_proc__) || !defined(__BFIN_DEF_ADSP_BF536_proc__)
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#endif
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#ifndef __BFIN_CDEF_ADSP_BF536_proc__
#define __BFIN_CDEF_ADSP_BF536_proc__
-#include "../mach-common/ADSP-EDN-core_cdef.h"
+#include "BF534_cdef.h"
-#include "ADSP-EDN-BF534-extended_cdef.h"
-
-#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
#ifndef __BFIN_DEF_ADSP_BF536_proc__
#define __BFIN_DEF_ADSP_BF536_proc__
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF534-extended_def.h"
+#include "BF534_def.h"
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
-#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
-#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
-#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
-#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
-#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF536_proc__ */
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF537_proc__
-#define __BFIN_CDEF_ADSP_BF537_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF534-extended_cdef.h"
-
-#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF537_proc__ */
+#include "BF536_cdef.h"
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF537_proc__
-#define __BFIN_DEF_ADSP_BF537_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF534-extended_def.h"
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
-#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
-#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
-#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
-#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
-#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF537_proc__ */
+#include "BF536_def.h"
*/
/* This file should be up to date with:
- * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
+#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF538_proc__
+#define __BFIN_CDEF_ADSP_BF538_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
+#define bfin_read_SWRST() bfin_read16(SWRST)
+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
+#define bfin_read_SYSCR() bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
+#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
+#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
+#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
+#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
+#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
+#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
+#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
+#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
+#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
+#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
+#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
+#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
+#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
+#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
+#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
+#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
+#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
+#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
+#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
+#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
+#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
+#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
+#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
+#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
+#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
+#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
+#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
+#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
+#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
+#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
+#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
+#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
+#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
+#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
+#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
+#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
+#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
+#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
+#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
+#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
+#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
+#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
+#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
+#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
+#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
+#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
+#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
+#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
+#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
+#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
+#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
+#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
+#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
+#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
+#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
+#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
+#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
+#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
+#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
+#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
+#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
+#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
+#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
+#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
+#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
+#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
+#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
+#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
+#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
+#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
+#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
+#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
+#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
+#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
+#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
+#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
+#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
+#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
+#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
+#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
+#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
+#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
+#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
+#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
+#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
+#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
+#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
+#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
+#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
+#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
+#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
+#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
+#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
+#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
+#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
+#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
+#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
+#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
+#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
+#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
+#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
+#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
+#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
+#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
+#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
+#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
+#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
+#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
+#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
+#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
+#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
+#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
+#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
+#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
+#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
+#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
+#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
+#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
+#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
+#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
+#define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER)
+#define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val)
+#define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT)
+#define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
+#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
+#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
+#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
+#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
+#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
+#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
+#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
+#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
+#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
+#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
+#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
+#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
+#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
+#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
+#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
+#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
+#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
+#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
+#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
+#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
+#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
+#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
+#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
+#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
+#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
+#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
+#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
+#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
+#define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG)
+#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
+#define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT)
+#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
+#define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY)
+#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
+#define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT)
+#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
+#define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY)
+#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
+#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
+#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
+#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
+#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
+#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
+#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
+#define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG)
+#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
+#define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT)
+#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
+#define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY)
+#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
+#define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT)
+#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
+#define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY)
+#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
+#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
+#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
+#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
+#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
+#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
+#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
+#define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG)
+#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
+#define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT)
+#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
+#define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY)
+#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
+#define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT)
+#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
+#define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY)
+#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
+#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
+#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
+#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
+#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
+#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
+#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
+#define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG)
+#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
+#define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT)
+#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
+#define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY)
+#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
+#define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT)
+#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
+#define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY)
+#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
+#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
+#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
+#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
+#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
+#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
+#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
+#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
+#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
+#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
+#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
+#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
+#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
+#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
+#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
+#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
+#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
+#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
+#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
+#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
+#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
+#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
+#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
+#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
+#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
+#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
+#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
+#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
+#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
+#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
+#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
+#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
+#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
+#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
+#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
+#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
+#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
+#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
+#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
+#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
+#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
+#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
+#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
+#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
+#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
+#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
+#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
+#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
+#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
+#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
+#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
+#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
+#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
+#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
+#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
+#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
+#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
+#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
+#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
+#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
+#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
+#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
+#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
+#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
+#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
+#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
+#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
+#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
+#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
+#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
+#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
+#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
+#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
+#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
+#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
+#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
+#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
+#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
+#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
+#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
+#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
+#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
+#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
+#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
+#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
+#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
+#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
+#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
+#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
+#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
+#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
+#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
+#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
+#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
+#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
+#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
+#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
+#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
+#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
+#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
+#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
+#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
+#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
+#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
+#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
+#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
+#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
+#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
+#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
+#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
+#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
+#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
+#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
+#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
+#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
+#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
+#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
+#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
+#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
+#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
+#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
+#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
+#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
+#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
+#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
+#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
+#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
+#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
+#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
+#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
+#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
+#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
+#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
+#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
+#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
+#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
+#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
+#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
+#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
+#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
+#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
+#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
+#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
+#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
+#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
+#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
+#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
+#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
+#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
+#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
+#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
+#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
+#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
+#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
+#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
+#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
+#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
+#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
+#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
+#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
+#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
+#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
+#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
+#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
+#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
+#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
+#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
+#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
+#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
+#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
+#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
+#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
+#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
+#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
+#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
+#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
+#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
+#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
+#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
+#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
+#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
+#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
+#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
+#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
+#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
+#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
+#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
+#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
+#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
+#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
+#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
+#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
+#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
+#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
+#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
+#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
+#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
+#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
+#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
+#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
+#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
+#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
+#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
+#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
+#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
+#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
+#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
+#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
+#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
+#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
+#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
+#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
+#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
+#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
+#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
+#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
+#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
+#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
+#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
+#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
+#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
+#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
+#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
+#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
+#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
+#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
+#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
+#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
+#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
+#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
+#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
+#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
+#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
+#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
+#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
+#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
+#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
+#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
+#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
+#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
+#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
+#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
+#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
+#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
+#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
+#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
+#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
+#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
+#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
+#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
+#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
+#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
+#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
+#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
+#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
+#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
+#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
+#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
+#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
+#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
+#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
+#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
+#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
+#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
+#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
+#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
+#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
+#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
+#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
+#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
+#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
+#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
+#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
+#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
+#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
+#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
+#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
+#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
+#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
+#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
+#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
+#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
+#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
+#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
+#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
+#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
+#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
+#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
+#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
+#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
+#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
+#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
+#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
+#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
+#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
+#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
+#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
+#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
+#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
+#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
+#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
+#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
+#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
+#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
+#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
+#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
+#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
+#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
+#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
+#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
+#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
+#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
+#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
+#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
+#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
+#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
+#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
+#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
+#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
+#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
+#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
+#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
+#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
+#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
+#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
+#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
+#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
+#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
+#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
+#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
+#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
+#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
+#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
+#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
+#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
+#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
+#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
+#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
+#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
+#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
+#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
+#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
+#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
+#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
+#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
+#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
+#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
+#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
+#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
+#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
+#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
+#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
+#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
+#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
+#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
+#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
+#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
+#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
+#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
+#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
+#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
+#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
+#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
+#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
+#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
+#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
+#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
+#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
+#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
+#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
+#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
+#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
+#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
+#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
+#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
+#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
+#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
+#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
+#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
+#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
+#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
+#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
+#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
+#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
+#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
+#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
+#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
+#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
+#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
+#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
+#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
+#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
+#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
+#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
+#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
+#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
+#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
+#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
+#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
+#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
+#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
+#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
+#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
+#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
+#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
+#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
+#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
+#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
+#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
+#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
+#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
+#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
+#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
+#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
+#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
+#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
+#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
+#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
+#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
+#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
+#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
+#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
+#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
+#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
+#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
+#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
+#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
+#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
+#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
+#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
+#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
+#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
+#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
+#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
+#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
+#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
+#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
+#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
+#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
+#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
+#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
+#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
+#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
+#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
+#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
+#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
+#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
+#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
+#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
+#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
+#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
+#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
+#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
+#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
+#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
+#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
+#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
+#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
+#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
+#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
+#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
+#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
+#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
+#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
+#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
+#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
+#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
+#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
+#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
+#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
+#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
+#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
+#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
+#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
+#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
+#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
+#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
+#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
+#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
+#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
+#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
+#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
+#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
+#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
+#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
+#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
+#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
+#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
+#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
+#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
+#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
+#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
+#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
+#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
+#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
+#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
+#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
+#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
+#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
+#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
+#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
+#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
+#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
+#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
+#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
+#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
+#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
+#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
+#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
+#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
+#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
+#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
+#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
+#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
+#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
+#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
+#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
+#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
+#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
+#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
+#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
+#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
+#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
+#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
+#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
+#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
+#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
+#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
+#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
+#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
+#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
+#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
+#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
+#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
+#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
+#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
+#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
+#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
+#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
+#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
+#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
+#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
+#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
+#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
+#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
+#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
+#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
+#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
+#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
+#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
+#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
+#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
+#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
+#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
+#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
+#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
+#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
+#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
+#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
+#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
+#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
+#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
+#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
+#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
+#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
+#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
+#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
+#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
+#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
+#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
+#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
+#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
+#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
+#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
+#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
+#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
+#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
+#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
+#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
+#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
+#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
+#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
+#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
+#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
+#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
+#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
+#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
+#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
+#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
+#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
+#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
+#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
+#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
+#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
+#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
+#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
+#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
+#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
+#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
+#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
+#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
+#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
+#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
+#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
+#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
+#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
+#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
+#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
+#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
+#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
+#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
+#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
+#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
+#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
+#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
+#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
+#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
+#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
+#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
+#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
+#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
+#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
+#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
+#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
+#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
+#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
+#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
+#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
+#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
+#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
+#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
+#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
+#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
+#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
+#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
+#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
+#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
+#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
+#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
+#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
+#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
+#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
+#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
+#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
+#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
+#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
+#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
+#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
+#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
+#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
+#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
+#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
+#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
+#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
+#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
+#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
+#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
+#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
+#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
+#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
+#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
+#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
+#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
+#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
+#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
+#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
+#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
+#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
+#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
+#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
+#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
+#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
+#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
+#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
+#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
+#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
+#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
+#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
+#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
+#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
+#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
+#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
+#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
+#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
+#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
+#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
+#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
+#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
+#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
+#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
+#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
+#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
+#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
+#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
+#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
+#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
+#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
+#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
+#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
+#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
+#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
+#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
+#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
+#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
+#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
+#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
+#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
+#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
+#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
+#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
+#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
+#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
+#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
+#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
+#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
+#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
+#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
+#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
+#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
+#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
+#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
+#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
+#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
+#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
+#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
+#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
+#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
+#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
+#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
+#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
+#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
+#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
+#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
+#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
+#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
+#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
+#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
+#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
+#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
+#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
+#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
+#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
+#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
+#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
+#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
+#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
+#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
+#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
+#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
+#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
+#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
+#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
+#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
+#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
+#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
+#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
+#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
+#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
+#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
+#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
+#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
+#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
+#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
+#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
+#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
+#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
+#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
+#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
+#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
+#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
+#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
+#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
+#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
+#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
+#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
+#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
+#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
+#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
+#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
+#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
+#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
+#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
+#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
+#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
+#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
+#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
+#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
+#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
+#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
+#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
+#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
+#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
+#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
+#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
+#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
+#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
+#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
+#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
+#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
+#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
+#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
+#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
+#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
+#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
+#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF538_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF538_proc__
+#define __BFIN_DEF_ADSP_BF538_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define CHIPID 0xFFC00014
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration register */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register 0 */
+#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
+#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register 0 */
+#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
+#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register 0 */
+#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
+#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
+#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT 0xFFC00300
+#define RTC_ICTL 0xFFC00304
+#define RTC_ISTAT 0xFFC00308
+#define RTC_SWCNT 0xFFC0030C
+#define RTC_ALARM 0xFFC00310
+#define RTC_PREN 0xFFC00314
+#define UART0_THR 0xFFC00400
+#define UART0_RBR 0xFFC00400
+#define UART0_DLL 0xFFC00400
+#define UART0_DLH 0xFFC00404
+#define UART0_IER 0xFFC00404
+#define UART0_IIR 0xFFC00408
+#define UART0_LCR 0xFFC0040C
+#define UART0_MCR 0xFFC00410
+#define UART0_LSR 0xFFC00414
+#define UART0_SCR 0xFFC0041C
+#define UART0_GCTL 0xFFC00424
+#define UART1_THR 0xFFC02000
+#define UART1_RBR 0xFFC02000
+#define UART1_DLL 0xFFC02000
+#define UART1_DLH 0xFFC02004
+#define UART1_IER 0xFFC02004
+#define UART1_IIR 0xFFC02008
+#define UART1_LCR 0xFFC0200C
+#define UART1_MCR 0xFFC02010
+#define UART1_LSR 0xFFC02014
+#define UART1_SCR 0xFFC0201C
+#define UART1_GCTL 0xFFC02024
+#define UART2_THR 0xFFC02100
+#define UART2_RBR 0xFFC02100
+#define UART2_DLL 0xFFC02100
+#define UART2_DLH 0xFFC02104
+#define UART2_IER 0xFFC02104
+#define UART2_IIR 0xFFC02108
+#define UART2_LCR 0xFFC0210C
+#define UART2_MCR 0xFFC02110
+#define UART2_LSR 0xFFC02114
+#define UART2_SCR 0xFFC0211C
+#define UART2_GCTL 0xFFC02124
+#define SPI0_CTL 0xFFC00500
+#define SPI0_FLG 0xFFC00504
+#define SPI0_STAT 0xFFC00508
+#define SPI0_TDBR 0xFFC0050C
+#define SPI0_RDBR 0xFFC00510
+#define SPI0_BAUD 0xFFC00514
+#define SPI0_SHADOW 0xFFC00518
+#define SPI1_CTL 0xFFC02300
+#define SPI1_FLG 0xFFC02304
+#define SPI1_STAT 0xFFC02308
+#define SPI1_TDBR 0xFFC0230C
+#define SPI1_RDBR 0xFFC02310
+#define SPI1_BAUD 0xFFC02314
+#define SPI1_SHADOW 0xFFC02318
+#define SPI2_CTL 0xFFC02400
+#define SPI2_FLG 0xFFC02404
+#define SPI2_STAT 0xFFC02408
+#define SPI2_TDBR 0xFFC0240C
+#define SPI2_RDBR 0xFFC02410
+#define SPI2_BAUD 0xFFC02414
+#define SPI2_SHADOW 0xFFC02418
+#define TIMER0_CONFIG 0xFFC00600
+#define TIMER0_COUNTER 0xFFC00604
+#define TIMER0_PERIOD 0xFFC00608
+#define TIMER0_WIDTH 0xFFC0060C
+#define TIMER1_CONFIG 0xFFC00610
+#define TIMER1_COUNTER 0xFFC00614
+#define TIMER1_PERIOD 0xFFC00618
+#define TIMER1_WIDTH 0xFFC0061C
+#define TIMER2_CONFIG 0xFFC00620
+#define TIMER2_COUNTER 0xFFC00624
+#define TIMER2_PERIOD 0xFFC00628
+#define TIMER2_WIDTH 0xFFC0062C
+#define TIMER_ENABLE 0xFFC00640
+#define TIMER_DISABLE 0xFFC00644
+#define TIMER_STATUS 0xFFC00648
+#define SPORT0_TCR1 0xFFC00800
+#define SPORT0_TCR2 0xFFC00804
+#define SPORT0_TCLKDIV 0xFFC00808
+#define SPORT0_TFSDIV 0xFFC0080C
+#define SPORT0_TX 0xFFC00810
+#define SPORT0_RX 0xFFC00818
+#define SPORT0_RCR1 0xFFC00820
+#define SPORT0_RCR2 0xFFC00824
+#define SPORT0_RCLKDIV 0xFFC00828
+#define SPORT0_RFSDIV 0xFFC0082C
+#define SPORT0_STAT 0xFFC00830
+#define SPORT0_CHNL 0xFFC00834
+#define SPORT0_MCMC1 0xFFC00838
+#define SPORT0_MCMC2 0xFFC0083C
+#define SPORT0_MTCS0 0xFFC00840
+#define SPORT0_MTCS1 0xFFC00844
+#define SPORT0_MTCS2 0xFFC00848
+#define SPORT0_MTCS3 0xFFC0084C
+#define SPORT0_MRCS0 0xFFC00850
+#define SPORT0_MRCS1 0xFFC00854
+#define SPORT0_MRCS2 0xFFC00858
+#define SPORT0_MRCS3 0xFFC0085C
+#define SPORT1_TCR1 0xFFC00900
+#define SPORT1_TCR2 0xFFC00904
+#define SPORT1_TCLKDIV 0xFFC00908
+#define SPORT1_TFSDIV 0xFFC0090C
+#define SPORT1_TX 0xFFC00910
+#define SPORT1_RX 0xFFC00918
+#define SPORT1_RCR1 0xFFC00920
+#define SPORT1_RCR2 0xFFC00924
+#define SPORT1_RCLKDIV 0xFFC00928
+#define SPORT1_RFSDIV 0xFFC0092C
+#define SPORT1_STAT 0xFFC00930
+#define SPORT1_CHNL 0xFFC00934
+#define SPORT1_MCMC1 0xFFC00938
+#define SPORT1_MCMC2 0xFFC0093C
+#define SPORT1_MTCS0 0xFFC00940
+#define SPORT1_MTCS1 0xFFC00944
+#define SPORT1_MTCS2 0xFFC00948
+#define SPORT1_MTCS3 0xFFC0094C
+#define SPORT1_MRCS0 0xFFC00950
+#define SPORT1_MRCS1 0xFFC00954
+#define SPORT1_MRCS2 0xFFC00958
+#define SPORT1_MRCS3 0xFFC0095C
+#define SPORT2_TCR1 0xFFC02500
+#define SPORT2_TCR2 0xFFC02504
+#define SPORT2_TCLKDIV 0xFFC02508
+#define SPORT2_TFSDIV 0xFFC0250C
+#define SPORT2_TX 0xFFC02510
+#define SPORT2_RX 0xFFC02518
+#define SPORT2_RCR1 0xFFC02520
+#define SPORT2_RCR2 0xFFC02524
+#define SPORT2_RCLKDIV 0xFFC02528
+#define SPORT2_RFSDIV 0xFFC0252C
+#define SPORT2_STAT 0xFFC02530
+#define SPORT2_CHNL 0xFFC02534
+#define SPORT2_MCMC1 0xFFC02538
+#define SPORT2_MCMC2 0xFFC0253C
+#define SPORT2_MTCS0 0xFFC02540
+#define SPORT2_MTCS1 0xFFC02544
+#define SPORT2_MTCS2 0xFFC02548
+#define SPORT2_MTCS3 0xFFC0254C
+#define SPORT2_MRCS0 0xFFC02550
+#define SPORT2_MRCS1 0xFFC02554
+#define SPORT2_MRCS2 0xFFC02558
+#define SPORT2_MRCS3 0xFFC0255C
+#define SPORT3_TCR1 0xFFC02600
+#define SPORT3_TCR2 0xFFC02604
+#define SPORT3_TCLKDIV 0xFFC02608
+#define SPORT3_TFSDIV 0xFFC0260C
+#define SPORT3_TX 0xFFC02610
+#define SPORT3_RX 0xFFC02618
+#define SPORT3_RCR1 0xFFC02620
+#define SPORT3_RCR2 0xFFC02624
+#define SPORT3_RCLKDIV 0xFFC02628
+#define SPORT3_RFSDIV 0xFFC0262C
+#define SPORT3_STAT 0xFFC02630
+#define SPORT3_CHNL 0xFFC02634
+#define SPORT3_MCMC1 0xFFC02638
+#define SPORT3_MCMC2 0xFFC0263C
+#define SPORT3_MTCS0 0xFFC02640
+#define SPORT3_MTCS1 0xFFC02644
+#define SPORT3_MTCS2 0xFFC02648
+#define SPORT3_MTCS3 0xFFC0264C
+#define SPORT3_MRCS0 0xFFC02650
+#define SPORT3_MRCS1 0xFFC02654
+#define SPORT3_MRCS2 0xFFC02658
+#define SPORT3_MRCS3 0xFFC0265C
+#define PORTFIO 0xFFC00700
+#define PORTFIO_CLEAR 0xFFC00704
+#define PORTFIO_SET 0xFFC00708
+#define PORTFIO_TOGGLE 0xFFC0070C
+#define PORTFIO_MASKA 0xFFC00710
+#define PORTFIO_MASKA_CLEAR 0xFFC00714
+#define PORTFIO_MASKA_SET 0xFFC00718
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C
+#define PORTFIO_MASKB 0xFFC00720
+#define PORTFIO_MASKB_CLEAR 0xFFC00724
+#define PORTFIO_MASKB_SET 0xFFC00728
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C
+#define PORTFIO_DIR 0xFFC00730
+#define PORTFIO_POLAR 0xFFC00734
+#define PORTFIO_EDGE 0xFFC00738
+#define PORTFIO_BOTH 0xFFC0073C
+#define PORTFIO_INEN 0xFFC00740
+#define PORTCIO_FER 0xFFC01500
+#define PORTCIO 0xFFC01510
+#define PORTCIO_CLEAR 0xFFC01520
+#define PORTCIO_SET 0xFFC01530
+#define PORTCIO_TOGGLE 0xFFC01540
+#define PORTCIO_DIR 0xFFC01550
+#define PORTCIO_INEN 0xFFC01560
+#define PORTDIO_FER 0xFFC01504
+#define PORTDIO 0xFFC01514
+#define PORTDIO_CLEAR 0xFFC01524
+#define PORTDIO_SET 0xFFC01534
+#define PORTDIO_TOGGLE 0xFFC01544
+#define PORTDIO_DIR 0xFFC01554
+#define PORTDIO_INEN 0xFFC01564
+#define PORTEIO_FER 0xFFC01508
+#define PORTEIO 0xFFC01518
+#define PORTEIO_CLEAR 0xFFC01528
+#define PORTEIO_SET 0xFFC01538
+#define PORTEIO_TOGGLE 0xFFC01548
+#define PORTEIO_DIR 0xFFC01558
+#define PORTEIO_INEN 0xFFC01568
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+#define DMA0_TC_PER 0xFFC00B0C /* Traffic Control Periods */
+#define DMA0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00
+#define DMA0_START_ADDR 0xFFC00C04
+#define DMA0_CONFIG 0xFFC00C08
+#define DMA0_X_COUNT 0xFFC00C10
+#define DMA0_X_MODIFY 0xFFC00C14
+#define DMA0_Y_COUNT 0xFFC00C18
+#define DMA0_Y_MODIFY 0xFFC00C1C
+#define DMA0_CURR_DESC_PTR 0xFFC00C20
+#define DMA0_CURR_ADDR 0xFFC00C24
+#define DMA0_IRQ_STATUS 0xFFC00C28
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
+#define DMA0_CURR_X_COUNT 0xFFC00C30
+#define DMA0_CURR_Y_COUNT 0xFFC00C38
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40
+#define DMA1_START_ADDR 0xFFC00C44
+#define DMA1_CONFIG 0xFFC00C48
+#define DMA1_X_COUNT 0xFFC00C50
+#define DMA1_X_MODIFY 0xFFC00C54
+#define DMA1_Y_COUNT 0xFFC00C58
+#define DMA1_Y_MODIFY 0xFFC00C5C
+#define DMA1_CURR_DESC_PTR 0xFFC00C60
+#define DMA1_CURR_ADDR 0xFFC00C64
+#define DMA1_IRQ_STATUS 0xFFC00C68
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
+#define DMA1_CURR_X_COUNT 0xFFC00C70
+#define DMA1_CURR_Y_COUNT 0xFFC00C78
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80
+#define DMA2_START_ADDR 0xFFC00C84
+#define DMA2_CONFIG 0xFFC00C88
+#define DMA2_X_COUNT 0xFFC00C90
+#define DMA2_X_MODIFY 0xFFC00C94
+#define DMA2_Y_COUNT 0xFFC00C98
+#define DMA2_Y_MODIFY 0xFFC00C9C
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0
+#define DMA2_CURR_ADDR 0xFFC00CA4
+#define DMA2_IRQ_STATUS 0xFFC00CA8
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
+#define DMA2_CURR_X_COUNT 0xFFC00CB0
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
+#define DMA3_START_ADDR 0xFFC00CC4
+#define DMA3_CONFIG 0xFFC00CC8
+#define DMA3_X_COUNT 0xFFC00CD0
+#define DMA3_X_MODIFY 0xFFC00CD4
+#define DMA3_Y_COUNT 0xFFC00CD8
+#define DMA3_Y_MODIFY 0xFFC00CDC
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0
+#define DMA3_CURR_ADDR 0xFFC00CE4
+#define DMA3_IRQ_STATUS 0xFFC00CE8
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
+#define DMA3_CURR_X_COUNT 0xFFC00CF0
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00
+#define DMA4_START_ADDR 0xFFC00D04
+#define DMA4_CONFIG 0xFFC00D08
+#define DMA4_X_COUNT 0xFFC00D10
+#define DMA4_X_MODIFY 0xFFC00D14
+#define DMA4_Y_COUNT 0xFFC00D18
+#define DMA4_Y_MODIFY 0xFFC00D1C
+#define DMA4_CURR_DESC_PTR 0xFFC00D20
+#define DMA4_CURR_ADDR 0xFFC00D24
+#define DMA4_IRQ_STATUS 0xFFC00D28
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
+#define DMA4_CURR_X_COUNT 0xFFC00D30
+#define DMA4_CURR_Y_COUNT 0xFFC00D38
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40
+#define DMA5_START_ADDR 0xFFC00D44
+#define DMA5_CONFIG 0xFFC00D48
+#define DMA5_X_COUNT 0xFFC00D50
+#define DMA5_X_MODIFY 0xFFC00D54
+#define DMA5_Y_COUNT 0xFFC00D58
+#define DMA5_Y_MODIFY 0xFFC00D5C
+#define DMA5_CURR_DESC_PTR 0xFFC00D60
+#define DMA5_CURR_ADDR 0xFFC00D64
+#define DMA5_IRQ_STATUS 0xFFC00D68
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
+#define DMA5_CURR_X_COUNT 0xFFC00D70
+#define DMA5_CURR_Y_COUNT 0xFFC00D78
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80
+#define DMA6_START_ADDR 0xFFC00D84
+#define DMA6_CONFIG 0xFFC00D88
+#define DMA6_X_COUNT 0xFFC00D90
+#define DMA6_X_MODIFY 0xFFC00D94
+#define DMA6_Y_COUNT 0xFFC00D98
+#define DMA6_Y_MODIFY 0xFFC00D9C
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0
+#define DMA6_CURR_ADDR 0xFFC00DA4
+#define DMA6_IRQ_STATUS 0xFFC00DA8
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
+#define DMA6_CURR_X_COUNT 0xFFC00DB0
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
+#define DMA7_START_ADDR 0xFFC00DC4
+#define DMA7_CONFIG 0xFFC00DC8
+#define DMA7_X_COUNT 0xFFC00DD0
+#define DMA7_X_MODIFY 0xFFC00DD4
+#define DMA7_Y_COUNT 0xFFC00DD8
+#define DMA7_Y_MODIFY 0xFFC00DDC
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0
+#define DMA7_CURR_ADDR 0xFFC00DE4
+#define DMA7_IRQ_STATUS 0xFFC00DE8
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
+#define DMA7_CURR_X_COUNT 0xFFC00DF0
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8
+#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
+#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
+#define DMA8_NEXT_DESC_PTR 0xFFC01C00
+#define DMA8_START_ADDR 0xFFC01C04
+#define DMA8_CONFIG 0xFFC01C08
+#define DMA8_X_COUNT 0xFFC01C10
+#define DMA8_X_MODIFY 0xFFC01C14
+#define DMA8_Y_COUNT 0xFFC01C18
+#define DMA8_Y_MODIFY 0xFFC01C1C
+#define DMA8_CURR_DESC_PTR 0xFFC01C20
+#define DMA8_CURR_ADDR 0xFFC01C24
+#define DMA8_IRQ_STATUS 0xFFC01C28
+#define DMA8_PERIPHERAL_MAP 0xFFC01C2C
+#define DMA8_CURR_X_COUNT 0xFFC01C30
+#define DMA8_CURR_Y_COUNT 0xFFC01C38
+#define DMA9_NEXT_DESC_PTR 0xFFC01C40
+#define DMA9_START_ADDR 0xFFC01C44
+#define DMA9_CONFIG 0xFFC01C48
+#define DMA9_X_COUNT 0xFFC01C50
+#define DMA9_X_MODIFY 0xFFC01C54
+#define DMA9_Y_COUNT 0xFFC01C58
+#define DMA9_Y_MODIFY 0xFFC01C5C
+#define DMA9_CURR_DESC_PTR 0xFFC01C60
+#define DMA9_CURR_ADDR 0xFFC01C64
+#define DMA9_IRQ_STATUS 0xFFC01C68
+#define DMA9_PERIPHERAL_MAP 0xFFC01C6C
+#define DMA9_CURR_X_COUNT 0xFFC01C70
+#define DMA9_CURR_Y_COUNT 0xFFC01C78
+#define DMA10_NEXT_DESC_PTR 0xFFC01C80
+#define DMA10_START_ADDR 0xFFC01C84
+#define DMA10_CONFIG 0xFFC01C88
+#define DMA10_X_COUNT 0xFFC01C90
+#define DMA10_X_MODIFY 0xFFC01C94
+#define DMA10_Y_COUNT 0xFFC01C98
+#define DMA10_Y_MODIFY 0xFFC01C9C
+#define DMA10_CURR_DESC_PTR 0xFFC01CA0
+#define DMA10_CURR_ADDR 0xFFC01CA4
+#define DMA10_IRQ_STATUS 0xFFC01CA8
+#define DMA10_PERIPHERAL_MAP 0xFFC01CAC
+#define DMA10_CURR_X_COUNT 0xFFC01CB0
+#define DMA10_CURR_Y_COUNT 0xFFC01CB8
+#define DMA11_NEXT_DESC_PTR 0xFFC01CC0
+#define DMA11_START_ADDR 0xFFC01CC4
+#define DMA11_CONFIG 0xFFC01CC8
+#define DMA11_X_COUNT 0xFFC01CD0
+#define DMA11_X_MODIFY 0xFFC01CD4
+#define DMA11_Y_COUNT 0xFFC01CD8
+#define DMA11_Y_MODIFY 0xFFC01CDC
+#define DMA11_CURR_DESC_PTR 0xFFC01CE0
+#define DMA11_CURR_ADDR 0xFFC01CE4
+#define DMA11_IRQ_STATUS 0xFFC01CE8
+#define DMA11_PERIPHERAL_MAP 0xFFC01CEC
+#define DMA11_CURR_X_COUNT 0xFFC01CF0
+#define DMA11_CURR_Y_COUNT 0xFFC01CF8
+#define DMA12_NEXT_DESC_PTR 0xFFC01D00
+#define DMA12_START_ADDR 0xFFC01D04
+#define DMA12_CONFIG 0xFFC01D08
+#define DMA12_X_COUNT 0xFFC01D10
+#define DMA12_X_MODIFY 0xFFC01D14
+#define DMA12_Y_COUNT 0xFFC01D18
+#define DMA12_Y_MODIFY 0xFFC01D1C
+#define DMA12_CURR_DESC_PTR 0xFFC01D20
+#define DMA12_CURR_ADDR 0xFFC01D24
+#define DMA12_IRQ_STATUS 0xFFC01D28
+#define DMA12_PERIPHERAL_MAP 0xFFC01D2C
+#define DMA12_CURR_X_COUNT 0xFFC01D30
+#define DMA12_CURR_Y_COUNT 0xFFC01D38
+#define DMA13_NEXT_DESC_PTR 0xFFC01D40
+#define DMA13_START_ADDR 0xFFC01D44
+#define DMA13_CONFIG 0xFFC01D48
+#define DMA13_X_COUNT 0xFFC01D50
+#define DMA13_X_MODIFY 0xFFC01D54
+#define DMA13_Y_COUNT 0xFFC01D58
+#define DMA13_Y_MODIFY 0xFFC01D5C
+#define DMA13_CURR_DESC_PTR 0xFFC01D60
+#define DMA13_CURR_ADDR 0xFFC01D64
+#define DMA13_IRQ_STATUS 0xFFC01D68
+#define DMA13_PERIPHERAL_MAP 0xFFC01D6C
+#define DMA13_CURR_X_COUNT 0xFFC01D70
+#define DMA13_CURR_Y_COUNT 0xFFC01D78
+#define DMA14_NEXT_DESC_PTR 0xFFC01D80
+#define DMA14_START_ADDR 0xFFC01D84
+#define DMA14_CONFIG 0xFFC01D88
+#define DMA14_X_COUNT 0xFFC01D90
+#define DMA14_X_MODIFY 0xFFC01D94
+#define DMA14_Y_COUNT 0xFFC01D98
+#define DMA14_Y_MODIFY 0xFFC01D9C
+#define DMA14_CURR_DESC_PTR 0xFFC01DA0
+#define DMA14_CURR_ADDR 0xFFC01DA4
+#define DMA14_IRQ_STATUS 0xFFC01DA8
+#define DMA14_PERIPHERAL_MAP 0xFFC01DAC
+#define DMA14_CURR_X_COUNT 0xFFC01DB0
+#define DMA14_CURR_Y_COUNT 0xFFC01DB8
+#define DMA15_NEXT_DESC_PTR 0xFFC01DC0
+#define DMA15_START_ADDR 0xFFC01DC4
+#define DMA15_CONFIG 0xFFC01DC8
+#define DMA15_X_COUNT 0xFFC01DD0
+#define DMA15_X_MODIFY 0xFFC01DD4
+#define DMA15_Y_COUNT 0xFFC01DD8
+#define DMA15_Y_MODIFY 0xFFC01DDC
+#define DMA15_CURR_DESC_PTR 0xFFC01DE0
+#define DMA15_CURR_ADDR 0xFFC01DE4
+#define DMA15_IRQ_STATUS 0xFFC01DE8
+#define DMA15_PERIPHERAL_MAP 0xFFC01DEC
+#define DMA15_CURR_X_COUNT 0xFFC01DF0
+#define DMA15_CURR_Y_COUNT 0xFFC01DF8
+#define DMA16_NEXT_DESC_PTR 0xFFC01E00
+#define DMA16_START_ADDR 0xFFC01E04
+#define DMA16_CONFIG 0xFFC01E08
+#define DMA16_X_COUNT 0xFFC01E10
+#define DMA16_X_MODIFY 0xFFC01E14
+#define DMA16_Y_COUNT 0xFFC01E18
+#define DMA16_Y_MODIFY 0xFFC01E1C
+#define DMA16_CURR_DESC_PTR 0xFFC01E20
+#define DMA16_CURR_ADDR 0xFFC01E24
+#define DMA16_IRQ_STATUS 0xFFC01E28
+#define DMA16_PERIPHERAL_MAP 0xFFC01E2C
+#define DMA16_CURR_X_COUNT 0xFFC01E30
+#define DMA16_CURR_Y_COUNT 0xFFC01E38
+#define DMA17_NEXT_DESC_PTR 0xFFC01E40
+#define DMA17_START_ADDR 0xFFC01E44
+#define DMA17_CONFIG 0xFFC01E48
+#define DMA17_X_COUNT 0xFFC01E50
+#define DMA17_X_MODIFY 0xFFC01E54
+#define DMA17_Y_COUNT 0xFFC01E58
+#define DMA17_Y_MODIFY 0xFFC01E5C
+#define DMA17_CURR_DESC_PTR 0xFFC01E60
+#define DMA17_CURR_ADDR 0xFFC01E64
+#define DMA17_IRQ_STATUS 0xFFC01E68
+#define DMA17_PERIPHERAL_MAP 0xFFC01E6C
+#define DMA17_CURR_X_COUNT 0xFFC01E70
+#define DMA17_CURR_Y_COUNT 0xFFC01E78
+#define DMA18_NEXT_DESC_PTR 0xFFC01E80
+#define DMA18_START_ADDR 0xFFC01E84
+#define DMA18_CONFIG 0xFFC01E88
+#define DMA18_X_COUNT 0xFFC01E90
+#define DMA18_X_MODIFY 0xFFC01E94
+#define DMA18_Y_COUNT 0xFFC01E98
+#define DMA18_Y_MODIFY 0xFFC01E9C
+#define DMA18_CURR_DESC_PTR 0xFFC01EA0
+#define DMA18_CURR_ADDR 0xFFC01EA4
+#define DMA18_IRQ_STATUS 0xFFC01EA8
+#define DMA18_PERIPHERAL_MAP 0xFFC01EAC
+#define DMA18_CURR_X_COUNT 0xFFC01EB0
+#define DMA18_CURR_Y_COUNT 0xFFC01EB8
+#define DMA19_NEXT_DESC_PTR 0xFFC01EC0
+#define DMA19_START_ADDR 0xFFC01EC4
+#define DMA19_CONFIG 0xFFC01EC8
+#define DMA19_X_COUNT 0xFFC01ED0
+#define DMA19_X_MODIFY 0xFFC01ED4
+#define DMA19_Y_COUNT 0xFFC01ED8
+#define DMA19_Y_MODIFY 0xFFC01EDC
+#define DMA19_CURR_DESC_PTR 0xFFC01EE0
+#define DMA19_CURR_ADDR 0xFFC01EE4
+#define DMA19_IRQ_STATUS 0xFFC01EE8
+#define DMA19_PERIPHERAL_MAP 0xFFC01EEC
+#define DMA19_CURR_X_COUNT 0xFFC01EF0
+#define DMA19_CURR_Y_COUNT 0xFFC01EF8
+#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00
+#define MDMA0_D0_START_ADDR 0xFFC00E04
+#define MDMA0_D0_CONFIG 0xFFC00E08
+#define MDMA0_D0_X_COUNT 0xFFC00E10
+#define MDMA0_D0_X_MODIFY 0xFFC00E14
+#define MDMA0_D0_Y_COUNT 0xFFC00E18
+#define MDMA0_D0_Y_MODIFY 0xFFC00E1C
+#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20
+#define MDMA0_D0_CURR_ADDR 0xFFC00E24
+#define MDMA0_D0_IRQ_STATUS 0xFFC00E28
+#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C
+#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30
+#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38
+#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40
+#define MDMA0_S0_START_ADDR 0xFFC00E44
+#define MDMA0_S0_CONFIG 0xFFC00E48
+#define MDMA0_S0_X_COUNT 0xFFC00E50
+#define MDMA0_S0_X_MODIFY 0xFFC00E54
+#define MDMA0_S0_Y_COUNT 0xFFC00E58
+#define MDMA0_S0_Y_MODIFY 0xFFC00E5C
+#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60
+#define MDMA0_S0_CURR_ADDR 0xFFC00E64
+#define MDMA0_S0_IRQ_STATUS 0xFFC00E68
+#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C
+#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70
+#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78
+#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80
+#define MDMA0_D1_START_ADDR 0xFFC00E84
+#define MDMA0_D1_CONFIG 0xFFC00E88
+#define MDMA0_D1_X_COUNT 0xFFC00E90
+#define MDMA0_D1_X_MODIFY 0xFFC00E94
+#define MDMA0_D1_Y_COUNT 0xFFC00E98
+#define MDMA0_D1_Y_MODIFY 0xFFC00E9C
+#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0
+#define MDMA0_D1_CURR_ADDR 0xFFC00EA4
+#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8
+#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC
+#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0
+#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8
+#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0
+#define MDMA0_S1_START_ADDR 0xFFC00EC4
+#define MDMA0_S1_CONFIG 0xFFC00EC8
+#define MDMA0_S1_X_COUNT 0xFFC00ED0
+#define MDMA0_S1_X_MODIFY 0xFFC00ED4
+#define MDMA0_S1_Y_COUNT 0xFFC00ED8
+#define MDMA0_S1_Y_MODIFY 0xFFC00EDC
+#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0
+#define MDMA0_S1_CURR_ADDR 0xFFC00EE4
+#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8
+#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC
+#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0
+#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
+#define MDMA1_D0_START_ADDR 0xFFC01F04
+#define MDMA1_D0_CONFIG 0xFFC01F08
+#define MDMA1_D0_X_COUNT 0xFFC01F10
+#define MDMA1_D0_X_MODIFY 0xFFC01F14
+#define MDMA1_D0_Y_COUNT 0xFFC01F18
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
+#define MDMA1_S0_START_ADDR 0xFFC01F44
+#define MDMA1_S0_CONFIG 0xFFC01F48
+#define MDMA1_S0_X_COUNT 0xFFC01F50
+#define MDMA1_S0_X_MODIFY 0xFFC01F54
+#define MDMA1_S0_Y_COUNT 0xFFC01F58
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
+#define MDMA1_D1_START_ADDR 0xFFC01F84
+#define MDMA1_D1_CONFIG 0xFFC01F88
+#define MDMA1_D1_X_COUNT 0xFFC01F90
+#define MDMA1_D1_X_MODIFY 0xFFC01F94
+#define MDMA1_D1_Y_COUNT 0xFFC01F98
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
+#define MDMA1_S1_START_ADDR 0xFFC01FC4
+#define MDMA1_S1_CONFIG 0xFFC01FC8
+#define MDMA1_S1_X_COUNT 0xFFC01FD0
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
+#define PPI_CONTROL 0xFFC01000
+#define PPI_STATUS 0xFFC01004
+#define PPI_DELAY 0xFFC0100C
+#define PPI_COUNT 0xFFC01008
+#define PPI_FRAME 0xFFC01010
+#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI0_CONTROL 0xFFC01404 /* TWIO Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI0_INT_STAT 0xFFC01420 /* TWIO Master Interrupt Register */
+#define TWI0_INT_MASK 0xFFC01424 /* TWIO Master Interrupt Mask Register */
+#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
+#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
+#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
+#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
+#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
+#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
+#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
+#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
+#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
+#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
+#define CAN_DEBUG 0xFFC02A88 /* Config register */
+#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
+#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */
+#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
+#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */
+#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
+#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
+#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
+#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
+#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
+#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
+#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
+#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
+#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
+#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
+#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
+#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
+#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
+#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
+#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
+#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
+#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
+#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
+#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
+#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
+#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
+#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
+#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
+#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
+#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
+#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF538_proc__ */
--- /dev/null
+#include "BF538_cdef.h"
--- /dev/null
+#include "BF538_def.h"
--- /dev/null
+/*
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support old silicon - sorry */
+#if __SILICON_REVISION__ < 4
+# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
+#endif
+
+#if defined(__ADSPBF538__)
+# define ANOMALY_BF538 1
+#else
+# define ANOMALY_BF538 0
+#endif
+#if defined(__ADSPBF539__)
+# define ANOMALY_BF539 1
+#else
+# define ANOMALY_BF539 0
+#endif
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (1)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (1)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (1)
+/* SPI Slave Boot Mode Modifies Registers from Reset Value */
+#define ANOMALY_05000229 (1)
+/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
+#define ANOMALY_05000233 (1)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (1)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM Memory May Be Lost */
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
+/* False Hardware Error Exception when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
+/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
+/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
+#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
+/* Hibernate Leakage Current Is Higher Than Specified */
+#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
+/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000294 (1)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
+/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
+#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
+/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
+#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
+/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
+#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Specific GPIO Pins May Change State when Entering Hibernate */
+#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000182 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000220 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000234 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000254 (0)
+#define ANOMALY_05000257 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000430 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000485 (0)
+
+#endif
--- /dev/null
+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define BF538_FAMILY 1 /* Linux glue */
--- /dev/null
+/*
+ * Copyright (C) 2008-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 16
+#define BFIN_SPECIAL_GPIO_BANKS 3
+
+#define GPIO_PF0 0 /* PF */
+#define GPIO_PF1 1
+#define GPIO_PF2 2
+#define GPIO_PF3 3
+#define GPIO_PF4 4
+#define GPIO_PF5 5
+#define GPIO_PF6 6
+#define GPIO_PF7 7
+#define GPIO_PF8 8
+#define GPIO_PF9 9
+#define GPIO_PF10 10
+#define GPIO_PF11 11
+#define GPIO_PF12 12
+#define GPIO_PF13 13
+#define GPIO_PF14 14
+#define GPIO_PF15 15
+#define GPIO_PC0 16 /* PC */
+#define GPIO_PC1 17
+#define GPIO_PC4 20
+#define GPIO_PC5 21
+#define GPIO_PC6 22
+#define GPIO_PC7 23
+#define GPIO_PC8 24
+#define GPIO_PC9 25
+#define GPIO_PD0 32 /* PD */
+#define GPIO_PD1 33
+#define GPIO_PD2 34
+#define GPIO_PD3 35
+#define GPIO_PD4 36
+#define GPIO_PD5 37
+#define GPIO_PD6 38
+#define GPIO_PD7 39
+#define GPIO_PD8 40
+#define GPIO_PD9 41
+#define GPIO_PD10 42
+#define GPIO_PD11 43
+#define GPIO_PD12 44
+#define GPIO_PD13 45
+#define GPIO_PE0 48 /* PE */
+#define GPIO_PE1 49
+#define GPIO_PE2 50
+#define GPIO_PE3 51
+#define GPIO_PE4 52
+#define GPIO_PE5 53
+#define GPIO_PE6 54
+#define GPIO_PE7 55
+#define GPIO_PE8 56
+#define GPIO_PE9 57
+#define GPIO_PE10 58
+#define GPIO_PE11 59
+#define GPIO_PE12 60
+#define GPIO_PE13 61
+#define GPIO_PE14 62
+#define GPIO_PE15 63
+
+#define PORT_F GPIO_PF0
+#define PORT_C GPIO_PC0
+#define PORT_D GPIO_PD0
+#define PORT_E GPIO_PE0
+
+#endif /* _MACH_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES 64
+
+#define P_TMR2 (P_DONTCARE)
+#define P_TMR1 (P_DONTCARE)
+#define P_TMR0 (P_DONTCARE)
+#define P_TMRCLK (P_DONTCARE)
+#define P_PPI0_CLK (P_DONTCARE)
+#define P_PPI0_FS1 (P_DONTCARE)
+#define P_PPI0_FS2 (P_DONTCARE)
+
+#define P_TWI0_SCL (P_DONTCARE)
+#define P_TWI0_SDA (P_DONTCARE)
+#define P_TWI1_SCL (P_DONTCARE)
+#define P_TWI1_SDA (P_DONTCARE)
+
+#define P_SPORT1_TSCLK (P_DONTCARE)
+#define P_SPORT1_RSCLK (P_DONTCARE)
+#define P_SPORT0_TSCLK (P_DONTCARE)
+#define P_SPORT0_RSCLK (P_DONTCARE)
+#define P_SPORT1_DRSEC (P_DONTCARE)
+#define P_SPORT1_RFS (P_DONTCARE)
+#define P_SPORT1_DTPRI (P_DONTCARE)
+#define P_SPORT1_DTSEC (P_DONTCARE)
+#define P_SPORT1_TFS (P_DONTCARE)
+#define P_SPORT1_DRPRI (P_DONTCARE)
+#define P_SPORT0_DRSEC (P_DONTCARE)
+#define P_SPORT0_RFS (P_DONTCARE)
+#define P_SPORT0_DTPRI (P_DONTCARE)
+#define P_SPORT0_DTSEC (P_DONTCARE)
+#define P_SPORT0_TFS (P_DONTCARE)
+#define P_SPORT0_DRPRI (P_DONTCARE)
+
+#define P_UART0_RX (P_DONTCARE)
+#define P_UART0_TX (P_DONTCARE)
+
+#define P_SPI0_MOSI (P_DONTCARE)
+#define P_SPI0_MISO (P_DONTCARE)
+#define P_SPI0_SCK (P_DONTCARE)
+
+#define P_PPI0_D0 (P_DONTCARE)
+#define P_PPI0_D1 (P_DONTCARE)
+#define P_PPI0_D2 (P_DONTCARE)
+#define P_PPI0_D3 (P_DONTCARE)
+
+#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
+#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
+
+#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
+#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
+#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
+#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
+#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
+#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
+#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
+#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
+#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
+#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
+#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
+#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
+
+#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
+#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
+#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
+#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
+#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
+#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
+#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
+#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
+#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
+#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
+#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
+#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
+#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
+#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
+#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
+#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
+
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
+
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
+#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
+#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
+
+#endif /* _MACH_PORTMUX_H_ */
--- /dev/null
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+
+#endif
#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
#define __BFIN_CDEF_ADSP_EDN_BF542_extended__
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA() bfin_read16(PORTA)
#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB() bfin_read16(PORTB)
#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC() bfin_read16(PORTC)
#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD() bfin_read16(PORTD)
#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE() bfin_read16(PORTE)
#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF() bfin_read16(PORTF)
#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG() bfin_read16(PORTG)
#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH() bfin_read16(PORTH)
#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI() bfin_read16(PORTI)
#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ() bfin_read16(PORTJ)
#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA() bfin_read16(PORTA)
#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB() bfin_read16(PORTB)
#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC() bfin_read16(PORTC)
#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD() bfin_read16(PORTD)
#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE() bfin_read16(PORTE)
#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF() bfin_read16(PORTF)
#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG() bfin_read16(PORTG)
#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH() bfin_read16(PORTH)
#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI() bfin_read16(PORTI)
#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ() bfin_read16(PORTJ)
#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
#define __BFIN_CDEF_ADSP_EDN_BF547_extended__
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA() bfin_read16(PORTA)
#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB() bfin_read16(PORTB)
#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC() bfin_read16(PORTC)
#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD() bfin_read16(PORTD)
#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE() bfin_read16(PORTE)
#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF() bfin_read16(PORTF)
#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG() bfin_read16(PORTG)
#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH() bfin_read16(PORTH)
#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI() bfin_read16(PORTI)
#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ() bfin_read16(PORTJ)
#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
#define __BFIN_CDEF_ADSP_EDN_BF548_extended__
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA() bfin_read16(PORTA)
#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB() bfin_read16(PORTB)
#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC() bfin_read16(PORTC)
#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD() bfin_read16(PORTD)
#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE() bfin_read16(PORTE)
#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF() bfin_read16(PORTF)
#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG() bfin_read16(PORTG)
#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH() bfin_read16(PORTH)
#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI() bfin_read16(PORTI)
#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ() bfin_read16(PORTJ)
#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
#define __BFIN_CDEF_ADSP_EDN_BF549_extended__
-#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA() bfin_read16(PORTA)
#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB() bfin_read16(PORTB)
#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC() bfin_read16(PORTC)
#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD() bfin_read16(PORTD)
#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE() bfin_read16(PORTE)
#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF() bfin_read16(PORTF)
#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG() bfin_read16(PORTG)
#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH() bfin_read16(PORTH)
#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI() bfin_read16(PORTI)
#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ() bfin_read16(PORTJ)
#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */
#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pMXVR_CONFIG ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */
#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define pMXVR_STATE_0 ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */
#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define pMXVR_STATE_1 ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */
#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define pMXVR_INT_STAT_0 ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */
#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define pMXVR_INT_STAT_1 ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */
#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define pMXVR_INT_EN_0 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */
#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define pMXVR_INT_EN_1 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */
#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define pMXVR_POSITION ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */
#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define pMXVR_MAX_POSITION ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */
#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define pMXVR_DELAY ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */
#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define pMXVR_MAX_DELAY ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */
#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define pMXVR_LADDR ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */
#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define pMXVR_GADDR ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */
#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define pMXVR_AADDR ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */
#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define pMXVR_ALLOC_0 ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */
#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define pMXVR_ALLOC_1 ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */
#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define pMXVR_ALLOC_2 ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */
#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define pMXVR_ALLOC_3 ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */
#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define pMXVR_ALLOC_4 ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */
#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define pMXVR_ALLOC_5 ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */
#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define pMXVR_ALLOC_6 ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */
#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define pMXVR_ALLOC_7 ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */
#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define pMXVR_ALLOC_8 ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */
#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define pMXVR_ALLOC_9 ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */
#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define pMXVR_ALLOC_10 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */
#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define pMXVR_ALLOC_11 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */
#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define pMXVR_ALLOC_12 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */
#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define pMXVR_ALLOC_13 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */
#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define pMXVR_ALLOC_14 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */
#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define pMXVR_SYNC_LCHAN_0 ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */
#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define pMXVR_SYNC_LCHAN_1 ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */
#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define pMXVR_SYNC_LCHAN_2 ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */
#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define pMXVR_SYNC_LCHAN_3 ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */
#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define pMXVR_SYNC_LCHAN_4 ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */
#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define pMXVR_SYNC_LCHAN_5 ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */
#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define pMXVR_SYNC_LCHAN_6 ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */
#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define pMXVR_SYNC_LCHAN_7 ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */
#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define pMXVR_DMA0_CONFIG ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */
#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define pMXVR_DMA0_START_ADDR ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */
#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define pMXVR_DMA0_COUNT ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */
#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define pMXVR_DMA0_CURR_ADDR ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */
#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define pMXVR_DMA0_CURR_COUNT ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */
#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define pMXVR_DMA1_CONFIG ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */
#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define pMXVR_DMA1_START_ADDR ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */
#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define pMXVR_DMA1_COUNT ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */
#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define pMXVR_DMA1_CURR_ADDR ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */
#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define pMXVR_DMA1_CURR_COUNT ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */
#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define pMXVR_DMA2_CONFIG ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */
#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define pMXVR_DMA2_START_ADDR ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */
#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define pMXVR_DMA2_COUNT ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */
#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define pMXVR_DMA2_CURR_ADDR ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */
#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define pMXVR_DMA2_CURR_COUNT ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */
#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define pMXVR_DMA3_CONFIG ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */
#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define pMXVR_DMA3_START_ADDR ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */
#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define pMXVR_DMA3_COUNT ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */
#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define pMXVR_DMA3_CURR_ADDR ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */
#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define pMXVR_DMA3_CURR_COUNT ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */
#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define pMXVR_DMA4_CONFIG ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */
#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define pMXVR_DMA4_START_ADDR ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */
#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define pMXVR_DMA4_COUNT ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */
#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define pMXVR_DMA4_CURR_ADDR ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */
#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define pMXVR_DMA4_CURR_COUNT ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */
#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define pMXVR_DMA5_CONFIG ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */
#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define pMXVR_DMA5_START_ADDR ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */
#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define pMXVR_DMA5_COUNT ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */
#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define pMXVR_DMA5_CURR_ADDR ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */
#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define pMXVR_DMA5_CURR_COUNT ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */
#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define pMXVR_DMA6_CONFIG ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */
#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define pMXVR_DMA6_START_ADDR ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */
#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define pMXVR_DMA6_COUNT ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */
#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define pMXVR_DMA6_CURR_ADDR ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */
#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define pMXVR_DMA6_CURR_COUNT ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */
#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define pMXVR_DMA7_CONFIG ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */
#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define pMXVR_DMA7_START_ADDR ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */
#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define pMXVR_DMA7_COUNT ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */
#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define pMXVR_DMA7_CURR_ADDR ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */
#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define pMXVR_DMA7_CURR_COUNT ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */
#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define pMXVR_AP_CTL ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */
#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define pMXVR_APRB_START_ADDR ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */
#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define pMXVR_APRB_CURR_ADDR ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */
#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define pMXVR_APTB_START_ADDR ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */
#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define pMXVR_APTB_CURR_ADDR ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */
#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define pMXVR_CM_CTL ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */
#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define pMXVR_CMRB_START_ADDR ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */
#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define pMXVR_CMRB_CURR_ADDR ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */
#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define pMXVR_CMTB_START_ADDR ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */
#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define pMXVR_CMTB_CURR_ADDR ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */
#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define pMXVR_RRDB_START_ADDR ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */
#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define pMXVR_RRDB_CURR_ADDR ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */
#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define pMXVR_PAT_DATA_0 ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */
#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define pMXVR_PAT_EN_0 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */
#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define pMXVR_PAT_DATA_1 ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */
#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define pMXVR_PAT_EN_1 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */
#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define pMXVR_FRAME_CNT_0 ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */
#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define pMXVR_FRAME_CNT_1 ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */
#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define pMXVR_ROUTING_0 ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */
#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define pMXVR_ROUTING_1 ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */
#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define pMXVR_ROUTING_2 ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */
#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define pMXVR_ROUTING_3 ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */
#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define pMXVR_ROUTING_4 ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */
#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define pMXVR_ROUTING_5 ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */
#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define pMXVR_ROUTING_6 ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */
#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define pMXVR_ROUTING_7 ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */
#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define pMXVR_ROUTING_8 ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */
#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define pMXVR_ROUTING_9 ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */
#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define pMXVR_ROUTING_10 ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */
#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define pMXVR_ROUTING_11 ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */
#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define pMXVR_ROUTING_12 ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */
#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define pMXVR_ROUTING_13 ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */
#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define pMXVR_ROUTING_14 ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */
#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define pMXVR_BLOCK_CNT ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */
#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define pMXVR_CLK_CTL ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */
#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define pMXVR_CDRPLL_CTL ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */
#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define pMXVR_FMPLL_CTL ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */
#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define pMXVR_PIN_CTL ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */
#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define pMXVR_SCLK_CNT ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */
#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF541_proc__
-#define __BFIN_CDEF_ADSP_BF541_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF542-extended_cdef.h"
-
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF541_proc__ */
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF541_proc__
-#define __BFIN_DEF_ADSP_BF541_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF542-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-#endif /* __BFIN_DEF_ADSP_BF541_proc__ */
#include "ADSP-EDN-BF542-extended_cdef.h"
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
#include "ADSP-EDN-BF544-extended_cdef.h"
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
#include "ADSP-EDN-BF547-extended_cdef.h"
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
#include "ADSP-EDN-BF548-extended_cdef.h"
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
#include "ADSP-EDN-BF549-extended_cdef.h"
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
#define CHIPID 0xFFC00014
#define SWRST 0xFFC00100 /* Software Reset Register */
#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
*/
/* This file should be up to date with:
- * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000379 (1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Some ATAPI Modes Are Not Functional */
-#define ANOMALY_05000383 (1)
/* Boot from OTP Memory Not Functional */
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Routine Not Functional */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
+/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
+#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000475 (0)
#endif
#include "../mach-common/ADSP-EDN-core_cdef.h"
-#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
-
-#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR)
-#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS)
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0)
-#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((uint32_t volatile *)DCPLB_ADDR1)
-#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((uint32_t volatile *)DCPLB_ADDR2)
-#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((uint32_t volatile *)DCPLB_ADDR3)
-#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((uint32_t volatile *)DCPLB_ADDR4)
-#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((uint32_t volatile *)DCPLB_ADDR5)
-#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((uint32_t volatile *)DCPLB_ADDR6)
-#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((uint32_t volatile *)DCPLB_ADDR7)
-#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((uint32_t volatile *)DCPLB_ADDR8)
-#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((uint32_t volatile *)DCPLB_ADDR9)
-#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((uint32_t volatile *)DCPLB_ADDR10)
-#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((uint32_t volatile *)DCPLB_ADDR11)
-#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((uint32_t volatile *)DCPLB_ADDR12)
-#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((uint32_t volatile *)DCPLB_ADDR13)
-#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((uint32_t volatile *)DCPLB_ADDR14)
-#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((uint32_t volatile *)DCPLB_ADDR15)
-#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0)
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL)
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0)
-#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((uint32_t volatile *)ICPLB_ADDR1)
-#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((uint32_t volatile *)ICPLB_ADDR2)
-#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((uint32_t volatile *)ICPLB_ADDR3)
-#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((uint32_t volatile *)ICPLB_ADDR4)
-#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((uint32_t volatile *)ICPLB_ADDR5)
-#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((uint32_t volatile *)ICPLB_ADDR6)
-#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((uint32_t volatile *)ICPLB_ADDR7)
-#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((uint32_t volatile *)ICPLB_ADDR8)
-#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((uint32_t volatile *)ICPLB_ADDR9)
-#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((uint32_t volatile *)ICPLB_ADDR10)
-#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((uint32_t volatile *)ICPLB_ADDR11)
-#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((uint32_t volatile *)ICPLB_ADDR12)
-#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((uint32_t volatile *)ICPLB_ADDR13)
-#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((uint32_t volatile *)ICPLB_ADDR14)
-#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((uint32_t volatile *)ICPLB_ADDR15)
-#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND)
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
+#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
+#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
+#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val)
+#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
+#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val)
+#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
+#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val)
+#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
+#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val)
+#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
+#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val)
+#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
+#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val)
+#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
+#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
+#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
+#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
+#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
+#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val)
+#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
+#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR)
+#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
+#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
+#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
+#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
+#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
+#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
+#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
+#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
+#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
+#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
+#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR)
+#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
+#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
+#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
+#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
+#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
+#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
+#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
+#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
+#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val)
+#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR)
+#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
+#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
+#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
+#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
+#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
+#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
+#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
+#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
+#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
+#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
+#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR)
+#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
+#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
+#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
+#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
+#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
+#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
+#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val)
+#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
+#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR)
+#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
+#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
+#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
+#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
+#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
+#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
+#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
+#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
+#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
+#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
+#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR)
+#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
+#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
+#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
+#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
+#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
+#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
+#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
+#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
+#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val)
+#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
+#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR)
+#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
+#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
+#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
+#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
+#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
+#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
+#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
+#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
+#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
+#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
+#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR)
+#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
+#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
+#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
+#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
+#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
+#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
+#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
+#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
+#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val)
+#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
+#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR)
+#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
+#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
+#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
+#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
+#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
+#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
+#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
+#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
+#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
+#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
+#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR)
+#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
+#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
+#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
+#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
+#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
+#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
+#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
+#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
+#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val)
+#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
+#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR)
+#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
+#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
+#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
+#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
+#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
+#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
+#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
+#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
+#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
+#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
+#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR)
+#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
+#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
+#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
+#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
+#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
+#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
+#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
+#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
+#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val)
+#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
+#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR)
+#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
+#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
+#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
+#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
+#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
+#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
+#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
+#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
+#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
+#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
+#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR)
+#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
+#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
+#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
+#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
+#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
+#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
+#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
+#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
+#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val)
+#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
+#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR)
+#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
+#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
+#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
+#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
+#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
+#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
+#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
+#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
+#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
+#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
+#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR)
+#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
+#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
+#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
+#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
+#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
+#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
+#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
+#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
+#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val)
+#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
+#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR)
+#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
+#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
+#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
+#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
+#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
+#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
+#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
+#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
+#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
+#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
+#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR)
+#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
+#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
+#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
+#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
+#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
+#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
+#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
+#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
+#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val)
+#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
+#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR)
+#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
+#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
+#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
+#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
+#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
+#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
+#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
+#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
+#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
+#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
+#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR)
+#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
+#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
+#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
+#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
+#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
+#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
+#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
+#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
+#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
+#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
+#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
+#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
+#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
+#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
+#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
+#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
+#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
+#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
+#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
+#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
+#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
+#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR)
+#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
+#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
+#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
+#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
+#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
+#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
+#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
+#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
+#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
+#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
+#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
+#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
+#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
+#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
+#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
+#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
+#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
+#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
+#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
+#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
+#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
+#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR)
+#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
+#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
+#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
+#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
+#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
+#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
+#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
+#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
+#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val)
+#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
+#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val)
+#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
+#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val)
+#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
+#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR)
+#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
+#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
+#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
+#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
+#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
+#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
+#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
+#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
+#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
+#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
+#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR)
+#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
+#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
+#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
+#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
+#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
+#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
+#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
+#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
+#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val)
+#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
+#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR)
+#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
+#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
+#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
+#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
+#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
+#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
+#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
+#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
+#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
+#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
+#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR)
+#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
+#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
+#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
+#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
+#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
+#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
+#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
+#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
+#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val)
+#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR)
+#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
+#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
+#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
+#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
+#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
+#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
+#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
+#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
+#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
+#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
+#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR)
+#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
+#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
+#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
+#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
+#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
+#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
+#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val)
+#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
+#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR)
+#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
+#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
+#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
+#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
+#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
+#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
+#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
+#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
+#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
+#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
+#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR)
+#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
+#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
+#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
+#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
+#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
+#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
+#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
+#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
+#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val)
+#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
+#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR)
+#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
+#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
+#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
+#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
+#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
+#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
+#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
+#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
+#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
+#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
+#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR)
+#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
+#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
+#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
+#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
+#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
+#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
+#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
+#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
+#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val)
+#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
+#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR)
+#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
+#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
+#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
+#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
+#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
+#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
+#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
+#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
+#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
+#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
+#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR)
+#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
+#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
+#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
+#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
+#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
+#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
+#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
+#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
+#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val)
+#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
+#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR)
+#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
+#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
+#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
+#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
+#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
+#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
+#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
+#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
+#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
+#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
+#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR)
+#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
+#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
+#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
+#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
+#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
+#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
+#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
+#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
+#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val)
+#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
+#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR)
+#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
+#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
+#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
+#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
+#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
+#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
+#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
+#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
+#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
+#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
+#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR)
+#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
+#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
+#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
+#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
+#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
+#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
+#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
+#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
+#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val)
+#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
+#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR)
+#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
+#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
+#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
+#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
+#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
+#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
+#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
+#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
+#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
+#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
+#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR)
+#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
+#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
+#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
+#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
+#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
+#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
+#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
+#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
+#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val)
+#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
+#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR)
+#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
+#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
+#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
+#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
+#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
+#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
+#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
+#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
+#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
+#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
+#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR)
+#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
+#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
+#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
+#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
+#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
+#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
+#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
+#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
+#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
+#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
+#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
+#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
+#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
+#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
+#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
+#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
+#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
+#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
+#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
+#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
+#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
+#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR)
+#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
+#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
+#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
+#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
+#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
+#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
+#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
+#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
+#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
+#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
+#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
+#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
+#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
+#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
+#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
+#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
+#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
+#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
+#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
+#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
+#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
+#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR)
+#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
+#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
+#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
+#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
+#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
+#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
+#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
+#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
+#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
+#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
+#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
+#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
+#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
+#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
+#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
+#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
+#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
+#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
+#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
+#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
+#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
+#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
+#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
+#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
+#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
+#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
+#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
+#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
+#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
+#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
+#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
+#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
+#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
+#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
+#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
+#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
+#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
+#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
+#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
+#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
+#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
+#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
+#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
+#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
+#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
+#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
+#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
+#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
+#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
+#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
+#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
+#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
+#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
+#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
+#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
+#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
+#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
+#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
+#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
+#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
+#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
+#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
+#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
+#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
+#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
+#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
+#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
+#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
+#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
+#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
+#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
+#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
+#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
+#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
+#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
+#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
+#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
+#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
+#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
+#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
+#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
+#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
+#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
+#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
+#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
+#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
+#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
+#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
+#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
+#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
+#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
+#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
+#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
+#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
+#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
+#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
+#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
+#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
+#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
+#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
+#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
+#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
+#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
+#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
+#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
+#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
+#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
+#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
+#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
+#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
+#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
+#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
+#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
+#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
+#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
+#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
+#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
+#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
+#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
+#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
+#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
+#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
+#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
+#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
+#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
+#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
+#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
+#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
+#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
+#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
+#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
+#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
+#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
+#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
+#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
+#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
+#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
+#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
+#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
+#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
+#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
+#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
+#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
+#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
+#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
+#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
+#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
+#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
+#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
+#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
+#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
+#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
+#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
+#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
+#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
+#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
+#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
+#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
+#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
+#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
+#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
+#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
+#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
+#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
+#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
+#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
+#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
+#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
+#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
+#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
+#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
+#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
+#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
+#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
+#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
+#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
+#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
+#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
+#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
+#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
+#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
+#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
+#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
+#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
+#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
+#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
+#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
+#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
+#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
+#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
+#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
+#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
+#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
+#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
+#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
+#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
+#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
+#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
+#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
+#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
+#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
+#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
+#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
+#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
+#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
+#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
+#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
+#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
+#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
+#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
+#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
+#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
+#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
+#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
+#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
+#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
+#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
+#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
+#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
+#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val)
+#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE)
+#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val)
+#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE)
+#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val)
+#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
+#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val)
+#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE)
+#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val)
+#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE)
+#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val)
+#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
+#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val)
+#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
+#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val)
+#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
+#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val)
+#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
+#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val)
+#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
+#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val)
+#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
+#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val)
+#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
+#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val)
+#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
+#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val)
+#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
+#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val)
+#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
+#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val)
+#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
+#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val)
+#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
+#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val)
+#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
+#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val)
+#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
+#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val)
+#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
+#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val)
+#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
+#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val)
+#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
+#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val)
+#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
+#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val)
+#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
+#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val)
+#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
+#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val)
+#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
+#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val)
+#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
+#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val)
+#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
+#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val)
+#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
+#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val)
+#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
+#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val)
+#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
+#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val)
+#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
+#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val)
+#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
+#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val)
+#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
+#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val)
+#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
+#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val)
+#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
+#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val)
+#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
+#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val)
+#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
+#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val)
+#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
+#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val)
+#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
+#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val)
+#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
+#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val)
+#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
+#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val)
+#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
+#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val)
+#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
+#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val)
+#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
+#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val)
+#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
+#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val)
+#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
+#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val)
+#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
+#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val)
+#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
+#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val)
+#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
+#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val)
+#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
+#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val)
+#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
+#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val)
+#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
+#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val)
+#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
+#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val)
+#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
+#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val)
+#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
+#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val)
+#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
+#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val)
+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
-#define pSICA_SYSCR ((uint16_t volatile *)SICA_SYSCR)
#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val)
-#define pSICA_RVECT ((uint16_t volatile *)SICA_RVECT)
#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val)
-#define pSICA_IMASK0 ((uint32_t volatile *)SICA_IMASK0)
#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0, val)
-#define pSICA_IMASK1 ((uint32_t volatile *)SICA_IMASK1)
#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1, val)
-#define pSICA_ISR0 ((uint32_t volatile *)SICA_ISR0)
#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0, val)
-#define pSICA_ISR1 ((uint32_t volatile *)SICA_ISR1)
#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1, val)
-#define pSICA_IWR0 ((uint32_t volatile *)SICA_IWR0)
#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0, val)
-#define pSICA_IWR1 ((uint32_t volatile *)SICA_IWR1)
#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1, val)
-#define pSICA_IAR0 ((uint32_t volatile *)SICA_IAR0)
#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0, val)
-#define pSICA_IAR1 ((uint32_t volatile *)SICA_IAR1)
#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1, val)
-#define pSICA_IAR2 ((uint32_t volatile *)SICA_IAR2)
#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2, val)
-#define pSICA_IAR3 ((uint32_t volatile *)SICA_IAR3)
#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3, val)
-#define pSICA_IAR4 ((uint32_t volatile *)SICA_IAR4)
#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4, val)
-#define pSICA_IAR5 ((uint32_t volatile *)SICA_IAR5)
#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5, val)
-#define pSICA_IAR6 ((uint32_t volatile *)SICA_IAR6)
#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6, val)
-#define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7)
#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST)
#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
-#define pSICB_SYSCR ((uint16_t volatile *)SICB_SYSCR)
#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val)
-#define pSICB_RVECT ((uint16_t volatile *)SICB_RVECT)
#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val)
-#define pSICB_IMASK0 ((uint32_t volatile *)SICB_IMASK0)
#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0, val)
-#define pSICB_IMASK1 ((uint32_t volatile *)SICB_IMASK1)
#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1, val)
-#define pSICB_ISR0 ((uint32_t volatile *)SICB_ISR0)
#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0, val)
-#define pSICB_ISR1 ((uint32_t volatile *)SICB_ISR1)
#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1, val)
-#define pSICB_IWR0 ((uint32_t volatile *)SICB_IWR0)
#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0, val)
-#define pSICB_IWR1 ((uint32_t volatile *)SICB_IWR1)
#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1, val)
-#define pSICB_IAR0 ((uint32_t volatile *)SICB_IAR0)
#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0, val)
-#define pSICB_IAR1 ((uint32_t volatile *)SICB_IAR1)
#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1, val)
-#define pSICB_IAR2 ((uint32_t volatile *)SICB_IAR2)
#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2, val)
-#define pSICB_IAR3 ((uint32_t volatile *)SICB_IAR3)
#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3, val)
-#define pSICB_IAR4 ((uint32_t volatile *)SICB_IAR4)
#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4, val)
-#define pSICB_IAR5 ((uint32_t volatile *)SICB_IAR5)
#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5, val)
-#define pSICB_IAR6 ((uint32_t volatile *)SICB_IAR6)
#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6, val)
-#define pSICB_IAR7 ((uint32_t volatile *)SICB_IAR7)
#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7, val)
-#define pPPI0_CONTROL ((uint16_t volatile *)PPI0_CONTROL)
#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL, val)
-#define pPPI0_STATUS ((uint16_t volatile *)PPI0_STATUS)
#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS, val)
-#define pPPI0_DELAY ((uint16_t volatile *)PPI0_DELAY)
#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY, val)
-#define pPPI0_COUNT ((uint16_t volatile *)PPI0_COUNT)
#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT, val)
-#define pPPI0_FRAME ((uint16_t volatile *)PPI0_FRAME)
#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME, val)
-#define pPPI1_CONTROL ((uint16_t volatile *)PPI1_CONTROL)
#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL, val)
-#define pPPI1_STATUS ((uint16_t volatile *)PPI1_STATUS)
#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS, val)
-#define pPPI1_DELAY ((uint16_t volatile *)PPI1_DELAY)
#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY, val)
-#define pPPI1_COUNT ((uint16_t volatile *)PPI1_COUNT)
#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT, val)
-#define pPPI1_FRAME ((uint16_t volatile *)PPI1_FRAME)
#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL)
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((uint32_t volatile *)TBUF)
-#define bfin_read_TBUF() bfin_read32(TBUF)
-#define bfin_write_TBUF(val) bfin_write32(TBUF, val)
-#define pPFCTL ((uint32_t volatile *)PFCTL)
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define pSRAM_BASE_ADDR_CORE_A ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A)
-#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
-#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
-#define pSRAM_BASE_ADDR_CORE_B ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B)
-#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
-#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
-#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define pUART_THR ((uint16_t volatile *)UART_THR)
#define bfin_read_UART_THR() bfin_read16(UART_THR)
#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
-#define pUART_RBR ((uint16_t volatile *)UART_RBR)
#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
-#define pUART_DLL ((uint16_t volatile *)UART_DLL)
#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
-#define pUART_DLH ((uint16_t volatile *)UART_DLH)
#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
-#define pUART_IER ((uint16_t volatile *)UART_IER)
#define bfin_read_UART_IER() bfin_read16(UART_IER)
#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
-#define pUART_IIR ((uint16_t volatile *)UART_IIR)
#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
-#define pUART_LCR ((uint16_t volatile *)UART_LCR)
#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
-#define pUART_MCR ((uint16_t volatile *)UART_MCR)
#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
-#define pUART_LSR ((uint16_t volatile *)UART_LSR)
#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
-#define pUART_MSR ((uint16_t volatile *)UART_MSR)
#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR, val)
-#define pUART_SCR ((uint16_t volatile *)UART_SCR)
#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
-#define pUART_GCTL ((uint16_t volatile *)UART_GCTL)
#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
-#define pUART_GBL ((uint16_t volatile *)UART_GBL)
#define bfin_read_UART_GBL() bfin_read16(UART_GBL)
#define bfin_write_UART_GBL(val) bfin_write16(UART_GBL, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL)
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0)
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1)
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL)
#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL ((uint32_t volatile *)EBIU_SDBCTL)
#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC)
#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT)
#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
#include "../mach-common/ADSP-EDN-core_def.h"
-#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
-
-#define SRAM_BASE_ADDR 0xFFE00000
-#define DMEM_CONTROL 0xFFE00004
-#define DCPLB_STATUS 0xFFE00008
-#define DCPLB_FAULT_ADDR 0xFFE0000C
-#define DCPLB_ADDR0 0xFFE00100
-#define DCPLB_ADDR1 0xFFE00104
-#define DCPLB_ADDR2 0xFFE00108
-#define DCPLB_ADDR3 0xFFE0010C
-#define DCPLB_ADDR4 0xFFE00110
-#define DCPLB_ADDR5 0xFFE00114
-#define DCPLB_ADDR6 0xFFE00118
-#define DCPLB_ADDR7 0xFFE0011C
-#define DCPLB_ADDR8 0xFFE00120
-#define DCPLB_ADDR9 0xFFE00124
-#define DCPLB_ADDR10 0xFFE00128
-#define DCPLB_ADDR11 0xFFE0012C
-#define DCPLB_ADDR12 0xFFE00130
-#define DCPLB_ADDR13 0xFFE00134
-#define DCPLB_ADDR14 0xFFE00138
-#define DCPLB_ADDR15 0xFFE0013C
-#define DCPLB_DATA0 0xFFE00200
-#define DCPLB_DATA1 0xFFE00204
-#define DCPLB_DATA2 0xFFE00208
-#define DCPLB_DATA3 0xFFE0020C
-#define DCPLB_DATA4 0xFFE00210
-#define DCPLB_DATA5 0xFFE00214
-#define DCPLB_DATA6 0xFFE00218
-#define DCPLB_DATA7 0xFFE0021C
-#define DCPLB_DATA8 0xFFE00220
-#define DCPLB_DATA9 0xFFE00224
-#define DCPLB_DATA10 0xFFE00228
-#define DCPLB_DATA11 0xFFE0022C
-#define DCPLB_DATA12 0xFFE00230
-#define DCPLB_DATA13 0xFFE00234
-#define DCPLB_DATA14 0xFFE00238
-#define DCPLB_DATA15 0xFFE0023C
-#define DTEST_COMMAND 0xFFE00300
-#define DTEST_DATA0 0xFFE00400
-#define DTEST_DATA1 0xFFE00404
-#define IMEM_CONTROL 0xFFE01004
-#define ICPLB_STATUS 0xFFE01008
-#define ICPLB_FAULT_ADDR 0xFFE0100C
-#define ICPLB_ADDR0 0xFFE01100
-#define ICPLB_ADDR1 0xFFE01104
-#define ICPLB_ADDR2 0xFFE01108
-#define ICPLB_ADDR3 0xFFE0110C
-#define ICPLB_ADDR4 0xFFE01110
-#define ICPLB_ADDR5 0xFFE01114
-#define ICPLB_ADDR6 0xFFE01118
-#define ICPLB_ADDR7 0xFFE0111C
-#define ICPLB_ADDR8 0xFFE01120
-#define ICPLB_ADDR9 0xFFE01124
-#define ICPLB_ADDR10 0xFFE01128
-#define ICPLB_ADDR11 0xFFE0112C
-#define ICPLB_ADDR12 0xFFE01130
-#define ICPLB_ADDR13 0xFFE01134
-#define ICPLB_ADDR14 0xFFE01138
-#define ICPLB_ADDR15 0xFFE0113C
-#define ICPLB_DATA0 0xFFE01200
-#define ICPLB_DATA1 0xFFE01204
-#define ICPLB_DATA2 0xFFE01208
-#define ICPLB_DATA3 0xFFE0120C
-#define ICPLB_DATA4 0xFFE01210
-#define ICPLB_DATA5 0xFFE01214
-#define ICPLB_DATA6 0xFFE01218
-#define ICPLB_DATA7 0xFFE0121C
-#define ICPLB_DATA8 0xFFE01220
-#define ICPLB_DATA9 0xFFE01224
-#define ICPLB_DATA10 0xFFE01228
-#define ICPLB_DATA11 0xFFE0122C
-#define ICPLB_DATA12 0xFFE01230
-#define ICPLB_DATA13 0xFFE01234
-#define ICPLB_DATA14 0xFFE01238
-#define ICPLB_DATA15 0xFFE0123C
-#define ITEST_COMMAND 0xFFE01300
-#define ITEST_DATA0 0xFFE01400
-#define ITEST_DATA1 0xFFE01404
+#define PLL_CTL 0xFFC00000
+#define PLL_DIV 0xFFC00004
+#define VR_CTL 0xFFC00008
+#define PLL_STAT 0xFFC0000C
+#define PLL_LOCKCNT 0xFFC00010
+#define CHIPID 0xFFC00014
+#define SPI_CTL 0xFFC00500
+#define SPI_FLG 0xFFC00504
+#define SPI_STAT 0xFFC00508
+#define SPI_TDBR 0xFFC0050C
+#define SPI_RDBR 0xFFC00510
+#define SPI_BAUD 0xFFC00514
+#define SPI_SHADOW 0xFFC00518
+#define WDOGA_CTL 0xFFC00200
+#define WDOGA_CNT 0xFFC00204
+#define WDOGA_STAT 0xFFC00208
+#define WDOGB_CTL 0xFFC01200
+#define WDOGB_CNT 0xFFC01204
+#define WDOGB_STAT 0xFFC01208
+#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
+#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
+#define DMA1_0_CONFIG 0xFFC01C08
+#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00
+#define DMA1_0_START_ADDR 0xFFC01C04
+#define DMA1_0_X_COUNT 0xFFC01C10
+#define DMA1_0_Y_COUNT 0xFFC01C18
+#define DMA1_0_X_MODIFY 0xFFC01C14
+#define DMA1_0_Y_MODIFY 0xFFC01C1C
+#define DMA1_0_CURR_DESC_PTR 0xFFC01C20
+#define DMA1_0_CURR_ADDR 0xFFC01C24
+#define DMA1_0_CURR_X_COUNT 0xFFC01C30
+#define DMA1_0_CURR_Y_COUNT 0xFFC01C38
+#define DMA1_0_IRQ_STATUS 0xFFC01C28
+#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C
+#define DMA1_1_CONFIG 0xFFC01C48
+#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40
+#define DMA1_1_START_ADDR 0xFFC01C44
+#define DMA1_1_X_COUNT 0xFFC01C50
+#define DMA1_1_Y_COUNT 0xFFC01C58
+#define DMA1_1_X_MODIFY 0xFFC01C54
+#define DMA1_1_Y_MODIFY 0xFFC01C5C
+#define DMA1_1_CURR_DESC_PTR 0xFFC01C60
+#define DMA1_1_CURR_ADDR 0xFFC01C64
+#define DMA1_1_CURR_X_COUNT 0xFFC01C70
+#define DMA1_1_CURR_Y_COUNT 0xFFC01C78
+#define DMA1_1_IRQ_STATUS 0xFFC01C68
+#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C
+#define DMA1_2_CONFIG 0xFFC01C88
+#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80
+#define DMA1_2_START_ADDR 0xFFC01C84
+#define DMA1_2_X_COUNT 0xFFC01C90
+#define DMA1_2_Y_COUNT 0xFFC01C98
+#define DMA1_2_X_MODIFY 0xFFC01C94
+#define DMA1_2_Y_MODIFY 0xFFC01C9C
+#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0
+#define DMA1_2_CURR_ADDR 0xFFC01CA4
+#define DMA1_2_CURR_X_COUNT 0xFFC01CB0
+#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8
+#define DMA1_2_IRQ_STATUS 0xFFC01CA8
+#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC
+#define DMA1_3_CONFIG 0xFFC01CC8
+#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0
+#define DMA1_3_START_ADDR 0xFFC01CC4
+#define DMA1_3_X_COUNT 0xFFC01CD0
+#define DMA1_3_Y_COUNT 0xFFC01CD8
+#define DMA1_3_X_MODIFY 0xFFC01CD4
+#define DMA1_3_Y_MODIFY 0xFFC01CDC
+#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0
+#define DMA1_3_CURR_ADDR 0xFFC01CE4
+#define DMA1_3_CURR_X_COUNT 0xFFC01CF0
+#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8
+#define DMA1_3_IRQ_STATUS 0xFFC01CE8
+#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC
+#define DMA1_4_CONFIG 0xFFC01D08
+#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00
+#define DMA1_4_START_ADDR 0xFFC01D04
+#define DMA1_4_X_COUNT 0xFFC01D10
+#define DMA1_4_Y_COUNT 0xFFC01D18
+#define DMA1_4_X_MODIFY 0xFFC01D14
+#define DMA1_4_Y_MODIFY 0xFFC01D1C
+#define DMA1_4_CURR_DESC_PTR 0xFFC01D20
+#define DMA1_4_CURR_ADDR 0xFFC01D24
+#define DMA1_4_CURR_X_COUNT 0xFFC01D30
+#define DMA1_4_CURR_Y_COUNT 0xFFC01D38
+#define DMA1_4_IRQ_STATUS 0xFFC01D28
+#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C
+#define DMA1_5_CONFIG 0xFFC01D48
+#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40
+#define DMA1_5_START_ADDR 0xFFC01D44
+#define DMA1_5_X_COUNT 0xFFC01D50
+#define DMA1_5_Y_COUNT 0xFFC01D58
+#define DMA1_5_X_MODIFY 0xFFC01D54
+#define DMA1_5_Y_MODIFY 0xFFC01D5C
+#define DMA1_5_CURR_DESC_PTR 0xFFC01D60
+#define DMA1_5_CURR_ADDR 0xFFC01D64
+#define DMA1_5_CURR_X_COUNT 0xFFC01D70
+#define DMA1_5_CURR_Y_COUNT 0xFFC01D78
+#define DMA1_5_IRQ_STATUS 0xFFC01D68
+#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C
+#define DMA1_6_CONFIG 0xFFC01D88
+#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80
+#define DMA1_6_START_ADDR 0xFFC01D84
+#define DMA1_6_X_COUNT 0xFFC01D90
+#define DMA1_6_Y_COUNT 0xFFC01D98
+#define DMA1_6_X_MODIFY 0xFFC01D94
+#define DMA1_6_Y_MODIFY 0xFFC01D9C
+#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0
+#define DMA1_6_CURR_ADDR 0xFFC01DA4
+#define DMA1_6_CURR_X_COUNT 0xFFC01DB0
+#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8
+#define DMA1_6_IRQ_STATUS 0xFFC01DA8
+#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC
+#define DMA1_7_CONFIG 0xFFC01DC8
+#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0
+#define DMA1_7_START_ADDR 0xFFC01DC4
+#define DMA1_7_X_COUNT 0xFFC01DD0
+#define DMA1_7_Y_COUNT 0xFFC01DD8
+#define DMA1_7_X_MODIFY 0xFFC01DD4
+#define DMA1_7_Y_MODIFY 0xFFC01DDC
+#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0
+#define DMA1_7_CURR_ADDR 0xFFC01DE4
+#define DMA1_7_CURR_X_COUNT 0xFFC01DF0
+#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8
+#define DMA1_7_IRQ_STATUS 0xFFC01DE8
+#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC
+#define DMA1_8_CONFIG 0xFFC01E08
+#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00
+#define DMA1_8_START_ADDR 0xFFC01E04
+#define DMA1_8_X_COUNT 0xFFC01E10
+#define DMA1_8_Y_COUNT 0xFFC01E18
+#define DMA1_8_X_MODIFY 0xFFC01E14
+#define DMA1_8_Y_MODIFY 0xFFC01E1C
+#define DMA1_8_CURR_DESC_PTR 0xFFC01E20
+#define DMA1_8_CURR_ADDR 0xFFC01E24
+#define DMA1_8_CURR_X_COUNT 0xFFC01E30
+#define DMA1_8_CURR_Y_COUNT 0xFFC01E38
+#define DMA1_8_IRQ_STATUS 0xFFC01E28
+#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C
+#define DMA1_9_CONFIG 0xFFC01E48
+#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40
+#define DMA1_9_START_ADDR 0xFFC01E44
+#define DMA1_9_X_COUNT 0xFFC01E50
+#define DMA1_9_Y_COUNT 0xFFC01E58
+#define DMA1_9_X_MODIFY 0xFFC01E54
+#define DMA1_9_Y_MODIFY 0xFFC01E5C
+#define DMA1_9_CURR_DESC_PTR 0xFFC01E60
+#define DMA1_9_CURR_ADDR 0xFFC01E64
+#define DMA1_9_CURR_X_COUNT 0xFFC01E70
+#define DMA1_9_CURR_Y_COUNT 0xFFC01E78
+#define DMA1_9_IRQ_STATUS 0xFFC01E68
+#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C
+#define DMA1_10_CONFIG 0xFFC01E88
+#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80
+#define DMA1_10_START_ADDR 0xFFC01E84
+#define DMA1_10_X_COUNT 0xFFC01E90
+#define DMA1_10_Y_COUNT 0xFFC01E98
+#define DMA1_10_X_MODIFY 0xFFC01E94
+#define DMA1_10_Y_MODIFY 0xFFC01E9C
+#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0
+#define DMA1_10_CURR_ADDR 0xFFC01EA4
+#define DMA1_10_CURR_X_COUNT 0xFFC01EB0
+#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8
+#define DMA1_10_IRQ_STATUS 0xFFC01EA8
+#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC
+#define DMA1_11_CONFIG 0xFFC01EC8
+#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0
+#define DMA1_11_START_ADDR 0xFFC01EC4
+#define DMA1_11_X_COUNT 0xFFC01ED0
+#define DMA1_11_Y_COUNT 0xFFC01ED8
+#define DMA1_11_X_MODIFY 0xFFC01ED4
+#define DMA1_11_Y_MODIFY 0xFFC01EDC
+#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0
+#define DMA1_11_CURR_ADDR 0xFFC01EE4
+#define DMA1_11_CURR_X_COUNT 0xFFC01EF0
+#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8
+#define DMA1_11_IRQ_STATUS 0xFFC01EE8
+#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC
+#define DMA2_TC_PER 0xFFC00B0C
+#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
+#define DMA2_0_CONFIG 0xFFC00C08
+#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00
+#define DMA2_0_START_ADDR 0xFFC00C04
+#define DMA2_0_X_COUNT 0xFFC00C10
+#define DMA2_0_Y_COUNT 0xFFC00C18
+#define DMA2_0_X_MODIFY 0xFFC00C14
+#define DMA2_0_Y_MODIFY 0xFFC00C1C
+#define DMA2_0_CURR_DESC_PTR 0xFFC00C20
+#define DMA2_0_CURR_ADDR 0xFFC00C24
+#define DMA2_0_CURR_X_COUNT 0xFFC00C30
+#define DMA2_0_CURR_Y_COUNT 0xFFC00C38
+#define DMA2_0_IRQ_STATUS 0xFFC00C28
+#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C
+#define DMA2_1_CONFIG 0xFFC00C48
+#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40
+#define DMA2_1_START_ADDR 0xFFC00C44
+#define DMA2_1_X_COUNT 0xFFC00C50
+#define DMA2_1_Y_COUNT 0xFFC00C58
+#define DMA2_1_X_MODIFY 0xFFC00C54
+#define DMA2_1_Y_MODIFY 0xFFC00C5C
+#define DMA2_1_CURR_DESC_PTR 0xFFC00C60
+#define DMA2_1_CURR_ADDR 0xFFC00C64
+#define DMA2_1_CURR_X_COUNT 0xFFC00C70
+#define DMA2_1_CURR_Y_COUNT 0xFFC00C78
+#define DMA2_1_IRQ_STATUS 0xFFC00C68
+#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C
+#define DMA2_2_CONFIG 0xFFC00C88
+#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80
+#define DMA2_2_START_ADDR 0xFFC00C84
+#define DMA2_2_X_COUNT 0xFFC00C90
+#define DMA2_2_Y_COUNT 0xFFC00C98
+#define DMA2_2_X_MODIFY 0xFFC00C94
+#define DMA2_2_Y_MODIFY 0xFFC00C9C
+#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0
+#define DMA2_2_CURR_ADDR 0xFFC00CA4
+#define DMA2_2_CURR_X_COUNT 0xFFC00CB0
+#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8
+#define DMA2_2_IRQ_STATUS 0xFFC00CA8
+#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC
+#define DMA2_3_CONFIG 0xFFC00CC8
+#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0
+#define DMA2_3_START_ADDR 0xFFC00CC4
+#define DMA2_3_X_COUNT 0xFFC00CD0
+#define DMA2_3_Y_COUNT 0xFFC00CD8
+#define DMA2_3_X_MODIFY 0xFFC00CD4
+#define DMA2_3_Y_MODIFY 0xFFC00CDC
+#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0
+#define DMA2_3_CURR_ADDR 0xFFC00CE4
+#define DMA2_3_CURR_X_COUNT 0xFFC00CF0
+#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8
+#define DMA2_3_IRQ_STATUS 0xFFC00CE8
+#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC
+#define DMA2_4_CONFIG 0xFFC00D08
+#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00
+#define DMA2_4_START_ADDR 0xFFC00D04
+#define DMA2_4_X_COUNT 0xFFC00D10
+#define DMA2_4_Y_COUNT 0xFFC00D18
+#define DMA2_4_X_MODIFY 0xFFC00D14
+#define DMA2_4_Y_MODIFY 0xFFC00D1C
+#define DMA2_4_CURR_DESC_PTR 0xFFC00D20
+#define DMA2_4_CURR_ADDR 0xFFC00D24
+#define DMA2_4_CURR_X_COUNT 0xFFC00D30
+#define DMA2_4_CURR_Y_COUNT 0xFFC00D38
+#define DMA2_4_IRQ_STATUS 0xFFC00D28
+#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C
+#define DMA2_5_CONFIG 0xFFC00D48
+#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40
+#define DMA2_5_START_ADDR 0xFFC00D44
+#define DMA2_5_X_COUNT 0xFFC00D50
+#define DMA2_5_Y_COUNT 0xFFC00D58
+#define DMA2_5_X_MODIFY 0xFFC00D54
+#define DMA2_5_Y_MODIFY 0xFFC00D5C
+#define DMA2_5_CURR_DESC_PTR 0xFFC00D60
+#define DMA2_5_CURR_ADDR 0xFFC00D64
+#define DMA2_5_CURR_X_COUNT 0xFFC00D70
+#define DMA2_5_CURR_Y_COUNT 0xFFC00D78
+#define DMA2_5_IRQ_STATUS 0xFFC00D68
+#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C
+#define DMA2_6_CONFIG 0xFFC00D88
+#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80
+#define DMA2_6_START_ADDR 0xFFC00D84
+#define DMA2_6_X_COUNT 0xFFC00D90
+#define DMA2_6_Y_COUNT 0xFFC00D98
+#define DMA2_6_X_MODIFY 0xFFC00D94
+#define DMA2_6_Y_MODIFY 0xFFC00D9C
+#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0
+#define DMA2_6_CURR_ADDR 0xFFC00DA4
+#define DMA2_6_CURR_X_COUNT 0xFFC00DB0
+#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8
+#define DMA2_6_IRQ_STATUS 0xFFC00DA8
+#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC
+#define DMA2_7_CONFIG 0xFFC00DC8
+#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0
+#define DMA2_7_START_ADDR 0xFFC00DC4
+#define DMA2_7_X_COUNT 0xFFC00DD0
+#define DMA2_7_Y_COUNT 0xFFC00DD8
+#define DMA2_7_X_MODIFY 0xFFC00DD4
+#define DMA2_7_Y_MODIFY 0xFFC00DDC
+#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0
+#define DMA2_7_CURR_ADDR 0xFFC00DE4
+#define DMA2_7_CURR_X_COUNT 0xFFC00DF0
+#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8
+#define DMA2_7_IRQ_STATUS 0xFFC00DE8
+#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC
+#define DMA2_8_CONFIG 0xFFC00E08
+#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00
+#define DMA2_8_START_ADDR 0xFFC00E04
+#define DMA2_8_X_COUNT 0xFFC00E10
+#define DMA2_8_Y_COUNT 0xFFC00E18
+#define DMA2_8_X_MODIFY 0xFFC00E14
+#define DMA2_8_Y_MODIFY 0xFFC00E1C
+#define DMA2_8_CURR_DESC_PTR 0xFFC00E20
+#define DMA2_8_CURR_ADDR 0xFFC00E24
+#define DMA2_8_CURR_X_COUNT 0xFFC00E30
+#define DMA2_8_CURR_Y_COUNT 0xFFC00E38
+#define DMA2_8_IRQ_STATUS 0xFFC00E28
+#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C
+#define DMA2_9_CONFIG 0xFFC00E48
+#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40
+#define DMA2_9_START_ADDR 0xFFC00E44
+#define DMA2_9_X_COUNT 0xFFC00E50
+#define DMA2_9_Y_COUNT 0xFFC00E58
+#define DMA2_9_X_MODIFY 0xFFC00E54
+#define DMA2_9_Y_MODIFY 0xFFC00E5C
+#define DMA2_9_CURR_DESC_PTR 0xFFC00E60
+#define DMA2_9_CURR_ADDR 0xFFC00E64
+#define DMA2_9_CURR_X_COUNT 0xFFC00E70
+#define DMA2_9_CURR_Y_COUNT 0xFFC00E78
+#define DMA2_9_IRQ_STATUS 0xFFC00E68
+#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C
+#define DMA2_10_CONFIG 0xFFC00E88
+#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80
+#define DMA2_10_START_ADDR 0xFFC00E84
+#define DMA2_10_X_COUNT 0xFFC00E90
+#define DMA2_10_Y_COUNT 0xFFC00E98
+#define DMA2_10_X_MODIFY 0xFFC00E94
+#define DMA2_10_Y_MODIFY 0xFFC00E9C
+#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0
+#define DMA2_10_CURR_ADDR 0xFFC00EA4
+#define DMA2_10_CURR_X_COUNT 0xFFC00EB0
+#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8
+#define DMA2_10_IRQ_STATUS 0xFFC00EA8
+#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC
+#define DMA2_11_CONFIG 0xFFC00EC8
+#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0
+#define DMA2_11_START_ADDR 0xFFC00EC4
+#define DMA2_11_X_COUNT 0xFFC00ED0
+#define DMA2_11_Y_COUNT 0xFFC00ED8
+#define DMA2_11_X_MODIFY 0xFFC00ED4
+#define DMA2_11_Y_MODIFY 0xFFC00EDC
+#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0
+#define DMA2_11_CURR_ADDR 0xFFC00EE4
+#define DMA2_11_CURR_X_COUNT 0xFFC00EF0
+#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8
+#define DMA2_11_IRQ_STATUS 0xFFC00EE8
+#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC
+#define IMDMA_S0_CONFIG 0xFFC01848
+#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840
+#define IMDMA_S0_START_ADDR 0xFFC01844
+#define IMDMA_S0_X_COUNT 0xFFC01850
+#define IMDMA_S0_Y_COUNT 0xFFC01858
+#define IMDMA_S0_X_MODIFY 0xFFC01854
+#define IMDMA_S0_Y_MODIFY 0xFFC0185C
+#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860
+#define IMDMA_S0_CURR_ADDR 0xFFC01864
+#define IMDMA_S0_CURR_X_COUNT 0xFFC01870
+#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878
+#define IMDMA_S0_IRQ_STATUS 0xFFC01868
+#define IMDMA_D0_CONFIG 0xFFC01808
+#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800
+#define IMDMA_D0_START_ADDR 0xFFC01804
+#define IMDMA_D0_X_COUNT 0xFFC01810
+#define IMDMA_D0_Y_COUNT 0xFFC01818
+#define IMDMA_D0_X_MODIFY 0xFFC01814
+#define IMDMA_D0_Y_MODIFY 0xFFC0181C
+#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820
+#define IMDMA_D0_CURR_ADDR 0xFFC01824
+#define IMDMA_D0_CURR_X_COUNT 0xFFC01830
+#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838
+#define IMDMA_D0_IRQ_STATUS 0xFFC01828
+#define IMDMA_S1_CONFIG 0xFFC018C8
+#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0
+#define IMDMA_S1_START_ADDR 0xFFC018C4
+#define IMDMA_S1_X_COUNT 0xFFC018D0
+#define IMDMA_S1_Y_COUNT 0xFFC018D8
+#define IMDMA_S1_X_MODIFY 0xFFC018D4
+#define IMDMA_S1_Y_MODIFY 0xFFC018DC
+#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0
+#define IMDMA_S1_CURR_ADDR 0xFFC018E4
+#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0
+#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8
+#define IMDMA_S1_IRQ_STATUS 0xFFC018E8
+#define IMDMA_D1_CONFIG 0xFFC01888
+#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880
+#define IMDMA_D1_START_ADDR 0xFFC01884
+#define IMDMA_D1_X_COUNT 0xFFC01890
+#define IMDMA_D1_Y_COUNT 0xFFC01898
+#define IMDMA_D1_X_MODIFY 0xFFC01894
+#define IMDMA_D1_Y_MODIFY 0xFFC0189C
+#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0
+#define IMDMA_D1_CURR_ADDR 0xFFC018A4
+#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0
+#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8
+#define IMDMA_D1_IRQ_STATUS 0xFFC018A8
+#define MDMA1_S0_CONFIG 0xFFC01F48
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
+#define MDMA1_S0_START_ADDR 0xFFC01F44
+#define MDMA1_S0_X_COUNT 0xFFC01F50
+#define MDMA1_S0_Y_COUNT 0xFFC01F58
+#define MDMA1_S0_X_MODIFY 0xFFC01F54
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
+#define MDMA1_D0_CONFIG 0xFFC01F08
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
+#define MDMA1_D0_START_ADDR 0xFFC01F04
+#define MDMA1_D0_X_COUNT 0xFFC01F10
+#define MDMA1_D0_Y_COUNT 0xFFC01F18
+#define MDMA1_D0_X_MODIFY 0xFFC01F14
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
+#define MDMA1_S1_CONFIG 0xFFC01FC8
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
+#define MDMA1_S1_START_ADDR 0xFFC01FC4
+#define MDMA1_S1_X_COUNT 0xFFC01FD0
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
+#define MDMA1_D1_CONFIG 0xFFC01F88
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
+#define MDMA1_D1_START_ADDR 0xFFC01F84
+#define MDMA1_D1_X_COUNT 0xFFC01F90
+#define MDMA1_D1_Y_COUNT 0xFFC01F98
+#define MDMA1_D1_X_MODIFY 0xFFC01F94
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
+#define MDMA2_S0_CONFIG 0xFFC00F48
+#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40
+#define MDMA2_S0_START_ADDR 0xFFC00F44
+#define MDMA2_S0_X_COUNT 0xFFC00F50
+#define MDMA2_S0_Y_COUNT 0xFFC00F58
+#define MDMA2_S0_X_MODIFY 0xFFC00F54
+#define MDMA2_S0_Y_MODIFY 0xFFC00F5C
+#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60
+#define MDMA2_S0_CURR_ADDR 0xFFC00F64
+#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70
+#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78
+#define MDMA2_S0_IRQ_STATUS 0xFFC00F68
+#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C
+#define MDMA2_D0_CONFIG 0xFFC00F08
+#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00
+#define MDMA2_D0_START_ADDR 0xFFC00F04
+#define MDMA2_D0_X_COUNT 0xFFC00F10
+#define MDMA2_D0_Y_COUNT 0xFFC00F18
+#define MDMA2_D0_X_MODIFY 0xFFC00F14
+#define MDMA2_D0_Y_MODIFY 0xFFC00F1C
+#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20
+#define MDMA2_D0_CURR_ADDR 0xFFC00F24
+#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30
+#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38
+#define MDMA2_D0_IRQ_STATUS 0xFFC00F28
+#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C
+#define MDMA2_S1_CONFIG 0xFFC00FC8
+#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0
+#define MDMA2_S1_START_ADDR 0xFFC00FC4
+#define MDMA2_S1_X_COUNT 0xFFC00FD0
+#define MDMA2_S1_Y_COUNT 0xFFC00FD8
+#define MDMA2_S1_X_MODIFY 0xFFC00FD4
+#define MDMA2_S1_Y_MODIFY 0xFFC00FDC
+#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0
+#define MDMA2_S1_CURR_ADDR 0xFFC00FE4
+#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0
+#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8
+#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8
+#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC
+#define MDMA2_D1_CONFIG 0xFFC00F88
+#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80
+#define MDMA2_D1_START_ADDR 0xFFC00F84
+#define MDMA2_D1_X_COUNT 0xFFC00F90
+#define MDMA2_D1_Y_COUNT 0xFFC00F98
+#define MDMA2_D1_X_MODIFY 0xFFC00F94
+#define MDMA2_D1_Y_MODIFY 0xFFC00F9C
+#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0
+#define MDMA2_D1_CURR_ADDR 0xFFC00FA4
+#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0
+#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8
+#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8
+#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC
+#define TIMER0_CONFIG 0xFFC00600
+#define TIMER0_COUNTER 0xFFC00604
+#define TIMER0_PERIOD 0xFFC00608
+#define TIMER0_WIDTH 0xFFC0060C
+#define TIMER1_CONFIG 0xFFC00610
+#define TIMER1_COUNTER 0xFFC00614
+#define TIMER1_PERIOD 0xFFC00618
+#define TIMER1_WIDTH 0xFFC0061C
+#define TIMER2_CONFIG 0xFFC00620
+#define TIMER2_COUNTER 0xFFC00624
+#define TIMER2_PERIOD 0xFFC00628
+#define TIMER2_WIDTH 0xFFC0062C
+#define TIMER3_CONFIG 0xFFC00630
+#define TIMER3_COUNTER 0xFFC00634
+#define TIMER3_PERIOD 0xFFC00638
+#define TIMER3_WIDTH 0xFFC0063C
+#define TIMER4_CONFIG 0xFFC00640
+#define TIMER4_COUNTER 0xFFC00644
+#define TIMER4_PERIOD 0xFFC00648
+#define TIMER4_WIDTH 0xFFC0064C
+#define TIMER5_CONFIG 0xFFC00650
+#define TIMER5_COUNTER 0xFFC00654
+#define TIMER5_PERIOD 0xFFC00658
+#define TIMER5_WIDTH 0xFFC0065C
+#define TIMER6_CONFIG 0xFFC00660
+#define TIMER6_COUNTER 0xFFC00664
+#define TIMER6_PERIOD 0xFFC00668
+#define TIMER6_WIDTH 0xFFC0066C
+#define TIMER7_CONFIG 0xFFC00670
+#define TIMER7_COUNTER 0xFFC00674
+#define TIMER7_PERIOD 0xFFC00678
+#define TIMER7_WIDTH 0xFFC0067C
+#define TIMER8_CONFIG 0xFFC01600
+#define TIMER8_COUNTER 0xFFC01604
+#define TIMER8_PERIOD 0xFFC01608
+#define TIMER8_WIDTH 0xFFC0160C
+#define TIMER9_CONFIG 0xFFC01610
+#define TIMER9_COUNTER 0xFFC01614
+#define TIMER9_PERIOD 0xFFC01618
+#define TIMER9_WIDTH 0xFFC0161C
+#define TIMER10_CONFIG 0xFFC01620
+#define TIMER10_COUNTER 0xFFC01624
+#define TIMER10_PERIOD 0xFFC01628
+#define TIMER10_WIDTH 0xFFC0162C
+#define TIMER11_CONFIG 0xFFC01630
+#define TIMER11_COUNTER 0xFFC01634
+#define TIMER11_PERIOD 0xFFC01638
+#define TIMER11_WIDTH 0xFFC0163C
+#define TMRS4_ENABLE 0xFFC01640
+#define TMRS4_DISABLE 0xFFC01644
+#define TMRS4_STATUS 0xFFC01648
+#define TMRS8_ENABLE 0xFFC00680
+#define TMRS8_DISABLE 0xFFC00684
+#define TMRS8_STATUS 0xFFC00688
+#define FIO0_FLAG_D 0xFFC00700
+#define FIO0_FLAG_C 0xFFC00704
+#define FIO0_FLAG_S 0xFFC00708
+#define FIO0_FLAG_T 0xFFC0070C
+#define FIO0_MASKA_D 0xFFC00710
+#define FIO0_MASKA_C 0xFFC00714
+#define FIO0_MASKA_S 0xFFC00718
+#define FIO0_MASKA_T 0xFFC0071C
+#define FIO0_MASKB_D 0xFFC00720
+#define FIO0_MASKB_C 0xFFC00724
+#define FIO0_MASKB_S 0xFFC00728
+#define FIO0_MASKB_T 0xFFC0072C
+#define FIO0_DIR 0xFFC00730
+#define FIO0_POLAR 0xFFC00734
+#define FIO0_EDGE 0xFFC00738
+#define FIO0_BOTH 0xFFC0073C
+#define FIO0_INEN 0xFFC00740
+#define FIO1_FLAG_D 0xFFC01500
+#define FIO1_FLAG_C 0xFFC01504
+#define FIO1_FLAG_S 0xFFC01508
+#define FIO1_FLAG_T 0xFFC0150C
+#define FIO1_MASKA_D 0xFFC01510
+#define FIO1_MASKA_C 0xFFC01514
+#define FIO1_MASKA_S 0xFFC01518
+#define FIO1_MASKA_T 0xFFC0151C
+#define FIO1_MASKB_D 0xFFC01520
+#define FIO1_MASKB_C 0xFFC01524
+#define FIO1_MASKB_S 0xFFC01528
+#define FIO1_MASKB_T 0xFFC0152C
+#define FIO1_DIR 0xFFC01530
+#define FIO1_POLAR 0xFFC01534
+#define FIO1_EDGE 0xFFC01538
+#define FIO1_BOTH 0xFFC0153C
+#define FIO1_INEN 0xFFC01540
+#define FIO2_FLAG_D 0xFFC01700
+#define FIO2_FLAG_C 0xFFC01704
+#define FIO2_FLAG_S 0xFFC01708
+#define FIO2_FLAG_T 0xFFC0170C
+#define FIO2_MASKA_D 0xFFC01710
+#define FIO2_MASKA_C 0xFFC01714
+#define FIO2_MASKA_S 0xFFC01718
+#define FIO2_MASKA_T 0xFFC0171C
+#define FIO2_MASKB_D 0xFFC01720
+#define FIO2_MASKB_C 0xFFC01724
+#define FIO2_MASKB_S 0xFFC01728
+#define FIO2_MASKB_T 0xFFC0172C
+#define FIO2_DIR 0xFFC01730
+#define FIO2_POLAR 0xFFC01734
+#define FIO2_EDGE 0xFFC01738
+#define FIO2_BOTH 0xFFC0173C
+#define FIO2_INEN 0xFFC01740
+#define SPORT0_TCR1 0xFFC00800
+#define SPORT0_TCR2 0xFFC00804
+#define SPORT0_TCLKDIV 0xFFC00808
+#define SPORT0_TFSDIV 0xFFC0080C
+#define SPORT0_TX 0xFFC00810
+#define SPORT0_RX 0xFFC00818
+#define SPORT0_RCR1 0xFFC00820
+#define SPORT0_RCR2 0xFFC00824
+#define SPORT0_RCLKDIV 0xFFC00828
+#define SPORT0_RFSDIV 0xFFC0082C
+#define SPORT0_STAT 0xFFC00830
+#define SPORT0_CHNL 0xFFC00834
+#define SPORT0_MCMC1 0xFFC00838
+#define SPORT0_MCMC2 0xFFC0083C
+#define SPORT0_MTCS0 0xFFC00840
+#define SPORT0_MTCS1 0xFFC00844
+#define SPORT0_MTCS2 0xFFC00848
+#define SPORT0_MTCS3 0xFFC0084C
+#define SPORT0_MRCS0 0xFFC00850
+#define SPORT0_MRCS1 0xFFC00854
+#define SPORT0_MRCS2 0xFFC00858
+#define SPORT0_MRCS3 0xFFC0085C
+#define SPORT1_TCR1 0xFFC00900
+#define SPORT1_TCR2 0xFFC00904
+#define SPORT1_TCLKDIV 0xFFC00908
+#define SPORT1_TFSDIV 0xFFC0090C
+#define SPORT1_TX 0xFFC00910
+#define SPORT1_RX 0xFFC00918
+#define SPORT1_RCR1 0xFFC00920
+#define SPORT1_RCR2 0xFFC00924
+#define SPORT1_RCLKDIV 0xFFC00928
+#define SPORT1_RFSDIV 0xFFC0092C
+#define SPORT1_STAT 0xFFC00930
+#define SPORT1_CHNL 0xFFC00934
+#define SPORT1_MCMC1 0xFFC00938
+#define SPORT1_MCMC2 0xFFC0093C
+#define SPORT1_MTCS0 0xFFC00940
+#define SPORT1_MTCS1 0xFFC00944
+#define SPORT1_MTCS2 0xFFC00948
+#define SPORT1_MTCS3 0xFFC0094C
+#define SPORT1_MRCS0 0xFFC00950
+#define SPORT1_MRCS1 0xFFC00954
+#define SPORT1_MRCS2 0xFFC00958
+#define SPORT1_MRCS3 0xFFC0095C
#define SICA_SWRST 0xFFC00100
#define SICA_SYSCR 0xFFC00104
#define SICA_RVECT 0xFFC00108
#define PPI1_DELAY 0xFFC0130C
#define PPI1_COUNT 0xFFC01308
#define PPI1_FRAME 0xFFC01310
-#define TBUFCTL 0xFFE06000
-#define TBUFSTAT 0xFFE06004
-#define TBUF 0xFFE06100
-#define PFCTL 0xFFE08000
-#define PFCNTR0 0xFFE08100
-#define PFCNTR1 0xFFE08104
-#define SRAM_BASE_ADDR_CORE_A 0xFFE00000
-#define SRAM_BASE_ADDR_CORE_B 0xFFE00000
-#define EVT_OVERRIDE 0xFFE02100
#define UART_THR 0xFFC00400
#define UART_RBR 0xFFC00400
#define UART_DLL 0xFFC00400
*/
/* This file should be up to date with:
- * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* SCKELOW Feature Is Not Functional */
+#define ANOMALY_05000458 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
-#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
-#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
-
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pWDOGA_CTL ((uint16_t volatile *)WDOGA_CTL)
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val)
-#define pWDOGA_CNT ((uint32_t volatile *)WDOGA_CNT)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val)
-#define pWDOGA_STAT ((uint32_t volatile *)WDOGA_STAT)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val)
-#define pWDOGB_CTL ((uint16_t volatile *)WDOGB_CTL)
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val)
-#define pWDOGB_CNT ((uint32_t volatile *)WDOGB_CNT)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val)
-#define pWDOGB_STAT ((uint32_t volatile *)WDOGB_STAT)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val)
-#define pDMA1_TC_PER ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */
-#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
-#define pDMA1_TC_CNT ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */
-#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
-#define pDMA1_0_CONFIG ((uint16_t volatile *)DMA1_0_CONFIG)
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val)
-#define pDMA1_0_NEXT_DESC_PTR ((void * volatile *)DMA1_0_NEXT_DESC_PTR)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
-#define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR)
-#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
-#define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
-#define pDMA1_0_Y_COUNT ((uint16_t volatile *)DMA1_0_Y_COUNT)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
-#define pDMA1_0_X_MODIFY ((uint16_t volatile *)DMA1_0_X_MODIFY)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
-#define pDMA1_0_Y_MODIFY ((uint16_t volatile *)DMA1_0_Y_MODIFY)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
-#define pDMA1_0_CURR_DESC_PTR ((void * volatile *)DMA1_0_CURR_DESC_PTR)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
-#define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
-#define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
-#define pDMA1_0_CURR_Y_COUNT ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
-#define pDMA1_0_IRQ_STATUS ((uint16_t volatile *)DMA1_0_IRQ_STATUS)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
-#define pDMA1_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
-#define pDMA1_1_CONFIG ((uint16_t volatile *)DMA1_1_CONFIG)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val)
-#define pDMA1_1_NEXT_DESC_PTR ((void * volatile *)DMA1_1_NEXT_DESC_PTR)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
-#define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR)
-#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
-#define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
-#define pDMA1_1_Y_COUNT ((uint16_t volatile *)DMA1_1_Y_COUNT)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
-#define pDMA1_1_X_MODIFY ((uint16_t volatile *)DMA1_1_X_MODIFY)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
-#define pDMA1_1_Y_MODIFY ((uint16_t volatile *)DMA1_1_Y_MODIFY)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
-#define pDMA1_1_CURR_DESC_PTR ((void * volatile *)DMA1_1_CURR_DESC_PTR)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
-#define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
-#define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
-#define pDMA1_1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
-#define pDMA1_1_IRQ_STATUS ((uint16_t volatile *)DMA1_1_IRQ_STATUS)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
-#define pDMA1_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
-#define pDMA1_2_CONFIG ((uint16_t volatile *)DMA1_2_CONFIG)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val)
-#define pDMA1_2_NEXT_DESC_PTR ((void * volatile *)DMA1_2_NEXT_DESC_PTR)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
-#define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR)
-#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
-#define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
-#define pDMA1_2_Y_COUNT ((uint16_t volatile *)DMA1_2_Y_COUNT)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
-#define pDMA1_2_X_MODIFY ((uint16_t volatile *)DMA1_2_X_MODIFY)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
-#define pDMA1_2_Y_MODIFY ((uint16_t volatile *)DMA1_2_Y_MODIFY)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
-#define pDMA1_2_CURR_DESC_PTR ((void * volatile *)DMA1_2_CURR_DESC_PTR)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
-#define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
-#define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
-#define pDMA1_2_CURR_Y_COUNT ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
-#define pDMA1_2_IRQ_STATUS ((uint16_t volatile *)DMA1_2_IRQ_STATUS)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
-#define pDMA1_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
-#define pDMA1_3_CONFIG ((uint16_t volatile *)DMA1_3_CONFIG)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val)
-#define pDMA1_3_NEXT_DESC_PTR ((void * volatile *)DMA1_3_NEXT_DESC_PTR)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
-#define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR)
-#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
-#define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
-#define pDMA1_3_Y_COUNT ((uint16_t volatile *)DMA1_3_Y_COUNT)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
-#define pDMA1_3_X_MODIFY ((uint16_t volatile *)DMA1_3_X_MODIFY)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
-#define pDMA1_3_Y_MODIFY ((uint16_t volatile *)DMA1_3_Y_MODIFY)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
-#define pDMA1_3_CURR_DESC_PTR ((void * volatile *)DMA1_3_CURR_DESC_PTR)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
-#define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
-#define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
-#define pDMA1_3_CURR_Y_COUNT ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
-#define pDMA1_3_IRQ_STATUS ((uint16_t volatile *)DMA1_3_IRQ_STATUS)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
-#define pDMA1_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
-#define pDMA1_4_CONFIG ((uint16_t volatile *)DMA1_4_CONFIG)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val)
-#define pDMA1_4_NEXT_DESC_PTR ((void * volatile *)DMA1_4_NEXT_DESC_PTR)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
-#define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR)
-#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
-#define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
-#define pDMA1_4_Y_COUNT ((uint16_t volatile *)DMA1_4_Y_COUNT)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
-#define pDMA1_4_X_MODIFY ((uint16_t volatile *)DMA1_4_X_MODIFY)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
-#define pDMA1_4_Y_MODIFY ((uint16_t volatile *)DMA1_4_Y_MODIFY)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
-#define pDMA1_4_CURR_DESC_PTR ((void * volatile *)DMA1_4_CURR_DESC_PTR)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
-#define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
-#define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
-#define pDMA1_4_CURR_Y_COUNT ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
-#define pDMA1_4_IRQ_STATUS ((uint16_t volatile *)DMA1_4_IRQ_STATUS)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
-#define pDMA1_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
-#define pDMA1_5_CONFIG ((uint16_t volatile *)DMA1_5_CONFIG)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val)
-#define pDMA1_5_NEXT_DESC_PTR ((void * volatile *)DMA1_5_NEXT_DESC_PTR)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
-#define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR)
-#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
-#define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
-#define pDMA1_5_Y_COUNT ((uint16_t volatile *)DMA1_5_Y_COUNT)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
-#define pDMA1_5_X_MODIFY ((uint16_t volatile *)DMA1_5_X_MODIFY)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
-#define pDMA1_5_Y_MODIFY ((uint16_t volatile *)DMA1_5_Y_MODIFY)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
-#define pDMA1_5_CURR_DESC_PTR ((void * volatile *)DMA1_5_CURR_DESC_PTR)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
-#define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
-#define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
-#define pDMA1_5_CURR_Y_COUNT ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
-#define pDMA1_5_IRQ_STATUS ((uint16_t volatile *)DMA1_5_IRQ_STATUS)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
-#define pDMA1_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
-#define pDMA1_6_CONFIG ((uint16_t volatile *)DMA1_6_CONFIG)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val)
-#define pDMA1_6_NEXT_DESC_PTR ((void * volatile *)DMA1_6_NEXT_DESC_PTR)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
-#define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR)
-#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
-#define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
-#define pDMA1_6_Y_COUNT ((uint16_t volatile *)DMA1_6_Y_COUNT)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
-#define pDMA1_6_X_MODIFY ((uint16_t volatile *)DMA1_6_X_MODIFY)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
-#define pDMA1_6_Y_MODIFY ((uint16_t volatile *)DMA1_6_Y_MODIFY)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
-#define pDMA1_6_CURR_DESC_PTR ((void * volatile *)DMA1_6_CURR_DESC_PTR)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
-#define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
-#define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
-#define pDMA1_6_CURR_Y_COUNT ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
-#define pDMA1_6_IRQ_STATUS ((uint16_t volatile *)DMA1_6_IRQ_STATUS)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
-#define pDMA1_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
-#define pDMA1_7_CONFIG ((uint16_t volatile *)DMA1_7_CONFIG)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val)
-#define pDMA1_7_NEXT_DESC_PTR ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
-#define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR)
-#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
-#define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
-#define pDMA1_7_Y_COUNT ((uint16_t volatile *)DMA1_7_Y_COUNT)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
-#define pDMA1_7_X_MODIFY ((uint16_t volatile *)DMA1_7_X_MODIFY)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
-#define pDMA1_7_Y_MODIFY ((uint16_t volatile *)DMA1_7_Y_MODIFY)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
-#define pDMA1_7_CURR_DESC_PTR ((void * volatile *)DMA1_7_CURR_DESC_PTR)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
-#define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
-#define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
-#define pDMA1_7_CURR_Y_COUNT ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
-#define pDMA1_7_IRQ_STATUS ((uint16_t volatile *)DMA1_7_IRQ_STATUS)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
-#define pDMA1_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
-#define pDMA1_8_CONFIG ((uint16_t volatile *)DMA1_8_CONFIG)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val)
-#define pDMA1_8_NEXT_DESC_PTR ((void * volatile *)DMA1_8_NEXT_DESC_PTR)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
-#define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR)
-#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
-#define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
-#define pDMA1_8_Y_COUNT ((uint16_t volatile *)DMA1_8_Y_COUNT)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
-#define pDMA1_8_X_MODIFY ((uint16_t volatile *)DMA1_8_X_MODIFY)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
-#define pDMA1_8_Y_MODIFY ((uint16_t volatile *)DMA1_8_Y_MODIFY)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
-#define pDMA1_8_CURR_DESC_PTR ((void * volatile *)DMA1_8_CURR_DESC_PTR)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
-#define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
-#define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
-#define pDMA1_8_CURR_Y_COUNT ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
-#define pDMA1_8_IRQ_STATUS ((uint16_t volatile *)DMA1_8_IRQ_STATUS)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
-#define pDMA1_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
-#define pDMA1_9_CONFIG ((uint16_t volatile *)DMA1_9_CONFIG)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val)
-#define pDMA1_9_NEXT_DESC_PTR ((void * volatile *)DMA1_9_NEXT_DESC_PTR)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
-#define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR)
-#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
-#define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
-#define pDMA1_9_Y_COUNT ((uint16_t volatile *)DMA1_9_Y_COUNT)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
-#define pDMA1_9_X_MODIFY ((uint16_t volatile *)DMA1_9_X_MODIFY)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
-#define pDMA1_9_Y_MODIFY ((uint16_t volatile *)DMA1_9_Y_MODIFY)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
-#define pDMA1_9_CURR_DESC_PTR ((void * volatile *)DMA1_9_CURR_DESC_PTR)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
-#define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
-#define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
-#define pDMA1_9_CURR_Y_COUNT ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
-#define pDMA1_9_IRQ_STATUS ((uint16_t volatile *)DMA1_9_IRQ_STATUS)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
-#define pDMA1_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
-#define pDMA1_10_CONFIG ((uint16_t volatile *)DMA1_10_CONFIG)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
-#define pDMA1_10_NEXT_DESC_PTR ((void * volatile *)DMA1_10_NEXT_DESC_PTR)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
-#define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR)
-#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
-#define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
-#define pDMA1_10_Y_COUNT ((uint16_t volatile *)DMA1_10_Y_COUNT)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
-#define pDMA1_10_X_MODIFY ((uint16_t volatile *)DMA1_10_X_MODIFY)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
-#define pDMA1_10_Y_MODIFY ((uint16_t volatile *)DMA1_10_Y_MODIFY)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
-#define pDMA1_10_CURR_DESC_PTR ((void * volatile *)DMA1_10_CURR_DESC_PTR)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
-#define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
-#define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
-#define pDMA1_10_CURR_Y_COUNT ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
-#define pDMA1_10_IRQ_STATUS ((uint16_t volatile *)DMA1_10_IRQ_STATUS)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
-#define pDMA1_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
-#define pDMA1_11_CONFIG ((uint16_t volatile *)DMA1_11_CONFIG)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
-#define pDMA1_11_NEXT_DESC_PTR ((void * volatile *)DMA1_11_NEXT_DESC_PTR)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
-#define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR)
-#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
-#define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
-#define pDMA1_11_Y_COUNT ((uint16_t volatile *)DMA1_11_Y_COUNT)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
-#define pDMA1_11_X_MODIFY ((uint16_t volatile *)DMA1_11_X_MODIFY)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
-#define pDMA1_11_Y_MODIFY ((uint16_t volatile *)DMA1_11_Y_MODIFY)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
-#define pDMA1_11_CURR_DESC_PTR ((void * volatile *)DMA1_11_CURR_DESC_PTR)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
-#define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
-#define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
-#define pDMA1_11_CURR_Y_COUNT ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
-#define pDMA1_11_IRQ_STATUS ((uint16_t volatile *)DMA1_11_IRQ_STATUS)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
-#define pDMA1_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
-#define pDMA2_TC_PER ((uint16_t volatile *)DMA2_TC_PER)
-#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val)
-#define pDMA2_TC_CNT ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */
-#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val)
-#define pDMA2_0_CONFIG ((uint16_t volatile *)DMA2_0_CONFIG)
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val)
-#define pDMA2_0_NEXT_DESC_PTR ((void * volatile *)DMA2_0_NEXT_DESC_PTR)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
-#define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR)
-#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
-#define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
-#define pDMA2_0_Y_COUNT ((uint16_t volatile *)DMA2_0_Y_COUNT)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
-#define pDMA2_0_X_MODIFY ((uint16_t volatile *)DMA2_0_X_MODIFY)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
-#define pDMA2_0_Y_MODIFY ((uint16_t volatile *)DMA2_0_Y_MODIFY)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
-#define pDMA2_0_CURR_DESC_PTR ((void * volatile *)DMA2_0_CURR_DESC_PTR)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
-#define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
-#define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
-#define pDMA2_0_CURR_Y_COUNT ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
-#define pDMA2_0_IRQ_STATUS ((uint16_t volatile *)DMA2_0_IRQ_STATUS)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
-#define pDMA2_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
-#define pDMA2_1_CONFIG ((uint16_t volatile *)DMA2_1_CONFIG)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val)
-#define pDMA2_1_NEXT_DESC_PTR ((void * volatile *)DMA2_1_NEXT_DESC_PTR)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
-#define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR)
-#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
-#define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
-#define pDMA2_1_Y_COUNT ((uint16_t volatile *)DMA2_1_Y_COUNT)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
-#define pDMA2_1_X_MODIFY ((uint16_t volatile *)DMA2_1_X_MODIFY)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
-#define pDMA2_1_Y_MODIFY ((uint16_t volatile *)DMA2_1_Y_MODIFY)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
-#define pDMA2_1_CURR_DESC_PTR ((void * volatile *)DMA2_1_CURR_DESC_PTR)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
-#define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
-#define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
-#define pDMA2_1_CURR_Y_COUNT ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
-#define pDMA2_1_IRQ_STATUS ((uint16_t volatile *)DMA2_1_IRQ_STATUS)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
-#define pDMA2_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
-#define pDMA2_2_CONFIG ((uint16_t volatile *)DMA2_2_CONFIG)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val)
-#define pDMA2_2_NEXT_DESC_PTR ((void * volatile *)DMA2_2_NEXT_DESC_PTR)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
-#define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR)
-#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
-#define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
-#define pDMA2_2_Y_COUNT ((uint16_t volatile *)DMA2_2_Y_COUNT)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
-#define pDMA2_2_X_MODIFY ((uint16_t volatile *)DMA2_2_X_MODIFY)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
-#define pDMA2_2_Y_MODIFY ((uint16_t volatile *)DMA2_2_Y_MODIFY)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
-#define pDMA2_2_CURR_DESC_PTR ((void * volatile *)DMA2_2_CURR_DESC_PTR)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
-#define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
-#define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
-#define pDMA2_2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
-#define pDMA2_2_IRQ_STATUS ((uint16_t volatile *)DMA2_2_IRQ_STATUS)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
-#define pDMA2_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
-#define pDMA2_3_CONFIG ((uint16_t volatile *)DMA2_3_CONFIG)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val)
-#define pDMA2_3_NEXT_DESC_PTR ((void * volatile *)DMA2_3_NEXT_DESC_PTR)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
-#define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR)
-#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
-#define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
-#define pDMA2_3_Y_COUNT ((uint16_t volatile *)DMA2_3_Y_COUNT)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
-#define pDMA2_3_X_MODIFY ((uint16_t volatile *)DMA2_3_X_MODIFY)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
-#define pDMA2_3_Y_MODIFY ((uint16_t volatile *)DMA2_3_Y_MODIFY)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
-#define pDMA2_3_CURR_DESC_PTR ((void * volatile *)DMA2_3_CURR_DESC_PTR)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
-#define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
-#define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
-#define pDMA2_3_CURR_Y_COUNT ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
-#define pDMA2_3_IRQ_STATUS ((uint16_t volatile *)DMA2_3_IRQ_STATUS)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
-#define pDMA2_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
-#define pDMA2_4_CONFIG ((uint16_t volatile *)DMA2_4_CONFIG)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val)
-#define pDMA2_4_NEXT_DESC_PTR ((void * volatile *)DMA2_4_NEXT_DESC_PTR)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
-#define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR)
-#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
-#define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
-#define pDMA2_4_Y_COUNT ((uint16_t volatile *)DMA2_4_Y_COUNT)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
-#define pDMA2_4_X_MODIFY ((uint16_t volatile *)DMA2_4_X_MODIFY)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
-#define pDMA2_4_Y_MODIFY ((uint16_t volatile *)DMA2_4_Y_MODIFY)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
-#define pDMA2_4_CURR_DESC_PTR ((void * volatile *)DMA2_4_CURR_DESC_PTR)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
-#define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
-#define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
-#define pDMA2_4_CURR_Y_COUNT ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
-#define pDMA2_4_IRQ_STATUS ((uint16_t volatile *)DMA2_4_IRQ_STATUS)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
-#define pDMA2_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
-#define pDMA2_5_CONFIG ((uint16_t volatile *)DMA2_5_CONFIG)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val)
-#define pDMA2_5_NEXT_DESC_PTR ((void * volatile *)DMA2_5_NEXT_DESC_PTR)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
-#define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR)
-#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
-#define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
-#define pDMA2_5_Y_COUNT ((uint16_t volatile *)DMA2_5_Y_COUNT)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
-#define pDMA2_5_X_MODIFY ((uint16_t volatile *)DMA2_5_X_MODIFY)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
-#define pDMA2_5_Y_MODIFY ((uint16_t volatile *)DMA2_5_Y_MODIFY)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
-#define pDMA2_5_CURR_DESC_PTR ((void * volatile *)DMA2_5_CURR_DESC_PTR)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
-#define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
-#define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
-#define pDMA2_5_CURR_Y_COUNT ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
-#define pDMA2_5_IRQ_STATUS ((uint16_t volatile *)DMA2_5_IRQ_STATUS)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
-#define pDMA2_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
-#define pDMA2_6_CONFIG ((uint16_t volatile *)DMA2_6_CONFIG)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val)
-#define pDMA2_6_NEXT_DESC_PTR ((void * volatile *)DMA2_6_NEXT_DESC_PTR)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
-#define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR)
-#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
-#define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
-#define pDMA2_6_Y_COUNT ((uint16_t volatile *)DMA2_6_Y_COUNT)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
-#define pDMA2_6_X_MODIFY ((uint16_t volatile *)DMA2_6_X_MODIFY)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
-#define pDMA2_6_Y_MODIFY ((uint16_t volatile *)DMA2_6_Y_MODIFY)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
-#define pDMA2_6_CURR_DESC_PTR ((void * volatile *)DMA2_6_CURR_DESC_PTR)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
-#define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
-#define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
-#define pDMA2_6_CURR_Y_COUNT ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
-#define pDMA2_6_IRQ_STATUS ((uint16_t volatile *)DMA2_6_IRQ_STATUS)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
-#define pDMA2_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
-#define pDMA2_7_CONFIG ((uint16_t volatile *)DMA2_7_CONFIG)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val)
-#define pDMA2_7_NEXT_DESC_PTR ((void * volatile *)DMA2_7_NEXT_DESC_PTR)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
-#define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR)
-#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
-#define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
-#define pDMA2_7_Y_COUNT ((uint16_t volatile *)DMA2_7_Y_COUNT)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
-#define pDMA2_7_X_MODIFY ((uint16_t volatile *)DMA2_7_X_MODIFY)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
-#define pDMA2_7_Y_MODIFY ((uint16_t volatile *)DMA2_7_Y_MODIFY)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
-#define pDMA2_7_CURR_DESC_PTR ((void * volatile *)DMA2_7_CURR_DESC_PTR)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
-#define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
-#define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
-#define pDMA2_7_CURR_Y_COUNT ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
-#define pDMA2_7_IRQ_STATUS ((uint16_t volatile *)DMA2_7_IRQ_STATUS)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
-#define pDMA2_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
-#define pDMA2_8_CONFIG ((uint16_t volatile *)DMA2_8_CONFIG)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val)
-#define pDMA2_8_NEXT_DESC_PTR ((void * volatile *)DMA2_8_NEXT_DESC_PTR)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
-#define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR)
-#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
-#define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
-#define pDMA2_8_Y_COUNT ((uint16_t volatile *)DMA2_8_Y_COUNT)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
-#define pDMA2_8_X_MODIFY ((uint16_t volatile *)DMA2_8_X_MODIFY)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
-#define pDMA2_8_Y_MODIFY ((uint16_t volatile *)DMA2_8_Y_MODIFY)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
-#define pDMA2_8_CURR_DESC_PTR ((void * volatile *)DMA2_8_CURR_DESC_PTR)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
-#define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
-#define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
-#define pDMA2_8_CURR_Y_COUNT ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
-#define pDMA2_8_IRQ_STATUS ((uint16_t volatile *)DMA2_8_IRQ_STATUS)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
-#define pDMA2_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
-#define pDMA2_9_CONFIG ((uint16_t volatile *)DMA2_9_CONFIG)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val)
-#define pDMA2_9_NEXT_DESC_PTR ((void * volatile *)DMA2_9_NEXT_DESC_PTR)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
-#define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR)
-#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
-#define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
-#define pDMA2_9_Y_COUNT ((uint16_t volatile *)DMA2_9_Y_COUNT)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
-#define pDMA2_9_X_MODIFY ((uint16_t volatile *)DMA2_9_X_MODIFY)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
-#define pDMA2_9_Y_MODIFY ((uint16_t volatile *)DMA2_9_Y_MODIFY)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
-#define pDMA2_9_CURR_DESC_PTR ((void * volatile *)DMA2_9_CURR_DESC_PTR)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
-#define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
-#define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
-#define pDMA2_9_CURR_Y_COUNT ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
-#define pDMA2_9_IRQ_STATUS ((uint16_t volatile *)DMA2_9_IRQ_STATUS)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
-#define pDMA2_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
-#define pDMA2_10_CONFIG ((uint16_t volatile *)DMA2_10_CONFIG)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
-#define pDMA2_10_NEXT_DESC_PTR ((void * volatile *)DMA2_10_NEXT_DESC_PTR)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
-#define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR)
-#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
-#define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
-#define pDMA2_10_Y_COUNT ((uint16_t volatile *)DMA2_10_Y_COUNT)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
-#define pDMA2_10_X_MODIFY ((uint16_t volatile *)DMA2_10_X_MODIFY)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
-#define pDMA2_10_Y_MODIFY ((uint16_t volatile *)DMA2_10_Y_MODIFY)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
-#define pDMA2_10_CURR_DESC_PTR ((void * volatile *)DMA2_10_CURR_DESC_PTR)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
-#define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
-#define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
-#define pDMA2_10_CURR_Y_COUNT ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
-#define pDMA2_10_IRQ_STATUS ((uint16_t volatile *)DMA2_10_IRQ_STATUS)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
-#define pDMA2_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
-#define pDMA2_11_CONFIG ((uint16_t volatile *)DMA2_11_CONFIG)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
-#define pDMA2_11_NEXT_DESC_PTR ((void * volatile *)DMA2_11_NEXT_DESC_PTR)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
-#define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR)
-#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
-#define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
-#define pDMA2_11_Y_COUNT ((uint16_t volatile *)DMA2_11_Y_COUNT)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
-#define pDMA2_11_X_MODIFY ((uint16_t volatile *)DMA2_11_X_MODIFY)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
-#define pDMA2_11_Y_MODIFY ((uint16_t volatile *)DMA2_11_Y_MODIFY)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
-#define pDMA2_11_CURR_DESC_PTR ((void * volatile *)DMA2_11_CURR_DESC_PTR)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
-#define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
-#define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
-#define pDMA2_11_CURR_Y_COUNT ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
-#define pDMA2_11_IRQ_STATUS ((uint16_t volatile *)DMA2_11_IRQ_STATUS)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
-#define pDMA2_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
-#define pIMDMA_S0_CONFIG ((uint16_t volatile *)IMDMA_S0_CONFIG)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
-#define pIMDMA_S0_NEXT_DESC_PTR ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
-#define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
-#define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
-#define pIMDMA_S0_Y_COUNT ((uint16_t volatile *)IMDMA_S0_Y_COUNT)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
-#define pIMDMA_S0_X_MODIFY ((uint16_t volatile *)IMDMA_S0_X_MODIFY)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
-#define pIMDMA_S0_Y_MODIFY ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
-#define pIMDMA_S0_CURR_DESC_PTR ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
-#define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
-#define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
-#define pIMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
-#define pIMDMA_S0_IRQ_STATUS ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
-#define pIMDMA_D0_CONFIG ((uint16_t volatile *)IMDMA_D0_CONFIG)
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
-#define pIMDMA_D0_NEXT_DESC_PTR ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
-#define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
-#define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
-#define pIMDMA_D0_Y_COUNT ((uint16_t volatile *)IMDMA_D0_Y_COUNT)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
-#define pIMDMA_D0_X_MODIFY ((uint16_t volatile *)IMDMA_D0_X_MODIFY)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
-#define pIMDMA_D0_Y_MODIFY ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
-#define pIMDMA_D0_CURR_DESC_PTR ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
-#define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
-#define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
-#define pIMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
-#define pIMDMA_D0_IRQ_STATUS ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
-#define pIMDMA_S1_CONFIG ((uint16_t volatile *)IMDMA_S1_CONFIG)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
-#define pIMDMA_S1_NEXT_DESC_PTR ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
-#define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
-#define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
-#define pIMDMA_S1_Y_COUNT ((uint16_t volatile *)IMDMA_S1_Y_COUNT)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
-#define pIMDMA_S1_X_MODIFY ((uint16_t volatile *)IMDMA_S1_X_MODIFY)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
-#define pIMDMA_S1_Y_MODIFY ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
-#define pIMDMA_S1_CURR_DESC_PTR ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
-#define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
-#define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
-#define pIMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
-#define pIMDMA_S1_IRQ_STATUS ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
-#define pIMDMA_D1_CONFIG ((uint16_t volatile *)IMDMA_D1_CONFIG)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
-#define pIMDMA_D1_NEXT_DESC_PTR ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
-#define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
-#define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
-#define pIMDMA_D1_Y_COUNT ((uint16_t volatile *)IMDMA_D1_Y_COUNT)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
-#define pIMDMA_D1_X_MODIFY ((uint16_t volatile *)IMDMA_D1_X_MODIFY)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
-#define pIMDMA_D1_Y_MODIFY ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
-#define pIMDMA_D1_CURR_DESC_PTR ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
-#define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
-#define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
-#define pIMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
-#define pIMDMA_D1_IRQ_STATUS ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
-#define pMDMA1_S0_CONFIG ((uint16_t volatile *)MDMA1_S0_CONFIG)
-#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT)
-#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define pMDMA1_S0_Y_COUNT ((uint16_t volatile *)MDMA1_S0_Y_COUNT)
-#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define pMDMA1_S0_X_MODIFY ((uint16_t volatile *)MDMA1_S0_X_MODIFY)
-#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define pMDMA1_S0_Y_MODIFY ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)
-#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define pMDMA1_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define pMDMA1_S0_IRQ_STATUS ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define pMDMA1_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define pMDMA1_D0_CONFIG ((uint16_t volatile *)MDMA1_D0_CONFIG)
-#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT)
-#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define pMDMA1_D0_Y_COUNT ((uint16_t volatile *)MDMA1_D0_Y_COUNT)
-#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define pMDMA1_D0_X_MODIFY ((uint16_t volatile *)MDMA1_D0_X_MODIFY)
-#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define pMDMA1_D0_Y_MODIFY ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)
-#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define pMDMA1_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define pMDMA1_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define pMDMA1_S1_CONFIG ((uint16_t volatile *)MDMA1_S1_CONFIG)
-#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT)
-#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define pMDMA1_S1_Y_COUNT ((uint16_t volatile *)MDMA1_S1_Y_COUNT)
-#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define pMDMA1_S1_X_MODIFY ((uint16_t volatile *)MDMA1_S1_X_MODIFY)
-#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define pMDMA1_S1_Y_MODIFY ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)
-#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define pMDMA1_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define pMDMA1_S1_IRQ_STATUS ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define pMDMA1_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define pMDMA1_D1_CONFIG ((uint16_t volatile *)MDMA1_D1_CONFIG)
-#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT)
-#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define pMDMA1_D1_Y_COUNT ((uint16_t volatile *)MDMA1_D1_Y_COUNT)
-#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define pMDMA1_D1_X_MODIFY ((uint16_t volatile *)MDMA1_D1_X_MODIFY)
-#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define pMDMA1_D1_Y_MODIFY ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)
-#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define pMDMA1_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define pMDMA1_D1_IRQ_STATUS ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define pMDMA1_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define pMDMA2_S0_CONFIG ((uint16_t volatile *)MDMA2_S0_CONFIG)
-#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
-#define pMDMA2_S0_NEXT_DESC_PTR ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
-#define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR)
-#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
-#define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT)
-#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
-#define pMDMA2_S0_Y_COUNT ((uint16_t volatile *)MDMA2_S0_Y_COUNT)
-#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
-#define pMDMA2_S0_X_MODIFY ((uint16_t volatile *)MDMA2_S0_X_MODIFY)
-#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
-#define pMDMA2_S0_Y_MODIFY ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)
-#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
-#define pMDMA2_S0_CURR_DESC_PTR ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
-#define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR)
-#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
-#define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
-#define pMDMA2_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
-#define pMDMA2_S0_IRQ_STATUS ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)
-#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
-#define pMDMA2_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
-#define pMDMA2_D0_CONFIG ((uint16_t volatile *)MDMA2_D0_CONFIG)
-#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
-#define pMDMA2_D0_NEXT_DESC_PTR ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
-#define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR)
-#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
-#define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT)
-#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
-#define pMDMA2_D0_Y_COUNT ((uint16_t volatile *)MDMA2_D0_Y_COUNT)
-#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
-#define pMDMA2_D0_X_MODIFY ((uint16_t volatile *)MDMA2_D0_X_MODIFY)
-#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
-#define pMDMA2_D0_Y_MODIFY ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)
-#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
-#define pMDMA2_D0_CURR_DESC_PTR ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
-#define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR)
-#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
-#define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
-#define pMDMA2_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
-#define pMDMA2_D0_IRQ_STATUS ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)
-#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
-#define pMDMA2_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
-#define pMDMA2_S1_CONFIG ((uint16_t volatile *)MDMA2_S1_CONFIG)
-#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
-#define pMDMA2_S1_NEXT_DESC_PTR ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
-#define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR)
-#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
-#define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT)
-#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
-#define pMDMA2_S1_Y_COUNT ((uint16_t volatile *)MDMA2_S1_Y_COUNT)
-#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
-#define pMDMA2_S1_X_MODIFY ((uint16_t volatile *)MDMA2_S1_X_MODIFY)
-#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
-#define pMDMA2_S1_Y_MODIFY ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)
-#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
-#define pMDMA2_S1_CURR_DESC_PTR ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
-#define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR)
-#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
-#define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
-#define pMDMA2_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
-#define pMDMA2_S1_IRQ_STATUS ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)
-#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
-#define pMDMA2_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
-#define pMDMA2_D1_CONFIG ((uint16_t volatile *)MDMA2_D1_CONFIG)
-#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
-#define pMDMA2_D1_NEXT_DESC_PTR ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
-#define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR)
-#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
-#define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT)
-#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
-#define pMDMA2_D1_Y_COUNT ((uint16_t volatile *)MDMA2_D1_Y_COUNT)
-#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
-#define pMDMA2_D1_X_MODIFY ((uint16_t volatile *)MDMA2_D1_X_MODIFY)
-#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
-#define pMDMA2_D1_Y_MODIFY ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)
-#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
-#define pMDMA2_D1_CURR_DESC_PTR ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
-#define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR)
-#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
-#define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
-#define pMDMA2_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
-#define pMDMA2_D1_IRQ_STATUS ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)
-#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
-#define pMDMA2_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER11_CONFIG ((uint16_t volatile *)TIMER11_CONFIG)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
-#define pTIMER11_COUNTER ((uint32_t volatile *)TIMER11_COUNTER)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
-#define pTIMER11_PERIOD ((uint32_t volatile *)TIMER11_PERIOD)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
-#define pTIMER11_WIDTH ((uint32_t volatile *)TIMER11_WIDTH)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val)
-#define pTMRS4_ENABLE ((uint32_t volatile *)TMRS4_ENABLE)
-#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val)
-#define pTMRS4_DISABLE ((uint32_t volatile *)TMRS4_DISABLE)
-#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val)
-#define pTMRS4_STATUS ((uint32_t volatile *)TMRS4_STATUS)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val)
-#define pTMRS8_ENABLE ((uint32_t volatile *)TMRS8_ENABLE)
-#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val)
-#define pTMRS8_DISABLE ((uint32_t volatile *)TMRS8_DISABLE)
-#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val)
-#define pTMRS8_STATUS ((uint32_t volatile *)TMRS8_STATUS)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val)
-#define pFIO0_FLAG_D ((uint16_t volatile *)FIO0_FLAG_D)
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val)
-#define pFIO0_FLAG_C ((uint16_t volatile *)FIO0_FLAG_C)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val)
-#define pFIO0_FLAG_S ((uint16_t volatile *)FIO0_FLAG_S)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val)
-#define pFIO0_FLAG_T ((uint16_t volatile *)FIO0_FLAG_T)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val)
-#define pFIO0_MASKA_D ((uint16_t volatile *)FIO0_MASKA_D)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val)
-#define pFIO0_MASKA_C ((uint16_t volatile *)FIO0_MASKA_C)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val)
-#define pFIO0_MASKA_S ((uint16_t volatile *)FIO0_MASKA_S)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val)
-#define pFIO0_MASKA_T ((uint16_t volatile *)FIO0_MASKA_T)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val)
-#define pFIO0_MASKB_D ((uint16_t volatile *)FIO0_MASKB_D)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val)
-#define pFIO0_MASKB_C ((uint16_t volatile *)FIO0_MASKB_C)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val)
-#define pFIO0_MASKB_S ((uint16_t volatile *)FIO0_MASKB_S)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val)
-#define pFIO0_MASKB_T ((uint16_t volatile *)FIO0_MASKB_T)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val)
-#define pFIO0_DIR ((uint16_t volatile *)FIO0_DIR)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val)
-#define pFIO0_POLAR ((uint16_t volatile *)FIO0_POLAR)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val)
-#define pFIO0_EDGE ((uint16_t volatile *)FIO0_EDGE)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val)
-#define pFIO0_BOTH ((uint16_t volatile *)FIO0_BOTH)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val)
-#define pFIO0_INEN ((uint16_t volatile *)FIO0_INEN)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val)
-#define pFIO1_FLAG_D ((uint16_t volatile *)FIO1_FLAG_D)
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val)
-#define pFIO1_FLAG_C ((uint16_t volatile *)FIO1_FLAG_C)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val)
-#define pFIO1_FLAG_S ((uint16_t volatile *)FIO1_FLAG_S)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val)
-#define pFIO1_FLAG_T ((uint16_t volatile *)FIO1_FLAG_T)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val)
-#define pFIO1_MASKA_D ((uint16_t volatile *)FIO1_MASKA_D)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val)
-#define pFIO1_MASKA_C ((uint16_t volatile *)FIO1_MASKA_C)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val)
-#define pFIO1_MASKA_S ((uint16_t volatile *)FIO1_MASKA_S)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val)
-#define pFIO1_MASKA_T ((uint16_t volatile *)FIO1_MASKA_T)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val)
-#define pFIO1_MASKB_D ((uint16_t volatile *)FIO1_MASKB_D)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val)
-#define pFIO1_MASKB_C ((uint16_t volatile *)FIO1_MASKB_C)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val)
-#define pFIO1_MASKB_S ((uint16_t volatile *)FIO1_MASKB_S)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val)
-#define pFIO1_MASKB_T ((uint16_t volatile *)FIO1_MASKB_T)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val)
-#define pFIO1_DIR ((uint16_t volatile *)FIO1_DIR)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val)
-#define pFIO1_POLAR ((uint16_t volatile *)FIO1_POLAR)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val)
-#define pFIO1_EDGE ((uint16_t volatile *)FIO1_EDGE)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val)
-#define pFIO1_BOTH ((uint16_t volatile *)FIO1_BOTH)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val)
-#define pFIO1_INEN ((uint16_t volatile *)FIO1_INEN)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val)
-#define pFIO2_FLAG_D ((uint16_t volatile *)FIO2_FLAG_D)
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val)
-#define pFIO2_FLAG_C ((uint16_t volatile *)FIO2_FLAG_C)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val)
-#define pFIO2_FLAG_S ((uint16_t volatile *)FIO2_FLAG_S)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val)
-#define pFIO2_FLAG_T ((uint16_t volatile *)FIO2_FLAG_T)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val)
-#define pFIO2_MASKA_D ((uint16_t volatile *)FIO2_MASKA_D)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val)
-#define pFIO2_MASKA_C ((uint16_t volatile *)FIO2_MASKA_C)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val)
-#define pFIO2_MASKA_S ((uint16_t volatile *)FIO2_MASKA_S)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val)
-#define pFIO2_MASKA_T ((uint16_t volatile *)FIO2_MASKA_T)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val)
-#define pFIO2_MASKB_D ((uint16_t volatile *)FIO2_MASKB_D)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val)
-#define pFIO2_MASKB_C ((uint16_t volatile *)FIO2_MASKB_C)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val)
-#define pFIO2_MASKB_S ((uint16_t volatile *)FIO2_MASKB_S)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val)
-#define pFIO2_MASKB_T ((uint16_t volatile *)FIO2_MASKB_T)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val)
-#define pFIO2_DIR ((uint16_t volatile *)FIO2_DIR)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val)
-#define pFIO2_POLAR ((uint16_t volatile *)FIO2_POLAR)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val)
-#define pFIO2_EDGE ((uint16_t volatile *)FIO2_EDGE)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val)
-#define pFIO2_BOTH ((uint16_t volatile *)FIO2_BOTH)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val)
-#define pFIO2_INEN ((uint16_t volatile *)FIO2_INEN)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pEVT0 ((void * volatile *)EVT0)
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1)
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2)
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3)
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4)
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5)
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6)
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7)
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8)
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9)
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10)
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11)
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12)
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13)
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14)
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15)
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL)
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__
-#define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__
-
-#define PLL_CTL 0xFFC00000
-#define PLL_DIV 0xFFC00004
-#define VR_CTL 0xFFC00008
-#define PLL_STAT 0xFFC0000C
-#define PLL_LOCKCNT 0xFFC00010
-#define CHIPID 0xFFC00014
-#define SPI_CTL 0xFFC00500
-#define SPI_FLG 0xFFC00504
-#define SPI_STAT 0xFFC00508
-#define SPI_TDBR 0xFFC0050C
-#define SPI_RDBR 0xFFC00510
-#define SPI_BAUD 0xFFC00514
-#define SPI_SHADOW 0xFFC00518
-#define WDOGA_CTL 0xFFC00200
-#define WDOGA_CNT 0xFFC00204
-#define WDOGA_STAT 0xFFC00208
-#define WDOGB_CTL 0xFFC01200
-#define WDOGB_CNT 0xFFC01204
-#define WDOGB_STAT 0xFFC01208
-#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
-#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA1_0_CONFIG 0xFFC01C08
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00
-#define DMA1_0_START_ADDR 0xFFC01C04
-#define DMA1_0_X_COUNT 0xFFC01C10
-#define DMA1_0_Y_COUNT 0xFFC01C18
-#define DMA1_0_X_MODIFY 0xFFC01C14
-#define DMA1_0_Y_MODIFY 0xFFC01C1C
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20
-#define DMA1_0_CURR_ADDR 0xFFC01C24
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38
-#define DMA1_0_IRQ_STATUS 0xFFC01C28
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C
-#define DMA1_1_CONFIG 0xFFC01C48
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40
-#define DMA1_1_START_ADDR 0xFFC01C44
-#define DMA1_1_X_COUNT 0xFFC01C50
-#define DMA1_1_Y_COUNT 0xFFC01C58
-#define DMA1_1_X_MODIFY 0xFFC01C54
-#define DMA1_1_Y_MODIFY 0xFFC01C5C
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60
-#define DMA1_1_CURR_ADDR 0xFFC01C64
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78
-#define DMA1_1_IRQ_STATUS 0xFFC01C68
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C
-#define DMA1_2_CONFIG 0xFFC01C88
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80
-#define DMA1_2_START_ADDR 0xFFC01C84
-#define DMA1_2_X_COUNT 0xFFC01C90
-#define DMA1_2_Y_COUNT 0xFFC01C98
-#define DMA1_2_X_MODIFY 0xFFC01C94
-#define DMA1_2_Y_MODIFY 0xFFC01C9C
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0
-#define DMA1_2_CURR_ADDR 0xFFC01CA4
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC
-#define DMA1_3_CONFIG 0xFFC01CC8
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0
-#define DMA1_3_START_ADDR 0xFFC01CC4
-#define DMA1_3_X_COUNT 0xFFC01CD0
-#define DMA1_3_Y_COUNT 0xFFC01CD8
-#define DMA1_3_X_MODIFY 0xFFC01CD4
-#define DMA1_3_Y_MODIFY 0xFFC01CDC
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0
-#define DMA1_3_CURR_ADDR 0xFFC01CE4
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC
-#define DMA1_4_CONFIG 0xFFC01D08
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00
-#define DMA1_4_START_ADDR 0xFFC01D04
-#define DMA1_4_X_COUNT 0xFFC01D10
-#define DMA1_4_Y_COUNT 0xFFC01D18
-#define DMA1_4_X_MODIFY 0xFFC01D14
-#define DMA1_4_Y_MODIFY 0xFFC01D1C
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20
-#define DMA1_4_CURR_ADDR 0xFFC01D24
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38
-#define DMA1_4_IRQ_STATUS 0xFFC01D28
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C
-#define DMA1_5_CONFIG 0xFFC01D48
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40
-#define DMA1_5_START_ADDR 0xFFC01D44
-#define DMA1_5_X_COUNT 0xFFC01D50
-#define DMA1_5_Y_COUNT 0xFFC01D58
-#define DMA1_5_X_MODIFY 0xFFC01D54
-#define DMA1_5_Y_MODIFY 0xFFC01D5C
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60
-#define DMA1_5_CURR_ADDR 0xFFC01D64
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78
-#define DMA1_5_IRQ_STATUS 0xFFC01D68
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C
-#define DMA1_6_CONFIG 0xFFC01D88
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80
-#define DMA1_6_START_ADDR 0xFFC01D84
-#define DMA1_6_X_COUNT 0xFFC01D90
-#define DMA1_6_Y_COUNT 0xFFC01D98
-#define DMA1_6_X_MODIFY 0xFFC01D94
-#define DMA1_6_Y_MODIFY 0xFFC01D9C
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0
-#define DMA1_6_CURR_ADDR 0xFFC01DA4
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC
-#define DMA1_7_CONFIG 0xFFC01DC8
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0
-#define DMA1_7_START_ADDR 0xFFC01DC4
-#define DMA1_7_X_COUNT 0xFFC01DD0
-#define DMA1_7_Y_COUNT 0xFFC01DD8
-#define DMA1_7_X_MODIFY 0xFFC01DD4
-#define DMA1_7_Y_MODIFY 0xFFC01DDC
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0
-#define DMA1_7_CURR_ADDR 0xFFC01DE4
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC
-#define DMA1_8_CONFIG 0xFFC01E08
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00
-#define DMA1_8_START_ADDR 0xFFC01E04
-#define DMA1_8_X_COUNT 0xFFC01E10
-#define DMA1_8_Y_COUNT 0xFFC01E18
-#define DMA1_8_X_MODIFY 0xFFC01E14
-#define DMA1_8_Y_MODIFY 0xFFC01E1C
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20
-#define DMA1_8_CURR_ADDR 0xFFC01E24
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38
-#define DMA1_8_IRQ_STATUS 0xFFC01E28
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C
-#define DMA1_9_CONFIG 0xFFC01E48
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40
-#define DMA1_9_START_ADDR 0xFFC01E44
-#define DMA1_9_X_COUNT 0xFFC01E50
-#define DMA1_9_Y_COUNT 0xFFC01E58
-#define DMA1_9_X_MODIFY 0xFFC01E54
-#define DMA1_9_Y_MODIFY 0xFFC01E5C
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60
-#define DMA1_9_CURR_ADDR 0xFFC01E64
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78
-#define DMA1_9_IRQ_STATUS 0xFFC01E68
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C
-#define DMA1_10_CONFIG 0xFFC01E88
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80
-#define DMA1_10_START_ADDR 0xFFC01E84
-#define DMA1_10_X_COUNT 0xFFC01E90
-#define DMA1_10_Y_COUNT 0xFFC01E98
-#define DMA1_10_X_MODIFY 0xFFC01E94
-#define DMA1_10_Y_MODIFY 0xFFC01E9C
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0
-#define DMA1_10_CURR_ADDR 0xFFC01EA4
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC
-#define DMA1_11_CONFIG 0xFFC01EC8
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0
-#define DMA1_11_START_ADDR 0xFFC01EC4
-#define DMA1_11_X_COUNT 0xFFC01ED0
-#define DMA1_11_Y_COUNT 0xFFC01ED8
-#define DMA1_11_X_MODIFY 0xFFC01ED4
-#define DMA1_11_Y_MODIFY 0xFFC01EDC
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0
-#define DMA1_11_CURR_ADDR 0xFFC01EE4
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC
-#define DMA2_TC_PER 0xFFC00B0C
-#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA2_0_CONFIG 0xFFC00C08
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00
-#define DMA2_0_START_ADDR 0xFFC00C04
-#define DMA2_0_X_COUNT 0xFFC00C10
-#define DMA2_0_Y_COUNT 0xFFC00C18
-#define DMA2_0_X_MODIFY 0xFFC00C14
-#define DMA2_0_Y_MODIFY 0xFFC00C1C
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20
-#define DMA2_0_CURR_ADDR 0xFFC00C24
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38
-#define DMA2_0_IRQ_STATUS 0xFFC00C28
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C
-#define DMA2_1_CONFIG 0xFFC00C48
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40
-#define DMA2_1_START_ADDR 0xFFC00C44
-#define DMA2_1_X_COUNT 0xFFC00C50
-#define DMA2_1_Y_COUNT 0xFFC00C58
-#define DMA2_1_X_MODIFY 0xFFC00C54
-#define DMA2_1_Y_MODIFY 0xFFC00C5C
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60
-#define DMA2_1_CURR_ADDR 0xFFC00C64
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78
-#define DMA2_1_IRQ_STATUS 0xFFC00C68
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C
-#define DMA2_2_CONFIG 0xFFC00C88
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80
-#define DMA2_2_START_ADDR 0xFFC00C84
-#define DMA2_2_X_COUNT 0xFFC00C90
-#define DMA2_2_Y_COUNT 0xFFC00C98
-#define DMA2_2_X_MODIFY 0xFFC00C94
-#define DMA2_2_Y_MODIFY 0xFFC00C9C
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0
-#define DMA2_2_CURR_ADDR 0xFFC00CA4
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC
-#define DMA2_3_CONFIG 0xFFC00CC8
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0
-#define DMA2_3_START_ADDR 0xFFC00CC4
-#define DMA2_3_X_COUNT 0xFFC00CD0
-#define DMA2_3_Y_COUNT 0xFFC00CD8
-#define DMA2_3_X_MODIFY 0xFFC00CD4
-#define DMA2_3_Y_MODIFY 0xFFC00CDC
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0
-#define DMA2_3_CURR_ADDR 0xFFC00CE4
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC
-#define DMA2_4_CONFIG 0xFFC00D08
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00
-#define DMA2_4_START_ADDR 0xFFC00D04
-#define DMA2_4_X_COUNT 0xFFC00D10
-#define DMA2_4_Y_COUNT 0xFFC00D18
-#define DMA2_4_X_MODIFY 0xFFC00D14
-#define DMA2_4_Y_MODIFY 0xFFC00D1C
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20
-#define DMA2_4_CURR_ADDR 0xFFC00D24
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38
-#define DMA2_4_IRQ_STATUS 0xFFC00D28
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C
-#define DMA2_5_CONFIG 0xFFC00D48
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40
-#define DMA2_5_START_ADDR 0xFFC00D44
-#define DMA2_5_X_COUNT 0xFFC00D50
-#define DMA2_5_Y_COUNT 0xFFC00D58
-#define DMA2_5_X_MODIFY 0xFFC00D54
-#define DMA2_5_Y_MODIFY 0xFFC00D5C
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60
-#define DMA2_5_CURR_ADDR 0xFFC00D64
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78
-#define DMA2_5_IRQ_STATUS 0xFFC00D68
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C
-#define DMA2_6_CONFIG 0xFFC00D88
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80
-#define DMA2_6_START_ADDR 0xFFC00D84
-#define DMA2_6_X_COUNT 0xFFC00D90
-#define DMA2_6_Y_COUNT 0xFFC00D98
-#define DMA2_6_X_MODIFY 0xFFC00D94
-#define DMA2_6_Y_MODIFY 0xFFC00D9C
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0
-#define DMA2_6_CURR_ADDR 0xFFC00DA4
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC
-#define DMA2_7_CONFIG 0xFFC00DC8
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0
-#define DMA2_7_START_ADDR 0xFFC00DC4
-#define DMA2_7_X_COUNT 0xFFC00DD0
-#define DMA2_7_Y_COUNT 0xFFC00DD8
-#define DMA2_7_X_MODIFY 0xFFC00DD4
-#define DMA2_7_Y_MODIFY 0xFFC00DDC
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0
-#define DMA2_7_CURR_ADDR 0xFFC00DE4
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC
-#define DMA2_8_CONFIG 0xFFC00E08
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00
-#define DMA2_8_START_ADDR 0xFFC00E04
-#define DMA2_8_X_COUNT 0xFFC00E10
-#define DMA2_8_Y_COUNT 0xFFC00E18
-#define DMA2_8_X_MODIFY 0xFFC00E14
-#define DMA2_8_Y_MODIFY 0xFFC00E1C
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20
-#define DMA2_8_CURR_ADDR 0xFFC00E24
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38
-#define DMA2_8_IRQ_STATUS 0xFFC00E28
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C
-#define DMA2_9_CONFIG 0xFFC00E48
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40
-#define DMA2_9_START_ADDR 0xFFC00E44
-#define DMA2_9_X_COUNT 0xFFC00E50
-#define DMA2_9_Y_COUNT 0xFFC00E58
-#define DMA2_9_X_MODIFY 0xFFC00E54
-#define DMA2_9_Y_MODIFY 0xFFC00E5C
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60
-#define DMA2_9_CURR_ADDR 0xFFC00E64
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78
-#define DMA2_9_IRQ_STATUS 0xFFC00E68
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C
-#define DMA2_10_CONFIG 0xFFC00E88
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80
-#define DMA2_10_START_ADDR 0xFFC00E84
-#define DMA2_10_X_COUNT 0xFFC00E90
-#define DMA2_10_Y_COUNT 0xFFC00E98
-#define DMA2_10_X_MODIFY 0xFFC00E94
-#define DMA2_10_Y_MODIFY 0xFFC00E9C
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0
-#define DMA2_10_CURR_ADDR 0xFFC00EA4
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC
-#define DMA2_11_CONFIG 0xFFC00EC8
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0
-#define DMA2_11_START_ADDR 0xFFC00EC4
-#define DMA2_11_X_COUNT 0xFFC00ED0
-#define DMA2_11_Y_COUNT 0xFFC00ED8
-#define DMA2_11_X_MODIFY 0xFFC00ED4
-#define DMA2_11_Y_MODIFY 0xFFC00EDC
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0
-#define DMA2_11_CURR_ADDR 0xFFC00EE4
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC
-#define IMDMA_S0_CONFIG 0xFFC01848
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840
-#define IMDMA_S0_START_ADDR 0xFFC01844
-#define IMDMA_S0_X_COUNT 0xFFC01850
-#define IMDMA_S0_Y_COUNT 0xFFC01858
-#define IMDMA_S0_X_MODIFY 0xFFC01854
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860
-#define IMDMA_S0_CURR_ADDR 0xFFC01864
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868
-#define IMDMA_D0_CONFIG 0xFFC01808
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800
-#define IMDMA_D0_START_ADDR 0xFFC01804
-#define IMDMA_D0_X_COUNT 0xFFC01810
-#define IMDMA_D0_Y_COUNT 0xFFC01818
-#define IMDMA_D0_X_MODIFY 0xFFC01814
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820
-#define IMDMA_D0_CURR_ADDR 0xFFC01824
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828
-#define IMDMA_S1_CONFIG 0xFFC018C8
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0
-#define IMDMA_S1_START_ADDR 0xFFC018C4
-#define IMDMA_S1_X_COUNT 0xFFC018D0
-#define IMDMA_S1_Y_COUNT 0xFFC018D8
-#define IMDMA_S1_X_MODIFY 0xFFC018D4
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8
-#define IMDMA_D1_CONFIG 0xFFC01888
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880
-#define IMDMA_D1_START_ADDR 0xFFC01884
-#define IMDMA_D1_X_COUNT 0xFFC01890
-#define IMDMA_D1_Y_COUNT 0xFFC01898
-#define IMDMA_D1_X_MODIFY 0xFFC01894
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8
-#define MDMA1_S0_CONFIG 0xFFC01F48
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
-#define MDMA1_S0_START_ADDR 0xFFC01F44
-#define MDMA1_S0_X_COUNT 0xFFC01F50
-#define MDMA1_S0_Y_COUNT 0xFFC01F58
-#define MDMA1_S0_X_MODIFY 0xFFC01F54
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
-#define MDMA1_D0_CONFIG 0xFFC01F08
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
-#define MDMA1_D0_START_ADDR 0xFFC01F04
-#define MDMA1_D0_X_COUNT 0xFFC01F10
-#define MDMA1_D0_Y_COUNT 0xFFC01F18
-#define MDMA1_D0_X_MODIFY 0xFFC01F14
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
-#define MDMA1_S1_CONFIG 0xFFC01FC8
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
-#define MDMA1_S1_START_ADDR 0xFFC01FC4
-#define MDMA1_S1_X_COUNT 0xFFC01FD0
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
-#define MDMA1_D1_CONFIG 0xFFC01F88
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
-#define MDMA1_D1_START_ADDR 0xFFC01F84
-#define MDMA1_D1_X_COUNT 0xFFC01F90
-#define MDMA1_D1_Y_COUNT 0xFFC01F98
-#define MDMA1_D1_X_MODIFY 0xFFC01F94
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
-#define MDMA2_S0_CONFIG 0xFFC00F48
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40
-#define MDMA2_S0_START_ADDR 0xFFC00F44
-#define MDMA2_S0_X_COUNT 0xFFC00F50
-#define MDMA2_S0_Y_COUNT 0xFFC00F58
-#define MDMA2_S0_X_MODIFY 0xFFC00F54
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C
-#define MDMA2_D0_CONFIG 0xFFC00F08
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00
-#define MDMA2_D0_START_ADDR 0xFFC00F04
-#define MDMA2_D0_X_COUNT 0xFFC00F10
-#define MDMA2_D0_Y_COUNT 0xFFC00F18
-#define MDMA2_D0_X_MODIFY 0xFFC00F14
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C
-#define MDMA2_S1_CONFIG 0xFFC00FC8
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0
-#define MDMA2_S1_START_ADDR 0xFFC00FC4
-#define MDMA2_S1_X_COUNT 0xFFC00FD0
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC
-#define MDMA2_D1_CONFIG 0xFFC00F88
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80
-#define MDMA2_D1_START_ADDR 0xFFC00F84
-#define MDMA2_D1_X_COUNT 0xFFC00F90
-#define MDMA2_D1_Y_COUNT 0xFFC00F98
-#define MDMA2_D1_X_MODIFY 0xFFC00F94
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC
-#define TIMER0_CONFIG 0xFFC00600
-#define TIMER0_COUNTER 0xFFC00604
-#define TIMER0_PERIOD 0xFFC00608
-#define TIMER0_WIDTH 0xFFC0060C
-#define TIMER1_CONFIG 0xFFC00610
-#define TIMER1_COUNTER 0xFFC00614
-#define TIMER1_PERIOD 0xFFC00618
-#define TIMER1_WIDTH 0xFFC0061C
-#define TIMER2_CONFIG 0xFFC00620
-#define TIMER2_COUNTER 0xFFC00624
-#define TIMER2_PERIOD 0xFFC00628
-#define TIMER2_WIDTH 0xFFC0062C
-#define TIMER3_CONFIG 0xFFC00630
-#define TIMER3_COUNTER 0xFFC00634
-#define TIMER3_PERIOD 0xFFC00638
-#define TIMER3_WIDTH 0xFFC0063C
-#define TIMER4_CONFIG 0xFFC00640
-#define TIMER4_COUNTER 0xFFC00644
-#define TIMER4_PERIOD 0xFFC00648
-#define TIMER4_WIDTH 0xFFC0064C
-#define TIMER5_CONFIG 0xFFC00650
-#define TIMER5_COUNTER 0xFFC00654
-#define TIMER5_PERIOD 0xFFC00658
-#define TIMER5_WIDTH 0xFFC0065C
-#define TIMER6_CONFIG 0xFFC00660
-#define TIMER6_COUNTER 0xFFC00664
-#define TIMER6_PERIOD 0xFFC00668
-#define TIMER6_WIDTH 0xFFC0066C
-#define TIMER7_CONFIG 0xFFC00670
-#define TIMER7_COUNTER 0xFFC00674
-#define TIMER7_PERIOD 0xFFC00678
-#define TIMER7_WIDTH 0xFFC0067C
-#define TIMER8_CONFIG 0xFFC01600
-#define TIMER8_COUNTER 0xFFC01604
-#define TIMER8_PERIOD 0xFFC01608
-#define TIMER8_WIDTH 0xFFC0160C
-#define TIMER9_CONFIG 0xFFC01610
-#define TIMER9_COUNTER 0xFFC01614
-#define TIMER9_PERIOD 0xFFC01618
-#define TIMER9_WIDTH 0xFFC0161C
-#define TIMER10_CONFIG 0xFFC01620
-#define TIMER10_COUNTER 0xFFC01624
-#define TIMER10_PERIOD 0xFFC01628
-#define TIMER10_WIDTH 0xFFC0162C
-#define TIMER11_CONFIG 0xFFC01630
-#define TIMER11_COUNTER 0xFFC01634
-#define TIMER11_PERIOD 0xFFC01638
-#define TIMER11_WIDTH 0xFFC0163C
-#define TMRS4_ENABLE 0xFFC01640
-#define TMRS4_DISABLE 0xFFC01644
-#define TMRS4_STATUS 0xFFC01648
-#define TMRS8_ENABLE 0xFFC00680
-#define TMRS8_DISABLE 0xFFC00684
-#define TMRS8_STATUS 0xFFC00688
-#define FIO0_FLAG_D 0xFFC00700
-#define FIO0_FLAG_C 0xFFC00704
-#define FIO0_FLAG_S 0xFFC00708
-#define FIO0_FLAG_T 0xFFC0070C
-#define FIO0_MASKA_D 0xFFC00710
-#define FIO0_MASKA_C 0xFFC00714
-#define FIO0_MASKA_S 0xFFC00718
-#define FIO0_MASKA_T 0xFFC0071C
-#define FIO0_MASKB_D 0xFFC00720
-#define FIO0_MASKB_C 0xFFC00724
-#define FIO0_MASKB_S 0xFFC00728
-#define FIO0_MASKB_T 0xFFC0072C
-#define FIO0_DIR 0xFFC00730
-#define FIO0_POLAR 0xFFC00734
-#define FIO0_EDGE 0xFFC00738
-#define FIO0_BOTH 0xFFC0073C
-#define FIO0_INEN 0xFFC00740
-#define FIO1_FLAG_D 0xFFC01500
-#define FIO1_FLAG_C 0xFFC01504
-#define FIO1_FLAG_S 0xFFC01508
-#define FIO1_FLAG_T 0xFFC0150C
-#define FIO1_MASKA_D 0xFFC01510
-#define FIO1_MASKA_C 0xFFC01514
-#define FIO1_MASKA_S 0xFFC01518
-#define FIO1_MASKA_T 0xFFC0151C
-#define FIO1_MASKB_D 0xFFC01520
-#define FIO1_MASKB_C 0xFFC01524
-#define FIO1_MASKB_S 0xFFC01528
-#define FIO1_MASKB_T 0xFFC0152C
-#define FIO1_DIR 0xFFC01530
-#define FIO1_POLAR 0xFFC01534
-#define FIO1_EDGE 0xFFC01538
-#define FIO1_BOTH 0xFFC0153C
-#define FIO1_INEN 0xFFC01540
-#define FIO2_FLAG_D 0xFFC01700
-#define FIO2_FLAG_C 0xFFC01704
-#define FIO2_FLAG_S 0xFFC01708
-#define FIO2_FLAG_T 0xFFC0170C
-#define FIO2_MASKA_D 0xFFC01710
-#define FIO2_MASKA_C 0xFFC01714
-#define FIO2_MASKA_S 0xFFC01718
-#define FIO2_MASKA_T 0xFFC0171C
-#define FIO2_MASKB_D 0xFFC01720
-#define FIO2_MASKB_C 0xFFC01724
-#define FIO2_MASKB_S 0xFFC01728
-#define FIO2_MASKB_T 0xFFC0172C
-#define FIO2_DIR 0xFFC01730
-#define FIO2_POLAR 0xFFC01734
-#define FIO2_EDGE 0xFFC01738
-#define FIO2_BOTH 0xFFC0173C
-#define FIO2_INEN 0xFFC01740
-#define SPORT0_TCR1 0xFFC00800
-#define SPORT0_TCR2 0xFFC00804
-#define SPORT0_TCLKDIV 0xFFC00808
-#define SPORT0_TFSDIV 0xFFC0080C
-#define SPORT0_TX 0xFFC00810
-#define SPORT0_RX 0xFFC00818
-#define SPORT0_RCR1 0xFFC00820
-#define SPORT0_RCR2 0xFFC00824
-#define SPORT0_RCLKDIV 0xFFC00828
-#define SPORT0_RFSDIV 0xFFC0082C
-#define SPORT0_STAT 0xFFC00830
-#define SPORT0_CHNL 0xFFC00834
-#define SPORT0_MCMC1 0xFFC00838
-#define SPORT0_MCMC2 0xFFC0083C
-#define SPORT0_MTCS0 0xFFC00840
-#define SPORT0_MTCS1 0xFFC00844
-#define SPORT0_MTCS2 0xFFC00848
-#define SPORT0_MTCS3 0xFFC0084C
-#define SPORT0_MRCS0 0xFFC00850
-#define SPORT0_MRCS1 0xFFC00854
-#define SPORT0_MRCS2 0xFFC00858
-#define SPORT0_MRCS3 0xFFC0085C
-#define SPORT1_TCR1 0xFFC00900
-#define SPORT1_TCR2 0xFFC00904
-#define SPORT1_TCLKDIV 0xFFC00908
-#define SPORT1_TFSDIV 0xFFC0090C
-#define SPORT1_TX 0xFFC00910
-#define SPORT1_RX 0xFFC00918
-#define SPORT1_RCR1 0xFFC00920
-#define SPORT1_RCR2 0xFFC00924
-#define SPORT1_RCLKDIV 0xFFC00928
-#define SPORT1_RFSDIV 0xFFC0092C
-#define SPORT1_STAT 0xFFC00930
-#define SPORT1_CHNL 0xFFC00934
-#define SPORT1_MCMC1 0xFFC00938
-#define SPORT1_MCMC2 0xFFC0093C
-#define SPORT1_MTCS0 0xFFC00940
-#define SPORT1_MTCS1 0xFFC00944
-#define SPORT1_MTCS2 0xFFC00948
-#define SPORT1_MTCS3 0xFFC0094C
-#define SPORT1_MRCS0 0xFFC00950
-#define SPORT1_MRCS1 0xFFC00954
-#define SPORT1_MRCS2 0xFFC00958
-#define SPORT1_MRCS3 0xFFC0095C
-#define EVT0 0xFFE02000
-#define EVT1 0xFFE02004
-#define EVT2 0xFFE02008
-#define EVT3 0xFFE0200C
-#define EVT4 0xFFE02010
-#define EVT5 0xFFE02014
-#define EVT6 0xFFE02018
-#define EVT7 0xFFE0201C
-#define EVT8 0xFFE02020
-#define EVT9 0xFFE02024
-#define EVT10 0xFFE02028
-#define EVT11 0xFFE0202C
-#define EVT12 0xFFE02030
-#define EVT13 0xFFE02034
-#define EVT14 0xFFE02038
-#define EVT15 0xFFE0203C
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000
-#define TPERIOD 0xFFE03004
-#define TSCALE 0xFFE03008
-#define TCOUNT 0xFFE0300C
-
-#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */
#ifndef __BFIN_CDEF_ADSP_EDN_core__
#define __BFIN_CDEF_ADSP_EDN_core__
-#define pWPIACTL ((uint32_t volatile *)WPIACTL)
+#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
+#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
+#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
+#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
+#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
+#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
+#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
+#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
+#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
+#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
+#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
+#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
+#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
+#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
+#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
+#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
+#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
+#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
+#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
+#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
+#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
+#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
+#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
+#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
+#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
+#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
+#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
+#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
+#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
+#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
+#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
+#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
+#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
+#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
+#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
+#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
+#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
+#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
+
+#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
+#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
+#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
+#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
+#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
+#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
+#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
+#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
+#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
+#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
+#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
+#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
+#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
+#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
+#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
+#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
+#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
+#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
+#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
+#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
+#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
+#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
+#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
+#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
+#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
+#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
+#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
+#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
+#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
+#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
+#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
+#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
+#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
+#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
+#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
+#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
+#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
+
+#define bfin_read_EVT0() bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
+#define bfin_read_EVT1() bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
+#define bfin_read_EVT2() bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
+#define bfin_read_EVT3() bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
+#define bfin_read_EVT4() bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
+#define bfin_read_EVT5() bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
+#define bfin_read_EVT6() bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
+#define bfin_read_EVT7() bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
+#define bfin_read_EVT8() bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
+#define bfin_read_EVT9() bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
+#define bfin_read_EVT10() bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
+#define bfin_read_EVT11() bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
+#define bfin_read_EVT12() bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
+#define bfin_read_EVT13() bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
+#define bfin_read_EVT14() bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
+#define bfin_read_EVT15() bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
+
+#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
+#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
+#define bfin_read_ILAT() bfin_read32(ILAT)
+#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
+#define bfin_read_IMASK() bfin_read32(IMASK)
+#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
+#define bfin_read_IPEND() bfin_read32(IPEND)
+#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
+#define bfin_read_IPRIO() bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
+
+#define bfin_read_TCNTL() bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
+#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
+#define bfin_read_TSCALE() bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
+#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
+
+#define bfin_read_DSPID() bfin_read32(DSPID)
+#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
+#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
+
+#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
+#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
+#define bfin_read_TBUF() bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
+
#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val)
-#define pWPIA0 ((void * volatile *)WPIA0)
#define bfin_read_WPIA0() bfin_readPTR(WPIA0)
#define bfin_write_WPIA0(val) bfin_writePTR(WPIA0, val)
-#define pWPIA1 ((void * volatile *)WPIA1)
#define bfin_read_WPIA1() bfin_readPTR(WPIA1)
#define bfin_write_WPIA1(val) bfin_writePTR(WPIA1, val)
-#define pWPIA2 ((void * volatile *)WPIA2)
#define bfin_read_WPIA2() bfin_readPTR(WPIA2)
#define bfin_write_WPIA2(val) bfin_writePTR(WPIA2, val)
-#define pWPIA3 ((void * volatile *)WPIA3)
#define bfin_read_WPIA3() bfin_readPTR(WPIA3)
#define bfin_write_WPIA3(val) bfin_writePTR(WPIA3, val)
-#define pWPIA4 ((void * volatile *)WPIA4)
#define bfin_read_WPIA4() bfin_readPTR(WPIA4)
#define bfin_write_WPIA4(val) bfin_writePTR(WPIA4, val)
-#define pWPIA5 ((void * volatile *)WPIA5)
#define bfin_read_WPIA5() bfin_readPTR(WPIA5)
#define bfin_write_WPIA5(val) bfin_writePTR(WPIA5, val)
-#define pWPIACNT0 ((uint32_t volatile *)WPIACNT0)
#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val)
-#define pWPIACNT1 ((uint32_t volatile *)WPIACNT1)
#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val)
-#define pWPIACNT2 ((uint32_t volatile *)WPIACNT2)
#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val)
-#define pWPIACNT3 ((uint32_t volatile *)WPIACNT3)
#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val)
-#define pWPIACNT4 ((uint32_t volatile *)WPIACNT4)
#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val)
-#define pWPIACNT5 ((uint32_t volatile *)WPIACNT5)
#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val)
-#define pWPDACTL ((uint32_t volatile *)WPDACTL)
#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val)
-#define pWPDA0 ((void * volatile *)WPDA0)
#define bfin_read_WPDA0() bfin_readPTR(WPDA0)
#define bfin_write_WPDA0(val) bfin_writePTR(WPDA0, val)
-#define pWPDA1 ((void * volatile *)WPDA1)
#define bfin_read_WPDA1() bfin_readPTR(WPDA1)
#define bfin_write_WPDA1(val) bfin_writePTR(WPDA1, val)
-#define pWPDACNT0 ((uint32_t volatile *)WPDACNT0)
#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val)
-#define pWPDACNT1 ((uint32_t volatile *)WPDACNT1)
#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val)
-#define pWPSTAT ((uint32_t volatile *)WPSTAT)
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
-#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
+
+#define bfin_read_PFCTL() bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
+#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
+#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
#ifndef __BFIN_DEF_ADSP_EDN_core__
#define __BFIN_DEF_ADSP_EDN_core__
+#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
+#define DCPLB_FAULT_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
+
+#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_FAULT_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
+
+#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
+
+#define EVT_OVERRIDE 0xFFE02100
+#define ILAT 0xFFE0210C /* Interrupt Latch Register */
+#define IMASK 0xFFE02104 /* Interrupt Mask Register */
+#define IPEND 0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
+
+#define TCNTL 0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
+#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
+
+#define DSPID 0xFFE05000
+#define DBGSTAT 0xFFE05008
+
+#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF 0xFFE06100 /* Trace Buffer */
+
#define WPIACTL 0xFFE07000
#define WPIA0 0xFFE07040
#define WPIA1 0xFFE07044
#define WPDACNT0 0xFFE07180
#define WPDACNT1 0xFFE07184
#define WPSTAT 0xFFE07200
-#define DSPID 0xFFE05000
-#define DBGSTAT 0xFFE05008
+
+#define PFCTL 0xFFE08000
+#define PFCNTR0 0xFFE08100
+#define PFCNTR1 0xFFE08104
#endif /* __BFIN_DEF_ADSP_EDN_core__ */
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_extended__
-#define __BFIN_CDEF_ADSP_EDN_extended__
-
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */
-#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
-#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS)
-#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS)
-#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
-#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pMDMAFLX0_DMACNFG_D ((uint16_t volatile *)MDMAFLX0_DMACNFG_D)
-#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
-#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define pMDMAFLX0_XCOUNT_D ((uint16_t volatile *)MDMAFLX0_XCOUNT_D)
-#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D)
-#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define pMDMAFLX0_XMODIFY_D ((uint16_t volatile *)MDMAFLX0_XMODIFY_D)
-#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
-#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define pMDMAFLX0_YCOUNT_D ((uint16_t volatile *)MDMAFLX0_YCOUNT_D)
-#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D)
-#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define pMDMAFLX0_YMODIFY_D ((uint16_t volatile *)MDMAFLX0_YMODIFY_D)
-#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
-#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define pMDMAFLX0_IRQSTAT_D ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D)
-#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
-#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define pMDMAFLX0_PMAP_D ((uint16_t volatile *)MDMAFLX0_PMAP_D)
-#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D)
-#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define pMDMAFLX0_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D)
-#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
-#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define pMDMAFLX0_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D)
-#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
-#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define pMDMAFLX0_DMACNFG_S ((uint16_t volatile *)MDMAFLX0_DMACNFG_S)
-#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
-#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define pMDMAFLX0_XCOUNT_S ((uint16_t volatile *)MDMAFLX0_XCOUNT_S)
-#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S)
-#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define pMDMAFLX0_XMODIFY_S ((uint16_t volatile *)MDMAFLX0_XMODIFY_S)
-#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
-#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define pMDMAFLX0_YCOUNT_S ((uint16_t volatile *)MDMAFLX0_YCOUNT_S)
-#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S)
-#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define pMDMAFLX0_YMODIFY_S ((uint16_t volatile *)MDMAFLX0_YMODIFY_S)
-#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
-#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define pMDMAFLX0_IRQSTAT_S ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S)
-#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
-#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define pMDMAFLX0_PMAP_S ((uint16_t volatile *)MDMAFLX0_PMAP_S)
-#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S)
-#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define pMDMAFLX0_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S)
-#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
-#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define pMDMAFLX0_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S)
-#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
-#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define pMDMAFLX1_DMACNFG_D ((uint16_t volatile *)MDMAFLX1_DMACNFG_D)
-#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
-#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define pMDMAFLX1_XCOUNT_D ((uint16_t volatile *)MDMAFLX1_XCOUNT_D)
-#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D)
-#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define pMDMAFLX1_XMODIFY_D ((uint16_t volatile *)MDMAFLX1_XMODIFY_D)
-#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
-#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define pMDMAFLX1_YCOUNT_D ((uint16_t volatile *)MDMAFLX1_YCOUNT_D)
-#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D)
-#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define pMDMAFLX1_YMODIFY_D ((uint16_t volatile *)MDMAFLX1_YMODIFY_D)
-#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
-#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define pMDMAFLX1_IRQSTAT_D ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D)
-#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
-#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define pMDMAFLX1_PMAP_D ((uint16_t volatile *)MDMAFLX1_PMAP_D)
-#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D)
-#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define pMDMAFLX1_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D)
-#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
-#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define pMDMAFLX1_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D)
-#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
-#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define pMDMAFLX1_DMACNFG_S ((uint16_t volatile *)MDMAFLX1_DMACNFG_S)
-#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
-#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define pMDMAFLX1_XCOUNT_S ((uint16_t volatile *)MDMAFLX1_XCOUNT_S)
-#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S)
-#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define pMDMAFLX1_XMODIFY_S ((uint16_t volatile *)MDMAFLX1_XMODIFY_S)
-#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
-#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define pMDMAFLX1_YCOUNT_S ((uint16_t volatile *)MDMAFLX1_YCOUNT_S)
-#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S)
-#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define pMDMAFLX1_YMODIFY_S ((uint16_t volatile *)MDMAFLX1_YMODIFY_S)
-#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
-#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define pMDMAFLX1_IRQSTAT_S ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S)
-#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
-#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define pMDMAFLX1_PMAP_S ((uint16_t volatile *)MDMAFLX1_PMAP_S)
-#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S)
-#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define pMDMAFLX1_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S)
-#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
-#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define pMDMAFLX1_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S)
-#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
-#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define pDMAFLX0_DMACNFG ((uint16_t volatile *)DMAFLX0_DMACNFG)
-#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG)
-#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define pDMAFLX0_XCOUNT ((uint16_t volatile *)DMAFLX0_XCOUNT)
-#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT)
-#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define pDMAFLX0_XMODIFY ((uint16_t volatile *)DMAFLX0_XMODIFY)
-#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY)
-#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define pDMAFLX0_YCOUNT ((uint16_t volatile *)DMAFLX0_YCOUNT)
-#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT)
-#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define pDMAFLX0_YMODIFY ((uint16_t volatile *)DMAFLX0_YMODIFY)
-#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY)
-#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define pDMAFLX0_IRQSTAT ((uint16_t volatile *)DMAFLX0_IRQSTAT)
-#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT)
-#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define pDMAFLX0_PMAP ((uint16_t volatile *)DMAFLX0_PMAP)
-#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP)
-#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val)
-#define pDMAFLX0_CURXCOUNT ((uint16_t volatile *)DMAFLX0_CURXCOUNT)
-#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT)
-#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define pDMAFLX0_CURYCOUNT ((uint16_t volatile *)DMAFLX0_CURYCOUNT)
-#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT)
-#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define pDMAFLX1_DMACNFG ((uint16_t volatile *)DMAFLX1_DMACNFG)
-#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG)
-#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define pDMAFLX1_XCOUNT ((uint16_t volatile *)DMAFLX1_XCOUNT)
-#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT)
-#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define pDMAFLX1_XMODIFY ((uint16_t volatile *)DMAFLX1_XMODIFY)
-#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY)
-#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define pDMAFLX1_YCOUNT ((uint16_t volatile *)DMAFLX1_YCOUNT)
-#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT)
-#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define pDMAFLX1_YMODIFY ((uint16_t volatile *)DMAFLX1_YMODIFY)
-#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY)
-#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define pDMAFLX1_IRQSTAT ((uint16_t volatile *)DMAFLX1_IRQSTAT)
-#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT)
-#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define pDMAFLX1_PMAP ((uint16_t volatile *)DMAFLX1_PMAP)
-#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP)
-#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val)
-#define pDMAFLX1_CURXCOUNT ((uint16_t volatile *)DMAFLX1_CURXCOUNT)
-#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT)
-#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define pDMAFLX1_CURYCOUNT ((uint16_t volatile *)DMAFLX1_CURYCOUNT)
-#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT)
-#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define pDMAFLX2_DMACNFG ((uint16_t volatile *)DMAFLX2_DMACNFG)
-#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG)
-#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define pDMAFLX2_XCOUNT ((uint16_t volatile *)DMAFLX2_XCOUNT)
-#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT)
-#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define pDMAFLX2_XMODIFY ((uint16_t volatile *)DMAFLX2_XMODIFY)
-#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY)
-#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define pDMAFLX2_YCOUNT ((uint16_t volatile *)DMAFLX2_YCOUNT)
-#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT)
-#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define pDMAFLX2_YMODIFY ((uint16_t volatile *)DMAFLX2_YMODIFY)
-#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY)
-#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define pDMAFLX2_IRQSTAT ((uint16_t volatile *)DMAFLX2_IRQSTAT)
-#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT)
-#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define pDMAFLX2_PMAP ((uint16_t volatile *)DMAFLX2_PMAP)
-#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP)
-#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val)
-#define pDMAFLX2_CURXCOUNT ((uint16_t volatile *)DMAFLX2_CURXCOUNT)
-#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT)
-#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define pDMAFLX2_CURYCOUNT ((uint16_t volatile *)DMAFLX2_CURYCOUNT)
-#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT)
-#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define pDMAFLX3_DMACNFG ((uint16_t volatile *)DMAFLX3_DMACNFG)
-#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG)
-#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define pDMAFLX3_XCOUNT ((uint16_t volatile *)DMAFLX3_XCOUNT)
-#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT)
-#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define pDMAFLX3_XMODIFY ((uint16_t volatile *)DMAFLX3_XMODIFY)
-#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY)
-#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define pDMAFLX3_YCOUNT ((uint16_t volatile *)DMAFLX3_YCOUNT)
-#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT)
-#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define pDMAFLX3_YMODIFY ((uint16_t volatile *)DMAFLX3_YMODIFY)
-#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY)
-#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define pDMAFLX3_IRQSTAT ((uint16_t volatile *)DMAFLX3_IRQSTAT)
-#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT)
-#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define pDMAFLX3_PMAP ((uint16_t volatile *)DMAFLX3_PMAP)
-#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP)
-#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val)
-#define pDMAFLX3_CURXCOUNT ((uint16_t volatile *)DMAFLX3_CURXCOUNT)
-#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT)
-#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define pDMAFLX3_CURYCOUNT ((uint16_t volatile *)DMAFLX3_CURYCOUNT)
-#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT)
-#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define pDMAFLX4_DMACNFG ((uint16_t volatile *)DMAFLX4_DMACNFG)
-#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG)
-#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define pDMAFLX4_XCOUNT ((uint16_t volatile *)DMAFLX4_XCOUNT)
-#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT)
-#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define pDMAFLX4_XMODIFY ((uint16_t volatile *)DMAFLX4_XMODIFY)
-#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY)
-#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define pDMAFLX4_YCOUNT ((uint16_t volatile *)DMAFLX4_YCOUNT)
-#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT)
-#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define pDMAFLX4_YMODIFY ((uint16_t volatile *)DMAFLX4_YMODIFY)
-#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY)
-#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define pDMAFLX4_IRQSTAT ((uint16_t volatile *)DMAFLX4_IRQSTAT)
-#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT)
-#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define pDMAFLX4_PMAP ((uint16_t volatile *)DMAFLX4_PMAP)
-#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP)
-#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val)
-#define pDMAFLX4_CURXCOUNT ((uint16_t volatile *)DMAFLX4_CURXCOUNT)
-#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT)
-#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define pDMAFLX4_CURYCOUNT ((uint16_t volatile *)DMAFLX4_CURYCOUNT)
-#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT)
-#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define pDMAFLX5_DMACNFG ((uint16_t volatile *)DMAFLX5_DMACNFG)
-#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG)
-#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define pDMAFLX5_XCOUNT ((uint16_t volatile *)DMAFLX5_XCOUNT)
-#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT)
-#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define pDMAFLX5_XMODIFY ((uint16_t volatile *)DMAFLX5_XMODIFY)
-#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY)
-#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define pDMAFLX5_YCOUNT ((uint16_t volatile *)DMAFLX5_YCOUNT)
-#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT)
-#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define pDMAFLX5_YMODIFY ((uint16_t volatile *)DMAFLX5_YMODIFY)
-#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY)
-#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define pDMAFLX5_IRQSTAT ((uint16_t volatile *)DMAFLX5_IRQSTAT)
-#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT)
-#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define pDMAFLX5_PMAP ((uint16_t volatile *)DMAFLX5_PMAP)
-#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP)
-#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val)
-#define pDMAFLX5_CURXCOUNT ((uint16_t volatile *)DMAFLX5_CURXCOUNT)
-#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT)
-#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define pDMAFLX5_CURYCOUNT ((uint16_t volatile *)DMAFLX5_CURYCOUNT)
-#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT)
-#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define pDMAFLX6_DMACNFG ((uint16_t volatile *)DMAFLX6_DMACNFG)
-#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG)
-#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define pDMAFLX6_XCOUNT ((uint16_t volatile *)DMAFLX6_XCOUNT)
-#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT)
-#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define pDMAFLX6_XMODIFY ((uint16_t volatile *)DMAFLX6_XMODIFY)
-#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY)
-#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define pDMAFLX6_YCOUNT ((uint16_t volatile *)DMAFLX6_YCOUNT)
-#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT)
-#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define pDMAFLX6_YMODIFY ((uint16_t volatile *)DMAFLX6_YMODIFY)
-#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY)
-#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define pDMAFLX6_IRQSTAT ((uint16_t volatile *)DMAFLX6_IRQSTAT)
-#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT)
-#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define pDMAFLX6_PMAP ((uint16_t volatile *)DMAFLX6_PMAP)
-#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP)
-#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val)
-#define pDMAFLX6_CURXCOUNT ((uint16_t volatile *)DMAFLX6_CURXCOUNT)
-#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT)
-#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define pDMAFLX6_CURYCOUNT ((uint16_t volatile *)DMAFLX6_CURYCOUNT)
-#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT)
-#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define pDMAFLX7_DMACNFG ((uint16_t volatile *)DMAFLX7_DMACNFG)
-#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG)
-#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define pDMAFLX7_XCOUNT ((uint16_t volatile *)DMAFLX7_XCOUNT)
-#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT)
-#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define pDMAFLX7_XMODIFY ((uint16_t volatile *)DMAFLX7_XMODIFY)
-#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY)
-#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define pDMAFLX7_YCOUNT ((uint16_t volatile *)DMAFLX7_YCOUNT)
-#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT)
-#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define pDMAFLX7_YMODIFY ((uint16_t volatile *)DMAFLX7_YMODIFY)
-#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY)
-#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define pDMAFLX7_IRQSTAT ((uint16_t volatile *)DMAFLX7_IRQSTAT)
-#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT)
-#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define pDMAFLX7_PMAP ((uint16_t volatile *)DMAFLX7_PMAP)
-#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP)
-#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val)
-#define pDMAFLX7_CURXCOUNT ((uint16_t volatile *)DMAFLX7_CURXCOUNT)
-#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT)
-#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define pDMAFLX7_CURYCOUNT ((uint16_t volatile *)DMAFLX7_CURYCOUNT)
-#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT)
-#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS ((uint16_t volatile *)TIMER_STATUS)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
-#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
-#define pUART_THR ((uint16_t volatile *)UART_THR) /* Transmit Holding */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
-#define pUART_DLL ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
-#define pUART_DLH ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
-#define pUART_IER ((uint16_t volatile *)UART_IER)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
-#define pUART_IIR ((uint16_t volatile *)UART_IIR)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
-#define pUART_LCR ((uint16_t volatile *)UART_LCR)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
-#define pUART_MCR ((uint16_t volatile *)UART_MCR)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
-#define pUART_LSR ((uint16_t volatile *)UART_LSR)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
-#define pUART_SCR ((uint16_t volatile *)UART_SCR)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
-#define pUART_RBR ((uint16_t volatile *)UART_RBR) /* Receive Buffer */
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
-#define pUART_GCTL ((uint16_t volatile *)UART_GCTL)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
-#define pSPT0_TX_CONFIG0 ((uint16_t volatile *)SPT0_TX_CONFIG0)
-#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0)
-#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define pSPT0_TX_CONFIG1 ((uint16_t volatile *)SPT0_TX_CONFIG1)
-#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1)
-#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define pSPT0_RX_CONFIG0 ((uint16_t volatile *)SPT0_RX_CONFIG0)
-#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0)
-#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define pSPT0_RX_CONFIG1 ((uint16_t volatile *)SPT0_RX_CONFIG1)
-#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1)
-#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define pSPT0_TX ((uint32_t volatile *)SPT0_TX)
-#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX)
-#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val)
-#define pSPT0_RX ((uint32_t volatile *)SPT0_RX)
-#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX)
-#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val)
-#define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV)
-#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV)
-#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val)
-#define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV)
-#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV)
-#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val)
-#define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV)
-#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV)
-#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val)
-#define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV)
-#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV)
-#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val)
-#define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT)
-#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT)
-#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val)
-#define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0)
-#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0)
-#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val)
-#define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1)
-#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1)
-#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val)
-#define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2)
-#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2)
-#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val)
-#define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3)
-#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3)
-#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val)
-#define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0)
-#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0)
-#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val)
-#define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1)
-#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1)
-#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val)
-#define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2)
-#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2)
-#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val)
-#define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3)
-#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3)
-#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val)
-#define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1)
-#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1)
-#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val)
-#define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2)
-#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2)
-#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val)
-#define pSPT0_CHNL ((uint16_t volatile *)SPT0_CHNL)
-#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL)
-#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val)
-#define pSPT1_TX_CONFIG0 ((uint16_t volatile *)SPT1_TX_CONFIG0)
-#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0)
-#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define pSPT1_TX_CONFIG1 ((uint16_t volatile *)SPT1_TX_CONFIG1)
-#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1)
-#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define pSPT1_RX_CONFIG0 ((uint16_t volatile *)SPT1_RX_CONFIG0)
-#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0)
-#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define pSPT1_RX_CONFIG1 ((uint16_t volatile *)SPT1_RX_CONFIG1)
-#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1)
-#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define pSPT1_TX ((uint16_t volatile *)SPT1_TX)
-#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX)
-#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val)
-#define pSPT1_RX ((uint16_t volatile *)SPT1_RX)
-#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX)
-#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val)
-#define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV)
-#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV)
-#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val)
-#define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV)
-#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV)
-#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val)
-#define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV)
-#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV)
-#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val)
-#define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV)
-#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV)
-#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val)
-#define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT)
-#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT)
-#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val)
-#define pSPT1_MTCS0 ((uint32_t volatile *)SPT1_MTCS0)
-#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0)
-#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val)
-#define pSPT1_MTCS1 ((uint32_t volatile *)SPT1_MTCS1)
-#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1)
-#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val)
-#define pSPT1_MTCS2 ((uint32_t volatile *)SPT1_MTCS2)
-#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2)
-#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val)
-#define pSPT1_MTCS3 ((uint32_t volatile *)SPT1_MTCS3)
-#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3)
-#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val)
-#define pSPT1_MRCS0 ((uint32_t volatile *)SPT1_MRCS0)
-#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0)
-#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val)
-#define pSPT1_MRCS1 ((uint32_t volatile *)SPT1_MRCS1)
-#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1)
-#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val)
-#define pSPT1_MRCS2 ((uint32_t volatile *)SPT1_MRCS2)
-#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2)
-#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val)
-#define pSPT1_MRCS3 ((uint32_t volatile *)SPT1_MRCS3)
-#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3)
-#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val)
-#define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1)
-#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1)
-#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val)
-#define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2)
-#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2)
-#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val)
-#define pSPT1_CHNL ((uint16_t volatile *)SPT1_CHNL)
-#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL)
-#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val)
-#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-#define pPFCTL ((uint32_t volatile *)PFCTL)
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pFIO_FLAG_D ((uint16_t volatile *)FIO_FLAG_D)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define pFIO_FLAG_T ((uint16_t volatile *)FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define pFIO_MASKA_D ((uint16_t volatile *)FIO_MASKA_D)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val)
-#define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val)
-#define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val)
-#define pFIO_MASKA_T ((uint16_t volatile *)FIO_MASKA_T)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val)
-#define pFIO_MASKB_D ((uint16_t volatile *)FIO_MASKB_D)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val)
-#define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val)
-#define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val)
-#define pFIO_MASKB_T ((uint16_t volatile *)FIO_MASKB_T)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val)
-#define pFIO_DIR ((uint16_t volatile *)FIO_DIR)
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val)
-#define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val)
-#define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val)
-#define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val)
-#define pFIO_INEN ((uint16_t volatile *)FIO_INEN)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pDMA0_NEXT_DESC_PTR ((uint32_t volatile *)DMA0_NEXT_DESC_PTR)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((uint32_t volatile *)DMA0_CURR_DESC_PTR)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((uint32_t volatile *)DMA1_NEXT_DESC_PTR)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((uint32_t volatile *)DMA1_CURR_DESC_PTR)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((uint32_t volatile *)DMA2_NEXT_DESC_PTR)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((uint32_t volatile *)DMA2_CURR_DESC_PTR)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((uint32_t volatile *)DMA3_NEXT_DESC_PTR)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((uint32_t volatile *)DMA3_CURR_DESC_PTR)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((uint32_t volatile *)DMA4_NEXT_DESC_PTR)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((uint32_t volatile *)DMA4_CURR_DESC_PTR)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((uint32_t volatile *)DMA5_NEXT_DESC_PTR)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((uint32_t volatile *)DMA5_CURR_DESC_PTR)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((uint32_t volatile *)DMA6_CURR_DESC_PTR)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((uint32_t volatile *)DMA7_NEXT_DESC_PTR)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((uint32_t volatile *)DMA7_CURR_DESC_PTR)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_extended__ */
+++ /dev/null
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_extended__
-#define __BFIN_DEF_ADSP_EDN_extended__
-
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */
-#define DCPLB_FAULT_ADDR 0xFFE0000C
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_FAULT_STATUS 0xFFE01008
-#define ICPLB_FAULT_ADDR 0xFFE0100C
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-#define MDMAFLX0_DMACNFG_D 0xFFC00E08
-#define MDMAFLX0_XCOUNT_D 0xFFC00E10
-#define MDMAFLX0_XMODIFY_D 0xFFC00E14
-#define MDMAFLX0_YCOUNT_D 0xFFC00E18
-#define MDMAFLX0_YMODIFY_D 0xFFC00E1C
-#define MDMAFLX0_IRQSTAT_D 0xFFC00E28
-#define MDMAFLX0_PMAP_D 0xFFC00E2C
-#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30
-#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38
-#define MDMAFLX0_DMACNFG_S 0xFFC00E48
-#define MDMAFLX0_XCOUNT_S 0xFFC00E50
-#define MDMAFLX0_XMODIFY_S 0xFFC00E54
-#define MDMAFLX0_YCOUNT_S 0xFFC00E58
-#define MDMAFLX0_YMODIFY_S 0xFFC00E5C
-#define MDMAFLX0_IRQSTAT_S 0xFFC00E68
-#define MDMAFLX0_PMAP_S 0xFFC00E6C
-#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70
-#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78
-#define MDMAFLX1_DMACNFG_D 0xFFC00E88
-#define MDMAFLX1_XCOUNT_D 0xFFC00E90
-#define MDMAFLX1_XMODIFY_D 0xFFC00E94
-#define MDMAFLX1_YCOUNT_D 0xFFC00E98
-#define MDMAFLX1_YMODIFY_D 0xFFC00E9C
-#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8
-#define MDMAFLX1_PMAP_D 0xFFC00EAC
-#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0
-#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8
-#define MDMAFLX1_DMACNFG_S 0xFFC00EC8
-#define MDMAFLX1_XCOUNT_S 0xFFC00ED0
-#define MDMAFLX1_XMODIFY_S 0xFFC00ED4
-#define MDMAFLX1_YCOUNT_S 0xFFC00ED8
-#define MDMAFLX1_YMODIFY_S 0xFFC00EDC
-#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8
-#define MDMAFLX1_PMAP_S 0xFFC00EEC
-#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0
-#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8
-#define DMAFLX0_DMACNFG 0xFFC00C08
-#define DMAFLX0_XCOUNT 0xFFC00C10
-#define DMAFLX0_XMODIFY 0xFFC00C14
-#define DMAFLX0_YCOUNT 0xFFC00C18
-#define DMAFLX0_YMODIFY 0xFFC00C1C
-#define DMAFLX0_IRQSTAT 0xFFC00C28
-#define DMAFLX0_PMAP 0xFFC00C2C
-#define DMAFLX0_CURXCOUNT 0xFFC00C30
-#define DMAFLX0_CURYCOUNT 0xFFC00C38
-#define DMAFLX1_DMACNFG 0xFFC00C48
-#define DMAFLX1_XCOUNT 0xFFC00C50
-#define DMAFLX1_XMODIFY 0xFFC00C54
-#define DMAFLX1_YCOUNT 0xFFC00C58
-#define DMAFLX1_YMODIFY 0xFFC00C5C
-#define DMAFLX1_IRQSTAT 0xFFC00C68
-#define DMAFLX1_PMAP 0xFFC00C6C
-#define DMAFLX1_CURXCOUNT 0xFFC00C70
-#define DMAFLX1_CURYCOUNT 0xFFC00C78
-#define DMAFLX2_DMACNFG 0xFFC00C88
-#define DMAFLX2_XCOUNT 0xFFC00C90
-#define DMAFLX2_XMODIFY 0xFFC00C94
-#define DMAFLX2_YCOUNT 0xFFC00C98
-#define DMAFLX2_YMODIFY 0xFFC00C9C
-#define DMAFLX2_IRQSTAT 0xFFC00CA8
-#define DMAFLX2_PMAP 0xFFC00CAC
-#define DMAFLX2_CURXCOUNT 0xFFC00CB0
-#define DMAFLX2_CURYCOUNT 0xFFC00CB8
-#define DMAFLX3_DMACNFG 0xFFC00CC8
-#define DMAFLX3_XCOUNT 0xFFC00CD0
-#define DMAFLX3_XMODIFY 0xFFC00CD4
-#define DMAFLX3_YCOUNT 0xFFC00CD8
-#define DMAFLX3_YMODIFY 0xFFC00CDC
-#define DMAFLX3_IRQSTAT 0xFFC00CE8
-#define DMAFLX3_PMAP 0xFFC00CEC
-#define DMAFLX3_CURXCOUNT 0xFFC00CF0
-#define DMAFLX3_CURYCOUNT 0xFFC00CF8
-#define DMAFLX4_DMACNFG 0xFFC00D08
-#define DMAFLX4_XCOUNT 0xFFC00D10
-#define DMAFLX4_XMODIFY 0xFFC00D14
-#define DMAFLX4_YCOUNT 0xFFC00D18
-#define DMAFLX4_YMODIFY 0xFFC00D1C
-#define DMAFLX4_IRQSTAT 0xFFC00D28
-#define DMAFLX4_PMAP 0xFFC00D2C
-#define DMAFLX4_CURXCOUNT 0xFFC00D30
-#define DMAFLX4_CURYCOUNT 0xFFC00D38
-#define DMAFLX5_DMACNFG 0xFFC00D48
-#define DMAFLX5_XCOUNT 0xFFC00D50
-#define DMAFLX5_XMODIFY 0xFFC00D54
-#define DMAFLX5_YCOUNT 0xFFC00D58
-#define DMAFLX5_YMODIFY 0xFFC00D5C
-#define DMAFLX5_IRQSTAT 0xFFC00D68
-#define DMAFLX5_PMAP 0xFFC00D6C
-#define DMAFLX5_CURXCOUNT 0xFFC00D70
-#define DMAFLX5_CURYCOUNT 0xFFC00D78
-#define DMAFLX6_DMACNFG 0xFFC00D88
-#define DMAFLX6_XCOUNT 0xFFC00D90
-#define DMAFLX6_XMODIFY 0xFFC00D94
-#define DMAFLX6_YCOUNT 0xFFC00D98
-#define DMAFLX6_YMODIFY 0xFFC00D9C
-#define DMAFLX6_IRQSTAT 0xFFC00DA8
-#define DMAFLX6_PMAP 0xFFC00DAC
-#define DMAFLX6_CURXCOUNT 0xFFC00DB0
-#define DMAFLX6_CURYCOUNT 0xFFC00DB8
-#define DMAFLX7_DMACNFG 0xFFC00DC8
-#define DMAFLX7_XCOUNT 0xFFC00DD0
-#define DMAFLX7_XMODIFY 0xFFC00DD4
-#define DMAFLX7_YCOUNT 0xFFC00DD8
-#define DMAFLX7_YMODIFY 0xFFC00DDC
-#define DMAFLX7_IRQSTAT 0xFFC00DE8
-#define DMAFLX7_PMAP 0xFFC00DEC
-#define DMAFLX7_CURXCOUNT 0xFFC00DF0
-#define DMAFLX7_CURYCOUNT 0xFFC00DF8
-#define TIMER0_CONFIG 0xFFC00600
-#define TIMER0_COUNTER 0xFFC00604
-#define TIMER0_PERIOD 0xFFC00608
-#define TIMER0_WIDTH 0xFFC0060C
-#define TIMER1_CONFIG 0xFFC00610
-#define TIMER1_COUNTER 0xFFC00614
-#define TIMER1_PERIOD 0xFFC00618
-#define TIMER1_WIDTH 0xFFC0061C
-#define TIMER2_CONFIG 0xFFC00620
-#define TIMER2_COUNTER 0xFFC00624
-#define TIMER2_PERIOD 0xFFC00628
-#define TIMER2_WIDTH 0xFFC0062C
-#define TIMER_ENABLE 0xFFC00640
-#define TIMER_DISABLE 0xFFC00644
-#define TIMER_STATUS 0xFFC00648
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-#define UART_THR 0xFFC00400 /* Transmit Holding */
-#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART_IER 0xFFC00404
-#define UART_IIR 0xFFC00408
-#define UART_LCR 0xFFC0040C
-#define UART_MCR 0xFFC00410
-#define UART_LSR 0xFFC00414
-#define UART_SCR 0xFFC0041C
-#define UART_RBR 0xFFC00400 /* Receive Buffer */
-#define UART_GCTL 0xFFC00424
-#define SPT0_TX_CONFIG0 0xFFC00800
-#define SPT0_TX_CONFIG1 0xFFC00804
-#define SPT0_RX_CONFIG0 0xFFC00820
-#define SPT0_RX_CONFIG1 0xFFC00824
-#define SPT0_TX 0xFFC00810
-#define SPT0_RX 0xFFC00818
-#define SPT0_TSCLKDIV 0xFFC00808
-#define SPT0_RSCLKDIV 0xFFC00828
-#define SPT0_TFSDIV 0xFFC0080C
-#define SPT0_RFSDIV 0xFFC0082C
-#define SPT0_STAT 0xFFC00830
-#define SPT0_MTCS0 0xFFC00840
-#define SPT0_MTCS1 0xFFC00844
-#define SPT0_MTCS2 0xFFC00848
-#define SPT0_MTCS3 0xFFC0084C
-#define SPT0_MRCS0 0xFFC00850
-#define SPT0_MRCS1 0xFFC00854
-#define SPT0_MRCS2 0xFFC00858
-#define SPT0_MRCS3 0xFFC0085C
-#define SPT0_MCMC1 0xFFC00838
-#define SPT0_MCMC2 0xFFC0083C
-#define SPT0_CHNL 0xFFC00834
-#define SPT1_TX_CONFIG0 0xFFC00900
-#define SPT1_TX_CONFIG1 0xFFC00904
-#define SPT1_RX_CONFIG0 0xFFC00920
-#define SPT1_RX_CONFIG1 0xFFC00924
-#define SPT1_TX 0xFFC00910
-#define SPT1_RX 0xFFC00918
-#define SPT1_TSCLKDIV 0xFFC00908
-#define SPT1_RSCLKDIV 0xFFC00928
-#define SPT1_TFSDIV 0xFFC0090C
-#define SPT1_RFSDIV 0xFFC0092C
-#define SPT1_STAT 0xFFC00930
-#define SPT1_MTCS0 0xFFC00940
-#define SPT1_MTCS1 0xFFC00944
-#define SPT1_MTCS2 0xFFC00948
-#define SPT1_MTCS3 0xFFC0094C
-#define SPT1_MRCS0 0xFFC00950
-#define SPT1_MRCS1 0xFFC00954
-#define SPT1_MRCS2 0xFFC00958
-#define SPT1_MRCS3 0xFFC0095C
-#define SPT1_MCMC1 0xFFC00938
-#define SPT1_MCMC2 0xFFC0093C
-#define SPT1_CHNL 0xFFC00934
-#define PPI_CONTROL 0xFFC01000
-#define PPI_STATUS 0xFFC01004
-#define PPI_DELAY 0xFFC0100C
-#define PPI_COUNT 0xFFC01008
-#define PPI_FRAME 0xFFC01010
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define EVT_OVERRIDE 0xFFE02100
-#define CHIPID 0xFFC00014
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-#define PFCTL 0xFFE08000
-#define PFCNTR0 0xFFE08100
-#define PFCNTR1 0xFFE08104
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300
-#define RTC_ICTL 0xFFC00304
-#define RTC_ISTAT 0xFFC00308
-#define RTC_SWCNT 0xFFC0030C
-#define RTC_ALARM 0xFFC00310
-#define RTC_PREN 0xFFC00314
-#define SPI_CTL 0xFFC00500
-#define SPI_FLG 0xFFC00504
-#define SPI_STAT 0xFFC00508
-#define SPI_TDBR 0xFFC0050C
-#define SPI_RDBR 0xFFC00510
-#define SPI_BAUD 0xFFC00514
-#define SPI_SHADOW 0xFFC00518
-#define FIO_FLAG_D 0xFFC00700
-#define FIO_FLAG_C 0xFFC00704
-#define FIO_FLAG_S 0xFFC00708
-#define FIO_FLAG_T 0xFFC0070C
-#define FIO_MASKA_D 0xFFC00710
-#define FIO_MASKA_C 0xFFC00714
-#define FIO_MASKA_S 0xFFC00718
-#define FIO_MASKA_T 0xFFC0071C
-#define FIO_MASKB_D 0xFFC00720
-#define FIO_MASKB_C 0xFFC00724
-#define FIO_MASKB_S 0xFFC00728
-#define FIO_MASKB_T 0xFFC0072C
-#define FIO_DIR 0xFFC00730
-#define FIO_POLAR 0xFFC00734
-#define FIO_EDGE 0xFFC00738
-#define FIO_BOTH 0xFFC0073C
-#define FIO_INEN 0xFFC00740
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00
-#define DMA0_START_ADDR 0xFFC00C04
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10
-#define DMA0_X_MODIFY 0xFFC00C14
-#define DMA0_Y_COUNT 0xFFC00C18
-#define DMA0_Y_MODIFY 0xFFC00C1C
-#define DMA0_CURR_DESC_PTR 0xFFC00C20
-#define DMA0_CURR_ADDR 0xFFC00C24
-#define DMA0_IRQ_STATUS 0xFFC00C28
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
-#define DMA0_CURR_X_COUNT 0xFFC00C30
-#define DMA0_CURR_Y_COUNT 0xFFC00C38
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40
-#define DMA1_START_ADDR 0xFFC00C44
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50
-#define DMA1_X_MODIFY 0xFFC00C54
-#define DMA1_Y_COUNT 0xFFC00C58
-#define DMA1_Y_MODIFY 0xFFC00C5C
-#define DMA1_CURR_DESC_PTR 0xFFC00C60
-#define DMA1_CURR_ADDR 0xFFC00C64
-#define DMA1_IRQ_STATUS 0xFFC00C68
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
-#define DMA1_CURR_X_COUNT 0xFFC00C70
-#define DMA1_CURR_Y_COUNT 0xFFC00C78
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80
-#define DMA2_START_ADDR 0xFFC00C84
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90
-#define DMA2_X_MODIFY 0xFFC00C94
-#define DMA2_Y_COUNT 0xFFC00C98
-#define DMA2_Y_MODIFY 0xFFC00C9C
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0
-#define DMA2_CURR_ADDR 0xFFC00CA4
-#define DMA2_IRQ_STATUS 0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
-#define DMA2_CURR_X_COUNT 0xFFC00CB0
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
-#define DMA3_START_ADDR 0xFFC00CC4
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0
-#define DMA3_X_MODIFY 0xFFC00CD4
-#define DMA3_Y_COUNT 0xFFC00CD8
-#define DMA3_Y_MODIFY 0xFFC00CDC
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0
-#define DMA3_CURR_ADDR 0xFFC00CE4
-#define DMA3_IRQ_STATUS 0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
-#define DMA3_CURR_X_COUNT 0xFFC00CF0
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00
-#define DMA4_START_ADDR 0xFFC00D04
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10
-#define DMA4_X_MODIFY 0xFFC00D14
-#define DMA4_Y_COUNT 0xFFC00D18
-#define DMA4_Y_MODIFY 0xFFC00D1C
-#define DMA4_CURR_DESC_PTR 0xFFC00D20
-#define DMA4_CURR_ADDR 0xFFC00D24
-#define DMA4_IRQ_STATUS 0xFFC00D28
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
-#define DMA4_CURR_X_COUNT 0xFFC00D30
-#define DMA4_CURR_Y_COUNT 0xFFC00D38
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40
-#define DMA5_START_ADDR 0xFFC00D44
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50
-#define DMA5_X_MODIFY 0xFFC00D54
-#define DMA5_Y_COUNT 0xFFC00D58
-#define DMA5_Y_MODIFY 0xFFC00D5C
-#define DMA5_CURR_DESC_PTR 0xFFC00D60
-#define DMA5_CURR_ADDR 0xFFC00D64
-#define DMA5_IRQ_STATUS 0xFFC00D68
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
-#define DMA5_CURR_X_COUNT 0xFFC00D70
-#define DMA5_CURR_Y_COUNT 0xFFC00D78
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80
-#define DMA6_START_ADDR 0xFFC00D84
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90
-#define DMA6_X_MODIFY 0xFFC00D94
-#define DMA6_Y_COUNT 0xFFC00D98
-#define DMA6_Y_MODIFY 0xFFC00D9C
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0
-#define DMA6_CURR_ADDR 0xFFC00DA4
-#define DMA6_IRQ_STATUS 0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
-#define DMA6_CURR_X_COUNT 0xFFC00DB0
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
-#define DMA7_START_ADDR 0xFFC00DC4
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0
-#define DMA7_X_MODIFY 0xFFC00DD4
-#define DMA7_Y_COUNT 0xFFC00DD8
-#define DMA7_Y_MODIFY 0xFFC00DDC
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0
-#define DMA7_CURR_ADDR 0xFFC00DE4
-#define DMA7_IRQ_STATUS 0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
-#define DMA7_CURR_X_COUNT 0xFFC00DF0
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00
-#define MDMA_D0_START_ADDR 0xFFC00E04
-#define MDMA_D0_CONFIG 0xFFC00E08
-#define MDMA_D0_X_COUNT 0xFFC00E10
-#define MDMA_D0_X_MODIFY 0xFFC00E14
-#define MDMA_D0_Y_COUNT 0xFFC00E18
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20
-#define MDMA_D0_CURR_ADDR 0xFFC00E24
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40
-#define MDMA_S0_START_ADDR 0xFFC00E44
-#define MDMA_S0_CONFIG 0xFFC00E48
-#define MDMA_S0_X_COUNT 0xFFC00E50
-#define MDMA_S0_X_MODIFY 0xFFC00E54
-#define MDMA_S0_Y_COUNT 0xFFC00E58
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60
-#define MDMA_S0_CURR_ADDR 0xFFC00E64
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80
-#define MDMA_D1_START_ADDR 0xFFC00E84
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90
-#define MDMA_D1_X_MODIFY 0xFFC00E94
-#define MDMA_D1_Y_COUNT 0xFFC00E98
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0
-#define MDMA_S1_START_ADDR 0xFFC00EC4
-#define MDMA_S1_CONFIG 0xFFC00EC8
-#define MDMA_S1_X_COUNT 0xFFC00ED0
-#define MDMA_S1_X_MODIFY 0xFFC00ED4
-#define MDMA_S1_Y_COUNT 0xFFC00ED8
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8
-#define EBIU_AMGCTL 0xFFC00A00
-#define EBIU_AMBCTL0 0xFFC00A04
-#define EBIU_AMBCTL1 0xFFC00A08
-#define EBIU_SDGCTL 0xFFC00A10
-#define EBIU_SDBCTL 0xFFC00A14
-#define EBIU_SDRRC 0xFFC00A18
-#define EBIU_SDSTAT 0xFFC00A1C
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#endif /* __BFIN_DEF_ADSP_EDN_extended__ */
CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y += ins.o
SOBJS-y += memcmp.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#endif
#ifdef DEBUG
- if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
+ if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
hang();
#endif
serial_early_puts("Init global data\n");
gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
- memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+ memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
/* Board data initialization */
addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t));
memset((void *)bd, 0, sizeof(bd_t));
bd->bi_r_version = version_string;
- bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_cpu = BFIN_CPU;
bd->bi_board_name = BFIN_BOARD_NAME;
bd->bi_vco = get_vco();
bd->bi_cclk = get_cclk();
#endif
#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
+ puts("MMC: ");
mmc_initialize(bd);
#endif
*/
#define COMMON_INS(func, ops) \
+.section .text._ins##func; \
ENTRY(_ins##func) \
P0 = R0; /* P0 = port */ \
CLI_OUTER; /* 3 instructions before first read access */ \
.align 2
+.section .text._outsl
ENTRY(_outsl)
P0 = R0; /* P0 = port */
P1 = R1; /* P1 = address */
RTS;
ENDPROC(_outsl)
+.section .text._outsw
ENTRY(_outsw)
P0 = R0; /* P0 = port */
P1 = R1; /* P1 = address */
RTS;
ENDPROC(_outsw)
+.section .text._outsb
ENTRY(_outsb)
P0 = R0; /* P0 = port */
P1 = R1; /* P1 = address */
RTS;
ENDPROC(_outsb)
+.section .text._outsw_8
ENTRY(_outsw_8)
P0 = R0; /* P0 = port */
P1 = R1; /* P1 = address */
*(.dynbss)
*(.bss .bss.*)
*(COMMON)
+ . = ALIGN(4);
} >ram_data
__bss_vma = ADDR(.bss);
__bss_len = SIZEOF(.bss);
STANDALONE_LOAD_ADDR = 0x40000
+PLATFORM_CPPFLAGS += -fno-strict-aliasing
+PLATFORM_CPPFLAGS += -Wstrict-prototypes
+PLATFORM_CPPFLAGS += -mregparm=3
+PLATFORM_CPPFLAGS += -fomit-frame-pointer
+PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding)
+PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time))
+PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
+PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
+
+LDFLAGS += --cref --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o start16.o resetvec.o
COBJS = interrupts.o cpu.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <command.h>
#include <asm/interrupt.h>
+/* Constructor for a conventional segment GDT (or LDT) entry */
+/* This is a macro so it can be used in initializers */
+#define GDT_ENTRY(flags, base, limit) \
+ ((((base) & 0xff000000ULL) << (56-24)) | \
+ (((flags) & 0x0000f0ffULL) << 40) | \
+ (((limit) & 0x000f0000ULL) << (48-16)) | \
+ (((base) & 0x00ffffffULL) << 16) | \
+ (((limit) & 0x0000ffffULL)))
+
+/* Simple and small GDT entries for booting only */
+
+#define GDT_ENTRY_32BIT_CS 2
+#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1)
+#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1)
+#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1)
+
+/*
+ * Set up the GDT
+ */
+
+struct gdt_ptr {
+ u16 len;
+ u32 ptr;
+} __attribute__((packed));
+
+static void reload_gdt(void)
+{
+ /* There are machines which are known to not boot with the GDT
+ being 8-byte unaligned. Intel recommends 16 byte alignment. */
+ static const u64 boot_gdt[] __attribute__((aligned(16))) = {
+ /* CS: code, read/execute, 4 GB, base 0 */
+ [GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
+ /* DS: data, read/write, 4 GB, base 0 */
+ [GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
+ /* 16-bit CS: code, read/execute, 64 kB, base 0 */
+ [GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff),
+ /* 16-bit DS: data, read/write, 64 kB, base 0 */
+ [GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff),
+ };
+ static struct gdt_ptr gdt;
+
+ gdt.len = sizeof(boot_gdt)-1;
+ gdt.ptr = (u32)&boot_gdt;
+
+ asm volatile("lgdtl %0\n" \
+ "movl $((2+1)*8), %%ecx\n" \
+ "movl %%ecx, %%ds\n" \
+ "movl %%ecx, %%es\n" \
+ "movl %%ecx, %%fs\n" \
+ "movl %%ecx, %%gs\n" \
+ "movl %%ecx, %%ss" \
+ : : "m" (gdt) : "ecx");
+}
+
+
int cpu_init_f(void)
{
/* initialize FPU, reset EM, set MP and NE */
int cpu_init_r(void)
{
+ reload_gdt();
+
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
return 0;
return val;
}
-void dump_regs(struct pt_regs *regs)
+void dump_regs(struct irq_regs *regs)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
}
/* IRQ Low-Level Service Routine */
-__isr__ irq_llsr(struct pt_regs *regs)
+void irq_llsr(struct irq_regs *regs)
{
/*
* For detailed description of each exception, refer to:
* Order Number: 253665-029US, November 2008
* Table 6-1. Exceptions and Interrupts
*/
- switch (regs->orig_eax) {
+ switch (regs->irq_id) {
case 0x00:
printf("Divide Error (Division by zero)\n");
dump_regs(regs);
default:
/* Hardware or User IRQ */
- do_irq(regs->orig_eax);
+ do_irq(regs->irq_id);
}
}
* Interrupt entries are now very small (a push and a jump) but they are
* now slower (all registers pushed on stack which provides complete
* crash dumps in the low level handlers
+ *
+ * Interrupt Entry Point:
+ * - Interrupt has caused eflags, CS and EIP to be pushed
+ * - Interrupt Vector Handler has pushed orig_eax
+ * - pt_regs.esp needs to be adjusted by 40 bytes:
+ * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
+ * 4 bytes pushed by vector handler (irq_id)
+ * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
+ * NOTE: Only longs are pushed on/popped off the stack!
*/
asm(".globl irq_common_entry\n" \
".hidden irq_common_entry\n" \
".type irq_common_entry, @function\n" \
"irq_common_entry:\n" \
"cld\n" \
+ "pushl %ss\n" \
"pushl %gs\n" \
"pushl %fs\n" \
"pushl %es\n" \
"pushl %ds\n" \
"pushl %eax\n" \
+ "movl %esp, %eax\n" \
+ "addl $40, %eax\n" \
+ "pushl %eax\n" \
"pushl %ebp\n" \
"pushl %edi\n" \
"pushl %esi\n" \
"pushl %ecx\n" \
"pushl %ebx\n" \
"mov %esp, %eax\n" \
- "pushl %ebp\n" \
- "movl %esp,%ebp\n" \
- "pushl %eax\n" \
"call irq_llsr\n" \
- "popl %eax\n" \
- "leave\n"\
"popl %ebx\n" \
"popl %ecx\n" \
"popl %edx\n" \
"popl %edi\n" \
"popl %ebp\n" \
"popl %eax\n" \
+ "popl %eax\n" \
"popl %ds\n" \
"popl %es\n" \
"popl %fs\n" \
"popl %gs\n" \
+ "popl %ss\n" \
"add $4, %esp\n" \
"iret\n" \
DECLARE_INTERRUPT(0) \
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(SOC).a
+LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o
COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
void init_sc520(void)
{
- /* Set the UARTxCTL register at it's slower,
+ /*
+ * Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
writeb(0x07, &sc520_mmcr->uart1ctl);
/* first set the timer pin mapping */
writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
- /* enable PCI bus arbitrer */
- writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
+ /* enable PCI bus arbiter (concurrent mode) */
+ writeb(0x02, &sc520_mmcr->sysarbctl);
- writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
- writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
+ /* enable external grants */
+ writeb(0x1f, &sc520_mmcr->sysarbmenb);
+
+ /* enable posted-writes */
+ writeb(0x04, &sc520_mmcr->hbctl);
if (CONFIG_SYS_SC520_HIGH_SPEED) {
- writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
+ /* set it to 133 MHz and write back */
+ writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
} else {
- writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
+ /* set it to 100 MHz and write back */
+ writeb(0x01, &sc520_mmcr->cpuctl);
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
/* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
+ asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
/* set SDRAM speed here */
- refresh_rate/=78;
- if (refresh_rate<=1) {
- val = 0; /* 7.8us */
- } else if (refresh_rate==2) {
- val = 1; /* 15.6us */
- } else if (refresh_rate==3 || refresh_rate==4) {
- val = 2; /* 31.2us */
+ refresh_rate /= 78;
+ if (refresh_rate <= 1) {
+ val = 0; /* 7.8us */
+ } else if (refresh_rate == 2) {
+ val = 1; /* 15.6us */
+ } else if (refresh_rate == 3 || refresh_rate == 4) {
+ val = 2; /* 31.2us */
} else {
- val = 3; /* 62.4us */
+ val = 3; /* 62.4us */
}
tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
val = readb(&sc520_mmcr->drctmctl) & 0xf0;
if (cas_precharge_delay==3) {
- val |= 0x04; /* 3T */
+ val |= 0x04; /* 3T */
} else if (cas_precharge_delay==4) {
- val |= 0x08; /* 4T */
+ val |= 0x08; /* 4T */
} else if (cas_precharge_delay>4) {
val |= 0x0c;
}
writeb(val, &c520_mmcr->drctmctl);
#endif
- /* We read-back the configuration of the dram
- * controller that the assembly code wrote */
+ /*
+ * We read-back the configuration of the dram
+ * controller that the assembly code wrote
+ */
dram_ctrl = readl(&sc520_mmcr->drcbendadr);
bd->bi_dram[0].start = 0;
/* bank 0 enabled */
dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
bd->bi_dram[0].size = bd->bi_dram[1].start;
-
} else {
bd->bi_dram[0].size = 0;
bd->bi_dram[1].start = bd->bi_dram[0].start;
} else {
bd->bi_dram[3].size = 0;
}
-
-
-#if 0
- printf("Configured %d bytes of dram\n", dram_present);
-#endif
gd->ram_size = dram_present;
return dram_present;
.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
-
- /*
- * initialize dram controller registers
- */
.globl mem_init
mem_init:
- xorw %ax,%ax
- movl $DBCTL, %edi
- movb %al, (%edi) /* disable write buffer */
+ /* Preserve Boot Flags */
+ movl %ebx, %ebp
- movl $ECCCTL, %edi
- movb %al, (%edi) /* disable ECC */
+ /* initialize dram controller registers */
+ xorw %ax, %ax
+ movl $DBCTL, %edi
+ movb %al, (%edi) /* disable write buffer */
- movl $DRCTMCTL, %edi
- movb $0x1E,%al /* Set SDRAM timing for slowest */
- movb %al, (%edi)
+ movl $ECCCTL, %edi
+ movb %al, (%edi) /* disable ECC */
- /*
- * setup loop to do 4 external banks starting with bank 3
- */
- movl $0xff000000,%eax /* enable last bank and setup */
- movl $DRCBENDADR, %edi /* ending address register */
- movl %eax, (%edi)
+ movl $DRCTMCTL, %edi
+ movb $0x1e, %al /* Set SDRAM timing for slowest */
+ movb %al, (%edi)
- movl $DRCCFG, %edi /* setup */
- movw $0xbbbb,%ax /* dram config register for */
- movw %ax, (%edi)
+ /* setup loop to do 4 external banks starting with bank 3 */
+ movl $0xff000000, %eax /* enable last bank and setup */
+ movl $DRCBENDADR, %edi /* ending address register */
+ movl %eax, (%edi)
- /*
- * issue a NOP to all DRAMs
- */
- movl $DRCCTL, %edi /* setup DRAM control register with */
- movb $0x1,%al /* Disable refresh,disable write buffer */
- movb %al, (%edi)
- movl $CACHELINESZ, %esi /* just a dummy address to write for */
- movw %ax, (%esi)
- /*
- * delay for 100 usec? 200?
- * ******this is a cludge for now *************
- */
- movw $100,%cx
-sizdelay:
- loop sizdelay /* we need 100 usec here */
- /***********************************************/
+ movl $DRCCFG, %edi /* setup */
+ movw $0xbbbb, %ax /* dram config register for */
+ movw %ax, (%edi)
- /*
- * issue all banks precharge
- */
- movb $0x2,%al /* All banks precharge */
- movb %al, (%edi)
- movw %ax, (%esi)
+ /* issue a NOP to all DRAMs */
+ movl $DRCCTL, %edi /* setup DRAM control register with */
+ movb $0x01, %al /* Disable refresh,disable write buffer */
+ movb %al, (%edi)
+ movl $CACHELINESZ, %esi /* just a dummy address to write for */
+ movw %ax, (%esi)
- /*
- * issue 2 auto refreshes to all banks
- */
- movb $0x4,%al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $2,%cx
-refresh1:
- movw %ax, (%esi)
- loop refresh1
+ /* delay for 100 usec? */
+ movw $100, %cx
+sizdelay:
+ loop sizdelay
- /*
- * issue LOAD MODE REGISTER command
- */
- movb $0x3,%al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
+ /* issue all banks precharge */
+ movb $0x02, %al
+ movb %al, (%edi)
+ movw %ax, (%esi)
- /*
- * issue 8 more auto refreshes to all banks
- */
- movb $0x4,%al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $8,%cx
+ /* issue 2 auto refreshes to all banks */
+ movb $0x04, %al /* Auto refresh cmd */
+ movb %al, (%edi)
+ movw $0x02, %cx
+refresh1:
+ movw %ax, (%esi)
+ loop refresh1
+
+ /* issue LOAD MODE REGISTER command */
+ movb $0x03, %al /* Load mode register cmd */
+ movb %al, (%edi)
+ movw %ax, (%esi)
+
+ /* issue 8 more auto refreshes to all banks */
+ movb $0x04, %al /* Auto refresh cmd */
+ movb %al, (%edi)
+ movw $0x0008, %cx
refresh2:
- movw %ax, (%esi)
- loop refresh2
+ movw %ax, (%esi)
+ loop refresh2
- /*
- * set control register to NORMAL mode
- */
- movb $0x0,%al /* Normal mode value */
- movb %al, (%edi)
+ /* set control register to NORMAL mode */
+ movb $0x00, %al /* Normal mode value */
+ movb %al, (%edi)
- /*
- * size dram starting with external bank 3 moving to external bank 0
- */
- movl $0x3,%ecx /* start with external bank 3 */
+ /*
+ * size dram starting with external bank 3
+ * moving to external bank 0
+ */
+ movl $0x3, %ecx /* start with external bank 3 */
nextbank:
- /*
- * write col 11 wrap adr
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
- movl %eax, (%esi) /* write max col pattern at max col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 10 wrap adr
- */
+ /* write col 11 wrap adr */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
+ movl %eax, (%esi) /* write max col pattern at max col adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 10 wrap adr */
+ movl $COL10_ADR, %esi /* set address to 10 col wrap address */
+ movl $COL10_DATA, %eax /* pattern for 10 col wrap */
+ movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 9 wrap adr */
+ movl $COL09_ADR, %esi /* set address to 9 col wrap address */
+ movl $COL09_DATA, %eax /* pattern for 9 col wrap */
+ movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 8 wrap adr */
+ movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
+ movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
+ movl %eax, (%esi) /* write min col pattern @ min col adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 14 wrap adr */
+ movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
+ movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
+ movl %eax, (%esi) /* write max row pattern at max row adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 13 wrap adr */
+ movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
+ movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
+ movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 12 wrap adr */
+ movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
+ movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
+ movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 11 wrap adr */
+ movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
+ movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
+ movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
+ movl (%edi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
- movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 9 wrap adr
- */
- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
- movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 8 wrap adr
- */
- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
- movl %eax, (%esi) /* write min col pattern @ min col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 14 wrap adr
- */
- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
- movl %eax, (%esi) /* write max row pattern at max row adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 13 wrap adr
- */
- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
- movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 12 wrap adr
- */
- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
- movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 11 wrap adr
- */
- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
- movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 10 wrap adr --- this write is really to determine number of banks
- */
- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
- movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * read data @ row 12 wrap adr to determine * banks,
- * and read data @ row 14 wrap adr to determine * rows.
- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
- */
- xorw %di,%di /* value for 2 banks in DI */
- movl (%esi), %ebx /* read from 12 row wrap to check banks
- * (esi is setup from the write to row 12 wrap) */
- cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
- jz only2 /* if pattern == AA, we only have 2 banks */
+ /*
+ * write row 10 wrap adr --- this write is really to determine
+ * number of banks
+ */
+ movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
+ movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
+ movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
+ movl (%edi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /*
+ * read data @ row 12 wrap adr to determine * banks,
+ * and read data @ row 14 wrap adr to determine * rows.
+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+ */
+ xorw %di, %di /* value for 2 banks in DI */
+ movl (%esi), %ebx /* read from 12 row wrap to check banks */
+ /* (esi is setup from the write to row 12 wrap) */
+ cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
+ jz only2 /* if pattern == AA, we only have 2 banks */
/* 4 banks */
- movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
- jz only2
- cmpl $ROW12_DATA, %ebx /* and 12 */
- jnz bad_ram /* its bad if not 11 or 12! */
+ movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
+ cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
+ jz only2
+ cmpl $ROW12_DATA, %ebx /* and 12 */
+ jnz bad_ram /* its bad if not 11 or 12! */
/* fall through */
only2:
/*
* validate row mask
*/
- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
- movl (%esi), %eax /* read actual number of rows @ row14 adr */
+ movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
+ movl (%esi), %eax /* read actual number of rows @ row14 adr */
- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
- jb bad_ram
+ cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
+ jb bad_ram
- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
- ja bad_ram
+ cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
+ ja bad_ram
+
+ cmpb %ah, %al /* verify all 4 bytes of dword same */
+ jnz bad_ram
+ movl %eax, %ebx
+ shrl $16, %ebx
+ cmpw %bx, %ax
+ jnz bad_ram
+
+ /*
+ * read col 11 wrap adr for real column data value
+ */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl (%esi), %eax /* read real col number at max col adr */
+
+ /*
+ * validate column data
+ */
+ cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
+ jb bad_ram
+
+ cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
+ ja bad_ram
+
+ subl $COL08_DATA, %eax /* normalize column data to zero */
+ jc bad_ram
+ cmpb %ah, %al /* verify all 4 bytes of dword equal */
+ jnz bad_ram
+ movl %eax, %edx
+ shrl $16, %edx
+ cmpw %dx, %ax
+ jnz bad_ram
+
+ /*
+ * merge bank and col data together
+ */
+ addw %di, %dx /* merge of bank and col info in dl */
+
+ /*
+ * fix ending addr mask based upon col info
+ */
+ movb $0x03, %al
+ subb %dh, %al /* dh contains the overflow from the bank/col merge */
+ movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
+ xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
+ shrb %cl, %dh
+ incb %dh /* ending addr is 1 greater than real end */
+ xchgw %cx, %ax /* cx is bank number again */
- cmpb %ah,%al /* verify all 4 bytes of dword same */
- jnz bad_ram
- movl %eax,%ebx
- shrl $16,%ebx
- cmpw %bx,%ax
- jnz bad_ram
- /*
- * read col 11 wrap adr for real column data value
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl (%esi), %eax /* read real col number at max col adr */
- /*
- * validate column data
- */
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
- jb bad_ram
-
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
- ja bad_ram
-
- subl $COL08_DATA, %eax /* normalize column data to zero */
- jc bad_ram
- cmpb %ah,%al /* verify all 4 bytes of dword equal */
- jnz bad_ram
- movl %eax,%edx
- shrl $16,%edx
- cmpw %dx,%ax
- jnz bad_ram
- /*
- * merge bank and col data together
- */
- addw %di,%dx /* merge of bank and col info in dl */
- /*
- * fix ending addr mask based upon col info
- */
- movb $3,%al
- subb %dh,%al /* dh contains the overflow from the bank/col merge */
- movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
- xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
- shrb %cl,%dh /* */
- incb %dh /* ending addr is 1 greater than real end */
- xchgw %cx,%ax /* cx is bank number again */
- /*
- * issue all banks precharge
- */
bad_reint:
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x2,%al /* All banks precharge */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
+ /*
+ * issue all banks precharge
+ */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x02, %al /* All banks precharge */
+ movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+ movw %ax, (%esi)
- /*
- * update ENDING ADDRESS REGISTER
- */
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movl %ecx,%ebx
+ /*
+ * update ENDING ADDRESS REGISTER
+ */
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl %ecx, %ebx
addl %ebx, %edi
- movb %dh, (%edi)
- /*
- * update CONFIG REGISTER
- */
- xorb %dh,%dh
- movw $0x00f,%bx
- movw %cx,%ax
- shlw $2,%ax
- xchgw %cx,%ax
- shlw %cl,%dx
- shlw %cl,%bx
- notw %bx
- xchgw %cx,%ax
- movl $DRCCFG, %edi
- mov (%edi), %ax
- andw %bx,%ax
- orw %dx,%ax
- movw %ax, (%edi)
- jcxz cleanup
-
- decw %cx
- movl %ecx,%ebx
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movb $0xff,%al
+ movb %dh, (%edi)
+
+ /*
+ * update CONFIG REGISTER
+ */
+ xorb %dh, %dh
+ movw $0x000f, %bx
+ movw %cx, %ax
+ shlw $2, %ax
+ xchgw %cx, %ax
+ shlw %cl, %dx
+ shlw %cl, %bx
+ notw %bx
+ xchgw %cx, %ax
+ movl $DRCCFG, %edi
+ movw (%edi), %ax
+ andw %bx, %ax
+ orw %dx, %ax
+ movw %ax, (%edi)
+ jcxz cleanup
+
+ decw %cx
+ movl %ecx, %ebx
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movb $0xff, %al
addl %ebx, %edi
- movb %al, (%edi)
- /*
- * set control register to NORMAL mode
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x0,%al /* Normal mode value */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
- jmp nextbank
+ movb %al, (%edi)
+
+ /*
+ * set control register to NORMAL mode
+ */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x00, %al /* Normal mode value */
+ movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+ movw %ax, (%esi)
+ jmp nextbank
cleanup:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movw $4,%cx
- xorw %ax,%ax
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movw $0x04, %cx
+ xorw %ax, %ax
cleanuplp:
- movb (%edi), %al
- orb %al,%al
- jz emptybank
+ movb (%edi), %al
+ orb %al, %al
+ jz emptybank
- addb %ah,%al
- jns nottoomuch
+ addb %ah, %al
+ jns nottoomuch
- movb $0x7f,%al
+ movb $0x7f, %al
nottoomuch:
- movb %al,%ah
- orb $0x80,%al
- movb %al, (%edi)
+ movb %al, %ah
+ orb $0x80, %al
+ movb %al, (%edi)
emptybank:
- incl %edi
- loop cleanuplp
+ incl %edi
+ loop cleanuplp
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
- movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
- movb %al, (%edi)
+ movl $DRCTMCTL, %edi
+ movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
+ movb %al, (%edi)
#else
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
- /* set the CAS latency now since it is hard to do
- * when we run from the RAM */
- movl $DRCTMCTL, %edi /* DRAM timing register */
- movb (%edi), %al
+ /*
+ * Set the CAS latency now since it is hard to do
+ * when we run from the RAM
+ */
+ movl $DRCTMCTL, %edi /* DRAM timing register */
+ movb (%edi), %al
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
- andb $0xef, %al
+ andb $0xef, %al
#endif
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
- orb $0x10, %al
+ orb $0x10, %al
#endif
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
#endif
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x3,%al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x03, %al /* Load mode register cmd */
+ movb %al, (%edi)
+ movw %ax, (%esi)
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x18,%al /* Enable refresh and NORMAL mode */
- movb %al, (%edi)
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x18, %al /* Enable refresh and NORMAL mode */
+ movb %al, (%edi)
- jmp dram_done
+ jmp dram_done
bad_ram:
- xorl %edx,%edx
- xorl %edi,%edi
- jmp bad_reint
+ xorl %edx, %edx
+ xorl %edi, %edi
+ jmp bad_reint
dram_done:
+ /* Restore Boot Flags */
+ movl %ebx, %ebp
+ jmp mem_init_ret
#if CONFIG_SYS_SDRAM_ECC_ENABLE
- /*
- * We are in the middle of an existing 'call' - Need to store the
- * existing return address before making another 'call'
- */
- movl %ebp, %ebx
-
- /* Get the memory size */
- movl $init_ecc, %ebp
- jmpl get_mem_size
-
+.globl init_ecc
init_ecc:
- /* Restore the orignal return address */
- movl %ebx, %ebp
-
/* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
+ movl %eax, %ecx
+ shrl $0x1, %ecx
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
jne out
- shrl $1, %ecx
- andl %ecx,%ecx
+ shrl $0x1, %ecx
+ andl %ecx, %ecx
jz set_ecc
- shll $1, %edi
+ shll $0x1, %edi
jmp memtest0
set_ecc:
xorl %esi, %esi
xorl %edi, %edi
xorl %eax, %eax
- shrl $2, %ecx
+ shrl $0x2, %ecx
cld
rep stosl
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- mov $0x10, %al
- movb %al, (%edi)
- /* Turn on ECC */
- movl $ECCCTL, %edi
- mov $0x05, %al
- movb %al, (%edi)
-#endif
+
+ /* enable read, write buffers */
+ movb $0x11, %al
+ movl $DBCTL, %edi
+ movb %al, (%edi)
+
+ /* enable NMI mapping for ECC */
+ movl $ECCINT, %edi
+ movb $0x10, %al
+ movb %al, (%edi)
+
+ /* Turn on ECC */
+ movl $ECCCTL, %edi
+ movb $0x05, %al
+ movb %al,(%edi)
out:
- jmp *%ebp
+ jmp init_ecc_ret
+#endif
/*
* Read and decode the sc520 DRCBENDADR MMCR and return the number of
*/
.globl get_mem_size
get_mem_size:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
bank0: movl (%edi), %eax
movl %eax, %ecx
jz bank1
andl $0x0000007f, %eax
shll $22, %eax
- movl %eax, %ebx
+ movl %eax, %edx
bank1: movl (%edi), %eax
movl %eax, %ecx
jz bank2
andl $0x00007f00, %eax
shll $14, %eax
- movl %eax, %ebx
+ movl %eax, %edx
bank2: movl (%edi), %eax
movl %eax, %ecx
jz bank3
andl $0x007f0000, %eax
shll $6, %eax
- movl %eax, %ebx
+ movl %eax, %edx
bank3: movl (%edi), %eax
movl %eax, %ecx
jz done
andl $0x7f000000, %eax
shrl $2, %eax
- movl %eax, %ebx
+ movl %eax, %edx
done:
- movl %ebx, %eax
- jmp *%ebp
+ movl %edx, %eax
+ jmp get_mem_size_ret
/*
* U-boot - i386 Startup Code
*
- * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
+ * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m <denaiel@omicron.se>
*
* See file CREDITS for list of people who contributed to this
* project.
#include <config.h>
#include <version.h>
+#include <asm/global_data.h>
.section .text
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000,%eax
+ orl $0x60000000, %eax
movl %eax, %cr0
wbinvd
/* Tell 32-bit code it is being entered from an in-RAM copy */
- movw $0x0000, %bx
+ movw $GD_FLG_WARM_BOOT, %bx
_start:
/* This is the 32-bit cold-reset entry point */
- movl $0x18,%eax /* Load our segement registes, the
+ movl $0x18, %eax /* Load our segement registes, the
* gdt have already been loaded by start16.S */
- movw %ax,%fs
- movw %ax,%ds
- movw %ax,%gs
- movw %ax,%es
- movw %ax,%ss
+ movw %ax, %fs
+ movw %ax, %ds
+ movw %ax, %gs
+ movw %ax, %es
+ movw %ax, %ss
/* Clear the interupt vectors */
lidt blank_idt_ptr
- /*
- * Skip low-level board and memory initialization if not starting
- * from cold-reset. This allows us to do a fail safe boot-strap
- * into a new build of U-Boot from a known-good boot flash
- */
- movw $0x0001, %ax
- cmpw %ax, %bx
- jne mem_init_ret
-
- /* We call a few functions in the board support package
- * since we have no stack yet we'll have to use %ebp
- * to store the return address */
+ /* Skip low-level initialization if not starting from cold-reset */
+ movl %ebx, %ecx
+ andl $GD_FLG_COLD_BOOT, %ecx
+ jz skip_mem_init
/* Early platform init (setup gpio, etc ) */
- mov $early_board_init_ret, %ebp
jmp early_board_init
+.globl early_board_init_ret
early_board_init_ret:
- /* The __port80 entry-point should be usabe by now */
- /* so we try to indicate progress */
- movw $0x01, %ax
- movl $.progress0, %ebp
- jmp show_boot_progress_asm
-.progress0:
-
/* size memory */
- mov $mem_init_ret, %ebp
- jmp mem_init
+ jmp mem_init
+.globl mem_init_ret
mem_init_ret:
+skip_mem_init:
/* fetch memory size (into %eax) */
- mov $get_mem_size_ret, %ebp
- jmp get_mem_size
+ jmp get_mem_size
+.globl get_mem_size_ret
get_mem_size_ret:
- /*
- * We are now in 'Flat Protected Mode' and we know how much memory
- * the board has. The (temporary) Global Descriptor Table is not
- * in a 'Safe' place (it is either in Flash which can be erased or
- * reprogrammed or in a fail-safe boot-strap image which could be
- * over-written).
- *
- * Move the final gdt to a safe place (top of RAM) and load it.
- * This is not a trivial excercise - the lgdt instruction does not
- * have a register operand (memory only) and we may well be
- * running from Flash, so self modifying code will not work here.
- * To overcome this, we copy a stub into upper memory along with
- * the GDT.
- */
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+ /* Skip ECC initialization if not starting from cold-reset */
+ movl %ebx, %ecx
+ andl $GD_FLG_COLD_BOOT, %ecx
+ jz init_ecc_ret
+ jmp init_ecc
- /* Reduce upper memory limit by (Stub + GDT Pointer + GDT) */
- subl $(end_gdt_setup - start_gdt_setup), %eax
-
- /* Copy the GDT and Stub */
- movl $start_gdt_setup, %esi
- movl %eax, %edi
- movl $(end_gdt_setup - start_gdt_setup), %ecx
- shrl $2, %ecx
- cld
- rep movsl
+.globl init_ecc_ret
+init_ecc_ret:
+#endif
- /* write the lgdt 'parameter' */
- subl $(jmp_instr - start_gdt_setup - 4), %ebp
- addl %eax, %ebp
- movl $(gdt_ptr - start_gdt_setup), %ebx
- addl %eax, %ebx
- movl %ebx, (%ebp)
-
- /* write the gdt address into the pointer */
- movl $(gdt_addr - start_gdt_setup), %ebp
- addl %eax, %ebp
- movl $(gdt - start_gdt_setup), %ebx
- addl %eax, %ebx
- movl %ebx, (%ebp)
-
- /* Save the return address */
- movl $load_gdt_ret, %ebp
-
- /* Load the new (safe) Global Descriptor Table */
- jmp *%eax
-
-load_gdt_ret:
/* Check we have enough memory for stack */
movl $CONFIG_SYS_STACK_SIZE, %ecx
cmpl %ecx, %eax
- jae mem_ok
-
- /* indicate (lack of) progress */
- movw $0x81, %ax
- movl $.progress0a, %ebp
- jmp show_boot_progress_asm
-.progress0a:
- jmp die
+ jb die
mem_ok:
/* Set stack pointer to upper memory limit*/
- movl %eax, %esp
-
- /* indicate progress */
- movw $0x02, %ax
- movl $.progress1, %ebp
- jmp show_boot_progress_asm
-.progress1:
+ movl %eax, %esp
/* Test the stack */
pushl $0
- popl %eax
- cmpl $0, %eax
- jne no_stack
+ popl %ecx
+ cmpl $0, %ecx
+ jne die
push $0x55aa55aa
- popl %ebx
- cmpl $0x55aa55aa, %ebx
- je stack_ok
-
-no_stack:
- /* indicate (lack of) progress */
- movw $0x82, %ax
- movl $.progress1a, %ebp
- jmp show_boot_progress_asm
-.progress1a:
- jmp die
+ popl %ecx
+ cmpl $0x55aa55aa, %ecx
+ jne die
+ wbinvd
-stack_ok:
- /* indicate progress */
- movw $0x03, %ax
- movl $.progress2, %ebp
- jmp show_boot_progress_asm
-.progress2:
+ /* Determine our load offset */
+ call 1f
+1: popl %ecx
+ subl $1b, %ecx
- wbinvd
+ /* Set the upper memory limit parameter */
+ subl $CONFIG_SYS_STACK_SIZE, %eax
- /* Get upper memory limit */
- movl %esp, %ecx
- subl $CONFIG_SYS_STACK_SIZE, %ecx
+ /* Reserve space for global data */
+ subl $(GD_SIZE * 4), %eax
- /* Create a Stack Frame */
- pushl %ebp
- movl %esp, %ebp
+ /* %eax points to the global data structure */
+ movl %esp, (GD_RAM_SIZE * 4)(%eax)
+ movl %ebx, (GD_FLAGS * 4)(%eax)
+ movl %ecx, (GD_LOAD_OFF * 4)(%eax)
- /* stack_limit parameter */
- pushl %ecx
call board_init_f /* Enter, U-boot! */
/* indicate (lack of) progress */
movw $0x85, %ax
- movl $.progress4a, %ebp
- jmp show_boot_progress_asm
-.progress4a:
-
die: hlt
jmp die
hlt
blank_idt_ptr:
.word 0 /* limit */
.long 0 /* base */
-
-.align 4
-start_gdt_setup:
- lgdt gdt_ptr
-jmp_instr:
- jmp *%ebp
-
-.align 4
-gdt_ptr:
- .word 0x30 /* limit (48 bytes = 6 GDT entries) */
-gdt_addr:
- .long gdt /* base */
-
- /* The GDT table ...
- *
- * Selector Type
- * 0x00 NULL
- * 0x08 Unused
- * 0x10 32bit code
- * 0x18 32bit data/stack
- * 0x20 16bit code
- * 0x28 16bit data/stack
- */
-
-.align 4
-gdt:
- .word 0, 0, 0, 0 /* NULL */
- .word 0, 0, 0, 0 /* unused */
-
- .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
- .word 0 /* base address = 0 */
- .word 0x9B00 /* code read/exec */
- .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
-
- .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */
- .word 0x0 /* base address = 0 */
- .word 0x9300 /* data read/write */
- .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
-
- .word 0xFFFF /* 64kb */
- .word 0 /* base address = 0 */
- .word 0x9b00 /* data read/write */
- .word 0x0010 /* granularity = 1 (+5th nibble of limit) */
-
- .word 0xFFFF /* 64kb */
- .word 0 /* base address = 0 */
- .word 0x9300 /* data read/write */
- .word 0x0010 /* granularity = 1 (+5th nibble of limit) */
-end_gdt_setup:
* MA 02111-1307 USA
*/
+#include <asm/global_data.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
#define a32 .byte 0x67;
.code16
.globl start16
start16:
- /* First we let the BSP do some early initialization
+ /* Set the Cold Boot / Hard Reset flag */
+ movl $GD_FLG_COLD_BOOT, %ebx
+
+ /*
+ * First we let the BSP do some early initialization
* this code have to map the flash to its final position
*/
- mov $board_init16_ret, %bp
jmp board_init16
+.globl board_init16_ret
board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000,%eax
+ orl $0x60000000, %eax
movl %eax, %cr0
wbinvd
/* Now, we enter protected mode */
movl %cr0, %eax
- orl $1,%eax
+ orl $1, %eax
movl %eax, %cr0
/* Flush the prefetch queue */
jmp ff
ff:
- /* Tell 32-bit code it is being entered from hard-reset */
- movw $0x0001, %bx
-
/* Finally jump to the 32bit initialization code */
movw $code32start, %ax
- movw %ax,%bp
+ movw %ax, %bp
o32 cs ljmp *(%bp)
/* 48-bit far pointer */
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
+#ifndef __ASSEMBLY__
+
typedef struct {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
+ unsigned long load_off; /* Load Offset */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long cpu_clk; /* CPU clock in Hz! */
char env_buf[32]; /* buffer for getenv() before reloc. */
} gd_t;
+extern gd_t *gd;
+
+#endif
+
+/* Word Offsets into Global Data - MUST match struct gd_t */
+#define GD_BD 0
+#define GD_FLAGS 1
+#define GD_BAUDRATE 2
+#define GD_HAVE_CONSOLE 3
+#define GD_RELOC_OFF 4
+#define GD_LOAD_OFF 5
+#define GD_ENV_ADDR 6
+#define GD_ENV_VALID 7
+#define GD_CPU_CLK 8
+#define GD_BUS_CLK 9
+#define GD_RAM_SIZE 10
+#define GD_RESET_STATUS 11
+#define GD_JT 12
+
+#define GD_SIZE 13
+
/*
* Global Data Flags
*/
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
+#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
+#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
-extern gd_t *gd;
#define DECLARE_GLOBAL_DATA_PTR
#ifndef __ASM_INTERRUPT_H_
#define __ASM_INTERRUPT_H_ 1
+#include <asm/types.h>
+
/* arch/i386/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
extern char exception_stack[];
-#define __isr__ void __attribute__ ((regparm(0)))
-
#endif
#ifndef _I386_PTRACE_H
#define _I386_PTRACE_H
+#include <asm/types.h>
+
#define EBX 0
#define ECX 1
#define EDX 2
int xss;
} __attribute__ ((packed));
+struct irq_regs {
+ /* Pushed by irq_common_entry */
+ long ebx;
+ long ecx;
+ long edx;
+ long esi;
+ long edi;
+ long ebp;
+ long esp;
+ long eax;
+ long xds;
+ long xes;
+ long xfs;
+ long xgs;
+ long xss;
+ /* Pushed by vector handler (irq_<num>) */
+ long irq_id;
+ /* Pushed by cpu in response to interrupt */
+ long eip;
+ long xcs;
+ long eflags;
+} __attribute__ ((packed));
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
#define PTRACE_GETREGS 12
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y += bios.o
SOBJS-y += bios_pci.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#define BIOS_BASE ((char*)0xf0000)
#define BIOS_CS 0xf000
-extern ulong _i386boot_bios;
-extern ulong _i386boot_bios_size;
+extern ulong __bios_start;
+extern ulong __bios_size;
/* these are defined in a 16bit segment and needs
* to be accessed with the RELOC_16_xxxx() macros below
int bios_setup(void)
{
- ulong i386boot_bios = (ulong)&_i386boot_bios + gd->reloc_off;
- ulong i386boot_bios_size = (ulong)&_i386boot_bios_size;
+ ulong bios_start = (ulong)&__bios_start + gd->reloc_off;
+ ulong bios_size = (ulong)&__bios_size;
static int done=0;
int vector;
}
done = 1;
- if (i386boot_bios_size > 65536) {
+ if (bios_size > 65536) {
printf("BIOS too large (%ld bytes, max is 65536)\n",
- i386boot_bios_size);
+ bios_size);
return -1;
}
- memcpy(BIOS_BASE, (void*)i386boot_bios, i386boot_bios_size);
+ memcpy(BIOS_BASE, (void*)bios_start, bios_size);
/* clear bda */
memset(BIOS_DATA, 0, BIOS_DATA_SIZE);
DECLARE_GLOBAL_DATA_PTR;
/* Exports from the Linker Script */
-extern ulong _i386boot_text_start;
-extern ulong _i386boot_rel_dyn_start;
-extern ulong _i386boot_rel_dyn_end;
-extern ulong _i386boot_bss_start;
-extern ulong _i386boot_bss_size;
-
-void ram_bootstrap (void *, ulong);
+extern ulong __text_start;
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_start;
+extern ulong __bss_end;
const char version_string[] =
U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
NULL,
};
-static gd_t gd_data;
gd_t *gd;
/*
* Load U-Boot into RAM, initialize BSS, perform relocation adjustments
*/
-void board_init_f (ulong stack_limit)
+void board_init_f (ulong gdp)
{
- void *text_start = &_i386boot_text_start;
- void *u_boot_cmd_end = &__u_boot_cmd_end;
- Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start;
- Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end;
- void *bss_start = &_i386boot_bss_start;
- ulong bss_size = (ulong)&_i386boot_bss_size;
-
- ulong uboot_size;
+ void *text_start = &__text_start;
+ void *data_end = &__data_end;
+ void *rel_dyn_start = &__rel_dyn_start;
+ void *rel_dyn_end = &__rel_dyn_end;
+ void *bss_start = &__bss_start;
+ void *bss_end = &__bss_end;
+
+ ulong *dst_addr;
+ ulong *src_addr;
+ ulong *end_addr;
+
void *dest_addr;
ulong rel_offset;
- Elf32_Rel *re;
+ Elf32_Rel *re_src;
+ Elf32_Rel *re_end;
- void (*start_func)(void *, ulong);
-
- uboot_size = (ulong)u_boot_cmd_end - (ulong)text_start;
- dest_addr = (void *)stack_limit - (uboot_size + (ulong)bss_size);
+ /* Calculate destination RAM Address and relocation offset */
+ dest_addr = (void *)gdp - (bss_end - text_start);
rel_offset = text_start - dest_addr;
- start_func = ram_bootstrap - rel_offset;
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
+ /* Perform low-level initialization only when cold booted */
+ if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) {
+ /* First stage CPU initialization */
+ if (cpu_init_f() != 0)
+ hang();
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
+ /* First stage Board initialization */
+ if (board_early_init_f() != 0)
+ hang();
+ }
/* Copy U-Boot into RAM */
- memcpy(dest_addr, text_start, uboot_size);
+ dst_addr = (ulong *)dest_addr;
+ src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off);
+ end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off);
+
+ while (src_addr < end_addr)
+ *dst_addr++ = *src_addr++;
/* Clear BSS */
- memset(bss_start - rel_offset, 0, bss_size);
+ dst_addr = (ulong *)(bss_start - rel_offset);
+ end_addr = (ulong *)(bss_end - rel_offset);
+
+ while (dst_addr < end_addr)
+ *dst_addr++ = 0x00000000;
/* Perform relocation adjustments */
- for (re = rel_dyn_start; re < rel_dyn_end; re++)
- {
- if (re->r_offset >= TEXT_BASE)
- if (*(ulong *)re->r_offset >= TEXT_BASE)
- *(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset;
- }
+ re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off);
+ re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off);
- /* Enter the relocated U-Boot! */
- start_func(dest_addr, rel_offset);
- /* NOTREACHED - board_init_f() does not return */
- while(1);
-}
+ do {
+ if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
+ if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= CONFIG_SYS_TEXT_BASE)
+ *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset;
+ } while (re_src++ < re_end);
-/*
- * We cannot initialize gd_data in board_init_f() because we would be
- * attempting to write to flash (I have even tried using manual relocation
- * adjustments on pointers but it just won't work) and board_init_r() does
- * not have enough arguments to allow us to pass the relocation offset
- * straight up. This bootstrap function (which runs in RAM) is used to
- * setup gd_data in order to pass the relocation offset to the rest of
- * U-Boot.
- *
- * TODO: The compiler optimization barrier is intended to stop GCC from
- * optimizing this function into board_init_f(). It seems to work without
- * it, but I've left it in to be sure. I think also that the barrier in
- * board_init_r() is no longer needed, but left it in 'just in case'
- */
-void ram_bootstrap (void *dest_addr, ulong rel_offset)
-{
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
+ ((gd_t *)gdp)->reloc_off = rel_offset;
+ ((gd_t *)gdp)->flags |= GD_FLG_RELOC;
- /* tell others: relocation done */
- gd_data.reloc_off = rel_offset;
- gd_data.flags |= GD_FLG_RELOC;
+ /* Enter the relocated U-Boot! */
+ (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr);
- board_init_r(&gd_data, (ulong)dest_addr);
+ /* NOTREACHED - board_init_f() does not return */
+ while(1);
}
void board_init_r(gd_t *id, ulong dest_addr)
#define REALMODE_MAILBOX ((char*)0xe00)
-extern ulong _i386boot_realmode;
-extern ulong _i386boot_realmode_size;
+extern ulong __realmode_start;
+extern ulong __realmode_size;
extern char realmode_enter;
int realmode_setup(void)
{
- ulong i386boot_realmode = (ulong)&_i386boot_realmode + gd->reloc_off;
- ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size;
+ ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off;
+ ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
- if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
+ if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
- i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+ realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
return -1;
}
- memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size);
+ memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size);
asm("wbinvd\n");
return 0;
int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
void *base_ptr;
- void *bzImage_addr;
+ void *bzImage_addr = NULL;
+ char *s;
ulong bzImage_size = 0;
disable_interrupts();
/* Setup board for maximum PC/AT Compatibility */
setup_pcat_compatibility();
- /* argv[1] holds the address of the bzImage */
- bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ if (argc >= 2)
+ /* argv[1] holds the address of the bzImage */
+ s = argv[1];
+ else
+ s = getenv("fileaddr");
+
+ if (s)
+ bzImage_addr = (void *)simple_strtoul(s, NULL, 16);
- if (argc == 3)
+ if (argc >= 3)
+ /* argv[2] holds the size of the bzImage */
bzImage_size = simple_strtoul(argv[2], NULL, 16);
/* Lets look for*/
}
U_BOOT_CMD(
- zboot, 3, 0, do_zboot,
+ zboot, 2, 0, do_zboot,
"Boot bzImage",
""
);
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = lib$(CPU).o
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
rte;
#if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00020000 /* image length */
- .long TEXT_BASE /* image to be relocated at */
+ .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
jsr asm_dspi_rd_status
/* jump to memory and execute */
- move.l #(TEXT_BASE + 0x400), %a0
+ move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
move.l %a0, (%a1)
jmp (%a0)
/* Set vector base register at the beginning of the Flash */
#if defined(CONFIG_CF_SBF)
- move.l #TEXT_BASE, %d0
+ move.l #CONFIG_SYS_TEXT_BASE, %d0
movec %d0, %VBR
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = lib$(CPU).o
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
# CFLAGS += -DET_DEBUG
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = interrupts.o cpu.o speed.o cpu_init.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
{
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
-r */
+ wdt->sr = 0x5555; /* reset watchdog counter */
wdt->sr = 0xAAAA;
wdt->cr = 0; /* disable watchdog timer */
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Call the board specific reset actions first. */
if(board_reset) {
#endif
#ifdef CONFIG_M5272
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
return 0;
}
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(SIM_SYPCR, 0xc0);
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-.long _start - TEXT_BASE
+#if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long _start - CONFIG_SYS_TEXT_BASE
#else
.long _START
#endif
#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
- #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ #if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
#endif
#endif
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
-#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = lib$(CPU).o
START =
COBJS = cpu.o speed.o cpu_init.o interrupts.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = lib$(CPU).o
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
rte;
#if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00030000 /* image length */
- .long TEXT_BASE /* image to be relocated at */
+ .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.w #0x2700,%sr /* Mask off Interrupt */
jsr asm_dspi_rd_status
/* jump to memory and execute */
- move.l #(TEXT_BASE + 0x400), %a0
+ move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
jmp (%a0)
asm_dspi_wr_status:
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = lib$(CPU).o
START =
COBJS = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
#include <asm/immap.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_NEEDS_MANUAL_RELOC
+
#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_SYS_BOOT_GET_CMDLINE
+#define CONFIG_SYS_BOOT_GET_KBD
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y +=
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
static char *failed = "*** failed ***\n";
-#ifdef CONFIG_PCU_E
-extern flash_info_t flash_info[];
-#endif
-
#include <environment.h>
extern ulong __init_end;
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
#ifdef CONFIG_SYS_INIT_RAM_ADDR
bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR; /* start of SRAM memory */
- bd->bi_sramsize = CONFIG_SYS_INIT_RAM_END; /* size of SRAM memory */
+ bd->bi_sramsize = CONFIG_SYS_INIT_RAM_SIZE; /* size of SRAM memory */
#endif
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- cmd_tbl_t *cmdtp;
char *s;
bd_t *bd;
extern void malloc_bin_reloc (void);
monitor_flash_len = (ulong)&__init_end - dest_addr;
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS = irq.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
.text
mts rmsr, r0 /* disable cache */
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
+
+ /* Find-out if u-boot is running on BIG/LITTLE endian platform
+ * There are some steps which is necessary to keep in mind:
+ * 1. Setup offset value to r6
+ * 2. Store word offset value to address 0x0
+ * 3. Load just byte from address 0x0
+ * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
+ * value that's why is on address 0x0
+ * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
+ */
+ addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
+ swi r6, r0, 0
+ lbui r10, r0, 0
+ swi r6, r0, 0x40
+ swi r10, r0, 0x50
+
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
swi r6, r0, 0x0 /* reset address */
shi r7, r0, 0x2
shi r6, r0, 0x6
/*
- * Copy U-Boot code to TEXT_BASE
+ * Copy U-Boot code to CONFIG_SYS_TEXT_BASE
* solve problem with sbrk_base
*/
-#if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE)
+#if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE)
addi r4, r0, __end
addi r5, r0, __text_start
rsub r4, r5, r4 /* size = __end - __text_start */
/* user_vector_exception */
addik r6, r0, _exception_handler
sw r6, r1, r0
- lhu r7, r1, r0
- shi r7, r0, 0xa
- shi r6, r0, 0xe
+ /*
+ * BIG ENDIAN memory map for user exception
+ * 0x8: 0xB000XXXX
+ * 0xC: 0xB808XXXX
+ *
+ * then it is necessary to count address for storing the most significant
+ * 16bits from _exception_handler address and copy it to
+ * 0xa address. Big endian use offset in r10=0 that's why is it just
+ * 0xa address. The same is done for the least significant 16 bits
+ * for 0xe address.
+ *
+ * LITTLE ENDIAN memory map for user exception
+ * 0x8: 0xXXXX00B0
+ * 0xC: 0xXXXX08B8
+ *
+ * Offset is for little endian setup to 0x2. rsubi instruction decrease
+ * address value to ensure that points to proper place which is
+ * 0x8 for the most significant 16 bits and
+ * 0xC for the least significant 16 bits
+ */
+ lhu r7, r1, r10
+ rsubi r8, r10, 0xa
+ sh r7, r0, r8
+ rsubi r8, r10, 0xe
+ sh r6, r0, r8
#endif
#ifdef CONFIG_SYS_INTC_0
/* interrupt_handler */
addik r6, r0, _interrupt_handler
sw r6, r1, r0
- lhu r7, r1, r0
- shi r7, r0, 0x12
- shi r6, r0, 0x16
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x12
+ sh r7, r0, r8
+ rsubi r8, r10, 0x16
+ sh r6, r0, r8
#endif
/* hardware exception */
addik r6, r0, _hw_exception_handler
sw r6, r1, r0
- lhu r7, r1, r0
- shi r7, r0, 0x22
- shi r6, r0, 0x26
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x22
+ sh r7, r0, r8
+ rsubi r8, r10, 0x26
+ sh r6, r0, r8
/* enable instruction and data cache */
mfs r12, rmsr
#endif /* __GNUC__ */
+#ifdef __MICROBLAZEEL__
+#include <linux/byteorder/little_endian.h>
+#else
#include <linux/byteorder/big_endian.h>
+#endif
#endif /* __MICROBLAZE_BYTEORDER_H__ */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-/* Relocation to SDRAM works on all Microblaze boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y +=
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <version.h>
#include <watchdog.h>
#include <stdio_dev.h>
+#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_INTC_0
extern int interrupts_init (void);
#endif
+
#if defined(CONFIG_CMD_NET)
extern int eth_init (bd_t * bis);
#endif
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
- memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+ memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
bd = gd->bd;
puts ("SDRAM :\n");
printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
- printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE);
+ printf ("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
#if defined(CONFIG_CMD_FLASH)
puts ("FLASH: ");
#if defined(CONFIG_CMD_NET)
/* IP Address */
- bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
- eth_init (bd);
+ bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+ printf("Net: ");
+ eth_initialize(gd->bd);
+
+ uchar enetaddr[6];
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ printf("MAC: %pM\n", enetaddr);
#endif
/* main_loop */
char *of_flat_tree = NULL;
#if defined(CONFIG_OF_LIBFDT)
- ulong of_size = 0;
-
- /* find flattened device tree */
- ret = boot_get_fdt (flag, argc, argv, images, &of_flat_tree, &of_size);
- if (ret)
- return 1;
+ /* did generic code already find a device tree? */
+ if (images->ft_len)
+ of_flat_tree = images->ft_addr;
#endif
theKernel = (void (*)(char *, ulong, ulong))images->ep;
show_boot_progress (15);
- if (!(ulong) of_flat_tree)
- of_flat_tree = (char *)simple_strtoul (argv[3], NULL, 16);
-
+ if (!of_flat_tree && argc > 3)
+ of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
#ifdef DEBUG
printf ("## Transferring control to Linux (at address 0x%08lx) " \
"ramdisk 0x%08lx, FDT 0x%08lx...\n",
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS-y = cache.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_NEEDS_MANUAL_RELOC
+
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y +=
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
void board_init_r (gd_t *id, ulong dest_addr)
{
- cmd_tbl_t *cmdtp;
#ifndef CONFIG_SYS_NO_FLASH
ulong size;
#endif
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS = exceptions.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS +=
return (0);
}
-int do_reset(void)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
/* indirect call to go beyond 256MB limitation of toolchain */
* MA 02111-1307 USA
*/
-
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include <version.h>
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-/* Relocation to SDRAM works on all NIOS2 boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y += cache.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
- memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE );
+ memset( gd, 0, GENERATED_GBL_DATA_SIZE );
gd->bd = (bd_t *)(gd+1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
ulong initrd_end = images->rd_end;
char *of_flat_tree = NULL;
#if defined(CONFIG_OF_LIBFDT)
- ulong of_size = 0;
-
- /* find flattened device tree */
- if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size))
- return 1;
+ /* did generic code already find a device tree? */
+ if (images->ft_len)
+ of_flat_tree = images->ft_addr;
#endif
if (!of_flat_tree && argc > 3)
of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
#
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
STANDALONE_LOAD_ADDR = 0x40000
-PLATFORM_RELFLAGS += -mrelocatable
+PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections
PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
-PLATFORM_LDFLAGS += -n
+PLATFORM_LDFLAGS += -n --gc-sections
+
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_SPL
+LDSCRIPT := $(SRCTREE)/$(CONFIG_BOARDDIR)/u-boot-nand.lds
+else
+ifneq ($(wildcard $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds),)
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds
+endif
+endif
#
# When cross-compiling on NetBSD, we have to define __PPC__ or else we
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS = cache.o kgdb.o io.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
-void
-do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
/* flush and disable I/D cache */
addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
soft_restart(addr);
- while(1); /* not reached */
+
+ /* not reached */
+ while(1)
+ ;
+
+ return 1;
}
#endif
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
*/
+#include <asm-offsets.h>
#include <config.h>
#include <74xx_7xx.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#if !defined(CONFIG_DB64360) && \
!defined(CONFIG_DB64460) && \
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
- sync
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
- sync
/* the boot code is located below the exception table */
. = 0x2000
boot_cold:
-boot_warm:
/* disable everything */
li r0, 0
mtspr HID0, r0
bl cpu_init_f
sync
- mr r3, r21
-
- /* r3: BOOTFLAG */
/* run 1st part of board init code (from Flash) */
bl board_init_f
sync
- /* NOTREACHED */
+ /* NOTREACHED - board_init_f() does not return */
.globl invalidate_bats
invalidate_bats:
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
/* clear_bss: */
/*
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ * (C) Copyright 2010 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-/*
- * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
- */
-
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
+ arch/powerpc/cpu/74xx_7xx/start.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS-y := cpu.o
COBJS-y += serial.o
COBJS-y += speed.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
-COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
COBJS-$(CONFIG_CMD_IDE) += ide.o
COBJS-$(CONFIG_IIM) += iim.o
COBJS-$(CONFIG_PCI) += pci.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
-# (C) Copyright 2007-2009 DENX Software Engineering
+# (C) Copyright 2007-2010 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+
PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -msoft-float -mcpu=603e
-
-# Use default linker script.
-# A board port can override this setting in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc512x/u-boot.lds
#include <command.h>
#include <asm/io.h>
-#include "../../../../board/freescale/common/fsl_diu_fb.h"
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-#include <stdio_dev.h>
-#include <video_fb.h>
-#endif
+#include <fsl_diu_fb.h>
DECLARE_GLOBAL_DATA_PTR;
-static int xres, yres;
-
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
}
-int mpc5121_diu_init(void)
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
{
unsigned int pixel_format;
#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
- xres = CONFIG_VIDEO_XRES;
- yres = CONFIG_VIDEO_YRES;
+ *xres = CONFIG_VIDEO_XRES;
+ *yres = CONFIG_VIDEO_YRES;
#else
- xres = 1024;
- yres = 768;
+ *xres = 1024;
+ *yres = 768;
#endif
pixel_format = 0x88883316;
debug("mpc5121_diu_init\n");
- return fsl_diu_init(xres, pixel_format, 0);
+ return fsl_diu_init(*xres, pixel_format, 0);
}
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-void *video_hw_init(void)
-{
- GraphicDevice *pGD = (GraphicDevice *) &ctfb;
- struct fb_info *info;
-
- if (mpc5121_diu_init() < 0)
- return NULL;
-
- /* fill in Graphic device struct */
- sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz",
- xres, yres, 32, 64, 60);
-
- pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
- pGD->winSizeX = xres;
- pGD->winSizeY = yres;
- pGD->plnSizeX = pGD->winSizeX;
- pGD->plnSizeY = pGD->winSizeY;
-
- pGD->gdfBytesPP = 4;
- pGD->gdfIndex = GDF_32BIT_X888RGB;
-
- pGD->isaBase = 0;
- pGD->pciBase = 0;
- pGD->memSize = info->screen_size;
-
- /* Cursor Start Address */
- pGD->dprBase = 0;
- pGD->vprBase = 0;
- pGD->cprBase = 0;
-
- return (void *)pGD;
-}
-
-#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
* U-Boot - Startup Code for MPC512x based Embedded Boards
*/
+#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include <version.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING "MPC512X"
.globl _start
/* Start from here after reset/power on */
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
.globl _start_of_vectors
/* run low-level CPU init code (in Flash) */
bl cpu_init_f
- /* r3: BOOTFLAG */
- mr r3, r21
/* run 1st part of board init code (in Flash) */
bl board_init_f
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
/*
- * (C) Copyright 2007 DENX Software Engineering.
+ * (C) Copyright 2007-2010 DENX Software Engineering.
*
* See file CREDITS for list of people who contributed to this
* project.
OUTPUT_ARCH(powerpc)
SECTIONS
{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc512x/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc512x/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
*(.fixup)
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-#
-# File: config.mk
-#
-# Discription: compiler flags and make definitions
-#
-
-
PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xx/u-boot.lds
*
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc5xx.h>
#include <timestamp.h>
#include <linux/config.h>
#include <asm/processor.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
li r4, CONFIG_SYS_ISB /* Set ISB bit */
or r3, r3, r4
mtspr 638, r3
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x20
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
-boot_warm:
/* Initialize machine status; enable machine check interrupt */
/*----------------------------------------------------------------------*/
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (from Flash) */
+ /* NOTREACHED - board_init_f() does not return */
+
.globl _start_of_vectors
_start_of_vectors:
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
/*
- * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+ * (C) Copyright 2001-2010 Wolfgang Denk, DENX Software Engineering, wd@denx.de
* (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc5xx/start.o (.text)
+ arch/powerpc/cpu/mpc5xx/start.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
-/* . = env_start;
- .ppcenv :
- {
- common/env_embedded.o (.ppcenv)
- }
-*/
+ . = env_start;
+ .ppcenv :
+ {
+ common/env_embedded.o (.ppcenv)
+ }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
-
-START = start.o
-SOBJS = io.o firmware_sc_task_bestcomm.impl.o
-COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
- loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
-
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START := $(addprefix $(obj),$(START))
+LIB = $(obj)lib$(CPU).o
+
+SSTART = start.o
+CSTART = traps.o
+SOBJS += io.o
+SOBJS += firmware_sc_task_bestcomm.impl.o
+COBJS-y += i2c.o
+COBJS-y += cpu.o
+COBJS-y += cpu_init.o
+COBJS-y += ide.o
+COBJS-y += interrupts.o
+COBJS-y += loadtask.o
+COBJS-y += pci_mpc5200.o
+COBJS-y += serial.o
+COBJS-y += speed.o
+COBJS-$(CONFIG_CMD_USB) += usb_ohci.o
+COBJS-$(CONFIG_CMD_USB) += usb.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+START := $(addprefix $(obj),$(SSTART) $(CSTART))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot.lds
#include <mpc5xxx.h>
#include <i2c.h>
+#if !defined(CONFIG_I2C_MULTI_BUS)
#if (CONFIG_SYS_I2C_MODULE == 2)
#define I2C_BASE MPC5XXX_I2C2
#elif (CONFIG_SYS_I2C_MODULE == 1)
#else
#error CONFIG_SYS_I2C_MODULE is not properly configured
#endif
+#else
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
+ CONFIG_SYS_SPD_BUS_NUM;
+static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED,
+ CONFIG_SYS_I2C_SPEED};
+
+static const unsigned long i2c_dev[2] = {
+ MPC5XXX_I2C1,
+ MPC5XXX_I2C2,
+};
+
+#define I2C_BASE ((struct mpc5xxx_i2c *)i2c_dev[i2c_bus_num])
+#endif
#define I2C_TIMEOUT 6667
#define I2C_RETRIES 3
return ret;
}
+#if defined(CONFIG_I2C_MULTI_BUS)
+int i2c_set_bus_num(unsigned int bus)
+{
+ if (bus > 1)
+ return -1;
+
+ i2c_bus_num = bus;
+ i2c_init(i2c_bus_speed[bus], CONFIG_SYS_I2C_SLAVE);
+ return 0;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+ i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
+ return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return i2c_bus_num;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return i2c_bus_speed[i2c_bus_num];
+}
+#endif
+
+
#endif /* CONFIG_HARD_I2C */
/*
* U-Boot - Startup Code for MPC5xxx CPUs
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc5xxx.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On */
- nop
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
-boot_warm:
mfmsr r5 /* save msr contents */
/* Move CSBoot and adjust instruction pointer */
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (in Flash)*/
+ /* NOTREACHED - board_init_f() does not return */
+
/*
* Vector Table
*/
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc5xxx/start.o (.text)
- arch/powerpc/cpu/mpc5xxx/traps.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text*)
+ arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ common/env_embedded.o (.ppcenv*)
- *(.text)
- *(.got1)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
/*
- * (C) Copyright 2003-2007
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc5xxx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text*)
+ arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
*(COMMON)
+ *(.bss*)
+ *(.sbss*)
. = ALIGN(4);
}
_end = . ;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS = io.o fec_dma_tasks.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc8220/u-boot.lds
/*
* U-Boot - Startup Code for MPC8220 CPUs
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc8220.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On */
- nop
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
-boot_warm:
mfmsr r5 /* save msr contents */
/* replace default MBAR base address from 0x80000000
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (in Flash)*/
+ /* NOTREACHED - board_init_f() does not return */
+
/*
* Vector Table
*/
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
/*
- * (C) Copyright 2003-2004
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8220/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8220/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)drivers/i2c)
endif
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
$(obj)bedbug_603e.c:
ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc824x/u-boot.lds
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc824x.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
-boot_warm:
-
/* Initialize machine status; enable machine check interrupt */
/*----------------------------------------------------------------------*/
li r3, MSR_KERNEL /* Set FP, ME, RI flags */
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (from Flash) */
+ /* NOTREACHED - board_init_f() does not return */
+
.globl _start_of_vectors
_start_of_vectors:
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
/*
- * (C) Copyright 2001-2007
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc824x/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc824x/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o kgdb.o
COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o
+ $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \
-mstring -mcpu=603e -mmultiple
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc8260/u-boot.lds
/*
* U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc8260.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
- nop
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
lis r3, CONFIG_SYS_DEFAULT_IMMR@h
nop
stw r4, 0(r3)
nop
#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-boot_warm:
+
mfmsr r5 /* save msr contents */
#if defined(CONFIG_COGENT)
bl init_debug /* set up debugging stuff */
#endif
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (in Flash)*/
+ /* NOTREACHED - board_init_f() does not return */
+
/*
* Vector Table
*/
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
/*
- * (C) Copyright 2001-2007
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8260/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8260/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \
-ffixed-r2 -msoft-float
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc83xx/u-boot.lds
#ifdef CONFIG_USB_EHCI_FSL
#ifndef CONFIG_MPC834x
uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
out_le32(&out_win->tarl, 0);
out_le32(&out_win->tarh, 0);
- for (i = 0; i < 2; i++, reg++) {
+ for (i = 0; i < 2; i++) {
u32 ar;
- if (reg->size == 0)
+ if (reg[i].size == 0)
break;
out_win = &pex->bridge.pex_outbound_win[i + 1];
- out_le32(&out_win->bar, reg->phys_start);
- out_le32(&out_win->tarl, reg->bus_start);
+ out_le32(&out_win->bar, reg[i].phys_start);
+ out_le32(&out_win->tarl, reg[i].bus_start);
out_le32(&out_win->tarh, 0);
- ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
- if (reg->flags & PCI_REGION_IO)
+ ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
+ if (reg[i].flags & PCI_REGION_IO)
ar |= PEX_OWAR_TYPE_IO;
else
ar |= PEX_OWAR_TYPE_MEM;
* U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING "MPC83XX"
.globl _start
_start: /* time t 0 */
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
- nop
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-
-boot_cold: /* time t 3 */
lis r4, CONFIG_DEFAULT_IMMR@h
nop
-boot_warm: /* time t 5 */
+
mfmsr r5 /* save msr contents */
/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
/* run low-level CPU init code (in Flash)*/
bl cpu_init_f
- /* r3: BOOTFLAG */
- mr r3, r21
/* run 1st part of board init code (in Flash)*/
bl board_init_f
+ /* NOTREACHED - board_init_f() does not return */
+
#ifndef CONFIG_NAND_SPL
/*
* Vector Table
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
#endif
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
bne 1b
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
+ /* Wait for HW to catch up */
+ lwz r4, LBLAWAR1(r3)
+ twi 0,r4,0
+ isync
blr
/* Though all the LBIU Local Access Windows and LBC Banks will be
xor r4, r4, r4
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
+ /* Wait for HW to catch up */
+ lwz r4, LBLAWAR1(r3)
+ twi 0,r4,0
+ isync
blr
#endif /* CONFIG_SYS_FLASHBOOT */
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc83xx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc83xx/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o resetvec.o
SOBJS-$(CONFIG_MP) += release.o
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes)
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc85xx/u-boot.lds
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <post.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
print_laws();
print_lbc_regs();
}
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+
+/* Board-specific functions defined in each board's ddr.c */
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num);
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+ phys_addr_t *rpn);
+unsigned int
+ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
+static void dump_spd_ddr_reg(void)
+{
+ int i, j, k, m;
+ u8 *p_8;
+ u32 *p_32;
+ ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ generic_spd_eeprom_t
+ spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ fsl_ddr_get_spd(spd[i], i);
+
+ puts("SPD data of all dimms (zero vaule is omitted)...\n");
+ puts("Byte (hex) ");
+ k = 1;
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
+ printf("Dimm%d ", k++);
+ }
+ puts("\n");
+ for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
+ m = 0;
+ printf("%3d (0x%02x) ", k, k);
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ p_8 = (u8 *) &spd[i][j];
+ if (p_8[k]) {
+ printf("0x%02x ", p_8[k]);
+ m++;
+ } else
+ puts(" ");
+ }
+ }
+ if (m)
+ puts("\n");
+ else
+ puts("\r");
+ }
+
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ switch (i) {
+ case 0:
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ break;
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+ case 1:
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected controller number = %u\n",
+ __func__, i);
+ return;
+ }
+ }
+ printf("DDR registers dump for all controllers "
+ "(zero vaule is omitted)...\n");
+ puts("Offset (hex) ");
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
+ puts("\n");
+ for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+ m = 0;
+ printf("%6d (0x%04x)", k * 4, k * 4);
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ p_32 = (u32 *) ddr[i];
+ if (p_32[k]) {
+ printf(" 0x%08x", p_32[k]);
+ m++;
+ } else
+ puts(" ");
+ }
+ if (m)
+ puts("\n");
+ else
+ puts("\r");
+ }
+ puts("\n");
+}
+
+/* invalid the TLBs for DDR and setup new ones to cover p_addr */
+static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
+{
+ u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned long epn;
+ u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
+ int ddr_esel;
+
+ ptr = vstart;
+
+ while (ptr < (vstart + size)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
+
+ /* Setup new tlb to cover the physical address */
+ setup_ddr_tlbs_phys(p_addr, size>>20);
+
+ ptr = vstart;
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
+ } else {
+ printf("TLB error in function %s\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * slide the testing window up to test another area
+ * for 32_bit system, the maximum testable memory is limited to
+ * CONFIG_MAX_MEM_MAPPED
+ */
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ phys_addr_t test_cap, p_addr;
+ phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+
+#if !defined(CONFIG_PHYS_64BIT) || \
+ !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ test_cap = p_size;
+#else
+ test_cap = gd->ram_size;
+#endif
+ p_addr = (*vstart) + (*size) + (*phys_offset);
+ if (p_addr < test_cap - 1) {
+ p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
+ if (reset_tlb(p_addr, p_size, phys_offset) == -1)
+ return -1;
+ *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *size = (u32) p_size;
+ printf("Testing 0x%08llx - 0x%08llx\n",
+ (u64)(*vstart) + (*phys_offset),
+ (u64)(*vstart) + (*phys_offset) + (*size) - 1);
+ } else
+ return 1;
+
+ return 0;
+}
+
+/* initialization for testing area */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+
+ *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
+ *phys_offset = 0;
+
+#if !defined(CONFIG_PHYS_64BIT) || \
+ !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ puts("Cannot test more than ");
+ print_size(CONFIG_MAX_MEM_MAPPED,
+ " without proper 36BIT support.\n");
+ }
+#endif
+ printf("Testing 0x%08llx - 0x%08llx\n",
+ (u64)(*vstart) + (*phys_offset),
+ (u64)(*vstart) + (*phys_offset) + (*size) - 1);
+
+ return 0;
+}
+
+/* invalid TLBs for DDR and remap as normal after testing */
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ unsigned long epn;
+ u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
+ int ddr_esel;
+
+ /* disable the TLBs for this testing */
+ ptr = *vstart;
+
+ while (ptr < (*vstart) + (*size)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
+
+ puts("Remap DDR ");
+ setup_ddr_tlbs(gd->ram_size>>20);
+ puts("\n");
+
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ dump_spd_ddr_reg();
+}
+#endif
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
l2srbar = l2cache->l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
ulong spin_tbl_addr = get_spin_phys_addr();
u32 bootpg = determine_mp_bootpg();
u32 id = get_my_id();
+ const char *enable_method;
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
fdt_setprop_string(blob, off, "status",
"disabled");
}
+
+ if (hold_cores_in_reset(0)) {
+#ifdef CONFIG_FSL_CORENET
+ /* Cores held in reset, use BRR to release */
+ enable_method = "fsl,brr-holdoff";
+#else
+ /* Cores held in reset, use EEBPCR to release */
+ enable_method = "fsl,eebpcr-holdoff";
+#endif
+ } else {
+ /* Cores out of reset and in a spin-loop */
+ enable_method = "spin-table";
+
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ }
+
fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
+ enable_method);
} else {
printf ("cpu NULL\n");
}
return mfspr(SPRN_PIR);
}
+/*
+ * Determine if U-Boot should keep secondary cores in reset, or let them out
+ * of reset and hold them in a spinloop
+ */
+int hold_cores_in_reset(int verbose)
+{
+ const char *s = getenv("mp_holdoff");
+
+ /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
+ if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
+ if (verbose) {
+ puts("Secondary cores are being held in reset.\n");
+ puts("See 'mp_holdoff' environment variable\n");
+ }
+
+ return 1;
+ }
+
+ return 0;
+}
+
int cpu_reset(int nr)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
{
u32 *table, id = get_my_id();
+ if (hold_cores_in_reset(1))
+ return 0;
+
if (nr == id) {
table = (u32 *)get_spin_virt_addr();
printf("table base @ 0x%p\n", table);
u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
+ if (hold_cores_in_reset(1))
+ return 0;
+
if (nr == get_my_id()) {
printf("Invalid to release the boot core.\n\n");
return 1;
ulong fixup = (ulong)&__secondary_start_page;
u32 bootpg = determine_mp_bootpg();
+ /* Some OSes expect secondary cores to be held in reset */
+ if (hold_cores_in_reset(0))
+ return;
+
/* Store the bootpg's SDRAM address for use by secondary CPU cores */
__bootpg_addr = bootpg;
ulong get_spin_phys_addr(void);
ulong get_spin_virt_addr(void);
u32 get_my_id(void);
+int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_ADDR_UPPER 0
#define BOOT_ENTRY_ADDR_LOWER 1
#endif
struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
- SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
- SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
- SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
+ /*
+ * We assume currently that all JR are in the same partition
+ * and as such they need to represent the same LIODN due to
+ * a 4080 rev.2 h/w requirement that DECOs sharing from themselves
+ * or from another DECO have the two Non-SEQ LIODN values equal
+ */
+ SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */
+ SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */
+ SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */
+ SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <version.h>
*
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <timestamp.h>
beq 2b
/* Setup interrupt vectors */
- lis r1,TEXT_BASE@h
+ lis r1,CONFIG_SYS_MONITOR_BASE@h
mtspr IVPR,r1
li r1,0x0100
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
- lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
+ lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#else
/*
- * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
- * image has been relocated to TEXT_BASE on the second stage.
+ * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
+ * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
*/
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
- lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+ lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
- lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#endif
mtspr MAS0,r6
bl board_init_f
isync
+ /* NOTREACHED - board_init_f() does not return */
+
#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
}
#endif
-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+unsigned int
+setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
tlb_size = (camsize - 10) / 2;
- set_tlb(1, ram_tlb_address, ram_tlb_address,
+ set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
+ p_addr += 1UL << camsize;
}
if (memsize)
print_size(memsize, " left unmapped\n");
-
- /*
- * Confirm that the requested amount of memory was mapped.
- */
return memsize_in_meg;
}
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ return
+ setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
#endif /* !CONFIG_NAND_SPL */
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- *(.text)
- *(.got1)
+ *(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
.bootpg ADDR(.text) - 0x1000 :
{
- arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
+ arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg))
} :text = 0xffff
. = ADDR(.text) + 0x80000;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
} :bss
{
. = 0xfff00000;
.text : {
- *(.text)
+ *(.text*)
}
_etext = .;
.reloc : {
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
__init_end = .;
.resetvec ADDR(.text) + 0xffc : {
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
__bss_start = .;
.bss : {
- *(.sbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
}
_end = .;
}
#endif
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
PHDRS
{
text PT_LOAD;
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- *(.text)
- *(.got1)
+ *(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
.resetvec RESET_VECTOR_ADDRESS :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} :text = 0xffff
. = RESET_VECTOR_ADDRESS + 0x4;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
} :bss
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
-START = start.o
+SSTART = start.o
+CSTART = traps.o
SOBJS-y += cache.o
SOBJS-$(CONFIG_MP) += release.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-y += speed.o
-COBJS-y += traps.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START := $(addprefix $(obj),$(START))
+START := $(addprefix $(obj),$(SSTART) $(CSTART))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(ASOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
}
-void
-do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
while (1)
;
+
+ return 1;
}
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc86xx.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
- sync
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
- sync
/* the boot code is located below the exception table */
. = 0x2000
boot_cold:
-boot_warm:
/*
* NOTE: Only Cpu 0 will ever come here. Other cores go to an
* address specified by the BPTR
#endif
/* bl l2cache_enable */
- mr r3, r21
- /* r3: BOOTFLAG */
/* run 1st part of board init code (from Flash) */
bl board_init_f
sync
- /* NOTREACHED */
+ /* NOTREACHED - board_init_f() does not return */
.globl invalidate_bats
invalidate_bats:
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
/* clear_bss: */
/*
stw r5, 0(r4) /* Store physical value of CCSR */
isync
- lis r5, TEXT_BASE@h
- ori r5,r5,TEXT_BASE@l
+ lis r5, CONFIG_SYS_TEXT_BASE@h
+ ori r5,r5,CONFIG_SYS_TEXT_BASE@l
lwz r5, 0(r5)
isync
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
{
/* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc86xx/start.o (.text*)
+ arch/powerpc/cpu/mpc86xx/traps.o (.text*)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
# CFLAGS += -DET_DEBUG
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
-START-y += start.o
-START-y += kgdb.o
+SSTART-y += start.o
+CSTART-y += traps.o
COBJS-y += bedbug_860.o
COBJS-y += commproc.o
COBJS-y += cpu.o
COBJS-y += serial.o
COBJS-y += speed.o
COBJS-y += spi.o
-COBJS-y += traps.o
COBJS-y += upatch.o
COBJS-y += video.o
+SOBJS-y += kgdb.o
SOBJS-y += plprcr_write.o
-SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+SRCS := $(SSTART-y:.o=.S) $(CSTART-y:.o=.c) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START := $(addprefix $(obj),$(START-y))
+START := $(addprefix $(obj),$(SSTART-y) $(CSTART-y))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MHPC) || \
- defined(CONFIG_PCU_E) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_RPXCLASSIC) || \
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
+#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
#include <timestamp.h>
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/u-boot.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
_start:
lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
mtspr 638, r3
- li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
- b boot_cold
-
- . = EXC_OFF_SYS_RESET + 0x10
-
- .globl _start_warm
-_start_warm:
- li r21, BOOTFLAG_WARM /* Software reboot */
- b boot_warm
-
-boot_cold:
-boot_warm:
/* Initialize machine status; enable machine check interrupt */
/*----------------------------------------------------------------------*/
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
- mr r3, r21
- /* r3: BOOTFLAG */
bl board_init_f /* run 1st part of board init code (from Flash) */
+ /* NOTREACHED - board_init_f() does not return */
+
.globl _start_of_vectors
_start_of_vectors:
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib8xxx.a
+LIB = $(obj)lib8xxx.o
ifneq ($(CPU),mpc83xx)
COBJS-y += cpu.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
include $(SRCTREE)/rules.mk
include $(TOPDIR)/config.mk
-LIB = $(obj)libddr.a
+LIB = $(obj)libddr.o
COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
lc_common_dimm_params.o
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
include $(SRCTREE)/rules.mk
unsigned int sr_it;
unsigned int zq_en;
unsigned int wrlvl_en;
+ int cs_en = 1;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
* and each controller uses rank interleaving within
* itself. Therefore the starting and ending address
* on each controller is twice the amount present on
- * each controller.
+ * each controller. If any CS is not included in the
+ * interleaving, the memory on that CS is not accssible
+ * and the total memory size is reduced. The CS is also
+ * disabled.
*/
unsigned long long ctlr_density = 0;
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
ctlr_density = dimm_params[0].rank_density * 2;
+ if (i > 1)
+ cs_en = 0;
break;
case FSL_DDR_CS2_CS3:
ctlr_density = dimm_params[0].rank_density;
+ if (i > 0)
+ cs_en = 0;
break;
case FSL_DDR_CS0_CS1_CS2_CS3:
/*
);
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
- set_csn_config(dimm_number, i, ddr, popts, dimm_params);
- set_csn_config_2(i, ddr);
+ if (cs_en) {
+ set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+ set_csn_config_2(i, ddr);
+ } else
+ printf("CS%d is disabled.\n", i);
}
set_ddr_eor(ddr, popts);
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/mp.h>
+#include <asm/fsl_enet.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
fdt_del_node_and_alias(blob, "crypto");
}
#endif
+
+int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
+{
+ static const char *fsl_phy_enet_if_str[] = {
+ [MII] = "mii",
+ [RMII] = "rmii",
+ [GMII] = "gmii",
+ [RGMII] = "rgmii",
+ [RGMII_ID] = "rgmii-id",
+ [RGMII_RXID] = "rgmii-rxid",
+ [SGMII] = "sgmii",
+ [TBI] = "tbi",
+ [RTBI] = "rtbi",
+ [XAUI] = "xgmii",
+ [FSL_ETH_IF_NONE] = "",
+ };
+
+ if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str))
+ return fdt_setprop_string(blob, offset, "phy-connection-type", "");
+
+ return fdt_setprop_string(blob, offset, "phy-connection-type",
+ fsl_phy_enet_if_str[phyc]);
+}
{
[LAW_TRGT_IF_PCIE_1] = {
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
- (1 << 7) | (1 << 0xe) | (1 << 0xf),
+ (1 << 7) | (1 << 0xf),
+ },
+ [LAW_TRGT_IF_PCIE_2] = {
+ .cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf),
},
};
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
#include "ecc.h"
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
static void DQS_calibration_process(void);
#endif
#endif
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
static unsigned char spd_read(uchar chip, uint addr)
{
PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
#endif /* defined(DEBUG) */
}
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
#include "ecc.h"
-#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-
/*
* Only compile the DDR auto-calibration code for NOR boot and
* not for NAND boot (NAND SPL and NAND U-Boot - NUB)
return 0;
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
-#endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START := resetvec.o
START += start.o
COBJS := 40x_spd_sdram.o
+ifndef CONFIG_NAND_SPL
+ifndef CONFIG_NAND_U_BOOT
COBJS += 44x_spd_ddr.o
-COBJS += 44x_spd_ddr2.o
-ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
-COBJS += 4xx_ibm_ddr2_autocalib.o
endif
+endif
+COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
+COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o
-ifdef CONFIG_CMD_CHIP_CONFIG
-COBJS += cmd_chip_config.o
-endif
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += cmd_chip_config.o
COBJS += cpu.o
COBJS += cpu_init.o
COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
-ifdef CONFIG_CMD_ECCTEST
-COBJS += cmd_ecctest.o
-endif
+COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
COBJS += fdt.o
COBJS += interrupts.o
COBJS += iop480_uart.o
-ifdef CONFIG_CMD_REGINFO
-COBJS += reginfo.o
-endif
+COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o
COBJS += sdram.o
COBJS += speed.o
COBJS += tlb.o
COBJS += usb.o
COBJS += usb_ohci.o
COBJS += usbdev.o
+COBJS-$(CONFIG_XILINX_440) += xilinx_irq.o
ifndef CONFIG_XILINX_440
COBJS += 4xx_uart.o
COBJS += gpio.o
COBJS += miiphy.o
COBJS += uic.o
-else
-COBJS += xilinx_irq.o
endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
int error;
if (argc < 3) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
error = simple_strtoul(argv[2], NULL, 16);
if ((error < 1) || (error > 2)) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
printf("Using address %p for %d bit ECC error injection\n",
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
else
PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
endif
-
-# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/ppc4xx/u-boot.lds
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
+#if defined(CONFIG_APM821XX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "RESERVED",
+ "RESERVED",
+ "RESERVED",
+ "NAND (8 bits)",
+ "NOR (8 bits)",
+ "NOR (8 bits) w/PLL Bypassed",
+ "I2C (Addr 0x54)",
+ "I2C (Addr 0x52)",
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
+#endif
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
strcpy(addstr, "No Security support");
break;
+ case PVR_APM821XX_RA:
+ puts("APM821XX Rev. A");
+ strcpy(addstr, "Security support");
+ break;
+
case PVR_VIRTEX5:
puts("440x5 VIRTEX5");
break;
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
+ !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
#endif
#if defined(CONFIG_WATCHDOG)
- val = mfspr(tcr);
+ val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
val &= ~0x30000000; /* clear WRC bits */
val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
#endif
- mtspr(tcr, val);
+ mtspr(SPRN_TCR, val);
- val = mfspr(tsr);
+ val = mfspr(SPRN_TSR);
val |= 0x80000000; /* enable watchdog timer */
- mtspr(tsr, val);
+ mtspr(SPRN_TSR, val);
reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
asm volatile("mtpit %0" : : "r" (val));
}
-
-static __inline__ void set_tcr(unsigned long val)
-{
- asm volatile("mttcr %0" : : "r" (val));
-}
-
-
static __inline__ void set_evpr(unsigned long val)
{
asm volatile("mtevpr %0" : : "r" (val));
#elif defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
return 0;
}
+#if defined(CONFIG_APM821XX)
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+ unsigned long plld;
+ unsigned long temp;
+ unsigned long mul;
+ unsigned long cpudv;
+ unsigned long plb2dv;
+ unsigned long ddr2dv;
+
+ /* Calculate Forward divisor A and Feeback divisor */
+ mfcpr(CPR0_PLLD, plld);
+
+ temp = CPR0_PLLD_FWDVA(plld);
+ sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
+
+ temp = CPR0_PLLD_FDV(plld);
+ sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
+
+ /* Calculate OPB clock divisor */
+ mfcpr(CPR0_OPBD, temp);
+ temp = CPR0_OPBD_OPBDV(temp);
+ sysInfo->pllOpbDiv = temp ? temp : 4;
+
+ /* Calculate Peripheral clock divisor */
+ mfcpr(CPR0_PERD, temp);
+ temp = CPR0_PERD_PERDV(temp);
+ sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+ /* Calculate CPU clock divisor */
+ mfcpr(CPR0_CPUD, temp);
+ temp = CPR0_CPUD_CPUDV(temp);
+ cpudv = temp ? temp : 8;
+
+ /* Calculate PLB2 clock divisor */
+ mfcpr(CPR0_PLB2D, temp);
+ temp = CPR0_PLB2D_PLB2DV(temp);
+ plb2dv = temp ? temp : 4;
+
+ /* Calculate DDR2 clock divisor */
+ mfcpr(CPR0_DDR2D, temp);
+ temp = CPR0_DDR2D_DDR2DV(temp);
+ ddr2dv = temp ? temp : 4;
+
+ /* Calculate 'M' based on feedback source */
+ mfcpr(CPR0_PLLC, temp);
+ temp = CPR0_PLLC_SEL(temp);
+ if (temp == 0) {
+ /* PLL internal feedback */
+ mul = sysInfo->pllFbkDiv;
+ } else {
+ /* PLL PerClk feedback */
+ mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
+ * plb2dv * 2 * sysInfo->pllOpbDiv *
+ sysInfo->pllExtBusDiv;
+ }
+
+ /* Now calculate the individual clocks */
+ sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
+ sysInfo->freqProcessor = sysInfo->freqVCOMhz /
+ sysInfo->pllFwdDivA / cpudv;
+ sysInfo->freqPLB = sysInfo->freqVCOMhz /
+ sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
+ sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
+ sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
+ sysInfo->freqDDR = sysInfo->freqVCOMhz /
+ sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
+ sysInfo->freqUART = sysInfo->freqPLB;
+}
+
+#else
/*
* AMCC_TODO: verify this routine against latest EAS, cause stuff changed
* with latest EAS
return;
}
+#endif
#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
*-------------------------------------------------------------------------------
*/
-/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
- *
+/*
+ * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
*
- * The processor starts at 0xfffffffc and the code is executed
- * from flash/rom.
- * in memory, but as long we don't jump around before relocating.
- * board_init lies at a quite high address and when the cpu has
- * jumped there, everything is ok.
- * This works because the cpu gives the FLASH (CS0) the whole
- * address space at startup, and board_init lies as a echo of
- * the flash somewhere up there in the memorymap.
+ * The following description only applies to the NOR flash style booting.
+ * NAND booting is different. For more details about NAND booting on 4xx
+ * take a look at doc/README.nand-boot-ppc440.
*
- * board_init will change CS0 to be positioned at the correct
- * address and (s)dram will be positioned at address 0
+ * The CPU starts at address 0xfffffffc (last word in the address space).
+ * The U-Boot image therefore has to be located in the "upper" area of the
+ * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
+ * the boot chip-select (CS0) is quite big and covers this area. On the
+ * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
+ * reconfigure this CS0 (and other chip-selects as well when configured
+ * this way) in the boot process to the "correct" values matching the
+ * board layout.
*/
+
+#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
#include <timestamp.h>
# endif
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
#endif
/*
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
+ /* NOTREACHED - board_init_f() does not return */
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
* 4xx RAM-booting U-Boot image is started from offset 0
*/
/* Clear Dcache to use as RAM */
addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
- addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
- ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
+ addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_APM821XX)
lis r1, 0x0000
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
mtdcr L2_CACHE_CFG,r1
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
+ defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_APM821XX)
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,ISRAM1_DPC
mtdcr ISRAM1_PMEG,r1
lis r1,0x0004 /* BAS = 4_0004_0000 */
- ori r1,r1,0x0984 /* 64k */
+ ori r1,r1,ISRAM1_SIZE /* ocm size */
mtdcr ISRAM1_SB0CR,r1
#endif
#elif defined(CONFIG_460SX)
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
+ /* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_440 */
GET_GOT /* initialize GOT access */
bl board_init_f /* run first part of init code (from Flash) */
+ /* NOTREACHED - board_init_f() does not return */
#endif /* CONFIG_IOP480 */
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CONFIG_SYS_INIT_RAM_END@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
/*
* Convert the size, in bytes, to the number of cache lines/blocks
lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
- lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
- ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
+ lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
+ ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
mtctr r4
lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
- ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
+ ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
bl cpu_init_f /* run low-level CPU init code (from Flash) */
- /* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
+ /* NOTREACHED - board_init_f() does not return */
+
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
relocate_code:
#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
/*
- * We need to flush the initial global data (gd_t) before the dcache
- * will be invalidated.
+ * We need to flush the initial global data (gd_t) and bd_info
+ * before the dcache will be invalidated.
*/
/* Save registers */
mr r10, r4
mr r11, r5
- /* Flush initial global data range */
- mr r3, r4
- addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
- bl flush_dcache_range
+ /*
+ * Flush complete dcache, this is faster than flushing the
+ * ranges for global_data and bd_info instead.
+ */
+ bl flush_dcache
#if defined(CONFIG_SYS_INIT_DCACHE_CS)
/*
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CONFIG_SYS_INIT_RAM_END@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
add r4, r4, r3
bl invalidate_dcache_range
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
+ cmpwi r0,0
add r0,r0,r11
- stw r10,0(r3)
+ stw r4,0(r3)
+ beq- 5f
stw r0,0(r4)
- bdnz 3b
+5: bdnz 3b
4:
clear_bss:
/*
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
-static __inline__ void set_tsr(unsigned long val)
-{
-#if defined(CONFIG_440)
- asm volatile("mtspr 0x150, %0" : : "r" (val));
-#else
- asm volatile("mttsr %0" : : "r" (val));
-#endif
-}
-
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
/*
* Reset PIT interrupt
*/
- set_tsr(0x08000000);
+ mtspr(SPRN_TSR, 0x08000000);
/*
* Call timer_interrupt routine in interrupts.c
#include "config.h" /* CONFIG_BOARDDIR */
#ifndef RESET_VECTOR_ADDRESS
+#ifdef CONFIG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
+#else
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#endif
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
PHDRS
{
text PT_LOAD;
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- *(.text)
- *(.got1)
+ *(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
* start.o, since the first shadow TLB only covers 4k
* of address space.
*/
+#ifdef CONFIG_INIT_TLB
+ CONFIG_INIT_TLB (.bootpg)
+#else
CONFIG_BOARDDIR/init.o (.bootpg)
+#endif
} :text = 0xffff
#endif
.resetvec RESET_VECTOR_ADDRESS :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} :text = 0xffff
. = RESET_VECTOR_ADDRESS + 0x4;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
} :bss
--- /dev/null
+/*
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _APM821XX_H_
+#define _APM821XX_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+#define SDR0_SRST0_DMC 0x00200000
+#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
+
+/* AHB config. */
+#define AHB_TOP 0xA4
+#define AHB_BOT 0xA5
+
+/* clk divisors */
+#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
+#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
+#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
+#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
+#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
+#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/
+#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
+#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
+
+/*
+ + * Clocking Controller
+ + */
+#define CPR0_CLKUPD 0x0020
+#define CPR0_PLLC 0x0040
+#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24)
+#define CPR0_PLLD 0x0060
+#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24)
+#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16)
+#define CPR0_CPUD 0x0080
+#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24)
+#define CPR0_PLB2D 0x00a0
+#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
+#define CPR0_OPBD 0x00c0
+#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24)
+#define CPR0_PERD 0x00e0
+#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24)
+#define CPR0_DDR2D 0x0100
+#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
+#define CLK_ICFG 0x0140
+
+#endif /* _APM821XX_H_ */
#define _ASM_CONFIG_H_
#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_SYS_BOOT_GET_CMDLINE
+#define CONFIG_SYS_BOOT_GET_KBD
#ifndef CONFIG_MAX_MEM_MAPPED
#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define CONFIG_SYS_NUM_TLBCAMS 16
#endif
-/* Relocation to SDRAM works on all PPC boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
+
+typedef struct fixed_ddr_parm{
+ int min_freq;
+ int max_freq;
+ fsl_ddr_cfg_regs_t *ddr_settings;
+} fixed_ddr_parm_t;
#endif
--- /dev/null
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_ENET_H
+#define __ASM_PPC_FSL_ENET_H
+
+enum fsl_phy_enet_if {
+ MII,
+ RMII,
+ GMII,
+ RGMII,
+ RGMII_ID,
+ RGMII_RXID,
+ RGMII_TXID,
+ SGMII,
+ TBI,
+ RTBI,
+ XAUI,
+ FSL_ETH_IF_NONE,
+};
+
+int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc);
+
+#endif /* __ASM_PPC_FSL_ENET_H */
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
}
#endif /* __ASSEMBLY__ */
+#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000
+#define CONFIG_SYS_MPC512x_USB_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+
#endif /* __IMMAP_512x__ */
u32 cpcerreaddr; /* error extended address */
u32 cpcerraddr; /* error address */
u32 cpcerrctl; /* error control */
- u32 res9[105]; /* pad out to 4k */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
} cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
#define EBC_NUM_BANKS 6
#endif
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_APM821XX)
#define EBC_NUM_BANKS 3
#endif
/*
* Internal SRAM
*/
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_APM821XX)
#define ISRAM0_DCR_BASE 0x380
#else
#define ISRAM0_DCR_BASE 0x020
#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_APM821XX)
#define ISRAM1_DCR_BASE 0x0B0
#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
#endif /* CONFIG_460EX || CONFIG_460GT */
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
+#elif defined(CONFIG_APM821XX)
+#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
+#endif
+
/*
* L2 Cache
*/
#if defined (CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
#define L2_CACHE_BASE 0x030
#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
*/
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
/*
* Memory controller registers
*/
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#else /* CONFIG_405EX */
+#else /* CONFIG_405EX || CONFIG_APM821XX */
#define SDRAM_MCSTAT 0x14 /* memory controller status */
-#endif /* CONFIG_405EX */
+#endif /* CONFIG_405EX || CONFIG_APM821XX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCES 0x98 /* ECC error status */
#define SDRAM_CID 0xA4 /* core ID */
-#ifndef CONFIG_405EX
+#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
#define SDRAM_RID 0xA8 /* revision ID */
#endif
#define SDRAM_FCSR 0xB0 /* feedback calibration status */
#define SDRAM_RTSR 0xB1 /* run time status tracking */
-#ifdef CONFIG_405EX
+#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
#define SDRAM_RID 0xF8 /* revision ID */
#endif
*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX)
+ defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
#define UIC_MAX 4
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SPE */
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_APM821XX)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#include <asm/ppc460sx.h>
#endif
+#if defined(CONFIG_APM821XX)
+#include <asm/apm821xx.h>
+#endif
+
/*
* Configure which SDRAM/DDR/DDR2 controller is equipped
*/
-// test-only: what to do with these???
#if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
#endif
#define GPT0_DCT0 0x00000110
#define GPT0_DCIS 0x0000011C
-#if 0 // test-only
-/*
- * All PPC4xx share the same NS16550 UART(s). Only base addresses
- * may differ. We define here the integration of the common NS16550
- * driver for all PPC4xx SoC's. The board config header must specify
- * on which UART the console should be located via CONFIG_CONS_INDEX.
- */
-#if 0 /* test-only */
-#define CONFIG_SERIAL_MULTI
-#endif
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#endif
-
#if defined(CONFIG_440)
#include <asm/ppc440.h>
#else
#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */
unsigned long bi_vcofreq; /* VCO Freq, in MHz */
#endif
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
+ unsigned long bi_bootflags; /* boot / reboot flag (Unused) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y += ppccache.o
SOBJS-y += ppcstring.o
SOBJS-y += ticks.o
SOBJS-y += reloc.o
-COBJS-y += bat_rw.o
+COBJS-$(CONFIG_BAT_RW) += bat_rw.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o
echo " Upgrade to a recent toolchain."; \
exit 1; \
fi;
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
static char *failed = "*** failed ***\n";
-#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
+#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
extern flash_info_t flash_info[];
#endif
}
void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
+int __board_flash_wp_on(void)
+{
+ /*
+ * Most flashes can't be detected when write protection is enabled,
+ * so provide a way to let U-Boot gracefully ignore write protected
+ * devices.
+ */
+ return 0;
+}
+int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on")));
static int init_func_ram (void)
{
*/
addr_sp -= sizeof (bd_t);
bd = (bd_t *) addr_sp;
+ memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
#ifdef CONFIG_SYS_SRAM_BASE
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
-#else
- bd->bi_sramstart = 0;
- bd->bi_sramsize = 0;
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
}
#endif
- bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
-
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
+#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
+ /*
+ * Some systems need to relocate the env_addr pointer early because the
+ * location it points to will get invalidated before env_relocate is
+ * called. One example is on systems that might use a L2 or L3 cache
+ * in SRAM mode and initialize that cache from SRAM mode back to being
+ * a cache in cpu_init_r.
+ */
+ gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
+#endif
+
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
#endif
-#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
- * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
- * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
- * bridge there.
+ * Do early PCI configuration _before_ the flash gets initialised,
+ * because PCU ressources are crucial for flash access on some boards.
*/
pci_init ();
#endif
-#if defined(CONFIG_BAB7xx)
+#if defined(CONFIG_WINBOND_83C553)
/*
* Initialise the ISA bridge
*/
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("FLASH: ");
- if ((flash_size = flash_init ()) > 0) {
+ if (board_flash_wp_on()) {
+ printf("Uninitialized - Write Protect On\n");
+ /* Since WP is on, we can't find real size. Set to 0 */
+ flash_size = 0;
+ } else if ((flash_size = flash_init ()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size (flash_size, "");
/*
#endif
-# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
+# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
- bd->bi_flashoffset = TEXT_BASE + flash_size;
+ bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
-# else
- bd->bi_flashoffset = 0;
# endif
-#else /* CONFIG_SYS_NO_FLASH */
-
- bd->bi_flashsize = 0;
- bd->bi_flashstart = 0;
- bd->bi_flashoffset = 0;
#endif /* !CONFIG_SYS_NO_FLASH */
WATCHDOG_RESET ();
if (s && ((*s == 'y') || (*s == 'Y'))) {
bd->bi_iic_fast[0] = 1;
bd->bi_iic_fast[1] = 1;
- } else {
- bd->bi_iic_fast[0] = 0;
- bd->bi_iic_fast[1] = 0;
}
}
-#else
- bd->bi_iic_fast[0] = 0;
- bd->bi_iic_fast[1] = 0;
#endif /* CONFIG_I2CFAST */
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CONFIG_SYS_EXTBDINFO */
WATCHDOG_RESET ();
-#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
+#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern ulong get_effective_memsize(void);
static ulong get_sp (void);
static void set_clocks_in_mhz (bd_t *kbd);
int
kgdb_setjmp(long *buf)
{
- asm ("mflr 0; stw 0,0(%0);"
- "stw 1,4(%0); stw 2,8(%0);"
- "mfcr 0; stw 0,12(%0);"
- "stmw 13,16(%0)"
- : : "r" (buf));
+ unsigned long temp;
+
+ asm volatile("mflr %0; stw %0,0(%1);"
+ "stw %%r1,4(%1); stw %%r2,8(%1);"
+ "mfcr %0; stw %0,12(%1);"
+ "stmw %%r13,16(%1)"
+ : "=&r"(temp) : "r" (buf));
/* XXX should save fp regs as well */
return 0;
}
void
kgdb_longjmp(long *buf, int val)
{
+ unsigned long temp;
+
if (val == 0)
val = 1;
- asm ("lmw 13,16(%0);"
- "lwz 0,12(%0); mtcrf 0x38,0;"
- "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);"
- "mtlr 0; mr 3,%1"
- : : "r" (buf), "r" (val));
+
+ asm volatile("lmw %%r13,16(%1);"
+ "lwz %0,12(%1); mtcrf 0x38,%0;"
+ "lwz %0,0(%1); lwz %%r1,4(%1); lwz %%r2,8(%1);"
+ "mtlr %0; mr %%r3,%2"
+ : "=&r"(temp) : "r" (buf), "r" (val));
}
static inline unsigned long
int init_timebase (void)
{
+ unsigned long temp;
+
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#endif
/* reset */
- asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
+ asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
+ : "=&r"(temp) );
#if defined(CONFIG_5xx) || defined(CONFIG_8xx)
/* enable */
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
+PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
SOBJS = start.o
COBJS = cpu.o interrupts.o watchdog.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.align 2
.global _start
-_start:
+_sh_start:
.long 0x00000010 /* Ppower ON reset PC*/
.long 0x00000000
.long 0x00000010 /* Manual reset PC */
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
- add #(_start-1b), r5
+ add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
+._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
SOBJS = start.o
COBJS = cpu.o interrupts.o watchdog.o cache.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.align 2
.global _start
-_start:
+_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
- add #(_start-1b), r5
+ add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
+._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
SOBJS = start.o
COBJS = cpu.o interrupts.o watchdog.o cache.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007, 2010
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.align 2
.global _start
-_start:
+_sh_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
- add #(_start-1b), r5
+ add #(_sh_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
-._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
+._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-/* Relocation to SDRAM works on all sh boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS-y +=
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <miiphy.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern int cpu_init(void);
extern int board_init(void);
extern int dram_init(void);
static int sh_flash_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_flashsize = flash_init();
printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
static int sh_mem_env_init(void)
{
- mem_malloc_init(TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE -
+ mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
env_relocate();
jumptable_init();
#if defined(CONFIG_CMD_NET)
static int sh_net_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
return 0;
}
void sh_generic_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
bd_t *bd;
init_fnc_t **init_fnc_ptr;
- memset(gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+ memset(gd, 0, GENERATED_GBL_DATA_SIZE);
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
}
#endif
+#define MOUNT_ROOT_RDONLY 0x000
+#define RAMDISK_FLAGS 0x004
+#define ORIG_ROOT_DEV 0x008
+#define LOADER_TYPE 0x00c
+#define INITRD_START 0x010
+#define INITRD_SIZE 0x014
+#define COMMAND_LINE 0x100
+
+#define RD_PROMPT (1<<15)
+#define RD_DOLOAD (1<<14)
+#define CMD_ARG_RD_PROMPT "prompt_ramdisk="
+#define CMD_ARG_RD_DOLOAD "load_ramdisk="
+
+#ifdef CONFIG_SH_SDRAM_OFFSET
+#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
+#else
+#define GET_INITRD_START(initrd, linux) (initrd - linux)
+#endif
+
+static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
+{
+ *(unsigned long *)(param_addr) = data;
+}
+
+static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
+{
+ unsigned long val = 0;
+ char *p = strstr(cmdline, key);
+ if (p) {
+ p += strlen(key);
+ val = simple_strtol(p, NULL, base);
+ }
+ return val;
+}
+
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
/* Linux kernel load address */
unsigned char *param
= (unsigned char *)image_get_load(images->legacy_hdr_os);
/* Linux kernel command line */
- char *cmdline = (char *)param + 0x100;
+ char *cmdline = (char *)param + COMMAND_LINE;
/* PAGE_SIZE */
unsigned long size = images->ep - (unsigned long)param;
char *bootargs = getenv("bootargs");
/* Setup parameters */
memset(param, 0, size); /* Clear zero page */
+
+ /* Set commandline */
strcpy(cmdline, bootargs);
+ sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+ /* Initrd */
+ if (images->rd_start || images->rd_end) {
+ unsigned long ramdisk_flags = 0;
+ int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
+ if (val == 1)
+ ramdisk_flags |= RD_PROMPT;
+ else
+ ramdisk_flags &= ~RD_PROMPT;
+
+ val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+ if (val == 1)
+ ramdisk_flags |= RD_DOLOAD;
+ else
+ ramdisk_flags &= ~RD_DOLOAD;
+
+ set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
+ set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
+ set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
+ set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
+ set_sh_linux_param((unsigned long)param + INITRD_START,
+ GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+ set_sh_linux_param((unsigned long)param + INITRD_SIZE,
+ images->rd_end - images->rd_start);
+ }
+
+ /* Boot kernel */
kernel();
/* does not return */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS =
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(SRCTREE)/rules.mk
$(START): $(START:.o=.S)
- $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
- -I$(TOPDIR)/include -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
+ $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \
+ -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \
+ -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
$(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \
-I$(TOPDIR)/board -c -o $(START) $(START:.o=.S)
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
+ (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
+#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
struct property {
char *name;
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/asmmacro.h>
#include <asm/winmacro.h>
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
- set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
+ set (CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
+LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS =
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(SRCTREE)/rules.mk
$(START): $(START:.o=.S)
- $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
- -I$(TOPDIR)/include -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
+ $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \
+ -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \
+ -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \
$(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \
-I$(TOPDIR)/board -c -o $(START) $(START:.o=.S)
#define PROM_SIZE_MASK (PROM_OFFS-1)
#define __va(x) ( \
(void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \
+ (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
)
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE))
+#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
struct property {
char *name;
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/asmmacro.h>
#include <asm/winmacro.h>
sethi %hi(0x00800000), %o0
lda [%g0] 2, %o1
and %o0, %o1, %o0
- sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o1
- st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)+%o1]
+ sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o1
+ st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)+%o1]
/* call relocate*/
nop
WRITE_PAUSE
mov %l7, %o0 ! irq level
set handler_irq, %o1
- set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2
+ set (CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
add %o1, %o2, %o1
call %o1
add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
* c-code can be called.
*/
#define SAVE_ALL_HEAD \
- sethi %hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l4; \
- jmpl %l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l6;
+ sethi %hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l4; \
+ jmpl %l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l6;
#define SAVE_ALL \
SAVE_ALL_HEAD \
nop;
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
#endif
#include <linux/byteorder/big_endian.h>
#endif /* _SPARC_BYTEORDER_H */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_NEEDS_MANUAL_RELOC
+
#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
--- /dev/null
+#ifndef _ASM_SPARC_UNALIGNED_H
+#define _ASM_SPARC_UNALIGNED_H
+
+/*
+ * The SPARC can not do unaligned accesses, it must be split into multiple
+ * byte accesses. The SPARC is in big endian mode.
+ */
+#include <asm-generic/unaligned.h>
+
+#endif /* _ASM_SPARC_UNALIGNED_H */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).o
SOBJS =
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
printf("CONFIG_SYS_PROM_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
CONFIG_SYS_PROM_SIZE);
printf("CONFIG_SYS_GBL_DATA_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
- CONFIG_SYS_GBL_DATA_SIZE);
+ GENERATED_GBL_DATA_SIZE);
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
puts("AMBA:\n");
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
-#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cfm_flash.o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk
-ifndef TEXT_BASE
-TEXT_BASE = 0xFE000000
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0xFE000000
endif
-TEXT_BASE = 0xFFE00000
+CONFIG_SYS_TEXT_BASE = 0xFFE00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cpux9k2.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-TEXT_BASE = 0x23f00000
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size =
- get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#######################################################################
-#
-# Copyright (C) 2000, 2001, 2002, 2003
-# The LEOX team <team@leox.org>, http://www.leox.org
-#
-# LEOX.org is about the development of free hardware and software resources
-# for system on chip.
-#
-# Description: U-Boot port on the LEOX's ELPT860 CPU board
-# ~~~~~~~~~~~
-#
-#######################################################################
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#######################################################################
-
-#
-# ELPT860 board
-#
-
-TEXT_BASE = 0x02000000
-#TEXT_BASE = 0x00FB0000
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- lib/string.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/extable.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ common/libcommon.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ board/LEOX/elpt860/libelpt860.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+/* drivers/rtc/librtc.o (.text*) */
. = env_offset;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := edminiv2.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# MA 02110-1301 USA
#
-TEXT_BASE = 0x00100000
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfff90000
--- /dev/null
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := aspenite.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* Enable Console on UART1 */
+ MFP107_UART1_RXD,
+ MFP108_UART1_TXD,
+ MFP_EOC /*End of configureation*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ return 0;
+}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS = ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EVB64360 boards
-#
-
-TEXT_BASE = 0xfff00000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS = ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := guruplug.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
return 0;
}
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
#ifdef CONFIG_RESET_PHY_R
void mv_phy_88e1121_init(char *name)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mv88f6281gtw_ge.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
return 0;
}
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
#ifdef CONFIG_MV88E61XX_SWITCH
void reset_phy(void)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := openrd_base.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
return 0;
}
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := rd6281a.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
return 0;
}
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
void mv_phy_88e1116_init(char *name)
{
u16 reg;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sheevaplug.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
0
};
kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+int board_init(void)
+{
/*
* arch number of board
*/
return 0;
}
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o eccx.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Stäubli Faverges - <www.staubli.com>
-# Pierre AUBERT p.aubert@staubli.com
-# U-Boot port on RPXClassic LF (CLLF_BW31) board
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xff000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-/* XXX ?
- . = env_offset;
-*/
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RPXlite boards
-#
-
-TEXT_BASE = 0xfff00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-/* XXX ?
- . = env_offset;
-*/
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RPXlite dw boards : lite_dw
-#
-
-TEXT_BASE = 0xff000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-/* XXX ?
- . = env_offset;
-*/
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RedRock vision boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
. = env_offset;
common/env_embedded.o (.ppcenv)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
--- /dev/null
+#
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dockstar.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "dockstar.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
+ DOCKSTAR_OE_VAL_HIGH,
+ DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED (1 << 14)
+#define ORANGE_LED (1 << 15)
+#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
+#define NEITHER_LED 0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+ struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+ u32 oe = readl(&r->oe) | BOTH_LEDS;
+ writel(oe & ~leds, &r->oe); /* active low */
+ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case 15: /* booting Linux */
+ set_leds(BOTH_LEDS, NEITHER_LED);
+ break;
+ case 64: /* Ethernet initialization */
+ set_leds(GREEN_LED, GREEN_LED);
+ break;
+ default:
+ if (val < 0) /* error */
+ set_leds(ORANGE_LED, ORANGE_LED);
+ break;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DOCKSTAR_H
+#define __DOCKSTAR_H
+
+#define DOCKSTAR_OE_LOW (~(0))
+#define DOCKSTAR_OE_HIGH (~(0))
+#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DOCKSTAR_H */
--- /dev/null
+#
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Artis A-3000 boards
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
#
-# (C) Copyright 2001-2006
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
-SOBJS = init.o
+COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <netdev.h>
+#include <led-display.h>
+#include <linux/err.h>
+
+#include "mt46v32m16.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize;
+}
+
+int checkboard (void)
+{
+ puts ("Board: A4M072\n");
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, num_if = 0;
+
+ /* Initialize TSECs first */
+ if ((rv = cpu_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize FEC.\n");
+
+ if ((rv = pci_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+ return num_if;
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Initialize EEPROM write-protect GPIO pin.
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ /* Enable GPIO pin */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
+ /* Set direction, output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
+ /* De-assert write enable */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+#endif
+ return 0;
+}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access */
+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+ CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+#endif
+
+#ifdef CONFIG_CMD_DISPLAY
+#define DISPLAY_BUF_SIZE 2
+static u8 display_buf[DISPLAY_BUF_SIZE];
+static u8 display_putc_pos;
+static u8 display_out_pos;
+
+void display_set(int cmd) {
+
+ if (cmd & DISPLAY_CLEAR) {
+ display_buf[0] = display_buf[1] = 0;
+ }
+
+ if (cmd & DISPLAY_HOME) {
+ display_putc_pos = 0;
+ }
+}
+
+#define SEG_A (1<<0)
+#define SEG_B (1<<1)
+#define SEG_C (1<<2)
+#define SEG_D (1<<3)
+#define SEG_E (1<<4)
+#define SEG_F (1<<5)
+#define SEG_G (1<<6)
+#define SEG_P (1<<7)
+#define SEG__ 0
+
+/*
+ * +- A -+
+ * | |
+ * F B
+ * | |
+ * +- G -+
+ * | |
+ * E C
+ * | |
+ * +- D -+ P
+ *
+ * 0..9 index 0..9
+ * A..Z index 10..35
+ * - index 36
+ * _ index 37
+ * . index 38
+ */
+
+#define SYMBOL_DASH (36)
+#define SYMBOL_UNDERLINE (37)
+#define SYMBOL_DOT (38)
+
+static u8 display_char2seg7_tbl[]=
+{
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
+ SEG_B | SEG_C, /* 1 */
+ SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
+ SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
+ SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
+ SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
+ SEG_A | SEG_B | SEG_C, /* 7 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
+ SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
+ SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
+ SEG_A | SEG_D | SEG_E | SEG_F, /* C */
+ SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
+ SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
+ SEG_A | SEG_E | SEG_F | SEG_G, /* F */
+ 0, /* g - not displayed */
+ SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
+ SEG_B | SEG_C, /* I */
+ 0, /* J - not displayed */
+ 0, /* K - not displayed */
+ SEG_D | SEG_E | SEG_F, /* L */
+ 0, /* m - not displayed */
+ 0, /* n - not displayed */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
+ SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
+ 0, /* q - not displayed */
+ 0, /* r - not displayed */
+ SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
+ SEG_D | SEG_E | SEG_F | SEG_G, /* t */
+ SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
+ 0, /* V - not displayed */
+ 0, /* w - not displayed */
+ 0, /* X - not displayed */
+ SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
+ 0, /* Z - not displayed */
+ SEG_G, /* - */
+ SEG_D, /* _ */
+ SEG_P /* . */
+};
+
+/* Convert char to the LED segments representation */
+static u8 display_char2seg7(char c)
+{
+ u8 val = 0;
+
+ if (c >= '0' && c <= '9')
+ c -= '0';
+ else if (c >= 'a' && c <= 'z')
+ c -= 'a' - 10;
+ else if (c >= 'A' && c <= 'Z')
+ c -= 'A' - 10;
+ else if (c == '-')
+ c = SYMBOL_DASH;
+ else if (c == '_')
+ c = SYMBOL_UNDERLINE;
+ else if (c == '.')
+ c = SYMBOL_DOT;
+ else
+ c = ' '; /* display unsupported symbols as space */
+
+ if (c != ' ')
+ val = display_char2seg7_tbl[(int)c];
+
+ return val;
+}
+
+int display_putc(char c)
+{
+ if (display_putc_pos >= DISPLAY_BUF_SIZE)
+ return -1;
+
+ display_buf[display_putc_pos++] = display_char2seg7(c);
+ /* one-symbol message should be steady */
+ if (display_putc_pos == 1)
+ display_buf[display_putc_pos] = display_char2seg7(c);
+
+ return c;
+}
+
+/*
+ * Flush current symbol to the LED display hardware
+ */
+static inline void display_flush(void)
+{
+ u32 val = display_buf[display_out_pos];
+
+ val |= (val << 8) | (val << 16) | (val << 24);
+ out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
+}
+
+/*
+ * Output contents of the software display buffer to the LED display every 0.5s
+ */
+void board_show_activity(ulong timestamp)
+{
+ static ulong last;
+ static u8 once;
+
+ if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
+ display_flush();
+ display_out_pos ^= 1;
+ last = timestamp;
+ once = 1;
+ }
+}
+
+/*
+ * Empty fake function
+ */
+void show_activity(int arg)
+{
+}
+#endif
+#if defined (CONFIG_SHOW_BOOT_PROGRESS)
+static int a4m072_status2code(int status, char *buf)
+{
+ char c = 0;
+
+ if (((status > 0) && (status <= 8)) ||
+ ((status >= 100) && (status <= 108)) ||
+ ((status < 0) && (status >= -9)) ||
+ (status == -100) || (status == -101) ||
+ ((status <= -103) && (status >= -113))) {
+ c = '5';
+ } else if (((status >= 9) && (status <= 14)) ||
+ ((status >= 120) && (status <= 123)) ||
+ ((status >= 125) && (status <= 129)) ||
+ ((status >= -13) && (status <= -10)) ||
+ (status == -120) || (status == -122) ||
+ ((status <= -124) && (status >= -127)) ||
+ (status == -129)) {
+ c = '8';
+ } else if (status == 15) {
+ c = '9';
+ } else if ((status <= -30) && (status >= -32)) {
+ c = 'A';
+ } else if (((status <= -35) && (status >= -40)) ||
+ ((status <= -42) && (status >= -51)) ||
+ ((status <= -53) && (status >= -58)) ||
+ (status == -64) ||
+ ((status <= -80) && (status >= -83)) ||
+ (status == -130) || (status == -140) ||
+ (status == -150)) {
+ c = 'B';
+ }
+
+ if (c == 0)
+ return -EINVAL;
+
+ buf[0] = (status < 0) ? '-' : c;
+ buf[1] = c;
+
+ return 0;
+}
+
+void show_boot_progress(int status)
+{
+ char buf[2];
+
+ if (a4m072_status2code(status, buf) < 0)
+ return;
+
+ display_putc(buf[0]);
+ display_putc(buf[1]);
+ display_set(DISPLAY_HOME);
+ display_out_pos = 0; /* reset output position */
+
+ /* we want to flush status 15 now */
+ if (status == 15)
+ display_flush();
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40010000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := actux1.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00e00000
+CONFIG_SYS_TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := actux2.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00e00000
+CONFIG_SYS_TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := actux3.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00e00000
+CONFIG_SYS_TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := actux4.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00e00000
+CONFIG_SYS_TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Analogue&Micro Adder boards family
-#
-TEXT_BASE = 0xFE000000
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += afeb9260.o
COBJS-y += partition.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# alaska board
-#
-
-TEXT_BASE = 0xfff00000
-# TEXT_BASE = 0x00100000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# we get text_base from board config header, so do not use this
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o
SOBJS =
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2007
+# (C) Copyright 2007-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# AMCC 405EZ Reference Platform (Acadia) board
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF80000
-endif
-
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
-ifdef CONFIG_NAND_U_BOOT
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2002-2007
+# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFA0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
-ifdef CONFIG_NAND_U_BOOT
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text*)
+ board/amcc/bamboo/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
-
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
#
# See file CREDITS for list of people who contributed to this
# project.
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := delta.o nand.o
-SOBJS := lowlevel_init.o
+COBJS-y := $(BOARD).o
+SOBJS := init.o
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
--- /dev/null
+/*
+ * Bluestone board support
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/apm821xx.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx-gpio.h>
+
+int board_early_init_f(void)
+{
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * UART0: 2 pins
+ */
+ mtsdr(SDR0_PFC1, 0x0000000);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: Bluestone Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 sdr0_srst1 = 0;
+
+ /* Setup PLB4-AHB bridge based on the system address map */
+ mtdcr(AHB_TOP, 0x8000004B);
+ mtdcr(AHB_BOT, 0x8000004B);
+
+ /*
+ * The AHB Bridge core is held in reset after power-on or reset
+ * so enable it now
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_AHB;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+
+ return 0;
+}
#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
-#
-# iad210 boards
+# Applied Micro APM821XX Evaluation board.
#
-TEXT_BASE = 0x08000000
-/*TEXT_BASE = 0x00200000 */
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /* TLB 0 */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 4, AC_RWX | SA_G)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+ 0, AC_RWX | SA_G)
+
+ /* TLB-entry for OCM */
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
+ AC_RWX | SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
+ CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
+ tlbtab_end
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
DECLARE_GLOBAL_DATA_PTR;
- struct board_bcsr {
- u8 board_id;
- u8 cpld_rev;
- u8 led_user;
- u8 board_status;
- u8 reset_ctrl;
- u8 flash_ctrl;
- u8 eth_ctrl;
- u8 usb_ctrl;
- u8 irq_ctrl;
+struct board_bcsr {
+ u8 board_id;
+ u8 cpld_rev;
+ u8 led_user;
+ u8 board_status;
+ u8 reset_ctrl;
+ u8 flash_ctrl;
+ u8 eth_ctrl;
+ u8 usb_ctrl;
+ u8 irq_ctrl;
};
#define BOARD_CANYONLANDS_PCIE 1
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
- if (pvr_460ex()) {
- /*
- * Configure USB-STP pins as alternate and not GPIO
- * It seems to be neccessary to configure the STP pins as GPIO
- * input at powerup (perhaps while USB reset is asserted). So
- * we configure those pins to their "real" function now.
- */
- gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
- }
#endif
return 0;
val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
return 0;
}
val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
+ /* Reconfigure USB-STP pins as input */
+ gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+ gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+
return 0;
}
}
#endif /* !defined(CONFIG_ARCHES) */
-#if defined(CONFIG_NAND_U_BOOT)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-phys_size_t initdram(int board_type)
-{
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
-#endif
-
#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
#
-# (C) Copyright 2008
+# (C) Copyright 2008-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
-ifdef CONFIG_NAND_U_BOOT
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
+ board/amcc/canyonlands/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x20000);
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x80000);
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# AMCC 440SPe Evaluation (Katmai) board
#
-TEXT_BASE = 0xFFFA0000
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
#
-# (C) Copyright 2007
+# (C) Copyright 2007-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFA0000
-endif
-
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
-ifdef CONFIG_NAND_U_BOOT
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0x00001000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
-else
-TEXT_BASE = 0xFFFB0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cmd_pll.o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFA0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# AMCC 440GX Reference Platform (Ocotea) board
#
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# AMCC 460SX Reference Platform (redwood) board
#
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xfffb0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y = $(BOARD).o sdram.o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# AMCC 440EPx Reference Platform (Sequoia) board
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
-ifdef CONFIG_NAND_U_BOOT
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else ifdef CONFIG_NAND_U_BOOT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+ defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+ defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
+ board/amcc/sequoia/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text*)
+ board/amcc/sequoia/init.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o lcd.o update.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o lcd.o update.o showinfo.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# AMCC 440GX Reference Platform (Taishan) board
#
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0x00001000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o cmd_yucca.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
+CONFIG_SYS_TEXT_BASE = 0x07FD0000
else
-TEXT_BASE = 0xfffb0000
+CONFIG_SYS_TEXT_BASE = 0xfffb0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Start at bottom of RAM, but at an aliased address so that it looks
-# like it's not in RAM. This is a bit of voodoo to allow it to be
-# run from RAM instead of Flash.
-TEXT_BASE = 0x08000000
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/amirix/ap1000/u-boot.lds
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amirix/ap1000/init.o (.text)
- arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
- arch/powerpc/cpu/ppc4xx/traps.o (.text)
- arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
- arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
- arch/powerpc/cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
+ board/amirix/ap1000/init.o (.text)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := apollon.o mem.o sys_info.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x83e80000
+CONFIG_SYS_TEXT_BASE = 0x83e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
-#TEXT_BASE = 0x40270000
+#CONFIG_SYS_TEXT_BASE = 0x40270000
# Handy to get symbols to debug ROM version.
-#TEXT_BASE = 0x0
-#TEXT_BASE = 0x08000000
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0x08000000
#define SDRAM_BASE_ADDRESS 0x80008000
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := armadillo.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#address where u-boot will be relocated
-TEXT_BASE = 0xc0f80000
+CONFIG_SYS_TEXT_BASE = 0xc0f80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS-y := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(COBJS)
# image should be loaded at 0x01000000
#
-TEXT_BASE = 0x01000000
+CONFIG_SYS_TEXT_BASE = 0x01000000
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
-echo -n "/* Integrator configuration implied " > ${config_file}
-echo " by Makefile target */" >> ${config_file}
-echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
-echo " /* Integrator board */" >> ${config_file}
-echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file}
-echo " 1 /* Integrator/AP */" >> ${config_file}
+cat > ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */
+_EOF
+
# ---------------------------------------------------------
# Set the core module defines according to Core Module
# ---------------------------------------------------------
ap720t_config)
cpu="arm720t"
- echo -n "#define CONFIG_CM720T" >> ${config_file}
- echo " 1 /* CPU core is ARM720T */ " >> ${config_file}
+ echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \
+ >> ${config_file}
variant="Core module CM720T"
;;
ap922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
- echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
- echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
+ echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+ >> ${config_file}
;;
ap920t_config)
cpu="arm920t"
variant="Core module CM920T"
- echo -n "#define CONFIG_CM920T" >> ${config_file}
- echo " 1 /* CPU core is ARM920T */" >> ${config_file}
+ echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+ >> ${config_file}
;;
ap926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
- echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
- echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
+ echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+ >> ${config_file}
;;
ap946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
- echo -n "#define CONFIG_CM946E_S" >> ${config_file}
- echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
+ echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+ >> ${config_file}
;;
*)
case "$cpu" in
arm_intcm)
- echo "/* Core module undefined/not ported */" >> ${config_file}
- echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
- echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
- echo -n " /* CM may not have " >> ${config_file}
- echo "multiple SSRAM mapping */" >> ${config_file}
- echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
- echo -n " /* CM may not support SPD " >> ${config_file}
- echo "query */" >> ${config_file}
- echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
- echo -n " /* CM may not support " >> ${config_file}
- echo "remapping */" >> ${config_file}
- echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
- echo -n " /* CM may not have " >> ${config_file}
- echo "initialization reg */" >> ${config_file}
- echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
- echo " /* CM may not have TCRAM */" >> ${config_file}
- echo -n " /* May not be processor " >> ${config_file}
- echo "without cache support */" >> ${config_file}
- echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
- echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
+ cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
;;
arm720t)
- echo -n " /* May not be processor " >> ${config_file}
- echo "without cache support */" >> ${config_file}
- echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file}
- echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file}
+ cat >> ${config_file} << _EOF
+/* May not be processor without cache support */
+#define CONFIG_SYS_NO_ICACHE 1
+#define CONFIG_SYS_NO_DCACHE 1
+_EOF
;;
esac
# ---------------------------------------------------------
# Set the platform defines
# ---------------------------------------------------------
-echo -n "/* Integrator configuration implied " > ${config_file}
-echo " by Makefile target */" >> ${config_file}
-echo -n "#define CONFIG_INTEGRATOR" >> ${config_file}
-echo " /* Integrator board */" >> ${config_file}
-echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file}
-echo " 1 /* Integrator/CP */" >> ${config_file}
+cat >> ${config_file} << _EOF
+/* Integrator configuration implied by Makefile target */
+#define CONFIG_INTEGRATOR /* Integrator board */
+#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */
+_EOF
cpu="arm_intcm"
variant="unknown core module"
cp922_XA10_config)
cpu="arm_intcm"
variant="unported core module CM922T_XA10"
- echo -n "#define CONFIG_CM922T_XA10" >> ${config_file}
- echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file}
+ echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \
+ >> ${config_file}
;;
cp920t_config)
cpu="arm920t"
variant="Core module CM920T"
- echo -n "#define CONFIG_CM920T" >> ${config_file}
- echo " 1 /* CPU core is ARM920T */" >> ${config_file}
+ echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \
+ >> ${config_file}
;;
cp926ejs_config)
cpu="arm926ejs"
variant="Core module CM926EJ-S"
- echo -n "#define CONFIG_CM926EJ_S" >> ${config_file}
- echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file}
+ echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \
+ >> ${config_file}
;;
cp946es_config)
cpu="arm946es"
variant="Core module CM946E-S"
- echo -n "#define CONFIG_CM946E_S" >> ${config_file}
- echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file}
+ echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \
+ >> ${config_file}
;;
cp1136_config)
cpu="arm1136"
variant="Core module CM1136EJF-S"
- echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file}
- echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file}
+ echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \
+ >> ${config_file}
;;
*)
if [ "$cpu" = "arm_intcm" ]
then
- echo "/* Core module undefined/not ported */" >> ${config_file}
- echo "#define CONFIG_ARM_INTCM 1" >> ${config_file}
- echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file}
- echo -n " /* CM may not have " >> ${config_file}
- echo "multiple SSRAM mapping */" >> ${config_file}
- echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file}
- echo -n " /* CM may not support SPD " >> ${config_file}
- echo "query */" >> ${config_file}
- echo -n "#undef CONFIG_CM_REMAP " >> ${config_file}
- echo -n " /* CM may not support " >> ${config_file}
- echo "remapping */" >> ${config_file}
- echo -n "#undef CONFIG_CM_INIT " >> ${config_file}
- echo -n " /* CM may not have " >> ${config_file}
- echo "initialization reg */" >> ${config_file}
- echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file}
- echo " /* CM may not have TCRAM */" >> ${config_file}
+ cat >> ${config_file} << _EOF
+/* Core module undefined/not ported */
+#define CONFIG_ARM_INTCM 1
+#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */
+#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */
+#undef CONFIG_CM_REMAP /* CM may not support remapping */
+#undef CONFIG_CM_INIT /* CM may not have initialization reg */
+#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
+_EOF
fi
fi # ap
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := versatile.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# image should be loaded at 0x01000000
#
-TEXT_BASE = 0x01000000
+CONFIG_SYS_TEXT_BASE = 0x01000000
#
-# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
-# (C) Copyright 2004-2006
+# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o nand.o flash.o
+COBJS := ca9x4_ct_vxp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+ gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+ gd->flags = 0;
+
+ icache_enable();
+ flash__init();
+ vexpress_timer_init();
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+static void flash__init(void)
+{
+ /* Setup the sytem control register to allow writing to flash */
+ writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+ &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+ gd->ram_size =
+ get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size =
+ get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size =
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+/*
+ * Start timer:
+ * Setup a 32 bit timer, running at 1KHz
+ * Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+ /*
+ * Set clock frequency in system controller:
+ * VEXPRESS_REFCLK is 32KHz
+ * VEXPRESS_TIMCLK is 1MHz
+ */
+ writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+ SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+ readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+ /*
+ * Set Timer0 to be:
+ * Enabled, free running, no interrupt, 32-bit, wrapping
+ */
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT | \
+ readl(&systimer_base->timer0control), \
+ &systimer_base->timer0control);
+
+ reset_timer_masked();
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(ulong addr)
+{
+ writeb(WDT_EN, &wdt_base->wdogcontrol);
+ writel(WDT_RESET_LOAD, &wdt_base->wdogload);
+ while (1)
+ ;
+}
+
+/*
+ * Delay x useconds AND perserve advance timstamp value
+ * assumes timer is ticking at 1 msec
+ */
+void __udelay(ulong usec)
+{
+ ulong tmo, tmp;
+
+ tmo = usec / 1000;
+ tmp = get_timer(0); /* get current timestamp */
+
+ /*
+ * If setting this forward will roll time stamp then
+ * reset "advancing" timestamp to 0 and set lastdec value
+ * otherwise set the advancing stamp to the wake up time
+ */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ while (get_timer_masked() < tmo)
+ ; /* loop till wakeup event */
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+ lastdec = readl(&systimer_base->timer0value) / 1000;
+ timestamp = 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = readl(&systimer_base->timer0value) / 1000;
+
+ if (lastdec >= now) { /* normal mode (non roll) */
+ timestamp += lastdec - now;
+ } else { /* count down timer overflowed */
+ /*
+ * nts = ts + ld - now
+ * ts = old stamp, ld = time before passing through - 1
+ * now = amount of time after passing though - 1
+ * nts = new "advancing time stamp"
+ */
+ timestamp += lastdec + SYSTIMER_RELOAD - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+ return readl((u32 *)SYS_ID);
+}
#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
# See file CREDITS for list of people who contributed to this
# project.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
-TEXT_BASE = 0xFFF00000
+# Linux-Kernel is expected to be at 0x60008000
+#
+CONFIG_SYS_TEXT_BASE = 0x60800000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := assabet.o
SOBJS := setup.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# The Intel Assabet 1 bank of 32 MiB SDRAM
#
-TEXT_BASE = 0xc1f00000
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o fpga.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = $(CONFIG_TEXT_BASE)
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ti113x.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/*====================================================================*/
-int i82365_init (void)
+static int i82365_init (void)
{
u_int val;
int i;
return 0;
}
-void i82365_exit (void)
+static void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91cap9adk.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x73000000
+CONFIG_SYS_TEXT_BASE = 0x73000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += led.o
-COBJS-y += misc.o
-ifdef CONFIG_HAS_DATAFLASH
-COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
-COBJS-y += partition.o
-endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * derived from previous work
+ *
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*/
#include <common.h>
-#include <exports.h>
#include <netdev.h>
-#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
-#if defined(CONFIG_DRIVER_ETHER)
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
+int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f ();
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
- writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
-
- /*
- * memory and cpu-speed are setup before relocation
- * so we do _nothing_ here
- */
+ writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
-/*
- * Name:
- * at91rm9200_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = dm9161_InitPhy;
- p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
- p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
- p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
-}
-#endif
-
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
- int rc = 0;
- rc = at91emac_register(bis, 0);
- return rc;
+ return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
+++ /dev/null
-TEXT_BASE = 0x21f00000
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas.devel@gmail.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
-#define GREEN_LED AT91C_PIO_PB0
-#define YELLOW_LED AT91C_PIO_PB1
-#define RED_LED AT91C_PIO_PB2
+/* bit mask in PIO port B */
+#define GREEN_LED (1<<0)
+#define YELLOW_LED (1<<1)
+#define RED_LED (1<<2)
void green_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.sodr);
}
-
void coloured_LED_init (void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
- AT91PS_PMC PMC = AT91C_BASE_PMC;
+ at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
- writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
+ writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
/* Disable peripherals on LEDs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}
+++ /dev/null
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <dataflash.h>
-
-int AT91F_GetMuxStatus(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
-
- if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
- return 1;
-
- return 0;
-}
-
-void AT91F_SelectMMC(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Set Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
-}
-
-void AT91F_SelectSPI(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Clear Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
-}
+++ /dev/null
-/*
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
-};
-
-/*define the area offsets*/
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
-};
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9260ek.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9261ek.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9263ek.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9m10g45ek.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x73f00000
+CONFIG_SYS_TEXT_BASE = 0x73f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += at91sam9rlek.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_LDFLAGS += --gc-sections
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += flash.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_LDFLAGS += --gc-sections
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
LDSCRIPT = $(src)board/atmel/atstk1000/u-boot.lds
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
if (io_sel & 1) {
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- printf (" eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf (" eTSEC2 is in sgmii mode.\n");
+ printf("eTSEC2 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf (" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
- printf (" eTSEC4 is in sgmii mode.\n");
+ printf("eTSEC4 is in sgmii mode.\n");
}
#ifdef CONFIG_PCIE1
pcie1_hose.region_count = 1;
#endif
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI1: disabled\n");
}
puts("\n");
SET_STD_PCI_INFO(pci_info[num], 2);
pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
- puts (" PCI2\n");
+ puts("PCI2\n");
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI2: disabled\n");
+ printf("PCI2: disabled\n");
}
puts("\n");
#else
+++ /dev/null
-#
-# Copyright 2004, 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# atum8548 board
-# TEXT_BASE = 0xfff80000
-# TEXT_BASE = 0xfffff000
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
#
#
-sinclude $(SRCTREE)/board/xilinx/ppc405-generic/config.mk
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
#
#
-sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
--- /dev/null
+#
+# Balloon3 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := balloon3.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <spartan3.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Init the FPGA */
+ balloon3_init_fpga();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_stuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_FPGA)
+/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+ if (nassert)
+ writel(0x80, GPCR3);
+ else
+ writel(0x80, GPSR3);
+ if (nflush)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+ return nassert;
+}
+
+/* Check GPIO83 -- INITB */
+int fpga_init_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x80000);
+}
+
+/* Check GPIO84 -- BUSY */
+int fpga_busy_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x100000);
+}
+
+/* Check GPIO111 -- DONE */
+int fpga_done_fn(int cookie)
+{
+ return readl(GPLR3) & 0x8000;
+}
+
+/* Configure GPIO104 as GPIO and deassert it */
+int fpga_pre_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
+ writel(0x100, GPCR3);
+ return 0;
+}
+
+/* Configure GPIO104 as nSKTSEL */
+int fpga_post_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
+ return 0;
+}
+
+/* Toggle RDnWR */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+ udelay(1000);
+
+ if (nassert_write)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+
+ return nassert_write;
+}
+
+/* Write program to the FPGA */
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ writeb(data, 0x10f00000);
+ return 0;
+}
+
+/* Toggle Clock pin -- NO-OP */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+/* Toggle ChipSelect pin -- NO-OP */
+int fpga_cs_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ NULL, /* abort */
+ fpga_post_config_fn,
+};
+
+Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+ (void *)&balloon3_fpga_fns, 0);
+
+/* Initialize the FPGA */
+void balloon3_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+}
+#else
+void balloon3_init_fpga(void) {}
+#endif /* CONFIG_FPGA */
+++ /dev/null
-This port of U-Boot is tuned to run on a range of Barco Control Rooms
-Streaming Video Solutions, including:
-
- - Streaming Video Card (SVC)
- - Sample Compress Network (SCN)
-
-For more information, see http://www.barcocontrolrooms.com/
-
-Code and configuration are originally based on the Sandpoint board
-
-Marc Leeman <marc.leeman@barco.com>
+++ /dev/null
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $
- * $Revision: 1.4 $
- * $Author: mleeman $
- * $Date: 2005/03/02 16:40:20 $
- *
- * Last ChangeLog Entry
- * $Log: barco.c,v $
- * Revision 1.4 2005/03/02 16:40:20 mleeman
- * remove empty labels (3.4 complains)
- *
- * Revision 1.3 2005/02/21 12:48:58 mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.2 2005/02/21 10:10:53 mleeman
- * - split up switch statement to a function call (Linux kernel coding guidelines)
- * ( feedback wd)
- *
- * Revision 1.1 2005/02/14 09:31:07 mleeman
- * renaming of files
- *
- * Revision 1.1 2005/02/14 09:23:46 mleeman
- * - moved 'barcohydra' directory to a more generic barco; since we will be
- * supporting and adding multiple boards
- *
- * Revision 1.3 2005/02/10 13:57:32 mleeman
- * fixed flash corruption: I should exit from the moment I find the correct value
- *
- * Revision 1.2 2005/02/09 12:56:23 mleeman
- * add generic header to track changes in sources
- *
- *
- *******************************************************************/
-
-/*
- * (C) Copyright 2004
- * Marc Leeman <marc.leeman@barco.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <malloc.h>
-#include <command.h>
-
-#include "config.h"
-#include "barco_svc.h"
-
-#define TRY_WORKING (3)
-#define BOOT_DEFAULT (2)
-#define BOOT_WORKING (1)
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Streaming Video Card for Hydra systems "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " Unity ##Test not implemented yet##\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size (CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg (MEAR1);
- emear1 = mpc824x_mpc107_getreg (EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_barcohydra_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_barcohydra_config_table,
-#endif
-};
-
-void pci_init_board (void)
-{
- pci_mpc824x_init (&hose);
-}
-
-int write_flash (char *addr, char value)
-{
- char *adr = (char *)0xFF800000;
- int cnt = 0;
- char status,oldstatus;
-
- *(adr+0x55) = 0xAA; udelay (1);
- *(adr+0xAA) = 0x55; udelay (1);
- *(adr+0x55) = 0xA0; udelay (1);
- *addr = value;
-
- status = *addr;
- do {
- oldstatus = status;
- status = *addr;
-
- if ((oldstatus & 0x40) == (status & 0x40)) {
- return 4;
- }
- cnt++;
- if (cnt > 10000) {
- return 2;
- }
- } while ( (status & 0x20) == 0 );
-
- oldstatus = *addr;
- status = *addr;
-
- if ((oldstatus & 0x40) == (status & 0x40)) {
- return 0;
- } else {
- *(adr+0x55) = 0xF0;
- return 1;
- }
-}
-
-unsigned update_flash (unsigned char *buf)
-{
- switch ((*buf) & 0x3) {
- case TRY_WORKING:
- printf ("found 3 and converted it to 2\n");
- write_flash ((char *)buf, (*buf) & 0xFE);
- *((unsigned char *)0xFF800000) = 0xF0;
- udelay (100);
- printf ("buf [%#010x] %#010x\n", (unsigned)buf, (*buf));
- /* XXX - fall through??? */
- case BOOT_WORKING :
- return BOOT_WORKING;
- }
- return BOOT_DEFAULT;
-}
-
-unsigned scan_flash (void)
-{
- char section[] = "kernel";
- int cfgFileLen = (CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH >> 1);
- int sectionPtr = 0;
- int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */
- int bufPtr;
- unsigned char *buf;
-
- buf = (unsigned char*)(CONFIG_SYS_FLASH_RANGE_BASE + CONFIG_SYS_FLASH_RANGE_SIZE \
- - CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH);
- for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) {
- if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
- return BOOT_DEFAULT;
- }
- /* This is the scanning loop, we try to find a particular
- * quoted value
- */
- switch (foundItem) {
- case 0:
- if ((section[sectionPtr] == 0)) {
- ++foundItem;
- } else if (buf[bufPtr] == section[sectionPtr]) {
- ++sectionPtr;
- } else {
- sectionPtr = 0;
- }
- break;
- case 1:
- ++foundItem;
- break;
- case 2:
- ++foundItem;
- break;
- case 3:
- default:
- return update_flash (&buf[bufPtr - 1]);
- }
- }
-
- printf ("Failed to read %s\n",section);
- return BOOT_DEFAULT;
-}
-
-TSBootInfo* find_boot_info (void)
-{
- unsigned bootimage = scan_flash ();
- TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo));
-
- switch (bootimage) {
- case TRY_WORKING:
- info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
- break;
- case BOOT_WORKING :
- info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
- break;
- case BOOT_DEFAULT:
- default:
- info->address= CONFIG_SYS_DEFAULT_KERNEL_ADDRESS;
-
- }
- info->size = *((unsigned int *)(info->address ));
-
- return info;
-}
-
-void barcobcd_boot (void)
-{
- TSBootInfo* start;
- char *bootm_args[2];
- char *buf;
- int cnt;
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
- buf = (char *)(0x00800000);
- /* make certain there are enough chars to print the command line here!
- */
- bootm_args[0] = (char *)malloc (16*sizeof(char));
- bootm_args[1] = (char *)malloc (16*sizeof(char));
-
- start = find_boot_info ();
-
- printf ("Booting kernel at address %#10x with size %#10x\n",
- start->address, start->size);
-
- /* give length of the kernel image to bootm */
- sprintf (bootm_args[0],"%x",start->size);
- /* give address of the kernel image to bootm */
- sprintf (bootm_args[1],"%x",(unsigned)buf);
-
- printf ("flash address: %#10x\n",start->address+8);
- printf ("buf address: %#10x\n",(unsigned)buf);
-
- /* aha, we reserve 8 bytes here... */
- for (cnt = 0; cnt < start->size ; cnt++) {
- buf[cnt] = ((char *)start->address)[cnt+8];
- }
-
- /* initialise RAM memory */
- *((unsigned int *)0xFEC00000) = 0x00141A98;
- do_bootm (NULL,0,2,bootm_args);
-}
-
-int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- barcobcd_boot ();
-
- return 0;
-}
-
-/* Currently, boot_working and boot_default are the same command. This is
- * left in here to see what we'll do in the future */
-
-U_BOOT_CMD (
- try_working, 1, 1, barcobcd_boot_image,
- "check flash value and boot the appropriate image",
- ""
- );
-
-U_BOOT_CMD (
- boot_working, 1, 1, barcobcd_boot_image,
- "check flash value and boot the appropriate image",
- ""
- );
-
-U_BOOT_CMD (
- boot_default, 1, 1, barcobcd_boot_image,
- "check flash value and boot the appropriate image",
- ""
- );
-/*
- * We are not using serial communication, so just provide empty functions
- */
-int serial_init (void)
-{
- return 0;
-}
-void serial_setbrg (void)
-{
- return;
-}
-void serial_putc (const char c)
-{
- return;
-}
-void serial_puts (const char *c)
-{
- return;
-}
-int serial_getc (void)
-{
- return 0;
-}
-int serial_tstc (void)
-{
- return 0;
-}
+++ /dev/null
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $
- * $Revision: 1.2 $
- * $Author: mleeman $
- * $Date: 2005/02/21 12:48:58 $
- *
- * Last ChangeLog Entry
- * $Log: barco_svc.h,v $
- * Revision 1.2 2005/02/21 12:48:58 mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.1 2005/02/14 09:31:07 mleeman
- * renaming of files
- *
- * Revision 1.1 2005/02/14 09:23:46 mleeman
- * - moved 'barcohydra' directory to a more generic barco; since we will be
- * supporting and adding multiple boards
- *
- * Revision 1.1 2005/02/08 15:40:19 mleeman
- * modified and added platform files
- *
- * Revision 1.2 2005/01/25 08:05:04 mleeman
- * more cleanup of the code
- *
- * Revision 1.1 2004/07/20 08:49:55 mleeman
- * Working version of the default and nfs kernel booting.
- *
- *
- *******************************************************************/
-
-#ifndef _LOCAL_BARCOHYDRA_H_
-#define _LOCAL_BARCOHYDRA_H_
-
-#include <flash.h>
-#include <asm/io.h>
-
-/* Defines for the barcohydra board */
-#ifndef CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH
-#define CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH (0x10000)
-#endif
-
-#ifndef CONFIG_SYS_DEFAULT_KERNEL_ADDRESS
-#define CONFIG_SYS_DEFAULT_KERNEL_ADDRESS (CONFIG_SYS_FLASH_BASE + 0x30000)
-#endif
-
-#ifndef CONFIG_SYS_WORKING_KERNEL_ADDRESS
-#define CONFIG_SYS_WORKING_KERNEL_ADDRESS (0xFFE00000)
-#endif
-
-
-typedef struct SBootInfo {
- unsigned int address;
- unsigned int size;
- unsigned char state;
-}TSBootInfo;
-
-/* barcohydra.c */
-int checkboard(void);
-phys_size_t initdram(int board_type);
-void pci_init_board(void);
-void check_flash(void);
-int write_flash(char *addr, char value);
-TSBootInfo* find_boot_info(void);
-void final_boot(void);
-#endif
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Barco Hydra/SCN boards
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Thomas Koeller, tkoeller@gmx.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__ 1
-#endif
-
-#include <config.h>
-#include <asm/processor.h>
-#include <mpc824x.h>
-#include <ppc_asm.tmpl>
-
-#if defined(USE_DINK32)
- /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
- #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
-#else
- #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
-#endif
-
- .text
-
- /* Values to program into memory controller registers */
-tbl: .long MCCR1, MCCR1VAL
- .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
- .long MCCR3
- .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
- (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
- (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
- .long MCCR4
- .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
- (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
- (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
- ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
- (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
- (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
- ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
- .long MSAR1
- .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
- .long EMSAR1
- .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
- .long MSAR2
- .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
- .long EMSAR2
- .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
- .long MEAR1
- .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
- .long EMEAR1
- .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
- .long MEAR2
- .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
- .long EMEAR2
- .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
- (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
- (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
- (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
- .long 0
-
-
- /*
- * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
- * must be done in assembly, since we have no stack at this point.
- */
- .global early_init_f
-early_init_f:
- mflr r10
-
- /* basic memory controller configuration */
- lis r3, CONFIG_ADDR_HIGH
- lis r4, CONFIG_DATA_HIGH
- bl lab
-lab: mflr r5
- lwzu r0, tbl - lab(r5)
-loop: lwz r1, 4(r5)
- stwbrx r0, 0, r3
- eieio
- stwbrx r1, 0, r4
- eieio
- lwzu r0, 8(r5)
- cmpli cr0, 0, r0, 0
- bne cr0, loop
-
- /* set bank enable bits */
- lis r0, MBER@h
- ori r0, 0, MBER@l
- li r1, CONFIG_SYS_BANK_ENABLE
- stwbrx r0, 0, r3
- eieio
- stb r1, 0(r4)
- eieio
-
- /* delay loop */
- lis r0, 0x0003
- mtctr r0
-delay: bdnz delay
-
- /* enable memory controller */
- lis r0, MCCR1@h
- ori r0, 0, MCCR1@l
- stwbrx r0, 0, r3
- eieio
- lwbrx r0, 0, r4
- oris r0, 0, MCCR1_MEMGO@h
- stwbrx r0, 0, r4
- eieio
-
- /* set up stack pointer */
- lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
- ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
-
- mtlr r10
- blr
+++ /dev/null
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $
- * $Revision: 1.3 $
- * $Author: mleeman $
- * $Date: 2005/02/21 12:48:58 $
- *
- * Last ChangeLog Entry
- * $Log: flash.c,v $
- * Revision 1.3 2005/02/21 12:48:58 mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.2 2005/02/21 11:04:04 mleeman
- * remove dead code and Coding style (feedback wd)
- *
- * Revision 1.1 2005/02/14 09:23:46 mleeman
- * - moved 'barcohydra' directory to a more generic barco; since we will be
- * supporting and adding multiple boards
- *
- * Revision 1.2 2005/02/09 12:56:23 mleeman
- * add generic header to track changes in sources
- *
- *
- *******************************************************************/
-
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <flash.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*flash command address offsets*/
-
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
-
-typedef struct{
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-static unsigned long flash_id(unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {AMD_ID_F033C, FLASH_AM033},
- {AMD_ID_F065D, FLASH_AM065},
- {ATM_ID_LV040, FLASH_AT040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){
- if(p->extval == chip){
- result = FLASH_VENDMASK | p->intval;
- break;
- }
- }
-
- /* find vendor id */
- for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){
- if(p->extval == mfct){
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
- }
-
- return result;
-}
-
-
-unsigned long flash_init(void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++){
- flash_info_t * const pflinfo = &flash_info[i];
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- /* Enable writes to Hydra/Argus flash */
- {
- register unsigned int temp;
- CONFIG_READ_WORD(PICR1,temp);
- temp |= PICR1_FLASH_WR_EN;
- CONFIG_WRITE_WORD(PICR1,temp);
- }
-
- for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){
- flash_info_t * const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
-
- /* write autoselect sequence */
- flash[0x5555] = 0xaa;
- flash[0x2aaa] = 0x55;
- flash[0x5555] = 0x90;
- __asm__ __volatile__("sync");
-
- pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
-
- switch(pflinfo->flash_id & FLASH_TYPEMASK){
- case FLASH_AM033:
- pflinfo->size = 0x00200000;
- pflinfo->sector_count = 64;
- for(j = 0; j < 64; j++){
- pflinfo->start[j] = base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_AM065:
- pflinfo->size = 0x00800000;
- pflinfo->sector_count =128;
- for(j = 0; j < 128; j++){
- pflinfo->start[j] = base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_AT040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 2;
- pflinfo->start[0] = base_address ;
- pflinfo->start[1] = base_address + 0x00004000;
- pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01;
- pflinfo->protect[1] = 0X02;
- break;
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for(j = 0; j < 8; j++){
- pflinfo->start[j] = base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for(j = 1; j < 16; j++){
- pflinfo->start[j+3] = base_address + 0x00010000 * j;
- }
- break;
- }
- /* Protect monitor and environment sectors */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__("sync");
- }
-
- return flash_info[0].size + flash_info[1].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t *info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if(info->flash_id != FLASH_UNKNOWN){
- switch(info->flash_id & FLASH_VENDMASK){
- case FLASH_MAN_ATM:
- mfct = "Atmel";
- break;
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch(info->flash_id & FLASH_TYPEMASK){
- case FLASH_AT040:
- type = "AT49LV040 (512K * 8, uniform sector size)";
- break;
- case FLASH_AM033:
- type = "AM29F033C (4 Mbit * 8, uniform sector size)";
- break;
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM065:
- type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf(
- "\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct,
- type,
- info->size >> 10,
- info->sector_count
- );
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++){
- unsigned long size;
- unsigned int erased;
- unsigned long * flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size =
- (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for(
- flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size) && erased;
- flash++
- ){
- erased = *flash == ~0x0UL;
- }
-
- printf(
- "%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ",
- info->protect[i] ? "RO" : " "
- );
- }
-
- puts("\n");
- return;
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
- sh8b = 3;
- }
- else{
- sh8b = 0;
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *)(info->start[0] + (
- (info->start[sect] - info->start[0]) << sh8b));
- if (info->flash_id & FLASH_MAN_SST){
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- udelay(30000); /* wait 30 ms */
- }
- else
- addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag){
- enable_interrupts();
- }
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0){
- goto DONE;
- }
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *)(info->start[0] + (
- (info->start[l_sect] - info->start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
- sh8b = 3;
- }
- else{
- sh8b = 0;
- }
-
- dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag){
- enable_interrupts();
- }
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*----------------------------------------------------------------------- */
+++ /dev/null
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $
- * $Revision: 1.2 $
- * $Author: mleeman $
- * $Date: 2005/02/21 12:48:58 $
- *
- * Last ChangeLog Entry
- * $Log: speed.h,v $
- * Revision 1.2 2005/02/21 12:48:58 mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.1 2005/02/14 09:23:46 mleeman
- * - moved 'barcohydra' directory to a more generic barco; since we will be
- * supporting and adding multiple boards
- *
- * Revision 1.2 2005/02/09 12:56:23 mleeman
- * add generic header to track changes in sources
- *
- *
- *******************************************************************/
-
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o cmd_bc3450.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# BC3450 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFC000000 boot low (standard configuration with room for max 64 MByte
-# Flash ROM)
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot low
-TEXT_BASE = 0xFC000000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o
+COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * U-boot - main board file for BCT brettl2
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/gpio.h>
+#include <asm/net.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+
+#include "../cm-bf537e/gpio_cfi_flash.h"
+#include "smsc9303.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: bct-brettl2 board\n");
+ printf(" Support: http://www.bct-electronic.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int retry = 3;
+ int ret;
+
+ ret = bfin_EMAC_initialize(bis);
+
+ uchar enetaddr[6];
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ printf("setting MAC %pM\n", enetaddr);
+ }
+ puts(" ");
+
+ puts("initialize SMSC LAN9303i ethernet switch\n");
+
+ while (retry-- > 0) {
+ if (init_smsc9303i_mii())
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+static void init_tlv320aic31(void)
+{
+ puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
+ peripheral_request(P_TMR0, "tlv320aic31 clock");
+ bfin_write_TIMER0_CONFIG(0x020d);
+ bfin_write_TIMER0_PERIOD(0x0008);
+ bfin_write_TIMER0_WIDTH(0x0008/2);
+ bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
+ SSYNC();
+ udelay(10000);
+
+ puts(" resetting tlv320aic31\n");
+
+ gpio_request(GPIO_PF2, "tlv320aic31");
+ gpio_direction_output(GPIO_PF2, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PF2, 1);
+ udelay(10000);
+ gpio_free(GPIO_PF2);
+}
+
+static void init_mute_pin(void)
+{
+ printf(" unmute class D amplifier\n");
+
+ gpio_request(GPIO_PF5, "mute");
+ gpio_direction_output(GPIO_PF5, 1);
+ gpio_free(GPIO_PF5);
+}
+
+/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
+static void turn_leds_off(void)
+{
+ printf(" turn LEDs off\n");
+
+ gpio_request(GPIO_PF6, "led");
+ gpio_direction_output(GPIO_PF6, 0);
+ gpio_free(GPIO_PF6);
+
+ gpio_request(GPIO_PF15, "led");
+ gpio_direction_output(GPIO_PF15, 0);
+ gpio_free(GPIO_PF15);
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ gpio_cfi_flash_init();
+ init_tlv320aic31();
+ init_mute_pin();
+ turn_leds_off();
+
+ return 0;
+}
--- /dev/null
+/*
+ * cled.c - control color led
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+
+int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr = 0x20000000 + 0x200000; /* AMS2 */
+ uchar data;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ data = simple_strtoul(argv[1], NULL, 10);
+ outb(data, addr);
+
+ printf("cled, write %02x\n", data);
+
+ return 0;
+}
+
+U_BOOT_CMD(cled, 2, 0, do_cled,
+ "set/clear color LED",
+ "");
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
-#
# See file CREDITS for list of people who contributed to this
# project.
#
# MA 02111-1307 USA
#
-#
-# mpc8260ads board
-#
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf536-0.3
-TEXT_BASE = 0xfe000000
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
--- /dev/null
+#define GPIO_PIN_1 GPIO_PG5
+#define GPIO_PIN_2 GPIO_PG6
+#define GPIO_PIN_3 GPIO_PG7
+#include "../cm-bf537e/gpio_cfi_flash.c"
--- /dev/null
+/*
+ * smsc9303.c - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <miiphy.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_write_reg(unsigned short reg, unsigned int data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+ unsigned short tmp1, tmp2;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
+ return 0;
+
+ *data = (tmp2 << 16) | tmp1;
+
+ return 1;
+}
+
+#if 0
+static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+#endif
+
+typedef struct {
+ unsigned short reg;
+ unsigned int value;
+} smsc9303i_config_entry1_t;
+
+static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
+{
+ {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
+ {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
+ {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
+};
+
+typedef struct
+{
+ unsigned char addr;
+ unsigned char reg;
+ unsigned short value;
+} smsc9303i_config_entry2_t;
+
+static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
+{
+ {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
+ {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
+ {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
+
+ {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
+ {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
+ {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
+
+ {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
+ {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
+ {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
+
+ {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
+ {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
+ {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
+ {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
+ {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
+ {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
+ {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
+ {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
+ {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
+};
+
+int init_smsc9303i_mii(void)
+{
+ unsigned int data;
+ unsigned int i;
+
+ printf(" reset SMSC LAN9303i\n");
+
+ gpio_request(GPIO_PG10, "smsc9303");
+ gpio_direction_output(GPIO_PG10, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PG10, 1);
+ udelay(10000);
+
+ gpio_free(GPIO_PG10);
+
+#if defined(CONFIG_MII_INIT)
+ mii_init();
+#endif
+
+ printf(" write SMSC LAN9303i configuration\n");
+
+ if (!smc9303i_read_reg(0x50, &data))
+ return 0;
+
+ if ((data >> 16) != 0x9303) {
+ /* chip id not found */
+ printf(" error identifying SMSC LAN9303i\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
+ const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
+
+ if (!smc9303i_write_reg(entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
+ const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
+
+ if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ return 1;
+}
--- /dev/null
+/*
+ * smsc9303.h - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+int init_smsc9303i_mii(void);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf518-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf526-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
int misc_init_r(void)
{
/* CLKIN Buffer Output Enable */
- *pVR_CTL |= CLKBUFOE;
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
return 0;
}
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.2
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_VIDEO) += video.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
#define LCD_Y_RES 240 /* Vertical Resolution */
#define DMA_BUS_SIZE 16
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 /* lq035q1 */
+#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
!defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
#define PPI_PACK_EN 0x80
#define PPI_POLS_1 0x8000
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
static struct spi_slave *slave;
static int lq035q1_control(unsigned char reg, unsigned short value)
{
/* enable and disable PPI functions */
void EnablePPI(void)
{
- *pPPI_CONTROL |= PORT_EN;
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
}
void DisablePPI(void)
{
- *pPPI_CONTROL &= ~PORT_EN;
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
}
void Init_Ports(void)
void Init_PPI(void)
{
- *pPPI_DELAY = H_START;
- *pPPI_COUNT = (H_ACTPIX-1);
- *pPPI_FRAME = V_LINES;
+ bfin_write_PPI_DELAY(H_START);
+ bfin_write_PPI_COUNT(H_ACTPIX - 1);
+ bfin_write_PPI_FRAME(V_LINES);
/* PPI control, to be replaced with definitions */
- *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
+ bfin_write_PPI_CONTROL(
+ PPI_TX_MODE | /* output mode , PORT_DIR */
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
PPI_PACK_EN | /* packing enabled PACK_EN */
- PPI_POLS_1; /* faling edge syncs POLS */
+ PPI_POLS_1 /* faling edge syncs POLS */
+ );
}
void Init_DMA(void *dst)
{
- *pDMA0_START_ADDR = dst;
+ bfin_write_DMA0_START_ADDR(dst);
/* X count */
- *pDMA0_X_COUNT = H_ACTPIX / 2;
- *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
+ bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
/* Y count */
- *pDMA0_Y_COUNT = V_LINES;
- *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA0_Y_COUNT(V_LINES);
+ bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
/* DMA Config */
- *pDMA0_CONFIG =
+ bfin_write_DMA0_CONFIG(
WDSIZE_16 | /* 16 bit DMA */
DMA2D | /* 2D DMA */
- FLOW_AUTO; /* autobuffer mode */
+ FLOW_AUTO /* autobuffer mode */
+ );
}
-
void EnableDMA(void)
{
- *pDMA0_CONFIG |= DMAEN;
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
}
void DisableDMA(void)
{
- *pDMA0_CONFIG &= ~DMAEN;
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
}
-
/* Init TIMER0 as Frame Sync 1 generator */
void InitTIMER0(void)
{
- *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
+ bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */
SSYNC();
- *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
+ bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */
SSYNC();
- *pTIMER0_PERIOD = H_PERIOD;
+ bfin_write_TIMER0_PERIOD(H_PERIOD);
SSYNC();
- *pTIMER0_WIDTH = H_PULSE;
+ bfin_write_TIMER0_WIDTH(H_PULSE);
SSYNC();
- *pTIMER0_CONFIG = PWM_OUT |
+ bfin_write_TIMER0_CONFIG(
+ PWM_OUT |
PERIOD_CNT |
TIN_SEL |
CLK_SEL |
- EMU_RUN;
+ EMU_RUN
+ );
SSYNC();
}
void EnableTIMER0(void)
{
- *pTIMER_ENABLE |= TIMEN0;
+ bfin_write_TIMER_ENABLE(TIMEN0);
SSYNC();
}
void DisableTIMER0(void)
{
- *pTIMER_DISABLE |= TIMDIS0;
+ bfin_write_TIMER_DISABLE(TIMDIS0);
SSYNC();
}
void InitTIMER1(void)
{
- *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
+ bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */
SSYNC();
- *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
+ bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */
SSYNC();
-
- *pTIMER1_PERIOD = V_PERIOD;
+ bfin_write_TIMER1_PERIOD(V_PERIOD);
SSYNC();
- *pTIMER1_WIDTH = V_PULSE;
+ bfin_write_TIMER1_WIDTH(V_PULSE);
SSYNC();
- *pTIMER1_CONFIG = PWM_OUT |
+ bfin_write_TIMER1_CONFIG(
+ PWM_OUT |
PERIOD_CNT |
TIN_SEL |
CLK_SEL |
- EMU_RUN;
+ EMU_RUN
+ );
SSYNC();
}
void EnableTIMER1(void)
{
- *pTIMER_ENABLE |= TIMEN1;
+ bfin_write_TIMER_ENABLE(TIMEN1);
SSYNC();
}
void DisableTIMER1(void)
{
- *pTIMER_DISABLE |= TIMDIS1;
+ bfin_write_TIMER_DISABLE(TIMDIS1);
SSYNC();
}
void EnableTIMER12(void)
{
- *pTIMER_ENABLE |= TIMEN1 | TIMEN0;
+ bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
SSYNC();
}
int video_init(void *dst)
{
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
Init_PPI();
EnablePPI();
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
EnableTIMER12();
#else
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
DisableDMA();
DisableTIMER0();
DisableTIMER1();
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
#endif
}
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 SDP board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+
+ /* Enable access to parallel flash */
+ gpio_request(GPIO_PG0, "parallel-flash");
+ gpio_direction_output(GPIO_PG0, 0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /* CLKIN Buffer Output Enable */
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+
+ return 0;
+}
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# MA 02111-1307 USA
#
-#
-# ATC boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_atc.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
-TEXT_BASE := 0xFF000000
+CONFIG_BFIN_CPU = bf527-0.2
-# RAM version
-#TEXT_BASE := 0x100000
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_STAMP_CF) += ide-cf.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
for (divisor = 0; sclk > 0; divisor++)
sclk -= 57600 * 16;
- *pPORTF_FER = 0x000F;
- *pPORTH_FER = 0xFFFF;
+ bfin_write_PORTF_FER(0x000F);
+ bfin_write_PORTH_FER(0xFFFF);
- *pUART_GCTL = 0x00;
- *pUART_LCR = 0x83;
+ bfin_write_UART_GCTL(0x00);
+ bfin_write_UART_LCR(0x83);
SSYNC();
- *pUART_DLL = (divisor & 0xFF);
+ bfin_write_UART_DLL(divisor & 0xFF);
SSYNC();
- *pUART_DLH = ((divisor >> 8) & 0xFF);
+ bfin_write_UART_DLH((divisor >> 8) & 0xFF);
SSYNC();
- *pUART_LCR = 0x03;
+ bfin_write_UART_LCR(0x03);
SSYNC();
- *pUART_GCTL = 0x01;
+ bfin_write_UART_GCTL(0x01);
SSYNC();
}
;
i = 0;
while ((buff[i] != '\0') && (i != 100)) {
- while (!(*pUART_LSR & 0x20)) ;
- *pUART_THR = buff[i];
+ while (!(bfin_read_pUART_LSR() & 0x20)) ;
+ bfin_write_UART_THR(buff[i]);
SSYNC();
i++;
}
int i, n;
unsigned short value;
- *pPORTF_FER &= ~PF5;
- *pPORTFIO_DIR &= ~PF5;
- *pPORTFIO_INEN |= PF5;
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5);
+ bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5);
+ bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5);
SSYNC();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
- value = *pPORTFIO & PF5;
- if (*pUART0_RBR == 0x0D) {
+ value = bfin_read_PORTFIO() & PF5;
+ if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
post_out_buff("\b2\0");
for (i = 0; i < KEY_LOOP; i++) {
- value = *pPORTFIO & PF5;
- if (*pUART0_RBR == 0x0D) {
+ value = bfin_read_PORTFIO() & PF5;
+ if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
post_out_buff("\b1\0");
for (i = 0; i < KEY_LOOP; i++) {
- value = *pPORTFIO & PF5;
- if (*pUART0_RBR == 0x0D) {
+ value = bfin_read_PORTFIO() & PF5;
+ if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
void post_init_pll(int mult, int div)
{
- *pSIC_IWR = 0x01;
- *pPLL_CTL = (mult << 9);
- *pPLL_DIV = div;
+ bfin_write_SIC_IWR(0x01);
+ bfin_write_PLL_CTL((mult << 9));
+ bfin_write_PLL_DIV(div);
asm("CLI R2;");
asm("IDLE;");
asm("STI R2;");
- while (!(*pPLL_STAT & 0x20)) ;
+ while (!(bfin_read_PLL_STAT() & 0x20)) ;
}
int post_init_sdram(int sclk)
SSYNC();
- *pEBIU_SDGCTL |= 0x1000000;
+ bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
/* Set the SDRAM Refresh Rate control register based on SSCLK value */
- *pEBIU_SDRRC = mem_SDRRC;
+ bfin_write_EBIU_SDRRC(mem_SDRRC);
/* SDRAM Memory Bank Control Register */
- *pEBIU_SDBCTL = mem_SDBCTL;
+ bfin_write_EBIU_SDBCTL(mem_SDBCTL);
/* SDRAM Memory Global Control Register */
- *pEBIU_SDGCTL = mem_SDGCTL;
+ bfin_write_EBIU_SDGCTL(mem_SDGCTL);
SSYNC();
return mem_SDRRC;
}
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
int i;
unsigned short value;
- *pPORTF_FER &= ~PF5;
- *pPORTFIO_DIR &= ~PF5;
- *pPORTFIO_INEN |= PF5;
+ gpio_request(GPIO_PF5, "post");
+ gpio_direction_input(GPIO_PF5);
printf("########Press SW10 to enter Memory POST########: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF5;
+ value = gpio_get_value(GPIO_PF5);
if (value != 0) {
break;
}
printf("Hotkey has been pressed, Enter POST . . . . . .\n");
return 1;
}
+
+ gpio_free(GPIO_PF5);
}
int uart_post_test(int flags)
****************************************************/
int led_post_test(int flags)
{
- *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
- *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
- udelay(1000000);
- printf("LED1 on");
- *pPORTFIO |= PF6;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED2 on");
- *pPORTFIO |= PF7;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED3 on");
- *pPORTFIO |= PF8;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED4 on");
- *pPORTFIO |= PF9;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("LED5 on");
- *pPORTFIO |= PF10;
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- printf("lED6 on");
- *pPORTFIO |= PF11;
- printf("\b\b\b\b\b\b\b ");
+ unsigned int leds[] = {
+ GPIO_PF6, GPIO_PF7, GPIO_PF8,
+ GPIO_PF9, GPIO_PF10, GPIO_PF11,
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(leds); ++i) {
+ gpio_request(leds[i], "post");
+ gpio_direction_output(leds[i], 0);
+
+ printf("LED%i on", i + 1);
+ gpio_set_value(leds[i], 1);
+ udelay(1000000);
+ printf("\b\b\b\b\b\b\b");
+
+ gpio_free(leds[i]);
+ }
+
return 0;
}
************************************************/
int button_post_test(int flags)
{
+ unsigned int buttons[] = {
+ GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5,
+ };
+ unsigned int sws[] = { 13, 12, 11, 10, };
int i, delay = 5;
unsigned short value = 0;
int result = 0;
- *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
- *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
- *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
+ for (i = 0; i < ARRAY_SIZE(buttons); ++i) {
+ gpio_request(buttons[i], "post");
+ gpio_direction_input(buttons[i]);
- printf("\n--------Press SW10: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF5;
- if (value != 0) {
- break;
+ delay = 5;
+ printf("\n--------Press SW%i: %2d ", sws[i], delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = gpio_get_value(buttons[i]);
+ if (value != 0)
+ break;
+ udelay(10000);
}
- udelay(10000);
+ printf("\b\b\b%2d ", delay);
}
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
-
- delay = 5;
- printf("\n--------Press SW11: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF4;
- if (value != 0) {
- break;
- }
- udelay(10000);
+ if (value != 0)
+ puts("\b\bOK");
+ else {
+ result = -1;
+ puts("\b\bfailed");
}
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
- delay = 5;
- printf("\n--------Press SW12: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF3;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
+ gpio_free(buttons[i]);
}
- delay = 5;
- printf("\n--------Press SW13: %2d ", delay);
- while (delay--) {
- for (i = 0; i < 100; i++) {
- value = *pPORTFIO & PF2;
- if (value != 0) {
- break;
- }
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- printf("\b\bOK");
- else {
- result = -1;
- printf("\b\bfailed");
- }
- printf("\n");
+ puts("\n");
+
return result;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf538-0.4
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_VIDEO) += video.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf548-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
{
#if defined(CONFIG_DEB_DMA_URGENT)
- *pEBIU_DDRQUE |= DEB2_URGENT;
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
#endif
- *pDMA12_START_ADDR = dst;
+ bfin_write_DMA12_START_ADDR(dst);
/* X count */
- *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
- *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+ bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
/* Y count */
- *pDMA12_Y_COUNT = LCD_Y_RES;
- *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+ bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
/* DMA Config */
- *pDMA12_CONFIG =
+ bfin_write_DMA12_CONFIG(
WDSIZE_32 | /* 32 bit DMA */
DMA2D | /* 2D DMA */
- FLOW_AUTO; /* autobuffer mode */
+ FLOW_AUTO /* autobuffer mode */
+ );
}
void Init_Ports(void)
void EnableDMA(void)
{
- *pDMA12_CONFIG |= DMAEN;
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
}
void DisableDMA(void)
{
- *pDMA12_CONFIG &= ~DMAEN;
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
}
/* enable and disable PPI functions */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.3
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf532-0.5
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/* U-boot - blackvme.c board specific routines
+ * (c) Wojtek Skulski 2010 info@skutek.com
+ * Board info: http://www.skutek.com
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ printf("Board: BlackVME\n");
+ printf("Support: http://www.skutek.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+/*
+ * The ax88180 driver had to be patched to work around a bug
+ * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
+ */
+int board_eth_init(bd_t *bis)
+{
+ return ax88180_initialize(bis);
+}
+#endif /* CONFIG_DRIVER_AX88180 */
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# MA 02111-1307 USA
#
-#
-# CU824 board
-#
+# This is not actually used for Blackfin boards so do not change it
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
-TEXT_BASE = 0xFFF00000
+CONFIG_BFIN_CPU = bf561-0.5
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
#
#
-# CU824 board
+# BMW board
#
-TEXT_BASE = 0xFFF00000
# NOTE: The flags below affect how the BCM570x driver is compiled
PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
- -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\
- -DTEXT_BASE=$(TEXT_BASE)
+ -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TTTech C2MON boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ net/libnet.o (.text*)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += sbc35_a9g20.o
COBJS-$(CONFIG_ATMEL_SPI) += spi.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += tny_a9260.o
COBJS-$(CONFIG_ATMEL_SPI) += spi.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
#$(shell mkdir -p $(obj)../common)
#endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
#../common/flash.o ../common/vpd.o ../common/am79c874.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2003
-# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CANMB board
-#
-# allowed and functional TEXT_BASE values:
-#
-# 0xfe000000 low boot at 0x00000100 (default board setting)
-# 0x00100000 RAM load and test
-#
-
-TEXT_BASE = 0xFE000000
-#TEXT_BASE = 0x00100000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cerf250.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of cerf PXA Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_NET
+++ /dev/null
-#
-# Cerf board with PXA250 cpu
-#
-#
-TEXT_BASE = 0xa3080000
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field, set SDRAM clocks free running */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
-
- ldr r0, [r1, #MDREFR_OFFSET]
- bic r0, r0, r2
- bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
- orr r0, r0, r3
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
- MDREFR_K2RUN |MDREFR_K2DB2)
- and r4, r4, r2
- bic r0, r0, r2
- orr r0, r0, r4
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r0, r0, #(MDREFR_SLFRSH)
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
- MDREFR_K1FREE | MDREFR_K2FREE)
- and r4, r4, r2
- orr r0, r0, r4
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
-.rept 8
- str r2, [r3]
-.endr
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o gpio_cfi_flash.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
-#include "gpio_cfi_flash.h"
+#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf527-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-#define GPIO_PIN_1 GPIO_PH9
-#define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2 GPIO_PG11
-#define GPIO_MASK_2 (1 << 22)
-#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
- unsigned long addr = (unsigned long)vaddr;
-
- gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_MASK_2
- gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
- SSYNC();
-
- return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
- __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
- return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
- gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-#ifdef GPIO_MASK_2
- gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
-#endif
- gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
-}
+#define GPIO_PIN_1 GPIO_PH9
+#define GPIO_PIN_2 GPIO_PG11
+#include "../cm-bf537e/gpio_cfi_flash.c"
+++ /dev/null
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf533-0.3
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o gpio_cfi_flash.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
/*
* gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
*
- * Copyright (c) 2009 Analog Devices Inc.
+ * Copyright (c) 2009-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/io.h>
#include "gpio_cfi_flash.h"
+/* Allow this driver to be shared among boards */
+#ifndef GPIO_PIN_1
#define GPIO_PIN_1 GPIO_PF4
+#endif
#define GPIO_MASK_1 (1 << 21)
-#define GPIO_MASK (GPIO_MASK_1)
+#ifndef GPIO_PIN_2
+#define GPIO_MASK_2 (0)
+#else
+#define GPIO_MASK_2 (1 << 22)
+#endif
+#ifndef GPIO_PIN_3
+#define GPIO_MASK_3 (0)
+#else
+#define GPIO_MASK_3 (1 << 23)
+#endif
+#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
void *gpio_cfi_flash_swizzle(void *vaddr)
{
gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-#ifdef GPIO_MASK_2
+#ifdef GPIO_PIN_2
gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
+#ifdef GPIO_PIN_3
+ gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
+#endif
+
SSYNC();
+ udelay(1);
return (void *)(addr & ~GPIO_MASK);
}
void gpio_cfi_flash_init(void)
{
gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-#ifdef GPIO_MASK_2
+ gpio_direction_output(GPIO_PIN_1, 0);
+#ifdef GPIO_PIN_2
gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+ gpio_direction_output(GPIO_PIN_2, 0);
+#endif
+#ifdef GPIO_PIN_3
+ gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
+ gpio_direction_output(GPIO_PIN_3, 0);
#endif
- gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o gpio_cfi_flash.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
-#include "gpio_cfi_flash.h"
+#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-#define GPIO_PIN_1 GPIO_PH0
-#define GPIO_MASK_1 (1 << 21)
-#define GPIO_MASK (GPIO_MASK_1)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
- unsigned long addr = (unsigned long)vaddr;
-
- gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_MASK_2
- gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
- SSYNC();
-
- return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
- __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
- return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
- gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-#ifdef GPIO_MASK_2
- gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
-#endif
- gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
-}
+#define GPIO_PIN_1 GPIO_PH0
+#include "../cm-bf537e/gpio_cfi_flash.c"
+++ /dev/null
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_VIDEO) += video.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf548-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
void Init_DMA(void *dst)
{
-
#if defined(CONFIG_DEB_DMA_URGENT)
- *pEBIU_DDRQUE |= DEB2_URGENT;
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
#endif
- *pDMA12_START_ADDR = dst;
+ bfin_write_DMA12_START_ADDR(dst);
/* X count */
- *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
- *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+ bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
/* Y count */
- *pDMA12_Y_COUNT = LCD_Y_RES;
- *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
+ bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+ bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
/* DMA Config */
- *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */
+ bfin_write_DMA12_CONFIG(
+ WDSIZE_32 | /* 32 bit DMA */
DMA2D | /* 2D DMA */
- FLOW_AUTO; /* autobuffer mode */
+ FLOW_AUTO /* autobuffer mode */
+ );
}
void Init_Ports(void)
void EnableDMA(void)
{
- *pDMA12_CONFIG |= DMAEN;
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
}
void DisableDMA(void)
{
- *pDMA12_CONFIG &= ~DMAEN;
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
}
/* enable and disable PPI functions */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.3
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cm4008.o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00f00000
+CONFIG_SYS_TEXT_BASE = 0x00f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cm41xx.o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x00f00000
+CONFIG_SYS_TEXT_BASE = 0x00f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o cmd_cm5200.o fwupdate.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xfc000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
#include "fwupdate.h"
-extern int do_bootm(cmd_tbl_t *, int, int, char * const []);
extern long do_fat_read(const char *, void *, unsigned long, int);
extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x20F00000
+CONFIG_SYS_TEXT_BASE = 0x20F00000
## For testing: load at 0x20100000 and "go" at 0x201000A4
-#TEXT_BASE = 0x20100000
+#CONFIG_SYS_TEXT_BASE = 0x20100000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := flash.o cmi.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EPQ Board Configuration
-#
-
-# Boot from flash at location 0x00000000
-TEXT_BASE = 0x02000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
(NONE means use Cogent motherboard serial port A).
-Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be
+Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be
the base address of the EPROM for the CPU module. This should be the
same as the value selected for CONFIG_SYS_MONITOR_BASE in
"include/config_cogent_*.h" (in fact, I have made this automatic via
-the -DTEXT_BASE=... option in CPPFLAGS).
+the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS).
Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
# Cogent Modular Architecture
#
-# Boot EPROM location
-TEXT_BASE = 0xfff00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
LDSCRIPT := $(SRCTREE)/board/cogent/u-boot.lds
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
+#include <config.h>
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- *(.text)
- common/env_embedded.o(.text)
- *(.got1)
+#ifdef CONFIG_MPC8260
+ arch/powerpc/cpu/mpc8260/start.o (.text*)
+#else
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+#endif
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := colibri_pxa270.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
return 0;
}
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (UHCHR & UHCHR_FSBIR);
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
+++ /dev/null
-TEXT_BASE = 0xa1000000
+++ /dev/null
-/*
- * Toradex Colibri PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
-
- mov pc, lr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o plx9030.o pd67290.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPC45 board
-#
-
-
-ifeq ($(CONFIG_BOOT_ROM),y)
- TEXT_BASE := 0xFFF00000
- PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
-else
- TEXT_BASE := 0xFFF00000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
#define HOST_TO_PCI(addr) ((addr) - 0xfe000000)
#define PCI_TO_HOST(addr) ((addr) + 0xfe000000)
-int i82365_init (void)
+static int i82365_init (void)
{
u_int val;
int i;
return 0;
}
-void i82365_exit (void)
+static void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPU86 boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_CPU86.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-
-ifeq ($(CONFIG_BOOT_ROM),y)
- TEXT_BASE := 0xFF800000
- PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
-else
- TEXT_BASE := 0xFF000000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CPU87 board
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in configs/cpu87.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-
-ifeq ($(CONFIG_BOOT_ROM),y)
- TEXT_BASE := 0xFF800000
- PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
-else
- TEXT_BASE := 0xFF000000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cradle.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE = 0xa0f80000
-#TEXT_BASE = 0
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int shift = led * 2;
unsigned long mask = 0x3 << shift;
- CRADLE_LED_CLR_REG = mask; /* clear bits */
- CRADLE_LED_SET_REG = (color << shift); /* set bits */
+ writel(mask, GPCR2); /* clear bits */
+ writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}
board_init (void)
/**********************************************************/
{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
led_code (0xf, YELLOW);
/* arch number of HHP Cradle */
return 1;
}
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return (PHYS_SDRAM_1_SIZE +
- PHYS_SDRAM_2_SIZE +
- PHYS_SDRAM_3_SIZE +
- PHYS_SDRAM_4_SIZE );
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
- .macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
- ldr r7, =0
- str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
- ldr r7, =\val
- str r7, [r6]
- .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- SET_LED 1
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- SET_LED 2
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End lowlevel_init
}
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
- return (L1_MEMSIZE);
-}
-
-/* ------------------------------------------------------------------------- */
/* stubs so we can print dates w/o any nvram RTC.*/
int rtc_get (struct rtc_time *tmp)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
# built in the depend stage. So... put bootscript.o here, not in OBJS
$(LIB): $(OBJS) $(SOBJS) $(obj)bootscript.o
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS) $(obj)bootscript.c \
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Note: I make an "image" from U-Boot itself, which prefixes 0x40 bytes of
-# header info, hence start address is thus shifted.
-TEXT_BASE = 0xFFFD0040
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := csb226.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-TEXT_BASE = 0xa1fe0000
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of CSB226 board */
gd->bd->bi_arch_number = MACH_TYPE_CSB226;
}
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
-
/**
* csb226_set_led: - switch LEDs on or off
*
switch(led) {
case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
+ writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED0;
+ writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
+ writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
+ writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
+ writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
+ writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
#COBJS = $(BOARD).o flash.o
#COBJS = $(BOARD).o strataflash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004
-# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Cogent CSB272 board
-#
-
-LDFLAGS += $(LINKER_UNDEFS)
-
-TEXT_BASE := 0xFFFC0000
-#TEXT_BASE := 0x00100000
-
-PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
#COBJS = $(BOARD).o flash.o
#COBJS = $(BOARD).o strataflash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004
-# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Cogent CSB472 board
-#
-
-LDFLAGS += $(LINKER_UNDEFS)
-
-TEXT_BASE := 0xFFFC0000
-#TEXT_BASE := 0x00100000
-
-PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := csb637.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23fc0000
+CONFIG_SYS_TEXT_BASE = 0x23fc0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := B2.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x0C100000
+CONFIG_SYS_TEXT_BASE = 0x0C100000
PLATFORM_CPPFLAGS += -Uarm
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000, 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Reserve 256 kB for Monitor
-#TEXT_BASE = 0xFFFC0000
-
-# Reserve 320 kB for Monitor
-TEXT_BASE = 0xFFFB0000
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
+#include "config.h" /* CONFIG_BOARDDIR */
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
OUTPUT_ARCH(powerpc)
-SECTIONS
+PHDRS
{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+SECTIONS
+{
/* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
+ . = + SIZEOF_HEADERS;
+ .text :
{
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- *(.text)
- *(.got1)
- }
+ *(.text*)
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
+ } :text
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
- .data :
+ .data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(256);
__init_end = .;
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
+ . = 0xFFFF8000;
+ .ppcenv :
+ {
+ common/env_embedded.o(.ppcenv);
+ }
+
+ .resetvec RESET_VECTOR_ADDRESS :
+ {
+ KEEP(*(.resetvec))
+ } :text = 0xffff
+
+ . = RESET_VECTOR_ADDRESS + 0x4;
+
+ /*
+ * Make sure that the bss segment isn't linked at 0x0, otherwise its
+ * address won't be updated during relocation fixups. Note that
+ * this is a temporary fix. Code to dynamically the fixup the bss
+ * location will be added in the future. When the bss relocation
+ * fixup code is present this workaround should be removed.
+ */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+ . |= 0x10;
+#endif
+
__bss_start = .;
- .bss (NOLOAD) :
+ .bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
- . = ALIGN(4);
- }
+ } :bss
+
+ . = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
tmp & 0x000000FF
);
-#ifdef CONFIG_FSL_DIU_FB
-# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
- mpc5121_diu_init();
-# endif
-#endif
return 0;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := qong.o
+COBJS := qong.o fpga.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0xa0000000
+CONFIG_SYS_TEXT_BASE = 0xa0000000
# PLATFORM_CPPFLAGS += -DDEBUG
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <mxc_gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+ return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+ return mxc_gpio_get(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+ qong_jtag_init,
+ qong_fpga_jtag_set_tdi,
+ qong_fpga_jtag_set_tms,
+ qong_fpga_jtag_set_tck,
+ qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+ {
+ Lattice_XP2,
+ lattice_jtag_mode,
+ 356519,
+ (void *) &qong_fpga_fns,
+ NULL,
+ 0,
+ "lfxp2_5e_ftbga256"
+ },
+};
+
+int qong_fpga_init(void)
+{
+ int i;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ fpga_add(fpga_lattice, &qong_fpga[i]);
+ }
+ return 0;
+}
+
+#endif
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
#include <nand.h>
#include <fsl_pmic.h>
+#include <mxc_gpio.h>
#include "qong_fpga.h"
DECLARE_GLOBAL_DATA_PTR;
static void qong_fpga_reset(void)
{
- mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+ mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
udelay(30);
- mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+ mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
udelay(300);
}
/* FPGA reset Pin */
/* rstn = 0 */
- mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
- mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+ mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
/* set interrupt pin as input */
- mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
-
+ mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
+
+ /* FPGA JTAG Interface */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+ mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
#endif
/* setup pins for UART1 */
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ /* Setup pins for USB2 Host */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+ mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+ mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+ mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
+ mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
+ mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
+ mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
+ mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
+ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
+
+ writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_QONG;
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+ qong_fpga_init();
+
return 0;
}
qong_fpga_reset();
/* Enable NAND flash */
- mx31_gpio_set(15, 1);
- mx31_gpio_set(14, 1);
- mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT);
- mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN);
- mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN);
- mx31_gpio_set(15, 0);
+ mxc_gpio_set(15, 1);
+ mxc_gpio_set(14, 1);
+ mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
+ mxc_gpio_set(15, 0);
}
int qong_nand_rdy(void *chip)
{
udelay(1);
- return mx31_gpio_get(16);
+ return mxc_gpio_get(16);
}
void qong_nand_select_chip(struct mtd_info *mtd, int chip)
{
if (chip >= 0)
- mx31_gpio_set(15, 0);
+ mxc_gpio_set(15, 0);
else
- mx31_gpio_set(15, 1);
+ mxc_gpio_set(15, 1);
}
#ifndef QONG_FPGA_H
#define QONG_FPGA_H
-#ifdef CONFIG_QONG_FPGA
#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_TDO_PIN 7
#define QONG_FPGA_RST_PIN 48
#define QONG_FPGA_IRQ_PIN 40
-#endif
+int qong_fpga_init(void);
#endif /* QONG_FPGA_H */
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)lib$(VENDOR).o
-COBJS := misc.o
+COBJS := misc.o davinci_pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
--- /dev/null
+/*
+ * DaVinci pinmux functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+ const int n_pins)
+{
+ int i;
+
+ /* check for invalid pinmux values */
+ for (i = 0; i < n_pins; i++) {
+ if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+ (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+ return -1;
+ }
+
+ /* configure the pinmuxes */
+ for (i = 0; i < n_pins; i++) {
+ const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+ const unsigned int value = pins[i].value << offset;
+ const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+ const dv_reg *mux = pins[i].mux;
+
+ writel(value | (readl(mux) & (~mask)), mux);
+ }
+
+ return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ * PINMUX_ITEM(uart_pins),
+ * PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++) {
+ if (davinci_configure_pin_mux(item[i].pins,
+ item[i].n_pins) != 0)
+ return -1;
+ }
+
+ return 0;
+}
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
-#include "misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return(0);
-}
-#else
+#ifndef CONFIG_PRELOADER
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
return 0;
}
-/* If there is a MAC address in the environment, and if it is not identical to
- * the MAC address in the EEPROM, then a warning is printed and the MAC address
- * from the environment is used.
- *
+/*
+ * Set the mii mode as MII or RMII
+ */
+#if defined(CONFIG_DRIVER_TI_EMAC)
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+ int val;
+
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ if (mode_sel == 0)
+ val &= ~(1 << 8);
+ else
+ val |= (1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+#endif
+/*
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the EEPROM.
*/
-void dv_configure_mac_address(uint8_t *rom_enetaddr)
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
{
- int i;
- u_int8_t env_enetaddr[6];
- char *tmp = getenv("ethaddr");
- char *end;
-
- /* Read Ethernet MAC address from the U-Boot environment.
- * If it is not defined, env_enetaddr[] will be cleared. */
- for (i = 0; i < 6; i++) {
- env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
- }
-
- /* Check if EEPROM and U-Boot environment MAC addresses match. */
- if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
- memcmp(env_enetaddr, rom_enetaddr, 6) != 0) {
- printf("Warning: MAC addresses don't match:\n");
- printf(" EEPROM MAC address: %pM\n", rom_enetaddr);
- printf(" \"ethaddr\" value: %pM\n", env_enetaddr) ;
- debug("### Using MAC address from environment\n");
- }
- if (!tmp) {
- char ethaddr[20];
+ uint8_t env_enetaddr[6];
+ eth_getenv_enetaddr_by_index(0, env_enetaddr);
+ if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
/* There is no MAC address in the environment, so we initialize
* it from the value in the EEPROM. */
- sprintf(ethaddr, "%pM", rom_enetaddr) ;
- debug("### Setting environment from EEPROM MAC address = \"%s\"\n",
- ethaddr);
- setenv("ethaddr", ethaddr);
+ debug("### Setting environment from EEPROM MAC address = "
+ "\"%pM\"\n",
+ env_enetaddr);
+ eth_setenv_enetaddr("ethaddr", rom_enetaddr);
}
}
-#endif /* DAVINCI_EMAC */
+#endif /* CONFIG_DRIVER_TI_EMAC */
-/*
- * Change the setting of a pin multiplexer field.
- *
- * Takes an array of pinmux settings similar to:
- *
- * struct pinmux_config uart_pins[] = {
- * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
- * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
- * };
- *
- * Stepping through the array, each pinmux[n] register has the given value
- * set in the pin mux field specified.
- *
- * The number of pins in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Returns 0 if all field numbers and values are in the correct range,
- * else returns -1.
- */
-int davinci_configure_pin_mux(const struct pinmux_config *pins,
- const int n_pins)
+#if defined(CONFIG_SOC_DA8XX)
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
{
- int i;
-
- /* check for invalid pinmux values */
- for (i = 0; i < n_pins; i++) {
- if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
- (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
- return -1;
- }
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
- /* configure the pinmuxes */
- for (i = 0; i < n_pins; i++) {
- const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
- const unsigned int value = pins[i].value << offset;
- const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
- const dv_reg *mux = pins[i].mux;
+ writel(0, &davinci_aintc_regs->ger);
- writel(value | (readl(mux) & (~mask)), mux);
- }
+ writel(0, &davinci_aintc_regs->hier);
- return 0;
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
}
+#endif
/*
- * Configure multiple pinmux resources.
- *
- * Takes an pinmux_resource array of pinmux_config and pin counts:
- *
- * const struct pinmux_resource pinmuxes[] = {
- * PINMUX_ITEM(uart_pins),
- * PINMUX_ITEM(i2c_pins),
- * };
- *
- * The number of items in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Each item entry is configured in the defined order. If configuration
- * of any item fails, -1 is returned and none of the following items are
- * configured. On success, 0 is returned.
+ * Enable PSC for various peripherals.
*/
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items)
{
int i;
- for (i = 0; i < n_items; i++) {
- if (davinci_configure_pin_mux(item[i].pins,
- item[i].n_pins) != 0)
- return -1;
- }
+ for (i = 0; i < n_items; i++)
+ lpsc_on(item[i].lpsc_no);
return 0;
}
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS-y += common.o
COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
+COBJS-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
COBJS := $(COBJS-y)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-/*
- * Miscellaneous DA8XX functions.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include "common.h"
-
-#ifndef CONFIG_USE_IRQ
-void irq_init(void)
-{
- /*
- * Mask all IRQs by clearing the global enable and setting
- * the enable clear for all the 90 interrupts.
- */
-
- writel(0, &davinci_aintc_regs->ger);
-
- writel(0, &davinci_aintc_regs->hier);
-
- writel(0xffffffff, &davinci_aintc_regs->ecr1);
- writel(0xffffffff, &davinci_aintc_regs->ecr2);
- writel(0xffffffff, &davinci_aintc_regs->ecr3);
-}
-#endif
-
-/*
- * Enable PSC for various peripherals.
- */
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++)
- lpsc_on(item[i].lpsc_no);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __COMMON_H
-#define __COMMON_H
-
-struct lpsc_resource {
- const int lpsc_no;
-};
-
-void irq_init(void);
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- int n_items);
-
-#endif /* __COMMON_H */
+++ /dev/null
-#
-# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
-# Physical Address:
-# C000'0000 to C400'0000
-#
-# Linux-Kernel is expected to be at C000'8000, entry C000'8000
-# (mem base + reserved)
-#
-# we load ourself to C108 '0000
-
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0xC1080000
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../common/misc.h"
-#include "common.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
{
u_int8_t mac_addr[6];
u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
+ struct eth_device *dev;
/* Read Ethernet MAC address from EEPROM */
if (dvevm_read_mac_address(mac_addr))
/* set address env if not already set */
- dv_configure_mac_address(mac_addr);
+ davinci_sync_env_enetaddr(mac_addr);
/* read the address back from env */
if (!eth_getenv_enetaddr("ethaddr", mac_addr))
return -1;
- /* provide the resulting addr to the driver */
- davinci_eth_set_mac_addr(mac_addr);
-
/* enable the Ethernet switch in the 3 port PHY */
if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
switch_start_cmd, sizeof(switch_start_cmd))) {
return -1;
}
+ dev = eth_get_dev();
+
+ /* provide the resulting addr to the driver */
+ memcpy(dev->enetaddr, mac_addr, 6);
+ dev->write_hwaddr(dev);
+
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#include <common.h>
#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../common/misc.h"
-#include "common.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
{ pinmux(4), 2, 5 }
};
+#ifdef CONFIG_DRIVER_TI_EMAC
+static const struct pinmux_config emac_pins[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 1 },
+#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
+ { pinmux(2), 8, 1 },
+ { pinmux(2), 8, 2 },
+ { pinmux(2), 8, 3 },
+ { pinmux(2), 8, 4 },
+ { pinmux(2), 8, 5 },
+ { pinmux(2), 8, 6 },
+ { pinmux(2), 8, 7 },
+ { pinmux(3), 8, 0 },
+ { pinmux(3), 8, 1 },
+ { pinmux(3), 8, 2 },
+ { pinmux(3), 8, 3 },
+ { pinmux(3), 8, 4 },
+ { pinmux(3), 8, 5 },
+ { pinmux(3), 8, 6 },
+ { pinmux(3), 8, 7 },
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
{ pinmux(4), 2, 2 },
{ pinmux(4), 2, 3 }
};
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 1 },
+ { pinmux(7), 1, 2 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(9), 1, 0 },
+ { pinmux(9), 1, 1 },
+ { pinmux(9), 1, 2 },
+ { pinmux(9), 1, 3 },
+ { pinmux(9), 1, 4 },
+ { pinmux(9), 1, 5 },
+ { pinmux(9), 1, 6 },
+ { pinmux(9), 1, 7 },
+ { pinmux(12), 1, 5 },
+ { pinmux(12), 1, 6 }
+};
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
#endif
PINMUX_ITEM(uart_pins),
PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(nand_pins),
+#endif
};
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_GPIO },
};
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
+#endif
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3] Maximum cpu clock rate supported by onboard SoC
+ * 0000b - 300 MHz
+ * 0001b - 372 MHz
+ * 0010b - 408 MHz
+ * 0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+ char *s;
+ u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+ u32 rev = 0;
+
+ s = getenv("maxcpuclk");
+ if (s)
+ maxcpuclk = simple_strtoul(s, NULL, 10);
+
+ if (maxcpuclk >= 456000000)
+ rev = 3;
+ else if (maxcpuclk >= 408000000)
+ rev = 2;
+ else if (maxcpuclk >= 372000000)
+ rev = 1;
+
+ return rev;
+}
+
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+ /*
+ * NAND CS setup - cycle counts based on da850evm NAND timings in the
+ * Linux kernel @ 25MHz EMIFA
+ */
+ writel((DAVINCI_ABCR_WSETUP(0) |
+ DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WHOLD(0) |
+ DAVINCI_ABCR_RSETUP(0) |
+ DAVINCI_ABCR_RSTROBE(1) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
+#ifdef CONFIG_DRIVER_TI_EMAC
+ if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+ return 1;
+
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
return 0;
}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ * DA850/OMAP-L138 EVM can interface to a daughter card for
+ * additional features. This card has an I2C GPIO Expander TCA6416
+ * to select the required functions like camera, RMII Ethernet,
+ * character LCD, video.
+ *
+ * Initialization of the expander involves configuring the
+ * polarity and direction of the ports. P07-P05 are used here.
+ * These ports are connected to a Mux chip which enables only one
+ * functionality at a time.
+ *
+ * For RMII phy to respond, the MII MDIO clock has to be disabled
+ * since both the PHY devices have address as zero. The MII MDIO
+ * clock is controlled via GPIO2[6].
+ *
+ * This code is valid for Beta version of the hardware
+ */
+int rmii_hw_init(void)
+{
+ const struct pinmux_config gpio_pins[] = {
+ { pinmux(6), 8, 1 }
+ };
+ u_int8_t buf[2];
+ unsigned int temp;
+ int ret;
+
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* I2C Exapnder configuration */
+ /* Set polarity to non-inverted */
+ buf[0] = 0x0;
+ buf[1] = 0x0;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ return ret;
+ }
+
+ /* Configure P07-P05 as outputs */
+ buf[0] = 0x1f;
+ buf[1] = 0xff;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* For Ethernet RMII selection
+ * P07(SelA)=0
+ * P06(SelB)=1
+ * P05(SelC)=1
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x read FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ buf[0] &= 0x1f;
+ buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
+ if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* Set the output as high */
+ temp = REG(GPIO_BANK2_REG_SET_ADDR);
+ temp |= (0x01 << 6);
+ REG(GPIO_BANK2_REG_SET_ADDR) = temp;
+
+ /* Set the GPIO direction as output */
+ temp = REG(GPIO_BANK2_REG_DIR_ADDR);
+ temp &= ~(0x01 << 6);
+ REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ /* Select RMII fucntion through the expander */
+ if (rmii_hw_init())
+ printf("RMII hardware init failed!!!\n");
+#endif
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
--- /dev/null
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Kick Registers need to be set to allow access to Pin Mux registers
+ */
+ writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ /* set cfgchip3 to select mii */
+ writel(readl(&davinci_syscfg_regs->cfgchip3) &
+ ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ char buf[32];
+
+ printf("ARM Clock : %s MHz\n",
+ strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+
+ return 0;
+}
--- /dev/null
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+static const struct pinmux_config mii_pins[] = {
+ { pinmux(2), 8, 1 },
+ { pinmux(2), 8, 2 },
+ { pinmux(2), 8, 3 },
+ { pinmux(2), 8, 4 },
+ { pinmux(2), 8, 5 },
+ { pinmux(2), 8, 6 },
+ { pinmux(2), 8, 7 }
+};
+
+static const struct pinmux_config mdio_pins[] = {
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+
+static const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 1 },
+ { pinmux(7), 1, 2 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(9), 1, 0 },
+ { pinmux(9), 1, 1 },
+ { pinmux(9), 1, 2 },
+ { pinmux(9), 1, 3 },
+ { pinmux(9), 1, 4 },
+ { pinmux(9), 1, 5 },
+ { pinmux(9), 1, 6 },
+ { pinmux(9), 1, 7 },
+ { pinmux(12), 1, 5 },
+ { pinmux(12), 1, 6 }
+};
+
+static const struct pinmux_config uart2_pins[] = {
+ { pinmux(0), 4, 6 },
+ { pinmux(0), 4, 7 },
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_config i2c_pins[] = {
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(mii_pins),
+ PINMUX_ITEM(mdio_pins),
+ PINMUX_ITEM(i2c_pins),
+ PINMUX_ITEM(nand_pins),
+ PINMUX_ITEM(uart2_pins),
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+void board_init_f(ulong bootflag)
+{
+ /*
+ * Kick Registers need to be set to allow access to Pin Mux registers
+ */
+ writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc);
+
+ /* Power on required peripherals
+ * ARM does not have acess by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc));
+
+ /* configure pinmux settings */
+ davinci_configure_pin_mux_items(pinmuxes,
+ ARRAY_SIZE(pinmuxes));
+
+ writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) |
+ (DAVINCI_UART_PWREMU_MGMT_FREE) |
+ (DAVINCI_UART_PWREMU_MGMT_URRST) |
+ (DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ NS16550_init((NS16550_t)(DAVINCI_UART2_BASE),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+ puts("Nand boot...\n");
+
+ nand_boot();
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r');
+
+ NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c);
+}
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <asm/arch/hardware.h>
#include <asm/arch/gpio_defs.h>
#include <asm/arch/nand_defs.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <asm/arch/nand_defs.h>
#include <asm/arch/gpio_defs.h>
#include <netdev.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
/* Read Ethernet MAC address from EEPROM */
if (dvevm_read_mac_address(eeprom_enetaddr))
- dv_configure_mac_address(eeprom_enetaddr);
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
davinci_emac_initialize();
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := board_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
- dv_configure_mac_address(eeprom_enetaddr);
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
i2c_read(0x39, 0x00, 1, &video_mode, 1);
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
# See file CREDITS for list of people who contributed to this
# project.
#
LIB = $(obj)lib$(BOARD).a
-COBJS := wepep250.o flash.o
-SOBJS := lowlevel_init.o
+COBJS-y += ea20.o
+
+COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
rm -f $(SOBJS) $(OBJS)
distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
+ rm -f $(LIB) core *.bak *~ .depend
#########################################################################
-
-# defines $(obj).depend target
+# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on da850evm.c, original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 5 }
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+ { pinmux(0), 4, 6 },
+ { pinmux(0), 4, 7 },
+ { pinmux(4), 2, 4 },
+ { pinmux(4), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define HAS_RMII 1
+static const struct pinmux_config emac_pins[] = {
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 1 },
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 1 },
+ { pinmux(7), 1, 2 },
+ { pinmux(7), 1, 4 },
+ { pinmux(7), 1, 5 },
+ { pinmux(9), 1, 0 },
+ { pinmux(9), 1, 1 },
+ { pinmux(9), 1, 2 },
+ { pinmux(9), 1, 3 },
+ { pinmux(9), 1, 4 },
+ { pinmux(9), 1, 5 },
+ { pinmux(9), 1, 6 },
+ { pinmux(9), 1, 7 },
+ { pinmux(12), 1, 5 },
+ { pinmux(12), 1, 6 }
+};
+#endif
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+ PINMUX_ITEM(spi1_pins),
+#endif
+ PINMUX_ITEM(uart_pins),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(nand_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+
+#ifdef CONFIG_NAND_DAVINCI
+ /*
+ * NAND CS setup - cycle counts based on da850evm NAND timings in the
+ * Linux kernel @ 25MHz EMIFA
+ */
+ writel((DAVINCI_ABCR_WSETUP(0) |
+ DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WHOLD(0) |
+ DAVINCI_ABCR_RSETUP(0) |
+ DAVINCI_ABCR_RSTROBE(1) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+ return 1;
+
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ /*
+ * This board has a RMII PHY. However, the MDC line on the SOM
+ * must not be disabled (there is no MII PHY on the
+ * baseboard) via the GPIO2[6], because this pin
+ * disables at the same time the SPI flash.
+ */
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := board_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
/* Set serial number from UID chip */
if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- forceenv("serial#", "FAILED");
+ setenv("serial#", "FAILED");
} else {
if (buf[0] != 0x70) {
/* Device Family Code */
printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- forceenv("serial#", "FAILED");
+ setenv("serial#", "FAILED");
}
}
/* Now check CRC */
if (tmp[0] != 0) {
printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
- forceenv("serial#", "FAILED");
+ setenv("serial#", "FAILED");
} else {
/* CRC OK, set "serial" env variable */
sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
- forceenv("serial#", (char *)&tmp[0]);
+ setenv("serial#", (char *)&tmp[0]);
}
return(0);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := board_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# we load ourself to 8400'0000 to provide at least 32MB spacing
# between us and the Integrity kernel image
-TEXT_BASE = 0x84000000
+CONFIG_SYS_TEXT_BASE = 0x84000000
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
/* Read Ethernet MAC address from EEPROM if available. */
if (sffsdr_read_mac_address(eeprom_enetaddr))
- dv_configure_mac_address(eeprom_enetaddr);
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
return(0);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := board_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-TEXT_BASE = 0x81080000
+CONFIG_SYS_TEXT_BASE = 0x81080000
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/hardware.h>
-#include "../common/misc.h"
+#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
- dv_configure_mac_address(eeprom_enetaddr);
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
return(0);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
NOTE! When you switch between the two boot flashes, the
base addresses will be swapped.
-Have this in mind when you compile u-boot. TEXT_BASE has
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
to match the address where u-boot is located when you
actually launch.
#
# ROM version
-TEXT_BASE = 0xbfc00000
+CONFIG_SYS_TEXT_BASE = 0xbfc00000
# RAM version
-#TEXT_BASE = 0x80100000
+#CONFIG_SYS_TEXT_BASE = 0x80100000
+++ /dev/null
-TEXT_BASE = 0x83008000
+++ /dev/null
-/*
- * (C) Copyright 2006
- * DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <da9030.h>
-#include <malloc.h>
-#include <command.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static void init_DA9030(void);
-static void keys_init(void);
-static void get_pressed_keys(uchar *s);
-static uchar *key_match(uchar *kbd_data);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* arch number of Lubbock-Board mk@tbd: fix this! */
- gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef DELTA_CHECK_KEYBD
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- char *str;
- int i;
-#endif /* DELTA_CHECK_KEYBD */
-
- setenv("stdout", "serial");
- setenv("stderr", "serial");
-
-#ifdef DELTA_CHECK_KEYBD
- keys_init();
-
- memset(kbd_data, '\0', KEYBD_DATALEN);
-
- /* check for pressed keys and setup keybd_env */
- get_pressed_keys(kbd_data);
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-
-# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-# endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
-#endif /* DELTA_CHECK_KEYBD */
-
- init_DA9030();
- return 0;
-}
-
-/*
- * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
- */
-#ifdef DELTA_CHECK_KEYBD
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-/*
- * Get pressed keys
- * s is a buffer of size KEYBD_DATALEN-1
- */
-static void get_pressed_keys(uchar *s)
-{
- unsigned long val;
- val = GPLR3;
-
- if(val & (1<<31))
- *s++ = KEYBD_KP_DKIN0;
- if(val & (1<<18))
- *s++ = KEYBD_KP_DKIN1;
- if(val & (1<<29))
- *s++ = KEYBD_KP_DKIN2;
- if(val & (1<<22))
- *s++ = KEYBD_KP_DKIN5;
-}
-
-static void keys_init()
-{
- CKENB |= CKENB_7_GPIO;
- udelay(100);
-
- /* Configure GPIOs */
- GPIO127 = 0xa840; /* KP_DKIN0 */
- GPIO114 = 0xa840; /* KP_DKIN1 */
- GPIO125 = 0xa840; /* KP_DKIN2 */
- GPIO118 = 0xa840; /* KP_DKIN5 */
-
- /* Configure GPIOs as inputs */
- GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
- GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
-
- udelay(100);
-}
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- /* uchar compare[KEYBD_DATALEN-1]; */
- uchar compare[KEYBD_DATALEN];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- /* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
- memcpy (compare, kbd_data, KEYBD_DATALEN);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
- printf ("### Check magic \"%s\"\n", magic);
-#endif
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
-#if 0
- printf ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
-#if 0
- printf ("### Delete PREBOOT\n");
-#endif
- *kbd_data = '\0';
- return (NULL);
-}
-
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- int i;
-
- /* Read keys */
- get_pressed_keys(kbd_data);
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-#endif /* DELTA_CHECK_KEYBD */
-
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
-}
-
-void i2c_init_board()
-{
- CKENB |= (CKENB_4_I2C);
-
- /* setup I2C GPIO's */
- GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
- GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
-}
-
-/* initialize the DA9030 Power Controller */
-static void init_DA9030()
-{
- uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-
- CKENB |= CKENB_7_GPIO;
- udelay(100);
-
- /* Rising Edge on EXTON to reset DA9030 */
- GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
- GPDR0 |= (1<<17); /* GPIO17 is output */
- GSDR0 = (1<<17);
- GPCR0 = (1<<17); /* drive GPIO17 low */
- GPSR0 = (1<<17); /* drive GPIO17 high */
-
-#if CONFIG_SYS_DA9030_EXTON_DELAY
- udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
-#endif
- GPCR0 = (1<<17); /* drive GPIO17 low */
-
- /* reset the watchdog and go active (0xec) */
- val = (SYS_CONTROL_A_HWRES_ENABLE |
- (0x6<<4) |
- SYS_CONTROL_A_WDOG_ACTION |
- SYS_CONTROL_A_WATCHDOG);
- if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
- printf("Error accessing DA9030 via i2c.\n");
- return;
- }
-
- val = 0x80;
- if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
- printf("Error accessing DA9030 via i2c.\n");
- return;
- }
-
- i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
- i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
- i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
- i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */
- i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */
- i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */
- i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */
- i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
- i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */
- i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */
- i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */
- i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */
- i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
- i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */
- i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
- i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
- i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */
-
- val = i2c_reg_read(addr, STATUS);
- if(val & STATUS_CHDET)
- printf("Charger detected, turning on LED.\n");
- else {
- printf("No charger detetected.\n");
- /* undervoltage? print error and power down */
- }
-}
-
-
-#if 0
-/* reset the DA9030 watchdog */
-void hw_watchdog_reset(void)
-{
- uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
- val = i2c_reg_read(addr, SYS_CONTROL_A);
- val |= SYS_CONTROL_A_WATCHDOG;
- i2c_reg_write(addr, SYS_CONTROL_A, val);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-.macro wait time
- ldr r2, =OSCR
- mov r3, #0
- str r3, [r2]
-0:
- ldr r3, [r2]
- cmp r3, \time
- bls 0b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- /* Set up GPIO pins first */
- mov r10, lr
-
- /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
- ldr r0, =GPIO97
- ldr r1, =0x801
- str r1, [r0]
-
- ldr r0, =GPIO98
- ldr r1, =0x801
- str r1, [r0]
-
- /* tebrandt - ASCR, clear the RDH bit */
- ldr r0, =ASCR
- ldr r1, [r0]
- bic r1, r1, #0x80000000
- str r1, [r0]
-
-mem_init:
- /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
- ldr r0, =ACCR
- ldr r1, [r0]
- orr r1, r1, #0x3000
- str r1, [r0]
- ldr r1, [r0]
-
- /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
- ldr r0, =MDCNFG
- ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
- /* ldr r1, =0x80000403 */
- str r1, [r0]
- ldr r1, [r0] /* delay until written */
-
- /* 3. wait nop power up waiting period (200ms)
- * optimization: Steps 4+6 can be done during this
- */
- wait #0x300
-
- /* 4. Perform an initial Rcomp-calibration cycle */
- ldr r0, =RCOMP
- ldr r1, =0x80000000
- str r1, [r0]
- ldr r1, [r0] /* delay until written */
- /* missing: program for automatic rcomp evaluation cycles */
-
- /* 5. DDR DRAM strobe delay calibration */
- ldr r0, =DDR_HCAL
- ldr r1, =0x88000007
- str r1, [r0]
- wait #5
- ldr r1, [r0] /* delay until written */
-
- /* Set MDMRS */
- ldr r0, =MDMRS
- ldr r1, =0x60000033
- str r1, [r0]
- wait #300
-
- /* Configure MDREFR */
- ldr r0, =MDREFR
- ldr r1, =0x00000006
- str r1, [r0]
- ldr r1, [r0]
-
- /* Enable the dynamic memory controller */
- ldr r0, =MDCNFG
- ldr r1, [r0]
- orr r1, r1, #MDCNFG_DMCEN
- str r1, [r0]
-
-#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
- /* scrub/init SDRAM if enabled/present */
- ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
- ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
- mov r0, #0 /* scrub with 0x0000:0000 */
- mov r1, #0
- mov r2, #0
- mov r3, #0
- mov r4, #0
- mov r5, #0
- mov r6, #0
- mov r7, #0
-10: /* fastScrubLoop */
- subs r9, r9, #32 /* 8 words/line */
- stmia r8!, {r0-r7}
- beq 15f
- b 10b
-#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
-
-15:
- /* Mask all interrupts */
- mov r1, #0
- mcr p6, 0, r1, c1, c0, 0 @ ICMR
-
- /* Disable software and data breakpoints */
- mov r0, #0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /* Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-endlowlevel_init:
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/arch/pxa-regs.h>
-
-#ifdef CONFIG_SYS_DFC_DEBUG1
-# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG1(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG2
-# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG2(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG3
-# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG3(fmt, args...)
-#endif
-
-/* These really don't belong here, as they are specific to the NAND Model */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr delta_bbt_descr = {
- .options = 0,
- .offs = 0,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout delta_oob = {
- .eccbytes = 6,
- .eccpos = {2, 3, 4, 5, 6, 7},
- .oobfree = { {8, 2}, {12, 4} }
-};
-
-/*
- * not required for Monahans DFC
- */
-static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- return;
-}
-
-#if 0
-/* read device ready pin */
-static int dfc_device_ready(struct mtd_info *mtdinfo)
-{
- if(NDSR & NDSR_RDY)
- return 1;
- else
- return 0;
- return 0;
-}
-#endif
-
-/*
- * Write buf to the DFC Controller Data Buffer
- */
-static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- unsigned long bytes_multi = len & 0xfffffffc;
- unsigned long rest = len & 0x3;
- unsigned long *long_buf;
- int i;
-
- DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
- if(bytes_multi) {
- for(i=0; i<bytes_multi; i+=4) {
- long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
- }
- }
- if(rest) {
- printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
- }
- return;
-}
-
-
-static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
-{
- int i=0, j;
-
- /* we have to be carefull not to overflow the buffer if len is
- * not a multiple of 4 */
- unsigned long bytes_multi = len & 0xfffffffc;
- unsigned long rest = len & 0x3;
- unsigned long *long_buf;
-
- DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
- /* if there are any, first copy multiple of 4 bytes */
- if(bytes_multi) {
- for(i=0; i<bytes_multi; i+=4) {
- long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
- }
- }
-
- /* ...then the rest */
- if(rest) {
- unsigned long rest_data = NDDB;
- for(j=0;j<rest; j++)
- buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
- }
-
- return;
-}
-
-/*
- * read a word. Not implemented as not used in NAND code.
- */
-static u16 dfc_read_word(struct mtd_info *mtd)
-{
- printf("dfc_read_word: UNIMPLEMENTED.\n");
- return 0;
-}
-
-/* global var, too bad: mk@tbd: move to ->priv pointer */
-static unsigned long read_buf = 0;
-static int bytes_read = -1;
-
-/*
- * read a byte from NDDB Because we can only read 4 bytes from NDDB at
- * a time, we buffer the remaining bytes. The buffer is reset when a
- * new command is sent to the chip.
- *
- * WARNING:
- * This function is currently only used to read status and id
- * bytes. For these commands always 8 bytes need to be read from
- * NDDB. So we read and discard these bytes right now. In case this
- * function is used for anything else in the future, we must check
- * what was the last command issued and read the appropriate amount of
- * bytes respectively.
- */
-static u_char dfc_read_byte(struct mtd_info *mtd)
-{
- unsigned char byte;
- unsigned long dummy;
-
- if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
- bytes_read = 0;
- }
- byte = (unsigned char) (read_buf>>(8 * bytes_read++));
- if(bytes_read >= 4)
- bytes_read = -1;
-
- DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
- return byte;
-}
-
-/* calculate delta between OSCR values start and now */
-static unsigned long get_delta(unsigned long start)
-{
- unsigned long cur = OSCR;
-
- if(cur < start) /* OSCR overflowed */
- return (cur + (start^0xffffffff));
- else
- return (cur - start);
-}
-
-/* delay function, this doesn't belong here */
-static void wait_us(unsigned long us)
-{
- unsigned long start = OSCR;
- us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
-
- while (get_delta(start) < us) {
- /* do nothing */
- }
-}
-
-static void dfc_clear_nddb(void)
-{
- NDCR &= ~NDCR_ND_RUN;
- wait_us(CONFIG_SYS_NAND_OTHER_TO);
-}
-
-/* wait_event with timeout */
-static unsigned long dfc_wait_event(unsigned long event)
-{
- unsigned long ndsr, timeout, start = OSCR;
-
- if(!event)
- return 0xff000000;
- else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
- timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
- * OSCR_CLK_FREQ, 1000);
- else
- timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
- * OSCR_CLK_FREQ, 1000);
-
- while(1) {
- ndsr = NDSR;
- if(ndsr & event) {
- NDSR |= event;
- break;
- }
- if(get_delta(start) > timeout) {
- DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
- return 0xff000000;
- }
-
- }
- return ndsr;
-}
-
-/* we don't always wan't to do this */
-static void dfc_new_cmd(void)
-{
- int retry = 0;
- unsigned long status;
-
- while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
- /* Clear NDSR */
- NDSR = 0xFFF;
-
- /* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
-
- status = dfc_wait_event(NDSR_WRCMDREQ);
-
- if(status & NDSR_WRCMDREQ)
- return;
-
- DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
- dfc_clear_nddb();
- }
- DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
-}
-
-/* this function is called after Programm and Erase Operations to
- * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
- unsigned long ndsr=0, event=0;
- int state = this->state;
-
- if(state == FL_WRITING) {
- event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
- } else if(state == FL_ERASING) {
- event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
- }
-
- ndsr = dfc_wait_event(event);
-
- if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
- return(0x1); /* Status Read error */
- return 0;
-}
-
-/* cmdfunc send commands to the DFC */
-static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
- int column, int page_addr)
-{
- /* register struct nand_chip *this = mtd->priv; */
- unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
-
- /* clear the ugly byte read buffer */
- bytes_read = -1;
- read_buf = 0;
-
- switch (command) {
- case NAND_CMD_READ0:
- DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- dfc_new_cmd();
- ndcb0 = (NAND_CMD_READ0 | (4<<16));
- column >>= 1; /* adjust for 16 bit bus */
- ndcb1 = (((column>>1) & 0xff) |
- ((page_addr<<8) & 0xff00) |
- ((page_addr<<8) & 0xff0000) |
- ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_READ1:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
- goto end;
- case NAND_CMD_READOOB:
- DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
- goto end;
- case NAND_CMD_READID:
- dfc_new_cmd();
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
- ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_PAGEPROG:
- /* sent as a multicommand in NAND_CMD_SEQIN */
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
- goto end;
- case NAND_CMD_ERASE1:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- dfc_new_cmd();
- ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
- ndcb1 = (page_addr & 0x00ffffff);
- goto write_cmd;
- case NAND_CMD_ERASE2:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
- goto end;
- case NAND_CMD_SEQIN:
- /* send PAGE_PROG command(0x1080) */
- dfc_new_cmd();
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
- ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
- column >>= 1; /* adjust for 16 bit bus */
- ndcb1 = (((column>>1) & 0xff) |
- ((page_addr<<8) & 0xff00) |
- ((page_addr<<8) & 0xff0000) |
- ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
- event = NDSR_WRDREQ;
- goto write_cmd;
- case NAND_CMD_STATUS:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
- dfc_new_cmd();
- ndcb0 = NAND_CMD_STATUS | (4<<21);
- event = NDSR_RDDREQ;
- goto write_cmd;
- case NAND_CMD_RESET:
- DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
- ndcb0 = NAND_CMD_RESET | (5<<21);
- event = NDSR_CS0_CMDD;
- goto write_cmd;
- default:
- printk("dfc_cmdfunc: error, unsupported command.\n");
- goto end;
- }
-
- write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
-
- /* wait_event: */
- dfc_wait_event(event);
- end:
- return;
-}
-
-static void dfc_gpio_init(void)
-{
- DFC_DEBUG2("Setting up DFC GPIO's.\n");
-
- /* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand_new.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
- unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
-
- /* set up GPIO Control Registers */
- dfc_gpio_init();
-
- /* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
-
-#undef CONFIG_SYS_TIMING_TIGHT
-#ifndef CONFIG_SYS_TIMING_TIGHT
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tCH);
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
- DFC_MAX_tCS);
- tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWH);
- tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWP);
- tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
- DFC_MAX_tRH);
- tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
- DFC_MAX_tRP);
- tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tR);
- tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tWHR);
- tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
- DFC_MAX_tAR);
-#else /* this is the tight timing */
-
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
- DFC_MAX_tCH);
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
- DFC_MAX_tCS);
- tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
- DFC_MAX_tWH);
- tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
- DFC_MAX_tWP);
- tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
- DFC_MAX_tRH);
- tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
- DFC_MAX_tRP);
- tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
- DFC_MAX_tR);
- tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
- DFC_MAX_tWHR);
- tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
- DFC_MAX_tAR);
-#endif /* CONFIG_SYS_TIMING_TIGHT */
-
-
- DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
-
- /* tRP value is split in the register */
- if(tRP & (1 << 4)) {
- tRP_high = 1;
- tRP &= ~(1 << 4);
- } else {
- tRP_high = 0;
- }
-
- NDTR0CS0 = (tCH << 19) |
- (tCS << 16) |
- (tWH << 11) |
- (tWP << 8) |
- (tRP_high << 6) |
- (tRH << 3) |
- (tRP << 0);
-
- NDTR1CS0 = (tR << 16) |
- (tWHR << 4) |
- (tAR << 0);
-
- /* If it doesn't work (unlikely) think about:
- * - ecc enable
- * - chip select don't care
- * - read id byte count
- *
- * Intentionally enabled by not setting bits:
- * - dma (DMA_EN)
- * - page size = 512
- * - cs don't care, see if we can enable later!
- * - row address start position (after second cycle)
- * - pages per block = 32
- * - ND_RDY : clears command buffer
- */
- /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
-
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
- NDCR_DWIDTH_C | /* 16bit DFC data bus width */
- NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
- (2 << 16) | /* read id count = 7 ???? mk@tbd */
- NDCR_ND_ARB_EN | /* enable bus arbiter */
- NDCR_RDYM | /* flash device ready ir masked */
- NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
- NDCR_CS1_PAGEDM |
- NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
- NDCR_CS1_CMDDM |
- NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
- NDCR_CS1_BBDM |
- NDCR_DBERRM | /* double bit error ir masked */
- NDCR_SBERRM | /* single bit error ir masked */
- NDCR_WRDREQM | /* write data request ir masked */
- NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
-
-
- /* wait 10 us due to cmd buffer clear reset */
- /* wait(10); */
-
-
- nand->cmd_ctrl = dfc_hwcontrol;
-/* nand->dev_ready = dfc_device_ready; */
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->ecc.layout = &delta_oob;
- nand->options = NAND_BUSWIDTH_16;
- nand->waitfunc = dfc_wait;
- nand->read_byte = dfc_read_byte;
- nand->read_word = dfc_read_word;
- nand->read_buf = dfc_read_buf;
- nand->write_buf = dfc_write_buf;
-
- nand->cmdfunc = dfc_cmdfunc;
- nand->badblock_pattern = &delta_bbt_descr;
- return 0;
-}
-
-#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o cmd_mtc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
-#
-
-#
-# digsyMTC board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFE000000 boot low
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := dnp1110.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# we load ourself to c1f8'0000, the upper 1 MB of the first (only) bank
#
-TEXT_BASE = 0xc1f80000
+CONFIG_SYS_TEXT_BASE = 0xc1f80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += eNET.o
COBJS-$(CONFIG_PCI) += eNET_pci.o
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x06000000
+CONFIG_SYS_TEXT_BASE = 0x06000000
CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
PLATFORM_RELFLAGS += -fvisibility=hidden
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
.globl early_board_init
early_board_init:
/* No 32-bit board specific initialisation */
- jmp *%ebp /* return to caller */
-
-.globl show_boot_progress_asm
-show_boot_progress_asm:
-
- movb %al, %dl /* Create Working Copy */
- andb $0x80, %dl /* Mask in only Error bit */
- shrb $0x02, %dl /* Shift Error bit to Error LED */
- andb $0x0f, %al /* Mask out 'Error' bit */
- orb %dl, %al /* Mask in ERR LED */
- movw $LED_LATCH_ADDRESS, %dx
- outb %al, %dx
- jmp *%ebp /* return to caller */
+ jmp early_board_init_ret
.globl cpu_halt_asm
cpu_halt_asm:
movl $0x000000cb, %eax
outl %eax, %dx
- /* the return address is stored in bp */
- jmp *%bp
+ jmp board_init16_ret
.section .bios, "ax"
.code16
SECTIONS
{
- . = 0x06000000; /* Location of bootcode in flash */
- _i386boot_text_start = .;
- .text : { *(.text); }
+ . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
+ __text_start = .;
+ .text : { *(.text*); }
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
. = ALIGN(4);
+ __u_boot_cmd_end = .;
- .data : { *(.data) }
. = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
- .interp : { *(.interp) }
. = ALIGN(4);
+ .data : { *(.data*) }
- .dynsym : { *(.dynsym) }
. = ALIGN(4);
+ .dynsym : { *(.dynsym*) }
- .dynstr : { *(.dynstr) }
. = ALIGN(4);
+ .hash : { *(.hash*) }
- .hash : { *(.hash) }
. = ALIGN(4);
+ .got : { *(.got*) }
- .got : { *(.got) }
. = ALIGN(4);
+ __data_end = .;
- .got.plt : { *(.got.plt) }
. = ALIGN(4);
-
- .dynamic (NOLOAD) : { *(.dynamic) }
+ __bss_start = ABSOLUTE(.);
+ .bss (NOLOAD) : { *(.bss) }
. = ALIGN(4);
+ __bss_end = ABSOLUTE(.);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
. = ALIGN(4);
- __u_boot_cmd_end = .;
- _i386boot_cmd_start = LOADADDR(.u_boot_cmd);
-
- _i386boot_rel_dyn_start = .;
+ __rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
- _i386boot_rel_dyn_end = .;
+ __rel_dyn_end = .;
- . = ALIGN(4);
- _i386boot_bss_start = ABSOLUTE(.);
- .bss (NOLOAD) : { *(.bss) }
- _i386boot_bss_size = SIZEOF(.bss);
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
/* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { *(.realmode) }
+ .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
- _i386boot_realmode = LOADADDR(.realmode);
- _i386boot_realmode_size = SIZEOF(.realmode);
+ __realmode_start = LOADADDR(.realmode);
+ __realmode_size = SIZEOF(.realmode);
/* 16bit BIOS emulation code (just enough to boot Linux) */
- .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) }
- _i386boot_bios = LOADADDR(.bios);
- _i386boot_bios_size = SIZEOF(.bios);
+ __bios_start = LOADADDR(.bios);
+ __bios_size = SIZEOF(.bios);
/* The load addresses below assumes that the flash
* will be mapped so that 0x387f0000 == 0xffff0000
* The fff0 offset of resetvec is important, however.
*/
. = 0xfffffe00;
- .start32 : AT (0x0603fe00) { *(.start32); }
+ .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
. = 0xf800;
- .start16 : AT (0x0603f800) { *(.start16); }
+ .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
. = 0xfff0;
- .resetvec : AT (0x0603fff0) { *(.resetvec); }
- _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
+ .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Sandpoint boards
-#
-
-#TEXT_BASE = 0x00090000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_LDFLAGS += --gc-sections
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
LDSCRIPT = $(src)board/earthlcd/favr-32-ezkit/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
ifdef CONFIG_EDB9301
-TEXT_BASE = 0x05700000
+CONFIG_SYS_TEXT_BASE = 0x05700000
endif
ifdef CONFIG_EDB9302
-TEXT_BASE = 0x05700000
+CONFIG_SYS_TEXT_BASE = 0x05700000
endif
ifdef CONFIG_EDB9302A
-TEXT_BASE = 0xc5700000
+CONFIG_SYS_TEXT_BASE = 0xc5700000
endif
ifdef CONFIG_EDB9307
-TEXT_BASE = 0x01f00000
+CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9307A
-TEXT_BASE = 0xc1f00000
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
endif
ifdef CONFIG_EDB9312
-TEXT_BASE = 0x01f00000
+CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9315
-TEXT_BASE = 0x01f00000
+CONFIG_SYS_TEXT_BASE = 0x01f00000
endif
ifdef CONFIG_EDB9315A
-TEXT_BASE = 0xc1f00000
+CONFIG_SYS_TEXT_BASE = 0xc1f00000
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
* do_reset is done here because in this case it is board specific, since the
* 7xx CPUs can only be reset by external HW (the RTC in this case).
*/
-void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_RTC_MK48T59)
/* trigger watchdog immediately */
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
+ return 0;
}
/* ------------------------------------------------------------------------- */
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MHPC boards
-#
-
-TEXT_BASE = 0xfe000000
-/*TEXT_BASE = 0x00200000 */
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2003
-# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TOP5200 board, on optional MINI5200 and EVAL5200 boards
-#
-# allowed and functional TEXT_BASE values:
-#
-# 0xff000000 low boot at 0x00000100 (default board setting)
-# 0xfff00000 high boot at 0xfff00100 (board needs modification)
-# 0x00100000 RAM load and test
-#
-
-TEXT_BASE = 0xff000000
-#TEXT_BASE = 0xfff00000
-#TEXT_BASE = 0x00100000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TOP860 board
-#
-
-TEXT_BASE = 0x80000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2010
+# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_ATMEL_SPI) += spi.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+static const struct {
+ u32 port;
+ u32 bit;
+} cs_to_portbit[2][4] = {
+ {{AT91_PIO_PORTA, 3}, {AT91_PIO_PORTC, 11},
+ {AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
+ {{AT91_PIO_PORTB, 3}, {AT91_PIO_PORTC, 5},
+ {AT91_PIO_PORTC, 4}, {AT91_PIO_PORTC, 3} }
+};
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
+ if (bus < 2 && cs < 4)
+ return 1;
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
+ at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
+ cs_to_portbit[slave->bus][slave->cs].bit, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
+ at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
+ cs_to_portbit[slave->bus][slave->cs].bit, 1);
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <spi.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwn.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(2));
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void macb_hw_init(void)
+{
+ /* Enable EMAC clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ /* Enable MCI clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI);
+
+ /* Initialize MCI hardware */
+ at91_mci_hw_init();
+
+ /* This calls the atmel_mmc_init in gen_atmel_mci.c */
+ return atmel_mci_init((void *)AT91_BASE_MCI);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ /*
+ * the only currently existing use of this function
+ * (fsl_esdhc.c) suggests this function must return
+ * *cs = TRUE if a card is NOT detected -> in most
+ * cases the value of the pin when the detect switch
+ * closes to GND
+ */
+ *cd = at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0;
+ return 0;
+}
+
+#endif
+
+int board_early_init_f(void)
+{
+ struct at91_shdwn *shdwn = (struct at91_shdwn *)AT91_SHDWN_BASE;
+
+ /*
+ * make sure the board can be powered on by
+ * any transition on WKUP
+ */
+ writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
+ &shdwn->mr);
+
+ /* Enable clocks for all PIOs */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+ /* set SCL0 and SDA0 to open drain */
+ at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
+ at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
+ at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
+ at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
+ at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
+ at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
+
+ /* set SCL1 and SDA1 to open drain */
+ at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
+ at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
+ at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
+ at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
+ at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
+ at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of TOP9000 Board */
+ gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ macb_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI0
+ /* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
+ at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
+#endif
+#ifdef CONFIG_ATMEL_SPI1
+ at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ /* read 'factory' part of EEPROM */
+ read_factory_r();
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ /*
+ * Initialize ethernet HW addresses prior to starting Linux,
+ * needed for nfsroot.
+ * TODO: We need to investigate if that is really necessary.
+ */
+ eth_init(gd->bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ int num = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0,
+ (void *)AT91_EMAC_BASE,
+ CONFIG_SYS_PHY_ID);
+ if (!rc)
+ num++;
+#endif
+#ifdef CONFIG_ENC28J60
+ rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
+ ENC_SPI_CLOCK, SPI_MODE_0);
+ if (!rc)
+ num++;
+# ifdef CONFIG_ENC28J60_2
+ rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
+ ENC_SPI_CLOCK, SPI_MODE_0);
+ if (!rc)
+ num++;
+# ifdef CONFIG_ENC28J60_3
+ rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
+ ENC_SPI_CLOCK, SPI_MODE_0);
+ if (!rc)
+ num++;
+# endif
+# endif
+#endif
+ return num;
+}
+
+/*
+ * I2C access functions
+ *
+ * Note:
+ * We need to access Bus 0 before relocation to access the
+ * environment settings.
+ * However i2c_get_bus_num() cannot be called before
+ * relocation.
+ */
+#ifdef CONFIG_SOFT_I2C
+void iic_init(void)
+{
+ /* ports are now initialized in board_early_init_f() */
+}
+
+int iic_read(void)
+{
+ switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ case 0:
+ return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
+ case 1:
+ return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
+ }
+ return 1;
+}
+
+void iic_sda(int bit)
+{
+ switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ case 0:
+ at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
+ break;
+ case 1:
+ at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
+ break;
+ }
+}
+
+void iic_scl(int bit)
+{
+ switch ((gd->flags & GD_FLG_RELOC) ? i2c_get_bus_num() : 0) {
+ case 0:
+ at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
+ break;
+ case 1:
+ at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
+ break;
+ }
+}
+
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ep7312.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0xc0f80000
+CONFIG_SYS_TEXT_BASE = 0xc0f80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EP82xx series boards by Embedded Planet
-#
-
-TEXT_BASE = 0xFFF00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o mii_phy.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EP8260 boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_ep8260.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-#TEXT_BASE = 0x00100000
-#TEXT_BASE = 0xFF000000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# EP82xxM series boards by Embedded Planet
-
-TEXT_BASE = 0xFFF00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright (C) 2005 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Embedded Planet EP88x boards
-#
-TEXT_BASE = 0xFC000000
/*
- * (C) Copyright 2001-2003
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified by Yuli Barcohen <yuli@arabellasw.com>
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ *(.text*)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFF80000
-TEXT_BASE = 0xFFFC0000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <i2c.h>
-#include "eric.h"
-#include <asm/processor.h>
-
-#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */
-#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
-#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
-#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
-
-void sdram_init(void);
-
-int board_early_init_f (void)
-{
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the ERIC board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
- | IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
- | indicates NO Power or HOST RESET active
- | check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
- | for real IRQ source
- | IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
- | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
- | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
- | else tristate)
- | Note for ERIC board:
- | An interrupt taken for the HOST (IRQ 28) indicates that
- | the HOST wrote a "1" to one of the following locations
- | - VGA CRT_GPIO0 (if R1216 is loaded)
- | - VGA CRT_GPIO1 (if R1217 is loaded)
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
-
- out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
- out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char *s = getenv ("serial#");
- char *e;
-
- puts ("Board: ");
-
- if (!s || strncmp (s, "ERIC", 9)) {
- puts ("### No HW ID - assuming ERIC");
- } else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for (; s < e; ++s) {
- putc (*s);
- }
- }
-
-
- putc ('\n');
-
- return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
-#ifndef CONFIG_ERIC
- int i;
- unsigned char datain[128];
- int TotalSize;
-#endif
-
- /*
- * ToDo: Move the asm init routine sdram_init() to this C file,
- * or even better use some common ppc4xx code available
- * in arch/powerpc/cpu/ppc4xx
- */
- sdram_init();
-
-#ifdef CONFIG_ERIC
- /*
- * we have no EEPROM on ERIC
- * so let init.S do the init job for SDRAM
- * and simply return 32MByte here
- */
- return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
-#else
-
- /* Read Serial Presence Detect Information */
- for (i = 0; i < 128; i++)
- datain[i] = 127;
- i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
- printf ("\nReading DIMM...\n");
-#if 0
- for (i = 0; i < 128; i++) {
- printf ("%d=0x%x ", i, datain[i]);
- if (((i + 1) % 10) == 0)
- printf ("\n");
- }
- printf ("\n");
-#endif
-
- /*****************************/
- /* Retrieve interesting data */
- /*****************************/
- /* size of a SDRAM bank */
- /* Number of bytes per side / number of banks per side */
- if (datain[31] == 0x08)
- TotalSize = 32;
- else if (datain[31] == 0x10)
- TotalSize = 64;
- else {
- printf ("IIC READ ERROR!!!\n");
- TotalSize = 32;
- }
-
- /* single-sided DIMM or double-sided DIMM? */
- if (datain[5] != 1) {
- /* double-sided DIMM => SDRAM banks 0..3 are valid */
- printf ("double-sided DIMM\n");
- TotalSize *= 2;
- }
- /* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
- else {
- printf ("single-sided DIMM\n");
- }
-
-
- /* return size in Mb unit => *(1024*1024) */
- return (TotalSize * 1024 * 1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#define FLASH_WORD_SIZE unsigned short
-#define FLASH_ID_MASK 0xFFFF
-#else
-#define FLASH_WORD_SIZE unsigned long
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-/* stolen from esteem192e/flash.c */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#else
-static int write_short (flash_info_t *info, ulong dest, ushort data);
-#endif
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
- {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
-#if 0 /* sand: */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
- FLASH_BASE0_PRELIM-1+size_b0,
- &flash_info[0]);
-#else
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else
- {
- size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1)
- {
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
- }
-
- if (size_b0)
- {
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB0CR = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
-#if 0 /* sand: */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
- FLASH_BASE0_PRELIM-1+size_b0,
- &flash_info[0]);
-#else
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1+size_b1-monitor_flash_len,
- base_b1+size_b1-1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0+size_b0-monitor_flash_len,
- base_b0+size_b0-1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- }/* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start adress table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
- (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
- (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * info->size/info->sector_count);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00008000;
- info->start[3] = base + 0x0000C000;
- info->start[4] = base + 0x00010000;
- info->start[5] = base + 0x00014000;
- info->start[6] = base + 0x00018000;
- info->start[7] = base + 0x0001C000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x000E0000;
- }
- }
- else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- }
-#else
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00002000;
- info->start[2] = base + 0x00004000;
- info->start[3] = base + 0x00006000;
- info->start[4] = base + 0x00008000;
- info->start[5] = base + 0x0000A000;
- info->start[6] = base + 0x0000C000;
- info->start[7] = base + 0x0000E000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00070000;
- }
- }
- else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- }
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00014000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x0001C000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000A000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x0000E000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
-
- } else {
-
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-#endif
- }
-
-
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar botboot[]=", bottom boot sect)\n";
- uchar topboot[]=", top boot sector)\n";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- if (info->flash_id & 0x0001 ) {
- boottype = botboot;
- } else {
- boottype = topboot;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype);
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype);
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype);
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype);
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype);
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype);
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype);
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype);
- break;
- case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype);
- break;
- case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype);
- break;
- case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype);
- break;
- case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype);
- break;
- case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype);
- break;
- case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype);
- break;
-
-#if 0 /* enable when devices are available */
-
- case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype);
- break;
- case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype);
- break;
-#endif
- case FLASH_28F320J3A: printf ("INTEL28F320J3A (32 Mbit%s",boottype);
- break;
- case FLASH_28F640J3A: printf ("INTEL28F640J3A (64 Mbit%s",boottype);
- break;
- case FLASH_28F128J3A: printf ("INTEL28F128J3A (128 Mbit%s",boottype);
- break;
-
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
- short i;
- ulong base = (ulong)addr;
- FLASH_WORD_SIZE value;
-
- /* Write auto select command: read Manufacturer ID */
-
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x00890089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x00900090;
- if(addr[0x0000] != 0x00890089){
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-#else
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x0089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x0090;
-
- if(addr[0x0000] != 0x0089){
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0090;
-#endif
- }
- value = addr[0];
-
- switch (value) {
- case (AMD_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (STM_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (SST_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
-
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (AMD_ID_LV400T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_LV320B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800T;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160T;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
-#if 0 /* enable when devices are available */
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-#endif
- case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 32 MBit */
- case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 64 MBit */
- case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 128 MBit */
-
- default:
- /* FIXME*/
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets(base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
- *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
- *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
- }
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-
- volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
- int flag, prot, sect, l_sect, barf;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- ((info->flash_id > FLASH_AMD_COMP) &&
- ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- if(info->flash_id < FLASH_AMD_COMP) {
-#ifndef CONFIG_SYS_FLASH_16BIT
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-#else
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0080;
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
-#endif
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
- addr[0] = (0x00300030 & FLASH_ID_MASK);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
- while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
- (0x00800080&FLASH_ID_MASK) )
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
-
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- barf = 0;
-#ifndef CONFIG_SYS_FLASH_16BIT
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00200020;
- addr[0] = 0x00D000D0;
- while(!(addr[0] & 0x00800080)); /* wait for error or finish */
- if( addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if( barf ) {
- barf >>=16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- }
-#else
- addr = (vu_short*)(info->start[sect]);
- addr[0] = 0x0020;
- addr[0] = 0x00D0;
- while(!(addr[0] & 0x0080)); /* wait for error or finish */
- if( addr[0] & 0x003A) /* check for error */
- barf = addr[0] & 0x003A;
-#endif
- if(barf) {
- printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
- if(barf & 0x0002) printf("Block locked, not erased.\n");
- if((barf & 0x0030) == 0x0030)
- printf("Command Sequence error.\n");
- if((barf & 0x0030) == 0x0020)
- printf("Block Erase error.\n");
- if(barf & 0x0008) printf("Vpp Low error.\n");
- rcode = 1;
- } else printf(".");
- l_sect = sect;
- }
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
-
- }
-
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*flash_info_t *addr2info (ulong addr)
-{
- flash_info_t *info;
- int i;
-
- for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
- if ((addr >= info->start[0]) &&
- (addr < (info->start[0] + info->size)) ) {
- return (info);
- }
- }
-
- return (NULL);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - target range includes protected sectors
- * 8 - target address not in Flash memory
- */
-
-/*int flash_write (uchar *src, ulong addr, ulong cnt)
-{
- int i;
- ulong end = addr + cnt - 1;
- flash_info_t *info_first = addr2info (addr);
- flash_info_t *info_last = addr2info (end );
- flash_info_t *info;
-
- if (cnt == 0) {
- return (0);
- }
-
- if (!info_first || !info_last) {
- return (8);
- }
-
- for (info = info_first; info <= info_last; ++info) {
- ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
-/* short s_end = info->sector_count - 1;
- for (i=0; i<info->sector_count; ++i) {
- ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
- if ((end >= info->start[i]) && (addr < e_addr) &&
- (info->protect[i] != 0) ) {
- return (4);
- }
- }
- }
-
-*/ /* finally write data to flash */
-/* for (info = info_first; info <= info_last && cnt>0; ++info) {
- ulong len;
-
- len = info->start[0] + info->size - addr;
- if (len > cnt)
- len = cnt;
- if ((i = write_buff(info, src, addr, len)) != 0) {
- return (i);
- }
- cnt -= len;
- addr += len;
- src += len;
- }
- return (0);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-#ifndef CONFIG_SYS_FLASH_16BIT
- ulong cp, wp, data;
- int l;
-#else
- ulong cp, wp;
- ushort data;
-#endif
- int i, rc;
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-
-#else
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start byte
- */
- if (addr - wp) {
- data = 0;
- data = (data << 8) | *src++;
- --cnt;
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
-/* l = 0; used for debuging */
- while (cnt >= 2) {
- data = 0;
- for (i=0; i<2; ++i) {
- data = (data << 8) | *src++;
- }
-
-/* if(!l){
- printf("%x",data);
- l = 1;
- } used for debuging */
-
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<2; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_short(info, wp, data));
-
-
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *) (info->start[0]);
- ulong start, barf;
- int flag;
-
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- if (info->flash_id > FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
- } else {
- /* intel stuff */
- *addr = 0x00400040;
- }
- *((vu_long *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if (info->flash_id > FLASH_AMD_COMP) {
-
- while ((*((vu_long *) dest) & 0x00800080) !=
- (data & 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- } else {
-
- while (!(addr[0] & 0x00800080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
-
- if (addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if (barf) {
- barf >>= 16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- printf ("\nFlash write error at address %lx\n",
- (unsigned long) dest);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if (barf & 0x0010)
- printf ("Programming error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- return (2);
- }
-
-
- }
-
- return (0);
-
- }
-
-#else
-
-static int write_short (flash_info_t * info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short *) (info->start[0]);
- ulong start, barf;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_short *) dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- if (info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x00A0;
- } else {
- /* intel stuff */
- *addr = 0x00D0;
- *addr = 0x0040;
- }
- *((vu_short *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if (info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- } else {
- /* intel stuff */
- while (!(addr[0] & 0x0080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
-
- if (addr[0] & 0x003A) { /* check for error */
- barf = addr[0] & 0x003A;
- printf ("\nFlash write error at address %lx\n",
- (unsigned long) dest);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if (barf & 0x0010)
- printf ("Programming error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- return (2);
- }
- *addr = 0x00B0;
- *addr = 0x0070;
- while (!(addr[0] & 0x0080)) { /* wait for error or finish */
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return (1);
- }
- *addr = 0x00FF;
- }
- return (0);
-}
-#endif
-/*-----------------------------------------------------------------------*/
+++ /dev/null
-/*------------------------------------------------------------------------------+ */
-/* */
-/* This source code is dual-licensed. You may use it under the terms */
-/* of the GNU General Public License version 2, or under the license */
-/* below. */
-/* */
-/* This source code has been made available to you by IBM on an AS-IS */
-/* basis. Anyone receiving this source is licensed under IBM */
-/* copyrights to use it in any way he or she deems fit, including */
-/* copying it, modifying it, compiling it, and redistributing it either */
-/* with or without modifications. No license under IBM patents or */
-/* patent applications is to be implied by the copyright license. */
-/* */
-/* Any user of this software should understand that IBM cannot provide */
-/* technical support for this software and will not be responsible for */
-/* any consequences resulting from the use of this software. */
-/* */
-/* Any person who transfers this source code or any derivative work */
-/* must include the IBM copyright notice, this paragraph, and the */
-/* preceding two paragraphs in the transferred software. */
-/* */
-/* COPYRIGHT I B M CORPORATION 1995 */
-/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* */
-/*----------------------------------------------------------------------------- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 0 (Flash) initialization (from openbios) */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS0_AP@h
- ori r4,r4,CS0_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS0_CR@h
- ori r4,r4,CS0_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 1 (NVRAM/RTC) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS1_AP@h
- ori r4,r4,CS1_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS1_CR@h
- ori r4,r4,CS1_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 2 (A/D converter) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB2AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS2_AP@h
- ori r4,r4,CS2_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB2CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS2_CR@h
- ori r4,r4,CS2_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 3 (Ethernet PHY Reset) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB3AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS3_AP@h
- ori r4,r4,CS3_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB3CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS3_CR@h
- ori r4,r4,CS3_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB4AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS4_AP@h
- ori r4,r4,CS4_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB4CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS4_CR@h
- ori r4,r4,CS4_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB5AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS5_AP@h
- ori r4,r4,CS5_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB5CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS5_CR@h
- ori r4,r4,CS5_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 6 (CPU LED0) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB6AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS6_AP@h
- ori r4,r4,CS6_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB6CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS6_CR@h
- ori r4,r4,CS5_CR@l
- mtdcr EBC0_CFGDATA,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 7 (CPU LED1) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,PB7AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS7_AP@h
- ori r4,r4,CS7_AP@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB7CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,CS7_CR@h
- ori r4,r4,CS7_CR@l
- mtdcr EBC0_CFGDATA,r4
-
-/* addis r4,r0,FPGA_BRDC@h */
-/* ori r4,r4,FPGA_BRDC@l */
-/* lbz r3,0(r4) /###*get FPGA board control reg */
-/* eieio */
-/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */
-/* stb r3,0(r4) */
-
- nop /* pass2 DCR errata #8 */
- blr
-
-/*----------------------------------------------------------------------------- */
-/* Function: sdram_init */
-/* Description: Configures SDRAM memory banks on ERIC. */
-/* We do manually init our SDRAM. */
-/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
-/* It is assumed that a 32MB 12x8(2) SDRAM is used. */
-/*----------------------------------------------------------------------------- */
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
-#ifdef CONFIG_SYS_SDRAM_MANUALLY
- /*------------------------------------------------------------------- */
- /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
- /*------------------------------------------------------------------- */
-
- addi r4,0,SDRAM0_B0CR
- mtdcr SDRAM0_CFGADDR,r4
- addis r4,0,MB0CF@h
- ori r4,r4,MB0CF@l
- mtdcr SDRAM0_CFGDATA,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
- /*------------------------------------------------------------------- */
-
- addi r4,0,SDRAM0_B1CR
- mtdcr SDRAM0_CFGADDR,r4
- addis r4,0,MB1CF@h
- ori r4,r4,MB1CF@l
- mtdcr SDRAM0_CFGDATA,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB2CF for bank 2. off */
- /*------------------------------------------------------------------- */
-
- addi r4,0,SDRAM0_B2CR
- mtdcr SDRAM0_CFGADDR,r4
- addis r4,0,MB2CF@h
- ori r4,r4,MB2CF@l
- mtdcr SDRAM0_CFGDATA,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB3CF for bank 3. off */
- /*------------------------------------------------------------------- */
-
- addi r4,0,SDRAM0_B3CR
- mtdcr SDRAM0_CFGADDR,r4
- addis r4,0,MB3CF@h
- ori r4,r4,MB3CF@l
- mtdcr SDRAM0_CFGDATA,r4
-
- /*------------------------------------------------------------------- */
- /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
- /* To set the appropriate timings, we need to know the SDRAM speed. */
- /* We can use the PLB speed since the SDRAM speed is the same as */
- /* the PLB speed. The PLB speed is the FBK divider times the */
- /* 405GP reference clock, which on the Walnut board is 33Mhz. */
- /* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
- /* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
- /* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
- /* maybe 133Mhz. */
- /*------------------------------------------------------------------- */
-
- mfdcr r5,CPC0_PSR /* determine FBK divider */
- /* via STRAP reg to calc PLB speed. */
- /* SDRAM speed is the same as the PLB */
- /* speed. */
- rlwinm r4,r5,4,0x3 /* get FBK divide bits */
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */
- ori r6,r6,SDTR_66@l
- addis r7,0,RTR_66 /* RTR value for 66Mhz */
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
- ori r6,r6,SDTR_100@l
- addis r7,0,RTR_100 /* RTR value for 100Mhz */
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
- ori r6,r6,0x4015
- addis r7,0,0x07F0 /* RTR value for 133Mhz */
-
-..sdram_ok:
- /*------------------------------------------------------------------- */
- /* Set SDTR1 */
- /*------------------------------------------------------------------- */
- addi r4,0,SDRAM0_TR
- mtdcr SDRAM0_CFGADDR,r4
- mtdcr SDRAM0_CFGDATA,r6
-
- /*------------------------------------------------------------------- */
- /* Set RTR */
- /*------------------------------------------------------------------- */
- addi r4,0,SDRAM0_RTR
- mtdcr SDRAM0_CFGADDR,r4
- mtdcr SDRAM0_CFGDATA,r7
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure 200usec have elapsed since reset. Assume worst */
- /* case that the core is running 200Mhz: */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0000
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 /* spin loop */
-
- /*------------------------------------------------------------------- */
- /* Set memory controller options reg, MCOPT1. */
- /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
- /* read/prefetch. */
- /*------------------------------------------------------------------- */
- addi r4,0,SDRAM0_CFG
- mtdcr SDRAM0_CFGADDR,r4
- addis r4,0,0x8080 /* set DC_EN=1 */
- ori r4,r4,0x0000
- mtdcr SDRAM0_CFGDATA,r4
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure 10msec have elapsed since reset. This is */
- /* required for the MPC952 to stabalize. Assume worst */
- /* case that the core is running 200Mhz: */
- /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
- /* This delay should occur before accessing SDRAM. */
- /*------------------------------------------------------------------- */
- addis r3,0,0x001E
- ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 /* spin loop */
-
-#else
-/*fixme: do SDRAM Autoconfig from EEPROM here */
-
-#endif
- mtlr r31 /* restore lr */
- blr
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-# FLASH:
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
-
-# SDRAM:
-#TEXT_BASE = 0x00FE0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#undef FPGA_DEBUG
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ABG405 boards
-#
-
-TEXT_BASE = 0xFFF80000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* ------------------------------------------------------------------------- */
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFA0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ASH405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
/* ------------------------------------------------------------------------- */
#if 0
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFC0000
$(shell mkdir -p $(obj)../common/xilinx_jtag)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFC8000
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_source (cmd_tbl_t *, int, int, char *[]);
#define ADDRMASK 0xfffff000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd CPCI2DP board
-#
-
-TEXT_BASE = 0xFFFC0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS += ../common/cmd_loadpci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG
# $(shell mkdir -p $(obj)../common/xilinx_jtag)
# endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IceCube board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFF000000 boot low for 16 MiB boards
-# 0xFF800000 boot low for 8 MiB boards
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
$(shell mkdir -p $(obj)../../Marvell/common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS = misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2004
-# Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# cpci750 board
-#
-
-TEXT_BASE = 0xfff00000
extern flash_info_t flash_info[];
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd CPCIISER4 boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-#TEXT_BASE = 0xFFFD0000
-TEXT_BASE = 0xFFFC0000
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFC0000
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/esd/dasa_sim/u-boot.lds
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)../common/xilinx_jtag)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFD0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd CPCIISER4 boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
-#TEXT_BASE = 0xFFFC0000
DECLARE_GLOBAL_DATA_PTR;
-/*cmd_boot.c*/
-
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFA0000
-endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd VOH405 boards
-#
-
-#TEXT_BASE = 0xFFF00000
-TEXT_BASE = 0xFFF80000
-#TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd HUB405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IceCube board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFF000000 boot low for 16 MiB boards
-# 0xFF800000 boot low for 8 MiB boards
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x23f00000
+CONFIG_SYS_TEXT_BASE = 0x23f00000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
SOBJS = writeibm.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
-# $(AR) $(ARFLAGS) $@ $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+# $(call cmd_link_o_target, $(OBJS))
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
/*
* Command loadpci: wait for signal from host and boot image.
*/
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFFD0000
DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);
# $(shell mkdir -p $(obj)../common/xilinx_jtag)
# endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IceCube board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFF000000 boot low for 16 MiB boards
-# 0xFF800000 boot low for 8 MiB boards
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd PLU405 boards
-#
-
-TEXT_BASE = 0xFFF80000
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
$(shell mkdir -p $(obj)../common/xilinx_jtag)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF80000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y = $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFC0000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
../common/cmd_loadpci.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF90000
-endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffc00000
+CONFIG_SYS_TEXT_BASE = 0xffc00000
/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o caddy.o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# VME8349E
-#
-
-TEXT_BASE = 0xFFF00000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd VOH405 boards
-#
-
-TEXT_BASE = 0xFFF80000
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
$(shell mkdir -p $(obj)../common/xilinx_jtag)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-TEXT_BASE = 0xFFFC8000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ASH405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := espt.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# board/espt/config.mk
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: ESPT-GIGA\n");
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ net/libnet.o (.text*)
+ board/esteem192e/libesteem192e.o (.text*)
+ *(.text.*printf)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o phantom.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Sangmoon, Etin Systems, dogoil@etinsys.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Debris boards
-#
-
-#TEXT_BASE = 0x00090000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o multiverse.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2005
-# Sangmoon, Etin Systems, dogoil@etinsys.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# KVME080 board
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# ETX_094 Boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc8xx/serial.o (.text)
- arch/powerpc/cpu/mpc8xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc8xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ *(.text.*printf*)
. = env_offset;
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ common/env_embedded.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := cpuat91.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21F00000
+CONFIG_SYS_TEXT_BASE = 0x21F00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := evb4510.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x007d0000
+CONFIG_SYS_TEXT_BASE = 0x007d0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS = misc.o
COBJS = $(BOARD).o flash.o serial.o memory.o pci.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EVB64260 boards
-#
-
-TEXT_BASE = 0xfff00000
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
+ arch/powerpc/cpu/74xx_7xx/start.o (.text*)
+ *(.text*)
- *(.text)
- *(.got1)
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o lamp.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
-# MPC885ADS boards
-#
-
-TEXT_BASE = 0xFE000000
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads
-HOSTCFLAGS += -I$(TOPDIR)/board/fads
-HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* values according to the manual */
#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
/*. = DEFINED(env_offset) ? env_offset : .;*/
- common/env_embedded.o (.ppcenv)
+ common/env_embedded.o (.ppcenv*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := a320evb.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# download area is 1200'0000
-TEXT_BASE = 0x13f80000
+CONFIG_SYS_TEXT_BASE = 0x13f80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+$(shell mkdir -p $(obj)board/freescale/common)
endif
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)libfreescale.o
COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
-COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#include <i2c.h>
#include <linux/ctype.h>
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
#include "../common/eeprom.h"
+#define MAX_NUM_PORTS 8
+#endif
-#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
-#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 8
+#define NXID_VERSION 0
#endif
-#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 23
+#define NXID_VERSION 1
+#endif
/**
* static eeprom: EEPROM layout for CCID or NXID formats
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
- u32 crc; /* 0x72 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
+ u32 crc; /* x+1 CRC32 checksum */
#endif
} e;
*/
static int prog_eeprom(void)
{
- int ret = 0; /* shut up gcc */
+ int ret = 0;
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+ /*
+ * The AT24C02 datasheet says that data can only be written in page
+ * mode, which means 8 bytes at a time, and it takes up to 5ms to
+ * complete a given write.
+ */
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
udelay(5000); /* 5ms write cycle timing */
}
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
+ has_been_read = 0;
return -1;
}
char *p = (char *) string;
unsigned int i;
- if (!string) {
+ if ((index >= MAX_NUM_PORTS) || !string) {
printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
return;
}
if (cmd == 'i') {
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memcpy(e.id, "NXID", sizeof(e.id));
- e.version = 0;
+ e.version = NXID_VERSION;
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
e.mac_count = simple_strtoul(argv[2], NULL, 16);
update_crc();
break;
- case '0' ... '7': /* "mac 0" through "mac 7" */
- set_mac_address(cmd - '0', argv[2]);
+ case '0' ... '9': /* "mac 0" through "mac 22" */
+ set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
break;
case 'h': /* help */
default:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_DDR_SPD) += ddr.o
+COBJS-y += ddr.o
+COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += law.o
COBJS-y += tlb.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
#
# P4080DS board
#
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
RESET_VECTOR_ADDRESS = 0xeffffffc
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
{
u8 sw;
struct cpu_type *cpu = gd->cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
printf("Board: %sDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
puts("36-bit Addressing\n");
#endif
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
/* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
- puts("Initializing....\n");
-
- dram_size = fsl_ddr_sdram();
-
- setup_ddr_tlbs(dram_size / 0x100000);
-
- puts(" DDR: ");
- return dram_size;
-}
-
#ifdef CONFIG_MP
void board_lmb_reserve(struct lmb *lmb)
{
#include <common.h>
#include <i2c.h>
-
+#include <hwconfig.h>
+#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num);
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+extern fixed_ddr_parm_t fixed_ddr_parm_1[];
+#endif
+
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ sys_info_t sysinfo;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ unsigned int lawbar1_target_id;
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freqDDRBus));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
+ (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freqDDRBus));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_1[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
+#endif
+
+ /*
+ * setup laws for DDR. If not interleaving, presuming half memory on
+ * DDR1 and the other half on DDR2
+ */
+ if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ LAW_TRGT_IF_DDR_INTRLV) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ } else {
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ /* We require both controllers have identical DIMMs */
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ lawbar1_target_id = LAW_TRGT_IF_DDR_2;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#else
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#endif
+ }
+ return ddr_size;
+}
static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
{
/* Enable ZQ calibration */
popts->zq_en = 1;
}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+ int use_spd = 0;
+
+ puts("Initializing....");
+
+#ifdef CONFIG_DDR_SPD
+ /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
+ if (hwconfig_sub("fsl_ddr", "sdram")) {
+ if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
+ use_spd = 1;
+ else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
+ use_spd = 0;
+ else
+ use_spd = 1;
+ } else
+ use_spd = 1;
+#endif
+
+ if (use_spd) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("using fixed parameters\n");
+ dram_size = fixed_sdram();
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define DATARATE_800MHZ 800000000
+#define DATARATE_900MHZ 900000000
+#define DATARATE_1000MHZ 1000000000
+#define DATARATE_1200MHZ 1200000000
+#define DATARATE_1300MHZ 1300000000
+
+#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5 0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
+ {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
+ {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
+ {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
+ {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+ {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
+ {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
+ {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
+ {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
+ {0, 0, NULL}
+};
static struct pci_controller pcie3_hose;
#endif
+#ifdef CONFIG_PCIE4
+static struct pci_controller pcie4_hose;
+#endif
+
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[3];
+ struct fsl_pci_info pci_info[4];
u32 devdisr;
int first_free_busno = 0;
int num = 0;
LAW_TRGT_IF_PCIE_1);
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf(" PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
LAW_TRGT_IF_PCIE_2);
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf(" PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
+ printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
LAW_TRGT_IF_PCIE_3);
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf(" PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
+ printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
#endif
+
+#ifdef CONFIG_PCIE4
+ pcie_configured = is_serdes_configured(PCIE4);
+
+ if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
+ set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
+ LAW_TRGT_IF_PCIE_4);
+ set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_4);
+ SET_STD_PCIE_INFO(pci_info[num], 4);
+ pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
+ printf("PCIE4: connected to as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie4_hose, first_free_busno);
+ } else {
+ printf("PCIE4: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
+#endif
}
void pci_of_setup(void *blob, bd_t *bd)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/m68k/cpu/mcf52x2/start.o (.text)
- arch/m68k/cpu/mcf52x2/libmcf52x2.a (.text)
- arch/m68k/lib/libm68k.a (.text)
+ arch/m68k/cpu/mcf52x2/libmcf52x2.o (.text)
+ arch/m68k/lib/libm68k.o (.text)
common/dlmalloc.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/m68k/cpu/mcf5227x/start.o (.text)
- arch/m68k/cpu/mcf5227x/libmcf5227x.a (.text)
- arch/m68k/lib/libm68k.a (.text)
- lib/libgeneric.a (.text)
+ arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text)
+ arch/m68k/lib/libm68k.o (.text)
+ lib/libgeneric.o (.text)
common/cmd_mem.o (.text)
common/main.o (.text)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-/*TEXT_BASE = 0xFFC00000*/
+/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
\ No newline at end of file
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
arch/m68k/cpu/mcf523x/cpu_init.o (.text)
arch/m68k/cpu/mcf523x/interrupts.o (.text)
arch/m68k/cpu/mcf523x/speed.o (.text)
- arch/m68k/lib/libm68k.a (.text)
+ arch/m68k/lib/libm68k.o (.text)
common/dlmalloc.o (.text)
common/cmd_bootm.o (.text)
common/cmd_flash.o (.text)
common/cmd_mem.o (.text)
common/console.o (.text)
common/main.o (.text)
- lib/libgeneric.a (.text)
+ lib/libgeneric.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
#include <malloc.h>
#include <asm/immap.h>
-
-/* Prototypes */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
int checkboard (void) {
ulong val;
uchar val8;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFF800000
+CONFIG_SYS_TEXT_BASE = 0xFF800000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
OUTPUT_ARCH(m68k)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
-GROUP(libgcc.a)
+GROUP(libgcc.o)
SECTIONS
{
/* Read-only sections, merged into text segment: */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xffe00000
+CONFIG_SYS_TEXT_BASE = 0xffe00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFFE00000
+CONFIG_SYS_TEXT_BASE = 0xFFE00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/m68k/cpu/mcf532x/start.o (.text)
- arch/m68k/cpu/mcf532x/libmcf532x.a (.text)
- arch/m68k/lib/libm68k.a (.text)
+ arch/m68k/cpu/mcf532x/libmcf532x.o (.text)
+ arch/m68k/lib/libm68k.o (.text)
common/dlmalloc.o (.text)
lib/zlib.o (.text)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/m68k/cpu/mcf5445x/start.o (.text)
- arch/m68k/cpu/mcf5445x/libmcf5445x.a (.text)
- arch/m68k/lib/libm68k.a (.text)
+ arch/m68k/cpu/mcf5445x/libmcf5445x.o (.text)
+ arch/m68k/lib/libm68k.o (.text)
common/cmd_flash.o (.text)
common/dlmalloc.o (.text)
common/main.o (.text)
common/image.o (.text)
- lib/libgeneric.a (.text)
+ lib/libgeneric.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFF800000
+CONFIG_SYS_TEXT_BASE = 0xFF800000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFF800000
+CONFIG_SYS_TEXT_BASE = 0xFF800000
$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2007 DENX Software Engineering
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF00000
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
CLOCK_SCCR2_I2C_EN | \
CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_SPDIF_EN)
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_USB1_EN | \
+ CLOCK_SCCR2_USB2_EN)
void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
* write commands in order to establish the device ID.
*/
-#ifdef CONFIG_ADS5121_REV2
+#ifdef CONFIG_MPC5121ADS_REV2
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
#else
if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 spridr = in_be32(&im->sysconf.spridr);
- printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
+ printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# Flash address
-TEXT_BASE = 0xFF000000
-# RAM address
-#TEXT_BASE = 0x00400000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float
+PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-ifndef NAND_SPL
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-endif
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFE000000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-ifndef NAND_SPL
-ifeq ($(CONFIG_MK_NAND), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
-endif
-endif
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFE000000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8323ERDB
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC832XEMDS
-#
-
-TEXT_BASE = 0xFE000000
};
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
-
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
/* initialize the PCA9555PW IO expander on the PIB board */
pib_init();
-#if defined(PCI_66M)
+#if defined(CONFIG_PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
-#elif defined(PCI_33M)
+#elif defined(CONFIG_PCI_33M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
printf("PCI clock is 33MHz\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8349EMDS
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8349E-mITX and MPC8349E-mITX-GP
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFEF00000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8360EMDS
-#
-
-TEXT_BASE = 0xFE000000
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
+#include <asm/fsl_enet.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, path,
- "phy-connection-type",
- "rgmii-rxid",
- sizeof("rgmii-rxid"));
+ fdt_fixup_phy_connection(blob, path,
+ RGMII_RXID);
}
#endif
#if defined(CONFIG_HAS_ETH1)
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, path,
- "phy-connection-type",
- "rgmii-rxid",
- sizeof("rgmii-rxid"));
+ fdt_fixup_phy_connection(blob, path,
+ RGMII_RXID);
}
#endif
}
/* initialize the PCA9555PW IO expander on the PIB board */
pib_init();
-#if defined(PCI_66M)
+#if defined(CONFIG_PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
-#elif defined(PCI_33M)
+#elif defined(CONFIG_PCI_33M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
printf("PCI clock is 33MHz\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8360ERDK
-#
-
-TEXT_BASE = 0xFF800000
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions, };
-#if defined(PCI_33M)
+#if defined(CONFIG_PCI_33M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
printf("PCI clock is 33MHz\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC837xEMDS
-#
-
-TEXT_BASE = 0xFE000000
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* CREDITS: Kim Phillips contribute to LIBFDT code
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
+#include <asm/fsl_enet.h>
#include <spd_sdram.h>
#include <tsec.h>
#include <libfdt.h>
static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
int phy_addr)
{
- const char *phy_type = "sgmii";
const u32 *ph;
int off;
int err;
return;
}
- err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
- strlen(phy_type) + 1);
+ err = fdt_fixup_phy_connection(blob, off, SGMII);
+
if (err) {
printf("WARNING: could not set phy-connection-type for %s: "
"%s.\n", alias, fdt_strerror(err));
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
- mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
+ mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
}
void ft_pcie_fixup(void *blob, bd_t *bd)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC837xERDB
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
# mpc8536ds board
#
ifndef NAND_SPL
-ifeq ($(CONFIG_MK_NAND), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-ifeq ($(CONFIG_MK_SDCARD), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_SDCARD), y)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
-ifeq ($(CONFIG_MK_SPIFLASH), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_SPIFLASH), y)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
-
ifndef RESET_VECTOR_ADDRESS
RESET_VECTOR_ADDRESS = 0xeffffffc
endif
devdisr, sdrs2_io_sel, io_sel);
if (sdrs2_io_sel == 7)
- printf(" Serdes2 disalbed\n");
+ printf("Serdes2 disalbed\n");
else if (sdrs2_io_sel == 4) {
- printf(" eTSEC1 is in sgmii mode.\n");
- printf(" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
} else if (sdrs2_io_sel == 6)
- printf(" eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
LAW_TRGT_IF_PCIE_3);
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
+ printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
LAW_TRGT_IF_PCIE_1);
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
+ printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
LAW_TRGT_IF_PCIE_2);
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
+ printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
LAW_TRGT_IF_PCI);
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8540ads board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
puts("Board: ADS\n");
#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
- printf(" PCI1: disabled\n");
+ printf("PCI1: disabled\n");
#endif
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8541cds board
-#
-TEXT_BASE = 0xfff80000
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- printf (" PCI1: %d bit, %s MHz, %s\n",
+ printf("PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
- printf (" PCI2: disabled\n");
+ printf("PCI2: disabled\n");
}
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8544ds board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
if (io_sel & 1) {
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- printf (" eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf (" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
}
puts("\n");
pcie3_hose.region_count = 1;
#endif
- printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
*/
in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
#else
pcie1_hose.region_count = 1;
#endif
- printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
pcie2_hose.region_count = 1;
#endif
- printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2004, 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8548cds board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
}
#endif
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
- printf (" PCI2: disabled\n");
+ printf("PCI2: disabled\n");
}
}
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8555cds board
-#
-TEXT_BASE = 0xfff80000
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- printf (" PCI1: %d bit, %s MHz, %s\n",
+ printf("PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
- printf (" PCI2: disabled\n");
+ printf("PCI2: disabled\n");
}
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8560ads board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
puts("Board: ADS\n");
#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
- printf(" PCI1: disabled\n");
+ printf("PCI1: disabled\n");
#endif
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += bcsr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8568mds board
-#
-TEXT_BASE = 0xfff80000
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += bcsr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
# mpc8569mds board
#
ifndef NAND_SPL
-ifeq ($(CONFIG_MK_NAND), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
popts->write_data_delay = 2;
/*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
+ * Enable half drive strength
*/
- popts->half_strength_driver_enable = 0;
+ popts->half_strength_driver_enable = 1;
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x4;
+
+ /* Rtt and Rtt_W override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_60_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: 8569 MDS\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
break;
}
- err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
- "rmii");
+ err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
+
if (err < 0) {
printf("WARNING: could not set phy-connection-type "
"%s.\n", fdt_strerror(err));
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
/* TLB 1 Initializations */
/*
- * TLBe 0: 64M Non-cacheable, guarded
+ * TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
- * 0xfc000000 256K NAND FLASH (CS3)
- * 0xfe000000 32M NOR FLASH (CS0)
+ * 0xfc000000 32MB NAND FLASH (CS3)
+ * 0xfe000000 32MB NOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
#
# mpc8572ds board
#
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
-
RESET_VECTOR_ADDRESS = 0xeffffffc
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- printf (" eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf (" eTSEC2 is in sgmii mode.\n");
+ printf("eTSEC2 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf (" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
- printf (" eTSEC4 is in sgmii mode.\n");
+ printf("eTSEC4 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
/*
in_be32(p);
}
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_FSL_DDR2) += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xfff00000
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
- printf(" PCI connected to PCI slots as %s" \
+ printf("PCI: connected to PCI slots as %s" \
" (base address %lx)\n",
pci_agent ? "Agent" : "Host",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
#include <common.h>
#include <command.h>
#include <asm/io.h>
-
-#ifdef CONFIG_FSL_DIU_FB
-
-#include "../common/fsl_diu_fb.h"
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-#include <stdio_dev.h>
-#include <video_fb.h>
-#endif
-
-static int xres, yres;
+#include <fsl_diu_fb.h>
void diu_set_pixel_clock(unsigned int pixclock)
{
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
}
-int mpc8610hpcd_diu_init(void)
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
{
char *monitor_port;
int gamma_fix;
monitor_port = getenv("monitor");
if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
- xres = 1280;
- yres = 1024;
+ *xres = 1280;
+ *yres = 1024;
if (pixis_arch == 0x01)
pixel_format = 0x88882317;
else
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
- xres = 1024;
- yres = 768;
+ *xres = 1024;
+ *yres = 768;
pixel_format = 0x88883316;
gamma_fix = 0;
out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
- xres = 1280;
- yres = 1024;
+ *xres = 1280;
+ *yres = 1024;
pixel_format = 0x88883316;
gamma_fix = 1;
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
} else { /* DVI */
- xres = 1280;
- yres = 1024;
+ *xres = 1280;
+ *yres = 1024;
pixel_format = 0x88882317;
gamma_fix = 0;
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
}
- return fsl_diu_init(xres, pixel_format, gamma_fix);
-}
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-
-/*
- * The Graphic Device
- */
-static GraphicDevice ctfb;
-
-void *video_hw_init(void)
-{
- struct fb_info *info;
-
- if (mpc8610hpcd_diu_init() < 0)
- return NULL;
-
- /* fill in Graphic device struct */
- sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60);
-
- ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info);
- ctfb.winSizeX = xres;
- ctfb.winSizeY = yres;
- ctfb.plnSizeX = ctfb.winSizeX;
- ctfb.plnSizeY = ctfb.winSizeY;
-
- ctfb.gdfBytesPP = 4;
- ctfb.gdfIndex = GDF_32BIT_X888RGB;
-
- ctfb.isaBase = 0;
- ctfb.pciBase = 0;
- ctfb.memSize = info->screen_size;
-
- /* Cursor Start Address */
- ctfb.dprBase = 0;
- ctfb.vprBase = 0;
- ctfb.cprBase = 0;
-
- return &ctfb;
+ return fsl_diu_init(*xres, pixel_format, gamma_fix);
}
-
-#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
-
-#endif /* CONFIG_FSL_DIU_FB */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Jeff Brown
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8641hpcn board
-# default CCSRBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xeff00000
return 0;
}
-const char *board_hwconfig = "foo:bar=baz";
-const char *cpu_hwconfig = "foo:bar=baz";
-
phys_size_t
initdram(int board_type)
{
void pci_init_board(void)
{
+ struct fsl_pci_info pci_info[2];
+ int pcie_ep;
+ int num = 0;
+
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
+ uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
- >> MPC8641_PORBMSR_HA_SHIFT;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- debug("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
- puts("PCI-EXPRESS 1: Disabled\n");
+ puts("PCIE1: disabled\n");
}
-}
#else
- puts("PCI-EXPRESS1: Disabled\n");
+ puts("PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-}
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf("PCIE2: connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
#else
- puts("PCI-EXPRESS 2: Disabled\n");
+ puts("PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
}
+++ /dev/null
-/*
- * Copyright 2006, 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- drivers/bios_emulator/atibios.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mx31ads.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0x87f00000
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/arm/cpu/arm1136/start.o (.text)
- board/freescale/mx31ads/libmx31ads.a (.text)
- arch/arm/lib/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
+ board/freescale/mx31ads/libmx31ads.o (.text)
+ arch/arm/lib/libarm.o (.text)
+ net/libnet.o (.text)
+ drivers/mtd/libmtd.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mx31pdk.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
ifdef CONFIG_NAND_SPL
-TEXT_BASE = 0x87ec0000
+CONFIG_SYS_TEXT_BASE = 0x87ec0000
else
-TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0x87f00000
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mx51evk.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
-TEXT_BASE = 0x97800000
+CONFIG_SYS_TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
+ALL += $(obj)u-boot.imx
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc13892.h>
-#include "mx51evk.h"
DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
-struct io_board_ctrl *mx51_io_board;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
return 0;
}
val &= ~PWGT2SPIEN;
pmic_reg_write(REG_POWER_MISC, val);
- /* Write needed to update Charger 0 */
- pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
- ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
- OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+ /* Externally powered */
+ val = pmic_reg_read(REG_CHARGE);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(REG_CHARGE, val);
/* power up the system first */
pmic_reg_write(REG_POWER_MISC, PWUP);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
+COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
# any later version.
#
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
-
RESET_VECTOR_ADDRESS = 0xeffffffc
--- /dev/null
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include "../common/ngpixis.h"
+#include <fsl_diu_fb.h>
+
+/* The CTL register is called 'csr' in the ngpixis_t structure */
+#define PX_CTL_ALTACC 0x80
+
+#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
+#define PX_BRDCFG0_ELBC_DIU 0x02
+
+#define PX_BRDCFG1_DVIEN 0x80
+#define PX_BRDCFG1_DFPEN 0x40
+#define PX_BRDCFG1_BACKLIGHT 0x20
+
+#define PMUXCR_ELBCDIU_MASK 0xc0000000
+#define PMUXCR_ELBCDIU_NOR16 0x80000000
+#define PMUXCR_ELBCDIU_DIU 0x40000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+/*
+ * Variables used by the DIU/LBC switching code. It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u8 px_brdcfg0;
+static u32 pmuxcr;
+static void *lbc_lcs0_ba;
+static void *lbc_lcs1_ba;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %lu\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+ out_be32(&gur->clkdvdr, temp); /* turn off clock */
+ out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char *monitor_port;
+ u32 pixel_format;
+ u8 temp;
+
+ /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
+ lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
+ lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ temp = in_8(&pixis->brdcfg1);
+
+ monitor_port = getenv("monitor");
+ if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+ *xres = 1024;
+ *yres = 768;
+ /* Enable the DFP port, disable the DVI and the backlight */
+ temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
+ temp |= PX_BRDCFG1_DFPEN;
+ } else { /* DVI */
+ *xres = 1280;
+ *yres = 1024;
+ /* Enable the DVI port, disable the DFP and the backlight */
+ temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+ temp |= PX_BRDCFG1_DVIEN;
+ }
+
+ out_8(&pixis->brdcfg1, temp);
+
+ /*
+ * Enable PIXIS indirect access mode. This is a hack that allows us to
+ * access PIXIS registers even when the LBC pins have been muxed to the
+ * DIU.
+ */
+ setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+ /*
+ * Route the LAD pins to the DIU. This will disable access to the eLBC,
+ * which means we won't be able to read/write any NOR flash addresses!
+ */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ px_brdcfg0 = in_8(lbc_lcs1_ba);
+ out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+
+ /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
+ pmuxcr = in_be32(&gur->pmuxcr);
+
+ return fsl_diu_init(*xres, pixel_format, 0);
+}
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
+ *
+ * On the Freescale P1022, the DIU video signal and the LBC address/data lines
+ * share the same pins, which means that when the DIU is active (e.g. the
+ * console is on the DVI display), NOR flash cannot be accessed. So we use the
+ * weak accessor feature of the CFI flash code to temporarily switch the pin
+ * mux from DIU to LBC whenever we want to read or write flash. This has a
+ * significant performance penalty, but it's the only way to make it work.
+ *
+ * There are two muxes: one on the chip, and one on the board. The chip mux
+ * controls whether the pins are used for the DIU or the LBC, and it is
+ * set via PMUXCR. The board mux controls whether those signals go to
+ * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
+ */
+static int set_mux_to_lbc(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Switch the muxes only if they're currently set to DIU mode */
+ if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+ PMUXCR_ELBCDIU_NOR16) {
+ /*
+ * In DIU mode, the PIXIS can only be accessed indirectly
+ * since we can't read/write the LBC directly.
+ */
+
+ /* Set the board mux to LBC. This will disable the display. */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ px_brdcfg0 = in_8(lbc_lcs1_ba);
+ out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
+ | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
+
+ /* Disable indirect PIXIS mode */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
+ clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
+
+ /* Set the chip mux to LBC mode, so that writes go to flash. */
+ out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
+ PMUXCR_ELBCDIU_NOR16);
+ in_be32(&gur->pmuxcr);
+
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * set_mux_to_diu - re-enable the DIU muxing
+ *
+ * This function restores the chip and board muxing to point to the DIU.
+ */
+static void set_mux_to_diu(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Enable indirect PIXIS mode */
+ setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+ /* Set the board mux to DIU. This will enable the display. */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ out_8(lbc_lcs1_ba, px_brdcfg0);
+ in_8(lbc_lcs1_ba);
+
+ /* Set the chip mux to DIU mode. */
+ out_be32(&gur->pmuxcr, pmuxcr);
+ in_be32(&gur->pmuxcr);
+}
+
+void flash_write8(u8 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writeb(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write16(u16 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writew(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write32(u32 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writel(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write64(u64 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+ uint32_t *p = addr;
+
+ /*
+ * There is no __raw_writeq(), so do the write manually. We don't trust
+ * the compiler, so we use inline assembly.
+ */
+ __asm__ __volatile__(
+ "stw%U0%X0 %2,%0;\n"
+ "stw%U1%X1 %3,%1;\n"
+ : "=m" (*p), "=m" (*(p + 1))
+ : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
+
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode. We
+ * read addr+4 because we just wrote to addr+4, so that's how we
+ * maintain execution order. set_mux_to_diu() includes a sync
+ * that will ensure the __raw_readb() completes before it
+ * switches the mux.
+ */
+ __raw_readb(addr + 4);
+ set_mux_to_diu();
+ }
+}
+
+u8 flash_read8(void *addr)
+{
+ u8 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readb(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readw(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u32 flash_read32(void *addr)
+{
+ u32 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readl(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u64 flash_read64(void *addr)
+{
+ u64 ret;
+
+ int sw = set_mux_to_lbc();
+
+ /* There is no __raw_readq(), so do the read manually */
+ ret = *(volatile u64 *)addr;
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+#endif
#include <asm/mp.h>
#include <netdev.h>
#include <i2c.h>
+#include <hwconfig.h>
#include "../common/ngpixis.h"
#define CONFIG_TFP410_I2C_ADDR 0x38
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+
int misc_init_r(void)
{
u8 temp;
+ const char *audclk;
+ size_t arglen;
- /* Enable the TFP410 Encoder */
+ /* For DVI, enable the TFP410 Encoder. */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /*
+ * Enable the reference clock for the WM8776 codec, and route the MUX
+ * pins for SSI. The default is the 12.288 MHz clock
+ */
+
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ out_8(&pixis->brdcfg1, temp);
+
return 0;
}
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
is_endpoint = fsl_setup_hose(hose, info->regs);
- printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
+ printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
info->pci_num, connected,
is_endpoint ? "Endpoint" : "Root Complex", info->regs);
bus_number = fsl_pci_init_port(info, hose, bus_number);
SET_STD_PCIE_INFO(pci_info, 1);
configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
} else {
- printf(" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
SET_STD_PCIE_INFO(pci_info, 2);
configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
} else {
- printf(" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
SET_STD_PCIE_INFO(pci_info, 3);
configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
} else {
- printf(" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
}
#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+ const char *audclk;
+ size_t arglen;
+ u32 freq;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ /* Update the WM8776 node's clock frequency property */
+ ft_codec_setup(blob, "wlf,wm8776");
}
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
#
ifndef NAND_SPL
-ifeq ($(CONFIG_MK_NAND), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_NAND), y)
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
-ifeq ($(CONFIG_MK_SDCARD), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_SDCARD), y)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
-ifeq ($(CONFIG_MK_SPIFLASH), y)
-TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifeq ($(CONFIG_SPIFLASH), y)
RESET_VECTOR_ADDRESS = 0xf8fffffc
endif
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
-
ifndef RESET_VECTOR_ADDRESS
RESET_VECTOR_ADDRESS = 0xeffffffc
endif
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
+#include <rtc.h>
DECLARE_GLOBAL_DATA_PTR;
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
+ rtc_reset();
return 0;
}
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf (" eTSEC2 is in sgmii mode.\n");
+ printf("eTSEC2 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
#else
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
#
# p2020ds board
#
-ifndef TEXT_BASE
-TEXT_BASE = 0xeff80000
-endif
-
RESET_VECTOR_ADDRESS = 0xeffffffc
return 0;
}
-const char *board_hwconfig = "foo:bar=baz";
-const char *cpu_hwconfig = "foo:bar=baz";
-
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf(" eTSEC2 is in sgmii mode.\n");
+ printf("eTSEC2 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf(" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
}
#endif
} else {
- printf(" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
- printf(" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf(" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
#else
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o m88e6060.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-# (C) Copyright 2004
-# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
-#
-# Support for the Elmeg VoVPN Gateway Module
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-TEXT_BASE = 0xfff00000
#if defined(CONFIG_HAVE_OWN_RESET)
int
-do_reset (void *cmdtp, int flag, int argc, char * const argv[])
+do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ioport_t *iop;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o strataflash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd PLU405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# U-BOOT IN FLASH
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON
-#TEXT_BASE = 0x40000000
+#CONFIG_SYS_TEXT_BASE = 0x40000000
# U-BOOT IN SDRAM
-#TEXT_BASE = 0x60000000
+#CONFIG_SYS_TEXT_BASE = 0x60000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# U-BOOT IN FLASH
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN SDRAM
-#TEXT_BASE = 0x40000000
+#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# U-BOOT IN FLASH
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN RAM
-#TEXT_BASE = 0x40000000
+#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# U-BOOT IN FLASH
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN RAM
-#TEXT_BASE = 0x40000000
+#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# RUN U-BOOT FROM PROM
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
# RUN U-BOOT FROM RAM
-#TEXT_BASE = 0x40000000
+#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# galaxy5200 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFE000000 boot low
-# 0x00100000 boot from RAM (for testing only) does not work
-#
-
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_galaxy5200_LOWBOOT
-TEXT_BASE = 0xFE000000
-endif
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := gcplus.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# bootp;tftp;bootm, repeat, etc.,.
#
-TEXT_BASE = 0xc8f00000
+CONFIG_SYS_TEXT_BASE = 0xc8f00000
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+int board_early_init_f(void)
+{
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ * -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * setup io-latches for reset
+ */
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+
+ /*
+ * wait for fpga-done
+ * fail ungraceful if fpga is not configuring properly
+ */
+ while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
+ ;
+
+ /*
+ * setup io-latches for boot (stop reset)
+ */
+ udelay(10);
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+ /*
+ * wait for fpga out of reset
+ * fail ungraceful if fpga is not working properly
+ */
+ while (1) {
+ fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
+ if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_IO) += io.o
+COBJS-$(CONFIG_IOCON) += iocon.o
+
+COBJS := $(BOARD).o $(COBJS-y)
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#include "../common/fpga.h"
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+
+enum {
+ REG_VERSIONS = 0x0002,
+ REG_FPGA_FEATURES = 0x0004,
+ REG_FPGA_VERSION = 0x0006,
+ REG_QUAD_SERDES_RESET = 0x0012,
+};
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+ HWVER_121 = 2,
+ HWVER_122 = 3,
+};
+
+int configure_gbit_phy(unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+ goto err_out;
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ u16 versions = fpga_get_reg(REG_VERSIONS);
+ u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+ u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ printf("Board: ");
+
+ printf("CATCenter Io");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ puts("\n ");
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ case HWVER_121:
+ printf(" HW-Ver 1.21\n");
+ break;
+
+ case HWVER_122:
+ printf(" HW-Ver 1.22\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+
+ return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+ unsigned int k;
+
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k)
+ configure_gbit_phy(k);
+
+ /* take fpga serdes blocks out of reset */
+ fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+#include "../common/osd.h"
+
+enum {
+ REG_VERSIONS = 0x0002,
+ REG_FPGA_VERSION = 0x0004,
+ REG_FPGA_FEATURES = 0x0006,
+};
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_104 = 1,
+ HWVER_110 = 2,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+};
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ u16 versions = fpga_get_reg(REG_VERSIONS);
+ u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+ u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ printf("Board: ");
+
+ printf("IoCon");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ puts("\n ");
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_104:
+ printf(" HW-Ver 1.04\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s)", feature_carriers);
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ return osd_probe();
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ */
+void fpga_gpio_set(int pin)
+{
+ out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+}
+
+void fpga_gpio_clear(int pin)
+{
+ out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+}
+
+int fpga_gpio_get(int pin)
+{
+ return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+}
#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-$(shell mkdir -p $(obj)../../tqc/tqm8xx)
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(VENDOR).o
-COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \
- ../../tqc/tqm8xx/load_sernum_ethaddr.o
+COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IOCON) += osd.o
+
+COBJS := $(COBJS-y)
+SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
/*
- * Voipac PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+static inline u16 fpga_get_reg(unsigned reg)
+{
+ return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
+}
+
+static inline void fpga_set_reg(unsigned reg, u16 val)
+{
+ return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
+}
-.globl lowlevel_init
-lowlevel_init:
- pxa_clock_setup
- mov pc, lr
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+
+ return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+
+ return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+
+ return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = CONFIG_SYS_GBIT_MII_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ }
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "fpga.h"
+
+#define CH7301_I2C_ADDR 0x75
+
+#define PIXCLK_640_480_60 25180000
+
+#define BASE_WIDTH 32
+#define BASE_HEIGHT 16
+#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
+
+enum {
+ REG_CONTROL = 0x0010,
+ REG_MPC3W_CONTROL = 0x001a,
+ REG_VIDEOCONTROL = 0x0042,
+ REG_OSDVERSION = 0x0100,
+ REG_OSDFEATURES = 0x0102,
+ REG_OSDCONTROL = 0x0104,
+ REG_XY_SIZE = 0x0106,
+ REG_VIDEOMEM = 0x0800,
+};
+
+enum {
+ CH7301_CM = 0x1c, /* Clock Mode Register */
+ CH7301_IC = 0x1d, /* Input Clock Register */
+ CH7301_GPIO = 0x1e, /* GPIO Control Register */
+ CH7301_IDF = 0x1f, /* Input Data Format Register */
+ CH7301_CD = 0x20, /* Connection Detect Register */
+ CH7301_DC = 0x21, /* DAC Control Register */
+ CH7301_HPD = 0x23, /* Hot Plug Detection Register */
+ CH7301_TCTL = 0x31, /* DVI Control Input Register */
+ CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
+ CH7301_TPD = 0x34, /* DVI PLL Divide Register */
+ CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
+ CH7301_TPF = 0x36, /* DVI PLL Filter Register */
+ CH7301_TCT = 0x37, /* DVI Clock Test Register */
+ CH7301_TSTP = 0x48, /* Test Pattern Register */
+ CH7301_PM = 0x49, /* Power Management register */
+ CH7301_VID = 0x4a, /* Version ID Register */
+ CH7301_DID = 0x4b, /* Device ID Register */
+ CH7301_DSP = 0x56, /* DVI Sync polarity Register */
+};
+
+static void mpc92469ac_calc_parameters(unsigned int fout,
+ unsigned int *post_div, unsigned int *feedback_div)
+{
+ unsigned int n = *post_div;
+ unsigned int m = *feedback_div;
+ unsigned int a;
+ unsigned int b = 14745600 / 16;
+
+ if (fout < 50169600)
+ n = 8;
+ else if (fout < 100339199)
+ n = 4;
+ else if (fout < 200678399)
+ n = 2;
+ else
+ n = 1;
+
+ a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+ m = a / b;
+
+ *post_div = n;
+ *feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned int fout)
+{
+ unsigned int n;
+ unsigned int m;
+ unsigned int bitval = 0;
+ mpc92469ac_calc_parameters(fout, &n, &m);
+
+ switch (n) {
+ case 1:
+ bitval = 0x00;
+ break;
+ case 2:
+ bitval = 0x01;
+ break;
+ case 4:
+ bitval = 0x02;
+ break;
+ case 8:
+ bitval = 0x03;
+ break;
+ }
+
+ fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+}
+
+static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+{
+ unsigned int k;
+
+ for (k = 0; k < charcount; ++k) {
+ if (offset + k >= BUFSIZE)
+ return -1;
+ fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+ }
+
+ return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned x;
+ unsigned y;
+ unsigned charcount;
+ unsigned len;
+ u8 color;
+ unsigned int k;
+ u16 buf[BUFSIZE];
+ char *text;
+
+ if (argc < 5) {
+ return cmd_usage(cmdtp);
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+ charcount = strlen(text);
+ len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+ for (k = 0; k < len; ++k)
+ buf[k] = (text[k] << 8) | color;
+
+ return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+}
+
+int osd_probe(void)
+{
+ u8 value;
+ u16 version = fpga_get_reg(REG_OSDVERSION);
+ u16 features = fpga_get_reg(REG_OSDFEATURES);
+ unsigned width;
+ unsigned height;
+
+ width = ((features & 0x3f00) >> 8) + 1;
+ height = (features & 0x001f) + 1;
+
+ printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ version/100, version%100, width, height);
+
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value != 0x17) {
+ printf(" Probing CH7301 failed, DID %02x\n", value);
+ return -1;
+ }
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+
+ mpc92469ac_set(PIXCLK_640_480_60);
+ fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
+ fpga_set_reg(REG_OSDCONTROL, 0x0049);
+
+ fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+
+ return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned x;
+ unsigned y;
+ unsigned k;
+ u16 buffer[BASE_WIDTH];
+ char *rp;
+ u16 *wp = buffer;
+ unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
+
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ return cmd_usage(cmdtp);
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ rp = argv[3];
+
+
+ while (*rp) {
+ char substr[5];
+
+ memcpy(substr, rp, 4);
+ substr[4] = 0;
+ *wp = simple_strtoul(substr, NULL, 16);
+
+ rp += 4;
+ wp++;
+ if (wp - buffer > BASE_WIDTH)
+ break;
+ }
+
+ for (k = 0; k < count; ++k) {
+ unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
+ osd_write_videomem(offset, buffer, wp - buffer);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ osdw, 5, 0, osd_write,
+ "write 16-bit hex encoded buffer to osd memory",
+ "pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+ osdp, 5, 0, osd_print,
+ "write ASCII buffer to osd memory",
+ "pos_x pos_y color text\n"
+);
/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#include <asm/arch/pxa-regs.h>
+#ifndef _OSD_H_
+#define _OSD_H_
- .global initPXAvoltage
+int osd_probe(void);
-initPXAvoltage:
- mov pc, lr
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS =
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# G&D 440EP/GR ETX-Module
#
-#TEXT_BASE = 0x00001000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
-# (C) Copyright 2008
+# (C) Copyright 2008-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# G&D CompactCenter
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFA0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS =
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# FLASH base address for GEN860T board
-#
-
-TEXT_BASE = 0x40000000
* Linker command file for the GEN860T board when the environment is
* stored in flash memory.
*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* Read-only sections, merged into text segment:
*/
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/*
* Read-write section, merged into data segment:
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data:
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
/*
* Linker command file for the GEN860T board.
*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* Read-only sections, merged into text segment:
*/
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/*
* Read-write section, merged into data segment:
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x00000000
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ lib/libgeneric.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ board/genietv/libgenietv.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+ *(.text.do_load_serial*)
+ *(.text.do_mem_*)
+ *(.text.do_bootm*)
. = env_offset;
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ common/env_embedded.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
}
. = ALIGN(256 * 1024);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o ee_access.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
#
ifeq ($(TBASE),0)
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
else
ifeq ($(TBASE),1)
-TEXT_BASE = 0xbfc10070
+CONFIG_SYS_TEXT_BASE = 0xbfc10070
else
ifeq ($(TBASE),2)
-TEXT_BASE = 0xbfc30070
+CONFIG_SYS_TEXT_BASE = 0xbfc30070
else
## Only to make ordinary make work
-TEXT_BASE = 0x90000000
+CONFIG_SYS_TEXT_BASE = 0x90000000
endif
endif
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := gw8260.o flash.o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Multidata HERMES-PRO ISDN Routers
-#
-
-TEXT_BASE = 0xFE000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ board/hermes/libhermes.o (.text*)
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
- arch/powerpc/lib/cache.o (.text)
- lib/crc32.o (.text)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Hidden Dragon boards
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
#define __ASSEMBLY__ 1
#endif
+#include <asm-offsets.h>
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# HYMOD boards
#
-TEXT_BASE = 0x40000000
-
PLATFORM_CPPFLAGS += -I$(TOPDIR)
OBJCFLAGS = --remove-section=.ppcenv
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf561-0.5
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IceCube board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFF000000 boot low for 16 MiB boards
-# 0xFF800000 boot low for 8 MiB boards
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
/* jump back to linux kernel code */
linux_wakeup = SAVED_ADDR;
printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
- linux_wakeup);
+ (unsigned long)linux_wakeup);
linux_wakeup();
}
#else
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# ICU862 boards
-#
-
-TEXT_BASE = 0x40F00000
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
-/*
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-*/
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
# MA 02111-1307 USA
#
-TEXT_BASE = 0xff800000
+CONFIG_SYS_TEXT_BASE = 0xff800000
OUTPUT_ARCH(m68k)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
-GROUP(libgcc.a)
+GROUP(libgcc.o)
SECTIONS
{
/* Read-only sections, merged into text segment: */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2005
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IDS 8247 Board
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_IDS8247.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-TEXT_BASE = 0xfff00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#undef DEBUG
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH8
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#elif FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#else /* FLASH_PORT_WIDTH8 */
-#define FLASH_PORT_WIDTH uchar
-#define FLASH_PORT_WIDTHV vu_char
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPWV * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immr->im_memctl;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- memctl->memc_or0 = 0xff800060;
- memctl->memc_br0 = 0xff800801;
-
- flash_get_offsets (0xff800000, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPWV * addr, flash_info_t * info)
-{
- FPW value;
-
- addr[0] = (FPW) 0x00900090;
-
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
-#ifdef FLASH_PORT_WIDTH8
- value = addr[2]; /* device ID */
-#else
- value = addr[1]; /* device ID */
-#endif
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
-
- int i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#elif defined(FLASH_PORT_WIDTH32)
- wp = (addr & ~3);
- port_width = 4;
-#else
- wp = addr;
- port_width = 1;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := impa7.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0xc1780000
+CONFIG_SYS_TEXT_BASE = 0xc1780000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := imx31_phycore.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0x87f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
#
# ROM version
-TEXT_BASE = 0xB0000000
+CONFIG_SYS_TEXT_BASE = 0xB0000000
# RAM version
-#TEXT_BASE = 0x80100000
+#CONFIG_SYS_TEXT_BASE = 0x80100000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o inkadiag.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# INKA 4X0 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFE00000 boot low
-#
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot low
-TEXT_BASE = 0xFFE00000
-## For testing: boot from RAM
-#TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := innokom.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-TEXT_BASE = 0xa1fe0000
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
- icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+ icr = readl(ICR);
+ writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
/* set gpio pin low _before_ we change direction to output */
- GPCR(70) = GPIO_bit(70);
+ writel(GPIO_bit(70), GPCR(70));
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
- GPDR(70) |= GPIO_bit(70); /* output */
+ writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
udelay(10);
- GPDR(70) &= ~GPIO_bit(70); /* input */
+ writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
udelay(10);
}
- ICR = icr;
+ writel(icr, ICR);
return 0;
}
char *str;
/* determine if the software update key is pressed during startup */
- if (GPLR0 & 0x00000800) {
+ if (readl(GPLR0) & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
-
/**
* innokom_set_led: - switch LEDs on or off
*
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf532-0.5
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys IP860 VMEBus Systems
-#
-
-TEXT_BASE = 0x10000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
- arch/powerpc/lib/ticks.o (.text)
-/**
- . = env_offset;
- common/env_embedded.o(.text)
-**/
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IPEK01 board
-#
-
-TEXT_BASE = 0xfc000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# iphase4539 board
-#
-
-TEXT_BASE = 0xffb00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
+COBJS := igep0020.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
#
-# Pandora uses OMAP3 (ARM-CortexA8) cpu
+# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# See file CREDITS for list of people who contributed to this
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0020.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 64 as output pin and send a magic pulse through it */
+ if (!omap_request_gpio(64)) {
+ omap_set_gpio_direction(64, 0);
+ omap_set_gpio_dataout(64, 1);
+ udelay(1);
+ omap_set_gpio_dataout(64, 0);
+ udelay(1);
+ omap_set_gpio_dataout(64, 1);
+ }
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0020_H_
+#define _IGEP0020_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "IGEP v2 board",
+ "ONENAND",
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00080701
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x08030703
+#define NET_LAN9221_GPMC_CONFIG5 0x00060908
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+static void setup_net_chip(void);
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
+#endif
#
-# (C) Copyright 2001-2006
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
+COBJS := igep0030.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
# (C) Copyright 2009
-# Frederik Kriewitz <frederik@kriewitz.eu>
+# ISEE 2007 SL, <www.iseebcn.com>
#
-# DevKit8000 uses OMAP3 (ARM-CortexA8) cpu
+# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# See file CREDITS for list of people who contributed to this
#
# Physical Address:
# 8000'0000 (bank0)
+# A000/0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0030.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_IGEP0030;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0030_H_
+#define _IGEP0030_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 IGEP module",
+ "ONENAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Interphase iSPAN Communications Controllers
-#
-#TEXT_BASE = 0xFF800000
-#TEXT_BASE = 0xFFBA0000
-TEXT_BASE = 0xFE7A0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IVM boards
-#
-
-TEXT_BASE = 0xFF000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ixdp425.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x00f80000
+CONFIG_SYS_TEXT_BASE = 0x00f80000
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# 2004 (c) MontaVista Software, Inc.
+#
# See file CREDITS for list of people who contributed to this
# project.
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := logodl.o flash.o
-SOBJS := lowlevel_init.o
+COBJS := jornada.o
+SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
/*
* (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
+ * 2004 (c) MontaVista Software, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
#include <common.h>
-#include <netdev.h>
+#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Miscelaneous platform dependent initialisations
- */
+/* ------------------------------------------------------------------------- */
-int board_init (void)
+int board_init(void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
+ gd->bd->bi_boot_params = 0xc0000100;
- /* arch number */
- gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
+ /*
+ * Turn on flashing.
+ * Would be nice to have some protection but
+ * that would have to be implemented in the
+ * flash init function, which isnt possible yet.
+ */
+ PPSR |= (1 << 7);
+ PPDR |= (1 << 7);
return 0;
}
-int board_late_init (void)
-{
- setenv ("stdout", "serial");
- setenv ("stderr", "serial");
- return 0;
-}
-
-int dram_init (void)
+int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
+ return (0);
}
-#endif
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG 0x00
+#define MDCAS00 0x04
+#define MDCAS01 0x08
+#define MDCAS02 0x0C
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+#define MDREFR 0x1C
+#define MDCAS20 0x20
+#define MDCAS21 0x24
+#define MDCAS22 0x28
+#define MSC2 0x2C
+#define SMCNFG 0x30
+
+#define GPDR 0x04
+#define GPSR 0x08
+#define GPCR 0x0C
+#define GAFR 0x1C
+
+#define PPDR 0x00
+#define PPSR 0x04
+#define PPAR 0x08
+
+#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
+#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
+#define MDREFR_K0DB2 (1 << 18)
+#define MDREFR_K1DB2 (1 << 22)
+#define MDREFR_K2DB2 (1 << 26)
+
+#define MDREFR_K0RUN (1 << 17)
+#define MDREFR_K1RUN (1 << 21)
+#define MDREFR_K2RUN (1 << 25)
+
+#define MDREFR_SLFRSH (1 << 31)
+#define MDREFR_E1PIN (1 << 20)
+
+#define PSSR 0x04
+#define PSSR_DH 0x00000008
+#define POSR 0x08
+#define RCSR 0x04
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+PWR_BASE: .word 0x90020000
+RST_BASE: .long 0x90030000
+PPC_BASE: .long 0x90060000
+GPIO_BASE: .long 0x90040000
+IC_BASE: .word 0x90050000
+
+cpuspeed: .word 0xa0
+/* calculated from old blob bootloader */
+mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
+mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
+mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
+mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
+msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
+msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
+mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
+mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
+mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
+mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
+mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
+msc2: .long 0x201d2959 /* msc2 0x201d2959 */
+smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
+
+pin_set_out: .long 0x37ff70
+pin_set_dir: .long 0x11480
+
+gpdr_set: .long 0x0B3A0900
+gpsr_set: .long 0x02100800
+gpcr_set: .long 0x092A0100
+gafr_set: .long 0x08600000
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+ /* this is required for flashing */
+ ldr r0, PPC_BASE
+ ldr r1, pin_set_out
+ str r1, [r0, #PPSR]
+ ldr r1, pin_set_dir
+ str r1, [r0, #PPDR]
+
+ /* Setting up the memory and stuff */
+ /***********************************/
+
+ ldr r0, MEM_BASE
+
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+ ldr r1, mdcas00
+ str r1, [r0, #MDCAS00]
+ ldr r1, mdcas01
+ str r1, [r0, #MDCAS01]
+ ldr r1, mdcas02
+ str r1, [r0, #MDCAS02]
+ ldr r1, mdcas20
+ str r1, [r0, #MDCAS20]
+ ldr r1, mdcas21
+ str r1, [r0, #MDCAS21]
+ ldr r1, mdcas22
+ str r1, [r0, #MDCAS22]
+
+ /* clear kxDB2 */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+
+ mov r4, #0x2000
+ spin: subs r4, r4, #1
+ bne spin
+
+ ldr r1, PWR_BASE
+ mov r2, #PSSR_DH
+ str r2, [r1, #PSSR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+ orr r2, r2, #MDREFR_DRI(12)
+ orr r2, r2, #MDREFR_K0DB2
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_K0RUN
+ orr r2, r2, #MDREFR_K1RUN
+ orr r2, r2, #MDREFR_K2RUN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_SLFRSH
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_E1PIN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, MEM_START
+.rept 8
+ ldr r3, [r2]
+.endr
+
+ ldr r2, [r0, #MDCNFG]
+ orr r2, r2, #0x00000003
+ orr r2, r2, #0x00030000
+ str r2, [r0, #MDCNFG]
+
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+ ldr r1, msc1
+ str r1, [r0, #MSC1]
+ ldr r1, msc2
+ str r1, [r0, #MSC2]
+ ldr r1, smcnfg
+ str r1, [r0, #SMCNFG]
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ mov pc, lr
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- cpu/pxa/start.o (.text)
- *(.text)
+ cpu/sa1100/start.o (.text)
+ *(.text)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
+
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o sdram.o flash.o host_bridge.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003 Picture Elements, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Picture Elements, Inc. JSE boards
-#
-
-TEXT_BASE = 0xFFF80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2007
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Jupiter board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-#PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -DDEBUG -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := tx25.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
ifdef CONFIG_NAND_SPL
-TEXT_BASE = 0x810c0000
+CONFIG_SYS_TEXT_BASE = 0x810c0000
else
-TEXT_BASE = 0x81fc0000
+CONFIG_SYS_TEXT_BASE = 0x81200000
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := kb9202.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
km8xx_hdlc_enet.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2007
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mgsvud boards
-#
-
-TEXT_BASE = 0xf0000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
- *(.eh_frame)
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x004000000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
return 0;
}
-int board_init(void)
+int board_early_init_f(void)
{
u32 tmp;
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
kw_gpio_set_valid(SUEN3_ENV_WP, 38);
kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
return 0;
}
);
#endif
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
- kw_sdram_bs(i));
- }
-
- return 0;
-}
-#else
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
kw_sdram_bs(i));
}
}
-#endif
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS += $(BOARD).o ../common/common.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2008
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xF0000000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
mgcoge_hdlc_enet.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2007
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
endif
-ifeq ($(perm),1)
-PLATFORM_CPPFLAGS += -DCONFIG_KORAT_PERMANENT
-TEXT_BASE = 0xFFFA0000
-else
-TEXT_BASE = 0xF7F60000
+ifndef CONFIG_KORAT_PERMANENT
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
endif
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o kup.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# KUP4K board
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
-/*
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-*/
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# KUP4X board
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
-/*
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-*/
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Lantec board (based on TQM8xxL config).
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000, 2001
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+ drivers/rtc/librtc.o (.text*)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := lart.o flash.o
SOBJS := flashasm.o lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0xc1780000
+CONFIG_SYS_TEXT_BASE = 0xc1780000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
OBJS = $(BOARD).o ide.o hwctl.o avr.o
OBJS := $(addprefix $(obj),$(OBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# LinkStation/LinkStation-HG:
-#
-# Valid values for TEXT_BASE are:
-#
-# Standard configuration - all models
-# 0xFFF00000 boot from flash
-#
-# Test configuration (boot from RAM using uloader.o)
-# LinkStation HD-HLAN and KuroBox Standard
-# 0x03F00000 boot from RAM
-# LinkStation HD-HGLAN and KuroBox HG
-# 0x07F00000 boot from RAM
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-# For flash image - all models
-TEXT_BASE = 0xFFF00000
-# For RAM image
-# HLAN and LAN
-#TEXT_BASE = 0x03F00000
-# HGLAN and HGTL
-#TEXT_BASE = 0x07F00000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
#include <pci.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern void init_AVR_DUART(void);
int checkboard (void)
{
- DECLARE_GLOBAL_DATA_PTR;
char *p;
bd_t *bd = gd->bd;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := am3517evm.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := imx27lite.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0xc0000000
+# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
+# makes relative and absolute relocation fixups interchangeable.
+#CONFIG_SYS_TEXT_BASE = 0
+
+CONFIG_SYS_TEXT_BASE = 0xc0000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := imx31_litekit.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0xa0000000
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
+void
+dram_init_banksize (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
int board_init (void)
{
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := zoom1.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
#include <asm/mach-types.h>
#include "zoom1.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-y += debug_board.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
#include "zoom2.h"
#include "zoom2_serial.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This the the zoom2, board specific, gpmc configuration for the
* quad uart on the debug board. The more general gpmc configurations
*/
int board_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
+++ /dev/null
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-#TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# # for the addresses _after_ relocation to RAM!! Otherwhise the
-# # .bss segment is assumed in flash...
-#
-TEXT_BASE = 0x083E0000
+++ /dev/null
-/*
- * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) 2003 August Hoeraendl, Logotronic GmbH
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#undef CONFIG_FLASH_16BIT
-
-#include <common.h>
-
-#define FLASH_BANK_SIZE 0x1000000
-#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- * has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-
-#define FLASH_ID_MASK 0xFFFF
-#else
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-#define write_word(in, de, da) write_word_amd(in, de, da)
-static void flash_get_offsets(ulong base, flash_info_t *info);
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-static void flash_sync_real_protect(flash_info_t *info);
-#endif
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-ulong flash_init(void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- {
- ulong flashbase = 0;
- flash_info[i].flash_id =
- (FLASH_MAN_AMD & FLASH_VENDMASK) |
- (FLASH_AM640U & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- switch (i)
- {
- case 0:
- flashbase = PHYS_FLASH_1;
- break;
- case 1:
- flashbase = PHYS_FLASH_2;
- break;
- default:
- panic("configured too many flash banks!\n");
- break;
- }
- for (j = 0; j < flash_info[i].sector_count; j++)
- {
- flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
- &flash_info[0]);
-
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
- && (info->flash_id & FLASH_BTYPE)) {
- int bootsect_size; /* number of bytes/boot sector */
- int sect_size; /* number of bytes/regular sector */
-
- bootsect_size = 0x00002000 * (sizeof(FPW)/2);
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < 8; ++i) {
- info->start[i] = base + (i * bootsect_size);
- }
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i - 7) * sect_size);
- }
- }
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
- && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
-
- int sect_size; /* number of bytes/sector */
-
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set up sector start address table (uniform sector type) */
- for( i = 0; i < info->sector_count; i++ )
- info->start[i] = base + (i * sect_size);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- uchar *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM640U:
- fmt = "29LV641D (64 Mbit, uniform sectors)\n";
- break;
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- fmt = "28F800C3%s (8 Mbit, %s)\n";
- break;
- case FLASH_INTEL800B:
- case FLASH_INTEL800T:
- fmt = "28F800B3%s (8 Mbit, %s)\n";
- break;
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- fmt = "28F160C3%s (16 Mbit, %s)\n";
- break;
- case FLASH_INTEL160B:
- case FLASH_INTEL160T:
- fmt = "28F160B3%s (16 Mbit, %s)\n";
- break;
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- fmt = "28F320C3%s (32 Mbit, %s)\n";
- break;
- case FLASH_INTEL320B:
- case FLASH_INTEL320T:
- fmt = "28F320B3%s (32 Mbit, %s)\n";
- break;
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- fmt = "28F640C3%s (64 Mbit, %s)\n";
- break;
- case FLASH_INTEL640B:
- case FLASH_INTEL640T:
- fmt = "28F640B3%s (64 Mbit, %s)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- /* Write auto select command: read Manufacturer ID */
-
- /* Write auto select command sequence and test FLASH answer */
- addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
-
- case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F800C3B:
- info->flash_id += FLASH_28F800C3B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F800B3B:
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F160C3B:
- info->flash_id += FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F160B3B:
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F320C3B:
- info->flash_id += FLASH_28F320C3B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F320B3B:
- info->flash_id += FLASH_INTEL320B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F640C3B:
- info->flash_id += FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F640B3B:
- info->flash_id += FLASH_INTEL640B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets((ulong)addr, info);
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-/*-----------------------------------------------------------------------
- */
-
-static void flash_sync_real_protect(flash_info_t *info)
-{
- FPWV *addr = (FPWV *)(info->start[0]);
- FPWV *sect;
- int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- /* check for protected sectors */
- *addr = (FPW)0x00900090;
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02.
- * D0 = 1 for each device if protected.
- * If at least one device is protected the sector is marked
- * protected, but mixed protected and unprotected devices
- * within a sector should never happen.
- */
- sect = (FPWV *)(info->start[i]);
- info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
- break;
-
- case FLASH_AM640U:
- default:
- /* no hardware protect that we support */
- break;
- }
-}
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_INTEL800B:
- case FLASH_INTEL160B:
- case FLASH_INTEL320B:
- case FLASH_INTEL640B:
- case FLASH_28F800C3B:
- case FLASH_28F160C3B:
- case FLASH_28F320C3B:
- case FLASH_28F640C3B:
- case FLASH_AM640U:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer(0);
- last = start;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- base[0x0555] = (FPW)0x00800080; /* erase mode */
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- case FLASH_MAN_INTEL:
- res = write_word_intel(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/**
- * write_buf: - Copy memory to flash.
- *
- * @param info:
- * @param src: source of copy transaction
- * @param addr: where to copy to
- * @param cnt: number of bytes to copy
- *
- * @return error code
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int l;
- int i, rc;
-
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
- for (; i<2 && cnt>0; ++i) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 2) {
- /* data = *((vushort*)src); */
- data = *((FPW*)src);
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- src += sizeof(FPW);
- wp += sizeof(FPW);
- cnt -= sizeof(FPW);
- }
-
- if (cnt == 0) return ERR_OK;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- }
- for (; i<2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 8);
- }
-
- return write_word(info, wp, data);
-}
-
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- base[0x0555] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for Intel FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
- *dest = (FPW)0x00400040; /* program setup */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00B000B0; /* Suspend program */
- res = 1;
- }
- }
-
- if (res == 0 && (*dest & (FPW)0x00100010))
- res = 1; /* write failed, time out error is close enough */
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
-
- return (res);
-}
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
- int rcode = 0; /* assume success */
- FPWV *addr; /* address of sector */
- FPW value;
-
- addr = (FPWV *) (info->start[sector]);
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- flash_reset (info); /* make sure in read mode */
- *addr = (FPW) 0x00600060L; /* lock command setup */
- if (prot)
- *addr = (FPW) 0x00010001L; /* lock sector */
- else
- *addr = (FPW) 0x00D000D0L; /* unlock sector */
- flash_reset (info); /* reset to read mode */
-
- /* now see if it really is locked/unlocked as requested */
- *addr = (FPW) 0x00900090;
- /* read sector protection at sector address, (A7 .. A0) = 0x02.
- * D0 = 1 for each device if protected.
- * If at least one device is protected the sector is marked
- * protected, but return failure. Mixed protected and
- * unprotected devices within a sector should never happen.
- */
- value = addr[2] & (FPW) 0x00010001;
- if (value == 0)
- info->protect[sector] = 0;
- else if (value == (FPW) 0x00010001)
- info->protect[sector] = 1;
- else {
- /* error, mixed protected and unprotected */
- rcode = 1;
- info->protect[sector] = 1;
- }
- if (info->protect[sector] != prot)
- rcode = 1; /* failed to protect/unprotect as requested */
-
- /* reload all protection bits from hardware for now */
- flash_sync_real_protect (info);
- break;
-
- case FLASH_AM640U:
- default:
- /* no hardware protect that we support */
- info->protect[sector] = prot;
- break;
- }
-
- return rcode;
-}
-#endif
+++ /dev/null
-/*
- * (C) 2002 Kyle Harris <kharris@nexus-tech.net>, Nexus Technologies, Inc.
- * (C) 2002 Marius Groeger <mgroeger@sysgo.de>, Sysgo GmbH
- * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/**
- * board_init: - setup some data structures
- *
- * @return: 0 in case of success
- */
-
-int board_init (void)
-{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- gd->bd->bi_arch_number = MACH_TYPE_LOGODL;
- gd->bd->bi_boot_params = 0x08000100;
- gd->bd->bi_baudrate = CONFIG_BAUDRATE;
-
- (*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */
- (*((volatile short*)0x14000000)) = 0xff; /* power on uart */
-
- return 0;
-}
-
-
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-
-/**
- * logodl_set_led: - switch LEDs on or off
- *
- * @param led: LED to switch (0,1)
- * @param state: switch on (1) or off (0)
- */
-
-void logodl_set_led(int led, int state)
-{
- switch(led) {
-
- case 0:
- if (state==1) {
- CONFIG_SYS_LED_A_CR = CONFIG_SYS_LED_A_BIT;
- } else if (state==0) {
- CONFIG_SYS_LED_A_SR = CONFIG_SYS_LED_A_BIT;
- }
- break;
-
- case 1:
- if (state==1) {
- CONFIG_SYS_LED_B_CR = CONFIG_SYS_LED_B_BIT;
- } else if (state==0) {
- CONFIG_SYS_LED_B_SR = CONFIG_SYS_LED_B_BIT;
- }
- break;
- }
-
- return;
-}
-
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
- if (status < -32) status = -1; /* let things compatible */
- /*
- switch(status) {
- case 1: logodl_set_led(0,1); break;
- case 5: logodl_set_led(1,1); break;
- case 15: logodl_set_led(2,1); break;
- }
- */
- logodl_set_led(0, (status & 1)==1);
- logodl_set_led(1, (status & 2)==2);
-
- return;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := flash.o lpc2292sodimm.o
SOBJTS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJTS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#address where u-boot will be relocated
-#TEXT_BASE = 0x0
-TEXT_BASE = 0x81500000
+#CONFIG_SYS_TEXT_BASE = 0x0
+CONFIG_SYS_TEXT_BASE = 0x81500000
#define BCFG1_VALUE 0x10001C61
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
MEMMAP_ADR:
.word MEMMAP
BCFG0_ADR:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := lpd7a40x.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# download area is 0xc0f00000
#
-TEXT_BASE = 0xc1fc0000
-#TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0xc1fc0000
+#CONFIG_SYS_TEXT_BASE = 0x00000000
#define DO_MEM_READ 2
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := lubbock.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-#TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3080000
-#TEXT_BASE = 0
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- orr r4, r4, #(MDREFR_SLFRSH)
- bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_NET
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# LWE Monitorcontroller Litronic LCD IV boards
-#
-
-TEXT_BASE = 0x40000000
-#TEXT_BASE = 0x41000000
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o kbd.o sdram.o
SOBJS = init.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
# lwmon5 (440EPx)
#
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
/*--------------------- Local macros and constants --------------------*/
#define _NOT_USED_ 0xFFFFFFFF
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG 0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG 0x810
/*------------------------- Keyboard controller -----------------------*/
/* command codes */
#define KEYBD_CMD_READ_KEYS 0x01
/* maximum number of "magic" key codes that can be assigned */
static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
static uchar *key_match (uchar *);
}
}
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+ uchar buf[sizeof(*data)];
+ int rval;
+
+ if (i2c_read(dspic_addr, reg, 2, buf, 2))
+ return -1;
+
+ rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+ *data = (buf[0] << 8) | buf[1];
+
+ return rval;
+}
+
+
/***********************************************************************
F* Function: int misc_init_r (void) P*A*Z*
*
uchar kbd_init_status = gd->kbd_status >> 8;
uchar kbd_status = gd->kbd_status;
uchar val;
+ ushort data, inv_data;
char *str;
int i;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+ /* read out start key from bse01 received via can */
+ _dspic_read(DSPIC_PON_STATUS_REG, &data);
+ /* check highbyte from status register */
+ if (data > 0xFF) {
+ _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+ /* check inverse data */
+ if ((data+inv_data) == 0xFFFF) {
+ /* don't overwrite local key */
+ if (kbd_data[1] == 0) {
+ /* read key value */
+ _dspic_read(DSPIC_PON_KEY_REG, &data);
+ str = (char *)&data;
+ /* swap bytes */
+ kbd_data[1] = str[1];
+ kbd_data[2] = str[0];
+ printf("CAN received startkey: 0x%X\n", data);
+ }
+ }
+ }
+
for (i = 0; i < KEYBD_DATALEN; ++i) {
sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
}
+
setenv ("keybd", keybd_env);
str = strdup ((char *)key_match (kbd_data)); /* decode keys */
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
#include <asm/processor.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
ulong flash_get_size(ulong base, int banknum);
int misc_init_r_kbd(void);
gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
- gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+ /* enable the CAN transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
reg = 0; /* reuse as counter */
out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
& ~CONFIG_SYS_DSPIC_TEST_MASK);
- while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+ while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
udelay(1000);
}
- gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
/* set "boot error" flag */
out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
return 0;
}
-/*---------------------------------------------------------------------------+
- | misc_init_r.
- +---------------------------------------------------------------------------*/
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+ return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+ u32 val0, val1;
+
+ /*
+ * lwmon5 is manufactured in 2 different board versions:
+ * The lwmon5a board has 64MiB NOR flash instead of the
+ * 128MiB of the original lwmon5. Unfortunately the CFI driver
+ * will report 2 banks of 64MiB even for the smaller flash
+ * chip, since the bank is mirrored. To fix this, we bring
+ * one bank into CFI query mode and read its response. This
+ * enables us to detect the real number of flash devices/
+ * banks which will be used later on by the common CFI driver.
+ */
+
+ /* Put bank 0 into CFI command mode and read */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+ val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+ val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+ /* Reset flash again out of query mode */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+ /* When not identical, we have 2 different flash devices/banks */
+ if (val0 != val1)
+ return 0;
+
+ /*
+ * Now we're sure that we're running on a LWMON5a board with
+ * only 64MiB NOR flash in one bank:
+ *
+ * Set flash base address and bank count for CFI driver probing.
+ */
+ cfi_flash_num_flash_banks = 1;
+ lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+ return 0;
+}
+
int misc_init_r(void)
{
u32 pbcr;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
+ unsigned long sdr0_pfc1, sdr0_srst;
/*
* FLASH stuff...
gd->bd->bi_flashoffset = 0;
mfebc(PB0CR, pbcr);
- switch (gd->bd->bi_flashsize) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- case 32 << 20:
- size_val = 5;
- break;
- case 64 << 20:
- size_val = 6;
- break;
- case 128 << 20:
- size_val = 7;
- break;
- }
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(PB0CR, pbcr);
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[1]);
+ flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
/* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[1]);
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
/*
* USB suff...
*/
+
+ /* Reset USB */
+ /* Reset of USB2PHY0 must be active at least 10 us */
+ mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+ udelay(2000);
+
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+ SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+ SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+ udelay(2000);
+
+ /* Errata CHIP_6 */
+
+ /* 1. Set internal PHY configuration */
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ /* 2. De-assert internal PHY reset */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+
+ /* 3. Wait for more than 1 ms */
+ udelay(2000);
+
+ /* 4. De-assert USB 2.0 Host main reset */
+ mfsdr(SDR0_SRST0, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst);
+ udelay(1000);
+
+ /* 5. De-assert reset of OPB2 cores */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+ udelay(1000);
+
+ /* 6. Set EHCI Configure FLAG */
+
+ /* 7. Reassert internal PHY reset: */
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+ udelay(1000);
+
/*
* Clear resets
*/
- udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
- udelay (1000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
{
char *s = getenv("serial#");
- printf("Board: lwmon5");
+ puts("Board: lwmon5");
if (s != NULL) {
puts(", serial# ");
extern GraphicDevice mb862xx;
-static const gdc_regs init_regs [] =
-{
- {0x0100, 0x00000f00},
- {0x0020, 0x801401df},
- {0x0024, 0x00000000},
- {0x0028, 0x00000000},
- {0x002c, 0x00000000},
- {0x0110, 0x00000000},
- {0x0114, 0x00000000},
- {0x0118, 0x01df0280},
- {0x0004, 0x031f0000},
- {0x0008, 0x027f027f},
- {0x000c, 0x015f028f},
- {0x0010, 0x020c0000},
- {0x0014, 0x01df01ea},
- {0x0018, 0x00000000},
- {0x001c, 0x01e00280},
- {0x0100, 0x80010f00},
- {0x0, 0x0}
+static const gdc_regs init_regs [] = {
+ { 0x0100, 0x00000f00 },
+ { 0x0020, 0x801401df },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x00000000 },
+ { 0x0110, 0x00000000 },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x01df0280 },
+ { 0x0004, 0x031f0000 },
+ { 0x0008, 0x027f027f },
+ { 0x000c, 0x015f028f },
+ { 0x0010, 0x020c0000 },
+ { 0x0014, 0x01df01ea },
+ { 0x0018, 0x00000000 },
+ { 0x001c, 0x01e00280 },
+ { 0x0100, 0x80010f00 },
+ { 0x0, 0x0 }
};
-const gdc_regs *board_get_regs (void)
+const gdc_regs *board_get_regs(void)
{
return init_regs;
}
/* Returns Lime base address */
-unsigned int board_video_init (void)
+unsigned int board_video_init(void)
{
/*
* Reset Lime controller
return CONFIG_SYS_LIME_BASE_0;
}
-#define DEFAULT_BRIGHTNESS 0x64
+#define DEFAULT_BRIGHTNESS 0x64
static void board_backlight_brightness(int brightness)
{
}
}
-void board_backlight_switch (int flag)
+void board_backlight_switch(int flag)
{
char * param;
int rc;
/*
* Return text to be printed besides the logo.
*/
-void video_get_info_str (int line_number, char *info)
+void video_get_info_str(int line_number, char *info)
{
- if (line_number == 1) {
- strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
- } else {
+ if (line_number == 1)
+ strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+ else
info [0] = '\0';
- }
}
-#endif
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
#endif /* CONFIG_VIDEO */
void board_reset(void)
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
- * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
-#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
MY_TLB_WORD2_I_ENABLE);
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
/*
* Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation.
*/
program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#endif
+
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
/*
* Clear possible errors resulting from data-eye-search.
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := m501sk.o eeprom.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x21f00000
+CONFIG_SYS_TEXT_BASE = 0x21f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# INKA 4X0 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFE00000 boot high
-#
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-#TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2008
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MUCMC52 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFE00000 boot high
-#
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-#TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
#COBJS = $(BOARD).o flash.o pcmcia.o
COBJS = $(BOARD).o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# UC100 boards
-#
-
-#TEXT_BASE = 0x40000000
-TEXT_BASE = 0x40700000
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# INKA 4X0 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFE00000 boot high
-#
-# 0x00100000 boot from RAM (for testing only)
-#
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-#TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)lib$(VENDOR).o
COBJS-y = mv_common.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o fpga.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFF800000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o pci.o fpga.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
clean:
+++ /dev/null
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-TEXT_BASE = 0xFFF00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o fpga.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
clean:
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFF800000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the first two sectors (=8KB) of our S29GL flash chip */
- arch/powerpc/cpu/mpc5xxx/start.o (.text)
- arch/powerpc/cpu/mpc5xxx/traps.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text*)
+ arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
+ board/matrix_vision/common/libmatrix_vision.o (.text*)
/* This is only needed to force failure if size of above code will ever */
/* increase and grow into reserved space. */
. = env_offset; /* ld error as soon as above ALIGN misplaces lc */
common/env_embedded.o (.ppcenv)
- *(.text)
- *(.got1)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
+ *(.bss*)
+ *(.sbss*)
. = ALIGN(4);
}
_end = . ;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o vpd.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0xfe000000
-/*TEXT_BASE = 0x00200000 */
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o lcd.o auto_update.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MCC200, PRS200 boards:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFC000000 boot low (standard configuration)
-# 0xFFF00000 boot high
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot low
-TEXT_BASE = 0xFC000000
-## Boot high
-# TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-y += ebi.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
-ifndef TEXT_BASE
-TEXT_BASE = 0x87000000
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0x87000000
endif
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_LDFLAGS += --gc-sections
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
PLATFORM_LDFLAGS += --gc-sections
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o serial.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0x18000000
-
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/ml2/u-boot.lds
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/ml2/init.o (.text)
- arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
- arch/powerpc/cpu/ppc4xx/traps.o (.text)
- arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
- arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
- arch/powerpc/cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
+ *(.data*)
+ *(.sdata*)
CONSTRUCTORS
}
_edata = .;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := modnet50.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x00f00000
+CONFIG_SYS_TEXT_BASE = 0x00f00000
#CROSS_COMPILE = arm-elf-
lowlevel_init:
#if defined(CONFIG_MODNET50)
- ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
+ ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - CONFIG_SYS_TEXT_BASE)
_jump_to_high:
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFFFA0000
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Promess Motion-PRO
-#
-
-TEXT_BASE = 0xfff00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o m48t59y.o pci.o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MOUSSE boards
-#
-TEXT_BASE = 0xFFF00000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
-
-LDSCRIPT := $(SRCTREE)/board/mousse/u-boot.lds
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc824x/start.o (.text)
- arch/powerpc/lib/board.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- *(.got1)
+ arch/powerpc/cpu/mpc824x/start.o (.text*)
+ *(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mp2usb.o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x27F00000
+CONFIG_SYS_TEXT_BASE = 0x27F00000
## For testing: load at 0x20100000 and "go" at 0x201000A4
-#TEXT_BASE = 0x20100000
+#CONFIG_SYS_TEXT_BASE = 0x20100000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-ifndef TEXT_BASE
-TEXT_BASE = 0xFC000000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# gda8540 board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-#TEXT_BASE = 0x1000000
-TEXT_BASE = 0xfff80000
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong size,src,ld_addr;
+ ulong ld_addr;
int result;
#if !defined(CONFIG_PATI)
+ ulong size = IMAGE_SIZE;
+ ulong src = MULTI_PURPOSE_SOCKET_ADDR;
backup_t back;
- src = MULTI_PURPOSE_SOCKET_ADDR;
- size = IMAGE_SIZE;
#endif
if (strcmp(argv[1], "flash") == 0)
}
#endif /* #if !defined(CONFIG_PATI) */
}
- if (strcmp(argv[1], "mem") == 0)
- {
- result=0;
- if(argc==3)
- {
- result = (int)simple_strtol(argv[2], NULL, 16);
- }
- src=(unsigned long)&result;
- src-=CONFIG_SYS_MEMTEST_START;
- src-=(100*1024); /* - 100k */
- src&=0xfff00000;
- size=0;
- do {
- size++;
- printf("\n\nPass %ld\n",size);
- mem_test(CONFIG_SYS_MEMTEST_START,src,1);
- if(ctrlc())
- break;
- if(result>0)
- result--;
-
- }while(result);
- return 0;
- }
#if !defined(CONFIG_PATI)
if (strcmp(argv[1], "clearenvvalues") == 0)
{
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/* NOT Used yet...
- add following code to PIP405.c :
-int testdram (void)
-{
- unsigned char s[32];
- int i;
-
- i = getenv_f("testmem", s, 32);
- if (i != 0) {
- i = (int) simple_strtoul (s, NULL, 10);
- if ((i > 0) && (i < 0xf)) {
- printf ("testing ");
- i = mem_test (0, ramsize, i);
- if (i > 0)
- printf ("ERROR ");
- else
- printf ("Ok ");
- }
- }
- return (1);
-}
-*/
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FALSE 0
-#define TRUE 1
-
-#define TEST_QUIET 8
-#define TEST_SHOW_PROG 4
-#define TEST_SHOW_ERR 2
-#define TEST_SHOW_ALL 1
-
-#define TESTPAT1 0xAA55AA55
-#define TESTPAT2 0x55AA55AA
-#define TEST_PASSED 0
-#define TEST_FAILED 1
-#define MEGABYTE (1024*1024)
-
-
-typedef struct {
- volatile unsigned long pat1;
- volatile unsigned long pat2;
-} RAM_MEMTEST_PATTERN2;
-
-typedef struct {
- volatile unsigned long addr;
-} RAM_MEMTEST_ADDRLINE;
-
-static __inline unsigned long Swap_32 (unsigned long val)
-{
- return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF));
-}
-
-void testm_puts (int quiet, char *buf)
-{
- if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL)
- puts (buf);
-}
-
-
-void Write_Error (int mode, unsigned long addr, unsigned long expected,
- unsigned long actual)
-{
-
- char dispbuf[64];
-
- sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ",
- addr, expected, actual);
- testm_puts (((mode & TEST_SHOW_ERR) ==
- TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf);
-}
-
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2
- */
-
-
-void RAM_MemTest_WritePattern2 (unsigned long startaddr,
- unsigned long size, unsigned long pat1,
- unsigned long pat2)
-{
- RAM_MEMTEST_PATTERN2 *p, *pe;
-
- p = (RAM_MEMTEST_PATTERN2 *) startaddr;
- pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
-
- while (p < pe) {
- p->pat1 = pat1;
- p->pat2 = pat2;
- p++;
- } /* endwhile */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2
- * returns the address of the first error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long pat1,
- unsigned long pat2)
-{
- RAM_MEMTEST_PATTERN2 *p, *pe;
- unsigned long actual1, actual2;
-
- p = (RAM_MEMTEST_PATTERN2 *) startaddr;
- pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
-
- while (p < pe) {
- actual1 = p->pat1;
- actual2 = p->pat2;
-
- if (actual1 != pat1) {
- Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1);
- return ((void *) &(p->pat1));
- }
- /* endif */
- if (actual2 != pat2) {
- Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2);
- return ((void *) &(p->pat2));
- }
- /* endif */
- p++;
- } /* endwhile */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with the address
- */
-
-void RAM_MemTest_WriteAddrLine (unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
-
- p = (RAM_MEMTEST_ADDRLINE *) startaddr;
- pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
-
- if (!swapped) {
- while (p < pe) {
- p->addr = (unsigned long) p;
- p++;
- } /* endwhile */
- } else {
- while (p < pe) {
- p->addr = Swap_32 ((unsigned long) p);
- p++;
- } /* endwhile */
- } /* endif */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
- unsigned long actual, expected;
-
- p = (RAM_MEMTEST_ADDRLINE *) startaddr;
- pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
-
- if (!swapped) {
- while (p < pe) {
- actual = p->addr;
- expected = (unsigned long) p;
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p++;
- } /* endwhile */
- } else {
- while (p < pe) {
- actual = p->addr;
- expected = Swap_32 ((unsigned long) p);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p++;
- } /* endwhile */
- } /* endif */
-
- return (NULL);
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr+size>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
- unsigned long actual, expected;
-
- p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr));
- pe = (RAM_MEMTEST_ADDRLINE *) startaddr;
-
- if (!swapped) {
- while (p > pe) {
- actual = p->addr;
- expected = (unsigned long) p;
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p--;
- } /* endwhile */
- } else {
- while (p > pe) {
- actual = p->addr;
- expected = Swap_32 ((unsigned long) p);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p--;
- } /* endwhile */
- } /* endif */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with walking bit pattern
- */
-
-void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size)
-{
- volatile unsigned long *p, *pe;
- unsigned long i;
-
- p = (unsigned long *) startaddr;
- pe = (unsigned long *) (startaddr + size);
- i = 0;
-
- while (p < pe) {
- *p = 1UL << i;
- i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
- p++;
- } /* endwhile */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr,
- unsigned long size)
-{
- volatile unsigned long *p, *pe;
- unsigned long actual, expected;
- unsigned long i;
-
- p = (unsigned long *) startaddr;
- pe = (unsigned long *) (startaddr + size);
- i = 0;
-
- while (p < pe) {
- actual = *p;
- expected = (1UL << i);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) p, expected, actual);
- return ((void *) p);
- } /* endif */
- i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
- p++;
- } /* endwhile */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with "random" pattern
- */
-
-void RAM_MemTest_WriteRandomPattern (unsigned long startaddr,
- unsigned long size,
- unsigned long *pat)
-{
- unsigned long i, p;
-
- p = *pat;
-
- for (i = 0; i < (size / 4); i++) {
- *(unsigned long *) (startaddr + i * 4) = p;
- if ((p % 2) > 0) {
- p ^= i;
- p >>= 1;
- p |= 0x80000000;
- } else {
- p ^= ~i;
- p >>= 1;
- } /* endif */
- } /* endfor */
- *pat = p;
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr,
- unsigned long size,
- unsigned long *pat)
-{
- void *perr = NULL;
- unsigned long i, p, p1;
-
- p = *pat;
-
- for (i = 0; i < (size / 4); i++) {
- p1 = *(unsigned long *) (startaddr + i * 4);
- if (p1 != p) {
- if (perr == NULL) {
- Write_Error (mode, startaddr + i * 4, p, p1);
- perr = (void *) (startaddr + i * 4);
- } /* endif */
- }
- /* endif */
- if ((p % 2) > 0) {
- p ^= i;
- p >>= 1;
- p |= 0x80000000;
- } else {
- p ^= ~i;
- p >>= 1;
- } /* endif */
- } /* endfor */
-
- *pat = p;
- return (perr);
-}
-
-
-void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2);
-}
-
-void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckPattern2
- (mode, startaddr, size, TESTPAT1, TESTPAT2));
-}
-
-void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1);
-}
-
-void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckPattern2
- (mode, startaddr, size, TESTPAT2, TESTPAT1));
-}
-
-void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WriteAddrLine (startaddr, size, FALSE);
-}
-
-void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE));
-}
-
-void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLineReverse
- (mode, startaddr, size, FALSE));
-}
-
-void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WriteAddrLine (startaddr, size, TRUE);
-}
-
-void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE));
-}
-
-void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLineReverse
- (mode, startaddr, size, TRUE));
-}
-
-
-typedef struct {
- void (*test_write) (unsigned long startaddr, unsigned long size,
- unsigned long *pat);
- char *test_write_desc;
- void *(*test_check1) (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat);
- void *(*test_check2) (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat);
-} RAM_MEMTEST_FUNC;
-
-
-#define TEST_STAGES 5
-static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
- {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1,
- NULL},
- {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2,
- NULL},
- {RAM_MemTest_WriteAddr1, "address line test...\n",
- RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1},
- {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n",
- RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2},
- {RAM_MemTest_WriteRandomPattern, "random data test...\n",
- RAM_MemTest_CheckRandomPattern, NULL}
-};
-
-
-int mem_test (unsigned long start, unsigned long ramsize, int quiet)
-{
- unsigned long errors, stage;
- unsigned long startaddr, size, i;
- const unsigned long blocksize = 0x80000; /* check in 512KB blocks */
- unsigned long *perr;
- unsigned long rdatapat;
- char dispbuf[80];
- int status = TEST_PASSED;
- int prog = 0;
-
- errors = 0;
- startaddr = start;
- size = ramsize;
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n",
- startaddr, size);
- testm_puts (quiet, dispbuf);
- for (stage = 0; stage < TEST_STAGES; stage++) {
- sprintf (dispbuf, test_stage[stage].test_write_desc);
- testm_puts (quiet, dispbuf);
- /* fill SDRAM */
- rdatapat = 0x12345678;
- sprintf (dispbuf, "writing block: ");
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- test_stage[stage].test_write (startaddr + i, blocksize,
- &rdatapat);
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- /* check SDRAM */
- rdatapat = 0x12345678;
- sprintf (dispbuf, "checking block: ");
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- if ((perr =
- test_stage[stage].test_check1 (quiet, startaddr + i,
- blocksize,
- &rdatapat)) != NULL) {
- status = TEST_FAILED;
- } /* endif */
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- if (test_stage[stage].test_check2 != NULL) {
- /* check2 SDRAM */
- sprintf (dispbuf, "2nd checking block: ");
- rdatapat = 0x12345678;
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- if ((perr =
- test_stage[stage].test_check2 (quiet, startaddr + i,
- blocksize,
- &rdatapat)) != NULL) {
- status = TEST_FAILED;
- } /* endif */
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- }
-
- } /* next stage */
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- while (prog-- > 0)
- printf ("\b \b");
- }
-
- if (status == TEST_FAILED)
- errors++;
-
- return (errors);
-}
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
- ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o
+ ../common/usb_uhci.o ../common/common_util.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"mip405 flash mps - updates U-Boot with image from MPS\n"
"mip405 info - displays board information\n"
- "mip405 led <on> - switches LED on (on=1) or off (on=0)\n"
- "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever"
+ "mip405 led <on> - switches LED on (on=1) or off (on=0)"
);
/* ------------------------------------------------------------------------- */
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o
+COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o
#### cmd_pati.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# EPQ Board Configuration
-#
-
-# Boot from flash at location 0x00000000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o \
../common/flash.o cmd_pip405.o ../common/pci.o \
../common/isa.o ../common/kbd.o \
../common/usb_uhci.o \
- ../common/memtst.o ../common/common_util.o
+ ../common/common_util.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := vcma9.o flash.o cmd_vcma9.o
-COBJS += ../common/common_util.o ../common/memtst.o
+COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-#TEXT_BASE = 0x30F80000
-TEXT_BASE = 0x33F80000
+#CONFIG_SYS_TEXT_BASE = 0x30F80000
+CONFIG_SYS_TEXT_BASE = 0x33F80000
/**************************************/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x002AAAAA;
- gpio->GPBUP = 0x000002BF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x000037F7;
- gpio->GPFCON = 0x00000000;
- gpio->GPFUP = 0x00000000;
- gpio->GPGCON = 0xFFEAFF5A;
- gpio->GPGUP = 0x0000F0DC;
- gpio->GPHCON = 0x0028AAAA;
- gpio->GPHUP = 0x00000656;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x002AAAAA;
+ gpio->gpbup = 0x000002BF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x000037F7;
+ gpio->gpfcon = 0x00000000;
+ gpio->gpfup = 0x00000000;
+ gpio->gpgcon = 0xFFEAFF5A;
+ gpio->gpgup = 0x0000F0DC;
+ gpio->gphcon = 0x0028AAAA;
+ gpio->gphup = 0x00000656;
/* setup correct IRQ modes for NIC */
- gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+ /* rising edge mode */
+ gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
/* select USB port 2 to be host or device (fix to host for now) */
- gpio->MISCCR |= 0x08;
+ gpio->misccr |= 0x08;
/* init serial */
gd->baudrate = CONFIG_BAUDRATE;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mpr2.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: MPR2\n");
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ms7720se.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define LED_BASE 0xB0800000
int checkboard(void)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ms7722se.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define LED_BASE 0xB0800000
int checkboard(void)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ms7750se.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <common.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2008
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFF000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2007
-# Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MUNICes board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFF00000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# CU824 board
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
+ arch/powerpc/cpu/mpc824x/start.o (.text*)
+ lib/libgeneric.o (.text*)
+ net/libnet.o (.text*)
+ drivers/pci/libpci.o (.text*)
+ arch/powerpc/cpu/mpc824x/libmpc824x.o (.text*)
+ board/mvblue/libmvblue.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+
+ *(.text*)
+ . = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mx1ads.o syncflash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-TEXT_BASE = 0x08400000
+CONFIG_SYS_TEXT_BASE = 0x08400000
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := mx1fs2.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This config file is used for compilation of IMX sources
#
-# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
# This allows for example having one copy located at the end of ram and stored
# in flash device and later on while developing use other location to test
# the code in RAM device only.
#
-TEXT_BASE = 0x08f00000
+CONFIG_SYS_TEXT_BASE = 0x08f00000
+++ /dev/null
-#
-# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# NC650 board
-#
-
-TEXT_BASE = 0x40700000
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#undef DEBUG
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
-#define CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH8
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#elif FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#else /* FLASH_PORT_WIDTH8 */
-#define FLASH_PORT_WIDTH uchar
-#define FLASH_PORT_WIDTHV vu_char
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPWV * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
- int scy, trlx, flash_or_timing, clk_diff;
-
- scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
- if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
- trlx = OR_TRLX;
- scy *= 2;
- } else
- trlx = 0;
-
- /* We assume that each 10MHz of bus clock require 1-clk SCY
- * adjustment.
- */
- clk_diff = (gd->bus_clk / 1000000) - 50;
-
- /* We need proper rounding here. This is what the "+5" and "-5"
- * are here for.
- */
- if (clk_diff >= 0)
- scy += (clk_diff + 5) / 10;
- else
- scy += (clk_diff - 5) / 10;
-
- /* For bus frequencies above 50MHz, we want to use relaxed
- * timing (OR_TRLX).
- */
- if (gd->bus_clk >= 50000000)
- trlx = OR_TRLX;
- else
- trlx = 0;
-
- if (trlx)
- scy /= 2;
-
- if (scy > 0xf)
- scy = 0xf;
- if (scy < 1)
- scy = 1;
-
- flash_or_timing = (scy << 4) | trlx |
- (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
-#endif
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Remap FLASH according to real size */
-#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-#else
- memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
-#endif
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPWV * addr, flash_info_t * info)
-{
- FPW value;
-
- addr[0] = (FPW) 0x00900090;
-
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
-#ifdef FLASH_PORT_WIDTH8
- value = addr[2]; /* device ID */
-#else
- value = addr[1]; /* device ID */
-#endif
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
-
- int i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#elif defined(FLASH_PORT_WIDTH32)
- wp = (addr & ~3);
- port_width = 4;
-#else
- wp = addr;
- port_width = 1;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-#if defined(CONFIG_IDS852_REV1)
-/*
- * hardware specific access to control-lines
- */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- this->IO_ADDR_W += 2;
- else
- this->IO_ADDR_W -= 2;
- if ( ctrl & NAND_ALE )
- this->IO_ADDR_W += 1;
- else
- this->IO_ADDR_W -= 1;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-#elif defined(CONFIG_IDS852_REV2)
-/*
- * hardware specific access to control-lines
- */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- if ( ctrl & NAND_ALE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x9);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- if ( ctrl & NAND_NCE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-#else
-#error Unknown IDS852 module revision
-#endif
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - eccm.ode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-
- nand->cmd_ctrl = nc650_hwcontrol;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->chip_delay = 12;
-/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Memory Controller Using
- *
- * CS0 - Flash memory (0x40000000)
- * CS3 - SDRAM (0x00000000}
- */
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_ 0xffffffff
-
-const uint sdram_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* MRS initialization (offset 5) */
-
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _not_used_, _not_used_, _not_used_
-};
-
-const uint nand_flash_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
- 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
-
- /* burst read. (offset 8 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* single write. (offset 18 in upm RAM) */
- 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
- 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
-
- /* burst write. (offset 20 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* refresh. (offset 30 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* exception. (offset 3c in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-#if !defined(CONFIG_CP850)
- puts ("Board: NC650");
-#else
- puts ("Board: CP850");
-#endif
-#if defined(CONFIG_IDS852_REV1)
- puts (" with IDS852 rev 1 module\n");
-#elif defined(CONFIG_IDS852_REV2)
- puts (" with IDS852 rev 2 module\n");
-#endif
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
- unsigned long reg;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 1 to the SDRAM bank at
- * preliminary address - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */
- udelay (200);
- memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */
- udelay (200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- if (size8 < size9) {
- size_b0 = size9;
- } else {
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
- }
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks.
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
- /* Configure UPMB for NAND flash access */
- upmconfig (UPMB, (uint *) nand_flash_table,
- sizeof (nand_flash_table) / sizeof (uint));
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-
-#if defined(CONFIG_CP850)
-
-#define DPRAM_VARNAME "KP850DIP"
-#define PARAM_ADDR 0x7C0
-#define NAME_ADDR 0x7F8
-#define BOARD_NAME "KP01"
-#define DEFAULT_LB "241111"
-
-int misc_init_r(void)
-{
- int iCompatMode = 0;
- char *pParam = NULL;
- char *envlb;
-
- /*
- First byte in CPLD read address space signals compatibility mode
- 0 - cp850
- 1 - kp852
- */
- pParam = (char*)(CONFIG_SYS_CPLD_BASE);
- if( *pParam != 0)
- iCompatMode = 1;
-
- if ( iCompatMode != 0) {
- /*
- In KP852 compatibility mode we have to write to
- DPRAM as early as possible the binary coded
- line config and board name.
- The line config is derived from the environment
- variable DPRAM_VARNAME by converting from ASCII
- to binary per character.
- */
- if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
- setenv( DPRAM_VARNAME, DEFAULT_LB);
- envlb = DEFAULT_LB;
- }
-
- /* Status string */
- printf("Mode: KP852(LB=%s)\n", envlb);
-
- /* copy appl init */
- pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
- while (*envlb) {
- *(pParam++) = *(envlb++) - '0';
- }
- *pParam = '\0';
-
- /* copy board id */
- pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
- strcpy( pParam, BOARD_NAME);
- } else {
- puts("Mode: CP850\n");
- }
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o phone_console.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# netVia Boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-# NOBJS : Netstal common objects
-NOBJS = fixed_sdram.o nm_bsp.o
-COBJS = $(BOARD).o
-SOBJS =
+COBJS = $(BOARD).o \
+ ../common/fixed_sdram.o \
+ ../common/nm_bsp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#
# Netstal Maschinen AG: HCU4 boards
#
-
-TEXT_BASE = 0xFFFB0000
-
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG -g
endif
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-
-# NOBJS : Netstal common objects
-NOBJS = nm_bsp.o
-COBJS = $(BOARD).o sdram.o
+COBJS = $(BOARD).o \
+ sdram.o \
+ ../common/nm_bsp.o
SOBJS = init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
# Netstal Maschinen AG: HCU5 boards
#
-
-TEXT_BASE = 0xFFFB0000
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-# NOBJS : Netstal common objects
-NOBJS = fixed_sdram.o nm_bsp.o
-COBJS = $(BOARD).o
-SOBJS =
+COBJS = $(BOARD).o \
+ ../common/fixed_sdram.o \
+ ../common/nm_bsp.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#
# Netstal Maschinen AG: MCU25 board
#
-TEXT_BASE = 0xFFFB0000
-
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG -g
endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := netstar.o
SOBJS := setup.o
$(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
$(obj)eeprom_start.o:
echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
# entry 1000'8000 (mem base + reserved)
#
# We load ourself to internal RAM at 2001'2000
-# Check map file when changing TEXT_BASE.
+# Check map file when changing CONFIG_SYS_TEXT_BASE.
# Everything has fit into 192kB internal SRAM!
#
-# XXX TEXT_BASE = 0x20012000
-TEXT_BASE = 0x13FC0000
+# XXX CONFIG_SYS_TEXT_BASE = 0x20012000
+CONFIG_SYS_TEXT_BASE = 0x13FC0000
#include <version.h>
_TEXT_BASE:
- .word TEXT_BASE /* SDRAM load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */
OMAP5910_LPG1_BASE: .word 0xfffbd000
OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# netVia Boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# netVia Boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# netVia Boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ns9750dev.o flash.o led.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x00780000
+CONFIG_SYS_TEXT_BASE = 0x00780000
.endm
_TEXT_BASE:
- .word TEXT_BASE @ sdram load addr from config.mk
+ .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config.mk
_PHYS_FLASH:
.word PHYS_FLASH_1 @ real flash address (without mirroring)
_CAS_LATENCY:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Nexus boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# boot low for 16 MiB boards
-TEXT_BASE = 0xFF000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := overo.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
-# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
#include <netdev.h>
#include <twl4030.h>
#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include "overo.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TWL4030_I2C_BUS 0
+#define EXPANSION_EEPROM_I2C_BUS 2
+#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
+
+#define GUMSTIX_SUMMIT 0x01000200
+#define GUMSTIX_TOBI 0x02000200
+#define GUMSTIX_TOBI_DUO 0x03000200
+#define GUMSTIX_PALO35 0x04000200
+#define GUMSTIX_PALO43 0x05000200
+#define GUMSTIX_CHESTNUT43 0x06000200
+#define GUMSTIX_PINTO 0x07000200
+#define GUMSTIX_GALLOP43 0x08000200
+
+#define ETTUS_USRP_E 0x01000300
+
+#define GUMSTIX_NO_EEPROM 0xffffffff
+
+static struct {
+ unsigned int device_vendor;
+ unsigned char revision;
+ unsigned char content;
+ char fab_revision[8];
+ char env_var[16];
+ char env_setting[64];
+} expansion_config;
+
#if defined(CONFIG_CMD_NET)
static void setup_net_chip(void);
#endif
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OVERO;
}
/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ * bus 2 for the availability of an AT24C01B serial EEPROM.
+ * returns the device_vendor field from the EEPROM
+ */
+unsigned int get_expansion_id(void)
+{
+ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+ /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
+ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ return GUMSTIX_NO_EEPROM;
+ }
+
+ /* read configuration data */
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+
+ return expansion_config.device_vendor;
+}
+
+/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
printf("Unable to detect mmc2 connection type\n");
}
+ switch (get_expansion_id()) {
+ case GUMSTIX_SUMMIT:
+ printf("Recognized Summit expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_TOBI:
+ printf("Recognized Tobi expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_TOBI_DUO:
+ printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ break;
+ case GUMSTIX_PALO35:
+ printf("Recognized Palo35 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd35");
+ break;
+ case GUMSTIX_PALO43:
+ printf("Recognized Palo43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case GUMSTIX_CHESTNUT43:
+ printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case GUMSTIX_PINTO:
+ printf("Recognized Pinto expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ break;
+ case GUMSTIX_GALLOP43:
+ printf("Recognized Gallop43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case ETTUS_USRP_E:
+ printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_USRP_E();
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
+ break;
+ default:
+ printf("Unrecognized expansion board\n");
+ }
+
+ if (expansion_config.content == 1)
+ setenv(expansion_config.env_var, expansion_config.env_setting);
+
dieid_num_r();
return 0;
#endif
return rc;
}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
+#define MUX_USRP_E() \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
+
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# OXC boards
-#
-
-#TEXT_BASE = 0x00090000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+#
+# Palm LifeDrive Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := palmld.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of PalmLD */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x7, PWM_CTRL0);
+ writel(0x16c, PWM_PERVAL0);
+ writel(0x11a, PWM_PWDUTY0);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
--- /dev/null
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := palmtc.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Palm Tungsten|C Support
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* Arch number of Palm Tungsten|C */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x5f, PWM_CTRL1);
+ writel(0x3ff, PWM_PERVAL1);
+ writel(892, PWM_PWDUTY1);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := pandora.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
#include <asm/mach-types.h>
#include "pandora.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define TWL4030_BB_CFG_BBCHEN (1 << 4)
#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
#define TWL4030_BB_CFG_BBISEL_500UA 2
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
NOTE! When you switch between the two boot flashes, the
base addresses will be swapped.
-Have this in mind when you compile u-boot. TEXT_BASE has
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
to match the address where u-boot is located when you
actually launch.
#
# ROM version
-#TEXT_BASE = 0xbfc00000
+#CONFIG_SYS_TEXT_BASE = 0xbfc00000
# SDRAM version
-TEXT_BASE = 0x83800000
+CONFIG_SYS_TEXT_BASE = 0x83800000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \
fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# PCIPPC-2 boards
-#
-
-TEXT_BASE = 0xfff00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# Check the U-Boot Image with a SHA1 checksum
ALL += $(obj)u-boot.sha1
-#TEXT_BASE = 0x00001000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
-else
-TEXT_BASE = 0xFFFA0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xF0000000
#endif
#ifdef CONFIG_FSL_DIU_FB
-# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
- mpc5121_diu_init();
-#endif
#if defined(CONFIG_SERIAL_MULTI)
set_lcd_brightness(0);
#endif
};
#endif
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ * ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
+ * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
+ * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
+ * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
+ * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
+ * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
+ * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
+ 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
+ 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
+ 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
+ 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
+ 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
+ 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
+ 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
+ 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
+ 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
+};
+#endif
+
void ft_board_setup(void *blob, bd_t *bd)
{
u32 val[8];
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
+#if defined(CONFIG_VIDEO)
+ fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
+#endif
/* Fixup NOR FLASH mapping */
val[i++] = 0; /* chip select number */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# phyCORE-MPC5200B tiny board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFF000000 boot low
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := pleb2.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE = 0xa1F80000
-#TEXT_BASE = 0xa3080000
-#TEXT_BASE = 0
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
-@ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
- 1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
- #ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- mov pc, r10
-
-@ End lowlevel_init
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# PM520 board
-#
-
-TEXT_BASE = 0xfff00000
-# TEXT_BASE = 0x00100000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys PM826 board:
-#
-
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot 64-bit flash
-TEXT_BASE = 0xFF000000
-
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys PM828 board:
-#
-
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot 64-bit flash
-TEXT_BASE = 0x40000000
-
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# pm854 board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
puts("Board: MicroSys PM854\n");
#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
- printf(" PCI1: disabled\n");
+ printf("PCI1: disabled\n");
#endif
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# PM856 board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
puts("Board: MicroSys PM856\n");
#ifdef CONFIG_PCI
- printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
- printf(" PCI1: disabled\n");
+ printf("PCI1: disabled\n");
#endif
/*
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cmd_pn62.o misc.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#if defined(CONFIG_CMD_BSP)
-extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
/*
* Command led: controls the various LEDs 0..11 on the PN62 card.
*/
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# PN62 boards
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS := init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2005
-# Richard Danter, Wind River Systems
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-TEXT_BASE = 0xFFF00000
-TEXT_END = 0xFFF40000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
/* Function prototypes */
-extern void unlock_ram_in_cache( void );
-extern void _start_warm(void);
+extern void _start(void);
/*
*
* Shell command to reset the board.
*/
-void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf( "Resetting...\n" );
icache_disable();
dcache_disable();
- /* Jump to warm start (in RAM) */
- _start_warm();
+ /* Jump to cold reset point (in RAM) */
+ _start();
/* Should never get here */
- while(1);
+ while(1)
+ ;
+
+ return 1;
}
int board_eth_init(bd_t *bis)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ppmc8260.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0xfe000000
-TEXT_END = 0xfe080000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o fpga.o nand.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-#
-# AMCC 440GX Reference Platform (Ocotea) board
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
$(shell mkdir -p $(obj)../../Marvell/common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
SOBJS = misc.o
COBJS = $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# p3mx boards (P3M750 & P3M7448)
-#
-
-TEXT_BASE = 0xfff00000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/env_embedded.o(.text) */
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := flash.o pdnb3.o nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x01f00000
+CONFIG_SYS_TEXT_BASE = 0x01f00000
DECLARE_GLOBAL_DATA_PTR;
-/* Prototypes */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COMOBJS := ../common/AMDLV065D.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x018e0000
+CONFIG_SYS_TEXT_BASE = 0x018e0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
$(shell mkdir -p $(obj)../common)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COMOBJS := ../common/AMDLV065D.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x01fc0000
+CONFIG_SYS_TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o sconsole.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#
# ROM version
-TEXT_BASE = 0xB0000000
+CONFIG_SYS_TEXT_BASE = 0xB0000000
# RAM version
-#TEXT_BASE = 0x80100000
+#CONFIG_SYS_TEXT_BASE = 0x80100000
FUNCPTR absEntry;
ulong *src,*dst;
- src = (ulong *)(TEXT_BASE + 0x428);
+ src = (ulong *)(CONFIG_SYS_TEXT_BASE + 0x428);
dst = (ulong *)0xbf0081d0;
- absEntry = (FUNCPTR)(TEXT_BASE + 0x400);
+ absEntry = (FUNCPTR)(CONFIG_SYS_TEXT_BASE + 0x400);
absEntry(src,dst,0x6);
src = (ulong *)((ulong)copydwords & 0xfffffff8);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := pxa_idp.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-#TEXT_BASE = 0xa1700000
-TEXT_BASE = 0xa3080000
-#TEXT_BASE = 0
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-/*
- * Memory setup
- */
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 3rd blink */
- bl blink
-#endif
-
- /* Set up GPIO pins first ----------------------------------------- */
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 4th debug blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 5th blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- orr r4, r4, #(MDREFR_SLFRSH)
- bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
-
- ldr r4, =CONFIG_SYS_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-#if 0
- /* FIXME turn on serial ports */
- /* look into moving this to board_init() */
- ldr r2, =(PXA_CS5_PHYS + 0x03C0002c)
- mov r3, #0x13
- str r3, [r2]
-#endif
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 6th blink */
- bl blink
-#endif
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
-#if 0
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#endif
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-#ifdef DEBUG_BLINK_ENABLE
- /* 7th blink */
- bl blink
-#endif
-
-endlowlevel_init:
-
- mov pc, r10
-
-
-#ifdef DEBUG_BLINK_ENABLE
-
-/* debug LED code */
-
-/* delay about 200ms */
-delay:
-
- /* reset OSCR to 0 */
- ldr r8, =OSCR
- mov r9, #0
- str r9, [r8]
-
- /* make sure new value has stuck */
-1:
- ldr r8, =OSCR
- ldr r9, [r8]
- mov r8, #0x10000
- cmp r9, r8
- bgt 1b
-
- /* now, wait for delay to expire */
-1:
- ldr r8, =OSCR
- ldr r9, [r8]
- mov r8, #0xd4000
- cmp r8, r9
- bgt 1b
-
- mov pc, lr
-
-/* blink code -- trashes r7, r8, r9 */
-
-.globl blink
-blink:
-
- mov r7, lr
-
- /* set GPIO10 as outout */
- ldr r8, =GPDR0
- ldr r9, [r8]
- orr r9, r9, #(1<<10)
- str r9, [r8]
-
- /* turn LED off */
- mov r9, #(1<<10)
- ldr r8, =GPCR0
- str r9, [r8]
- bl delay
-
- /* turn LED on */
- mov r9, #(1<<10)
- ldr r8, =GPSR0
- str r9, [r8]
- bl delay
-
- /* turn LED off */
- mov r9, #(1<<10)
- ldr r8, =GPCR0
- str r9, [r8]
-
- mov pc, r7
-
-#endif
#include <common.h>
#include <netdev.h>
#include <command.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
/* set PWM for LCD */
/* a value that works is 60Hz, 77% duty cycle */
- CKEN |= CKEN0_PWM0;
- PWM_CTRL0 = 0x3f;
- PWM_PERVAL0 = 0x3ff;
- PWM_PWDUTY0 = 792;
+ writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+ writel(0x3f, PWM_CTRL0);
+ writel(0x3ff, PWM_PERVAL0);
+ writel(792, PWM_PWDUTY0);
/* clear reset to AC97 codec */
- CKEN |= CKEN2_AC97;
- GCR = GCR_COLD_RST;
+ writel(readl(CKEN) | CKEN2_AC97, CKEN);
+ writel(GCR_COLD_RST, GCR);
/* enable LCD backlight */
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
-
#ifdef DEBUG_BLINKC_ENABLE
void delay_c(void)
{
/* reset OSCR to 0 */
- OSCR = 0;
- while(OSCR > 0x10000)
+ writel(0, OSCR);
+ while (readl(OSCR) > 0x10000)
;
- while(OSCR < 0xd4000)
+ while (readl(OSCR) < 0xd4000)
;
}
{
int led_bit = (1<<10);
- GPDR0 = led_bit;
- GPCR0 = led_bit;
+ writel(led_bit, GPDR0);
+ writel(led_bit, GPCR0);
delay_c();
- GPSR0 = led_bit;
+ writel(led_bit, GPSR0);
delay_c();
- GPCR0 = led_bit;
+ writel(led_bit, GPCR0);
}
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
#
# ROM version
-TEXT_BASE = 0xbfc00000
+CONFIG_SYS_TEXT_BASE = 0xbfc00000
# RAM version
-#TEXT_BASE = 0x80001000
+#CONFIG_SYS_TEXT_BASE = 0x80001000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o nand.o
SOBJS =
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o fpga.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RMU boards
-#
-
-TEXT_BASE = 0xfff00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-/* XXX ?
- . = env_offset;
-*/
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o pcmcia.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
-/***
- . = env_offset;
- common/env_embedded.o (.text)
-***/
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Rattler series boards by Analogue & Micro
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o kbd.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RBC823 boards
-#
-
-TEXT_BASE = 0xFFF00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ lib/libgeneric.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := migo_r.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: Renesas MigoR\n");
int dram_init (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := ap325rxa.o cpld-ap325rxa.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* PRI control register */
#define PRPRICR5 0xFF800048 /* LMB */
#define PRPRICR5_D 0x2a
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := r2dplus.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x0FFC0000
+CONFIG_SYS_TEXT_BASE = 0x0FFC0000
#include <asm/io.h>
#include <asm/pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: Renesas Solutions R2D Plus\n");
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := r7780mp.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x0FFC0000
+CONFIG_SYS_TEXT_BASE = 0x0FFC0000
#include <netdev.h>
#include "r7780mp.h"
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = lib$(BOARD).o
OBJS := rsk7203.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x0C7C0000
+CONFIG_SYS_TEXT_BASE = 0x0C7C0000
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7203\n");
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sh7763rdp.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# board/sh7763rdp/config.mk
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
-TEXT_BASE = 0x8FFC0000
+CONFIG_SYS_TEXT_BASE = 0x8FFC0000
# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define CPU_CMDREG 0xB1000006
#define PDCR 0xffef0006
#define PECR 0xffef0008
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-# TEXT_BASE refers to image _after_ relocation.
+# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-ifndef TEXT_BASE
-TEXT_BASE = 0x0ff80000
+ifdef CONFIG_SH_32BIT
+CONFIG_SYS_TEXT_BASE = 0x8FF80000
+else
+CONFIG_SYS_TEXT_BASE = 0x0ff80000
endif
#include <asm/pci.h>
#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int checkboard(void)
{
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# RMU boards
-#
-
-TEXT_BASE = 0xfff00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-/* XXX ?
- . = env_offset;
-*/
- common/env_embedded.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-TEXT_BASE = 0x23f00000
\ No newline at end of file
int dram_init(void)
{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
- return 0;
}
#ifdef CONFIG_RESET_PHY_R
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += pm9263.o
COBJS-y += led.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-TEXT_BASE = 0x23f00000
static void pm9263_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
int dram_init(void)
{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
- return 0;
}
#ifdef CONFIG_RESET_PHY_R
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += pm9g45.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-TEXT_BASE = 0x73f00000
static void pm9g45_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/*
* PD2 enables the 50MHz oscillator for Ethernet PHY
int dram_init(void)
{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
- return 0;
}
#ifdef CONFIG_RESET_PHY_R
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := rpxsuper.o flash.o mii_phy.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0x80F00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := rsdproto.o flash.o
SOBJS := flash_asm.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0xff000000
-/*TEXT_BASE = 0x00200000 */
-
-LDSCRIPT := $(SRCTREE)/board/rsdproto/u-boot.lds
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sacsng.o flash.o clkinit.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# 82xx boards
-#
-
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
extern void eth_loopback_test(void);
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
#include "clkinit.h"
#include "ioconfig.h" /* I/O configuration table */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := goni.o onenand.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x50000000 (256MiB)
#
-TEXT_BASE = 0x34800000
+CONFIG_SYS_TEXT_BASE = 0x34800000
int dram_init(void)
{
+ gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
+ PHYS_SDRAM_3_SIZE;
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-
- return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
}
- return s5p_mmc_init(0);
+ return s5p_mmc_init(0, 4);
}
#endif
*/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := smdk2400.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x0CF80000
+CONFIG_SYS_TEXT_BASE = 0x0CF80000
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
- clk_power->MPLLCON = 0x5c042;
- clk_power->CLKDIVN = 0;
+ clk_power->mpllcon = 0x5c042;
+ clk_power->clkdivn = 0;
/* set up the I/O ports */
- gpio->PACON = 0x3ffff;
- gpio->PBCON = 0xaaaaaaaa;
- gpio->PBUP = 0xffff;
- gpio->PECON = 0x0;
- gpio->PEUP = 0x0;
+ gpio->pacon = 0x3ffff;
+ gpio->pbcon = 0xaaaaaaaa;
+ gpio->pbup = 0xffff;
+ gpio->pecon = 0x0;
+ gpio->peup = 0x0;
#ifdef CONFIG_HWFLOW
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
/* 10, 10, 00, 00, 10, 00, 10 */
- gpio->PFCON=0xa22;
+ gpio->pfcon = 0xa22;
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
- gpio->PFUP=0x35;
+ gpio->pfup = 0x35;
#else
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
/* 00, 00, 00, 00, 10, 00, 10 */
- gpio->PFCON = 0x22;
+ gpio->pfcon = 0x22;
/* Disable pull-up on Rx and Tx pins */
- gpio->PFUP = 0x5;
+ gpio->pfup = 0x5;
#endif /* CONFIG_HWFLOW */
- gpio->PGCON = 0x0;
- gpio->PGUP = 0x0;
- gpio->OPENCR = 0x0;
+ gpio->pgcon = 0x0;
+ gpio->pgup = 0x0;
+ gpio->opencr = 0x0;
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := smdk2410.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x33F80000
+CONFIG_SYS_TEXT_BASE = 0x33F80000
/**************************************/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x00044555;
- gpio->GPBUP = 0x000007FF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x0000FFFF;
- gpio->GPFCON = 0x000055AA;
- gpio->GPFUP = 0x000000FF;
- gpio->GPGCON = 0xFF95FFBA;
- gpio->GPGUP = 0x0000FFFF;
- gpio->GPHCON = 0x002AFAAA;
- gpio->GPHUP = 0x000007FF;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x00044555;
+ gpio->gpbup = 0x000007FF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x0000FFFF;
+ gpio->gpfcon = 0x000055AA;
+ gpio->gpfup = 0x000000FF;
+ gpio->gpgcon = 0xFF95FFBA;
+ gpio->gpgup = 0x0000FFFF;
+ gpio->gphcon = 0x002AFAAA;
+ gpio->gphup = 0x000007FF;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := smdk6400.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef CONFIG_NAND_SPL
-TEXT_BASE = $(RAM_TEXT)
+CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
else
-TEXT_BASE = 0
+CONFIG_SYS_TEXT_BASE = 0
endif
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot-nand.lds
#endif
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
#include <netdev.h>
#include <asm/arch/s3c6400.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ------------------------------------------------------------------------- */
#define CS8900_Tacs 0x0 /* 0clk address set-up */
#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
cs8900_pre_init();
/* NOR-flash in SROM0 */
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
*/
#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#include <net.h>
-
-int board_late_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
- eth_init(gd->bd);
- return 0;
-}
-
-
-/* checks if addr is in RAM */
-int addr2ram(ulong addr)
+void board_init_f(unsigned long bootflag)
{
- int result = 0;
-
- if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
- result = 1;
-
- return result;
+ relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := smdkc100.o
COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x48000000 (128MiB)
#
-TEXT_BASE = 0x34800000
+CONFIG_SYS_TEXT_BASE = 0x34800000
*/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := universal.o onenand.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# 0x30000000 to 0x35000000 (80MiB)
# 0x40000000 to 0x48000000 (128MiB)
#
-TEXT_BASE = 0x34800000
+CONFIG_SYS_TEXT_BASE = 0x34800000
*/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* Set Initial global variables */
gpio = (struct s5pc110_gpio *)samsung_get_base_gpio();
-
#ifdef CONFIG_LCD
/*
* set reserved memory region for framebuffer.
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := universal.o onenand.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-TEXT_BASE = 0x44800000
+CONFIG_SYS_TEXT_BASE = 0x44800000
*/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
I2C_0, I2C_1, I2C_2, I2C_3,
I2C_4, I2C_5, I2C_6, I2C_7,
I2C_8, I2C_9, I2C_10, I2C_11,
- I2C_12, I2C_13,
+ I2C_12, I2C_13, I2C_NUM,
};
/* i2c0 (CAM) SDA: GPD1[0] SCL: GPD1[1] */
.scl_pin = 3,
};
-static struct i2c_gpio_bus i2c_gpio[] = {
- { .bus = &i2c_0, },
- { .bus = &i2c_1, },
- { .bus = NULL, }, /* Not used */
- { .bus = &i2c_3, },
- { .bus = &i2c_4, },
- { .bus = &i2c_5, },
- { .bus = &i2c_6, },
- { .bus = &i2c_7, },
- { .bus = NULL, }, /* For dedicated HDMI */
- { .bus = &i2c_9, },
- { .bus = &i2c_10, },
- { .bus = NULL, }, /* Not used */
- { .bus = &i2c_12, },
- { .bus = &i2c_13, },
-};
+static struct i2c_gpio_bus i2c_gpio[I2C_NUM];
static void check_battery(int mode);
static void check_micro_usb(int intr);
void i2c_init_board(void)
{
- int num_bus;
-
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
- num_bus = ARRAY_SIZE(i2c_gpio);
+ i2c_gpio[I2C_0].bus = &i2c_0;
+ i2c_gpio[I2C_1].bus = &i2c_1;
+ i2c_gpio[I2C_2].bus = NULL;
+ i2c_gpio[I2C_3].bus = &i2c_3;
+ i2c_gpio[I2C_4].bus = &i2c_4;
+ i2c_gpio[I2C_5].bus = &i2c_5;
+ i2c_gpio[I2C_6].bus = &i2c_6;
+ i2c_gpio[I2C_7].bus = &i2c_7;
+ i2c_gpio[I2C_8].bus = NULL;
+ i2c_gpio[I2C_9].bus = &i2c_9;
+ i2c_gpio[I2C_10].bus = &i2c_10;
+ i2c_gpio[I2C_11].bus = NULL;
+ i2c_gpio[I2C_12].bus = &i2c_12;
+ i2c_gpio[I2C_13].bus = &i2c_13;
i2c_gpio[I2C_0].bus->gpio_base = (unsigned int)&gpio1->d1;
i2c_gpio[I2C_1].bus->gpio_base = (unsigned int)&gpio1->d1;
i2c_gpio[I2C_12].bus->gpio_base = (unsigned int)&gpio1->e4;
i2c_gpio[I2C_13].bus->gpio_base = (unsigned int)&gpio1->e4;
- i2c_gpio_init(i2c_gpio, num_bus, I2C_5);
+ i2c_gpio_init(i2c_gpio, I2C_NUM, I2C_5);
}
static void check_hw_revision(void);
# TBS: end debugging
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
../common/sb_common.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# Travis B. Sawyer
#
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
# TBS: end debugging
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
../common/sb_common.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# MA 02111-1307 USA
#
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Sandpoint boards
-#
-
-#TEXT_BASE = 0x00090000
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
#define __ASSEMBLY__ 1
#endif
+#include <asm-offsets.h>
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/mpc824x/start.o (.text*)
+ *(.text.v*printf)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+
+ *(.text*)
+ . = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
- . = (. + 0x0FF) & 0xFFFFFF00;
+ . = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sbc2410x.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# download area is 3300'0000
-TEXT_BASE = 0x33F80000
+CONFIG_SYS_TEXT_BASE = 0x33F80000
/**************************************/
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
- clk_power->LOCKTIME = 0xFFFFFF;
+ clk_power->locktime = 0xFFFFFF;
/* configure MPLL */
- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
- gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x00044556;
- gpio->GPBUP = 0x000007FF;
- gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
- gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
- gpio->GPECON = 0xAAAAAAAA;
- gpio->GPEUP = 0x0000FFFF;
- gpio->GPFCON = 0x000055AA;
- gpio->GPFUP = 0x000000FF;
- gpio->GPGCON = 0xFF95FF3A;
- gpio->GPGUP = 0x0000FFFF;
- gpio->GPHCON = 0x0016FAAA;
- gpio->GPHUP = 0x000007FF;
-
- gpio->EXTINT0=0x22222222;
- gpio->EXTINT1=0x22222222;
- gpio->EXTINT2=0x22222222;
+ gpio->gpacon = 0x007FFFFF;
+ gpio->gpbcon = 0x00044556;
+ gpio->gpbup = 0x000007FF;
+ gpio->gpccon = 0xAAAAAAAA;
+ gpio->gpcup = 0x0000FFFF;
+ gpio->gpdcon = 0xAAAAAAAA;
+ gpio->gpdup = 0x0000FFFF;
+ gpio->gpecon = 0xAAAAAAAA;
+ gpio->gpeup = 0x0000FFFF;
+ gpio->gpfcon = 0x000055AA;
+ gpio->gpfup = 0x000000FF;
+ gpio->gpgcon = 0xFF95FF3A;
+ gpio->gpgup = 0x0000FFFF;
+ gpio->gphcon = 0x0016FAAA;
+ gpio->gphup = 0x000007FF;
+
+ gpio->extint0 = 0x22222222;
+ gpio->extint1 = 0x22222222;
+ gpio->extint2 = 0x22222222;
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o strataflash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000, 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Wind River sbc405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
- return spd_sdram ();
-}
-
-/* ------------------------------------------------------------------------- */
-
int testdram (void)
{
/* TODO: XXX XXX XXX */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# sbc8240 board
-#
-
-TEXT_BASE = 0xFFF00000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sbc8260.o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MBX8xx boards
-#
-
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright (c) 2006 Wind River Systems, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# SBC8349E
-#
-
-TEXT_BASE = 0xFF800000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-#
-# Copyright 2004, 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# sbc8548 board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfffa0000
-endif
uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
- printf (" PCI host: %d bit, %s MHz, %s, %s\n",
+ printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33000000) ? "33" :
(pci_speed == 66000000) ? "66" : "unknown",
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
- printf (" PCIE at base address %lx\n", pci_info[num].regs);
+ printf("PCIE: base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf("PCIE: disabled\n");
}
puts("\n");
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8560 board
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# based on mpc8560ads board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256K
-#
-TEXT_BASE = 0xfffc0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Jeff Brown
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# sbc8641 board
-# default CCSRBAR is at 0xff700000
-#
-TEXT_BASE = 0xfff00000
void pci_init_board(void)
{
+ struct fsl_pci_info pci_info[2];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
+ uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
+ int pcie_ep;
+ int num = 0;
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- struct pci_region *r = hose->regions;
-#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
- >> MPC8641_PORBMSR_HA_SHIFT;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
- if ((io_sel == 2 || io_sel == 3 || io_sel == 5
- || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
- && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- debug("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
+ int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf("PCIE1: connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- puts("PCI-EXPRESS 1: Disabled\n");
+ puts("PCIE1: disabled\n");
}
-}
#else
- puts("PCI-EXPRESS1: Disabled\n");
+ puts("PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-}
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf("PCIE2: connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
#else
- puts("PCI-EXPRESS 2: Disabled\n");
+ puts("PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
-
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o sc3nand.o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFA0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := scb9328.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This config file is used for compilation of scb93328 sources
#
-# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
# This allows for example having one copy located at the end of ram and stored
# in flash device and later on while developing use other location to test
# the code in RAM device only.
#
-TEXT_BASE = 0x08f00000
+CONFIG_SYS_TEXT_BASE = 0x08f00000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := shannon.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0xd8380000
+CONFIG_SYS_TEXT_BASE = 0xd8380000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-ifndef NAND_SPL
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-endif
-
-ifndef TEXT_BASE
-TEXT_BASE = 0x00100000
-endif
-
ifdef CONFIG_NAND_LP
PAD_TO = 0xFFF20000
else
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-void can_driver_enable (void);
-void can_driver_disable (void);
-
-int fpga_init(void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
- 0x1FF5FC47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Always return 1 (no second DRAM bank since based on TQM8xxL module)
- */
-
-int checkboard (void)
-{
- unsigned char *s;
- unsigned char buf[64];
-
- s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
-
- puts ("Board: Siemens CCM");
-
- if (s) {
- puts (" (");
-
- for (; *s; ++s) {
- if (*s == ' ')
- break;
- putc (*s);
- }
- putc (')');
- }
-
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * If Power-On-Reset switch off the Red and Green LED: At reset, the
- * data direction registers are cleared and must therefore be restored.
- */
-#define RSR_CSRS 0x08000000
-
-int power_on_reset(void)
-{
- /* Test Reset Status Register */
- return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
-}
-
-#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */
-#define PB_LED_RED 0x20000 /* red LED is on PB.14 */
-#define PB_LEDS (PB_LED_GREEN | PB_LED_RED);
-
-static void init_leds (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-
- immap->im_cpm.cp_pbpar &= ~PB_LEDS;
- immap->im_cpm.cp_pbodr &= ~PB_LEDS;
- immap->im_cpm.cp_pbdir |= PB_LEDS;
- /* Check stop reset status */
- if (power_on_reset()) {
- immap->im_cpm.cp_pbdat &= ~PB_LEDS;
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size = 0;
- unsigned long reg;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay(500);
-/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if (size < 0x02000000) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay(1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- can_driver_enable ();
- init_leds ();
-
- udelay(10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Warning - both the PUMA load mode and the CAN driver use UPM B,
- * so make sure only one of both is active.
- */
-void can_driver_enable (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* Initialize MBMR */
- memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
-
- /* Initialize UPMB for CAN: single read */
- memctl->memc_mdr = 0xFFFFC004;
- memctl->memc_mcr = 0x0100 | UPMB;
-
- memctl->memc_mdr = 0x0FFFD004;
- memctl->memc_mcr = 0x0101 | UPMB;
-
- memctl->memc_mdr = 0x0FFFC000;
- memctl->memc_mcr = 0x0102 | UPMB;
-
- memctl->memc_mdr = 0x3FFFC004;
- memctl->memc_mcr = 0x0103 | UPMB;
-
- memctl->memc_mdr = 0xFFFFDC05;
- memctl->memc_mcr = 0x0104 | UPMB;
-
- /* Initialize UPMB for CAN: single write */
- memctl->memc_mdr = 0xFFFCC004;
- memctl->memc_mcr = 0x0118 | UPMB;
-
- memctl->memc_mdr = 0xCFFCD004;
- memctl->memc_mcr = 0x0119 | UPMB;
-
- memctl->memc_mdr = 0x0FFCC000;
- memctl->memc_mcr = 0x011A | UPMB;
-
- memctl->memc_mdr = 0x7FFCC004;
- memctl->memc_mcr = 0x011B | UPMB;
-
- memctl->memc_mdr = 0xFFFDCC05;
- memctl->memc_mcr = 0x011C | UPMB;
-
- /* Initialize OR3 / BR3 for CAN Bus Controller */
- memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
- memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
-}
-
-void can_driver_disable (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* Reset OR3 / BR3 to disable CAN Bus Controller */
- memctl->memc_br3 = 0;
- memctl->memc_or3 = 0;
-
- memctl->memc_mbmr = 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-
-#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN)
-
-void reset_phy(void)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- ulong value;
-
- /* Configure all needed port pins for GPIO */
-#ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
-#else
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */
-#endif
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */
-
- immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
-
- value = immr->im_cpm.cp_pbdat;
-
- /* Assert Powerdown and Reset signals */
- value |= CONFIG_SYS_PB_ETH_POWERDOWN;
-
- /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#ifdef CONFIG_SYS_ETH_CFG1_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG1;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG1);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG2_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG2;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG2);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG3_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG3;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG3);
-#endif
-
- /* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
- immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
- udelay (10000);
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (10000);
-
- /* de-assert RESET signal of PHY */
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET;
- udelay (1000);
-}
-
-
-int misc_init_r (void)
-{
- fpga_init();
- return (0);
-}
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <common.h>
-
-#include "../common/fpga.h"
-
-fpga_t fpga_list[] = {
- { "PUMA" , PUMA_CONF_BASE ,
- CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE }
-};
-int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
-
-void can_driver_enable (void);
-void can_driver_disable (void);
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * PUMA access using UPM B
- */
-const uint puma_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
- /*
- * Precharge and MRS
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-ulong fpga_control (fpga_t* fpga, int cmd)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- switch (cmd) {
- case FPGA_INIT_IS_HIGH:
- immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
- return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
-
- case FPGA_INIT_SET_LOW:
- immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
- break;
-
- case FPGA_INIT_SET_HIGH:
- immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pcdat |= fpga->init_mask;
- break;
-
- case FPGA_PROG_SET_LOW:
- immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
- break;
-
- case FPGA_PROG_SET_HIGH:
- immr->im_ioport.iop_pcdat |= fpga->prog_mask;
- break;
-
- case FPGA_DONE_IS_HIGH:
- return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
-
- case FPGA_READ_MODE:
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-
- /* (re-) enable CAN drivers */
- can_driver_enable ();
-
- break;
-
- case FPGA_LOAD_MODE:
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- /*
- * We must disable the CAN drivers first because
- * they use UPM B, too.
- */
- can_driver_disable ();
- /*
- * Configure UPMB for FPGA
- */
- upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
- memctl->memc_or4 = PUMA_CONF_OR_LOAD;
- memctl->memc_br4 = PUMA_CONF_BR_LOAD;
- break;
-
- case FPGA_GET_ID:
- return *(volatile ulong *)fpga->conf_base;
-
- case FPGA_INIT_PORTS:
- immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
- immr->im_ioport.iop_pcso &= ~fpga->init_mask;
- immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
-
- immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
- immr->im_ioport.iop_pcso &= ~fpga->prog_mask;
- immr->im_ioport.iop_pcdir |= fpga->prog_mask;
-
- immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
- immr->im_ioport.iop_pcso &= ~fpga->done_mask;
- immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
-
- break;
-
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-/*
- . = env_offset;
- common/env_embedded.o(.text)
-*/
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o atm.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
- arch/powerpc/lib/time.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ net/libnet.o (.text*)
+ drivers/rtc/librtc.o (.text*)
+
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)../../tqc/tqm8xx)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
../../tqc/tqm8xx/load_sernum_ethaddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Siemens SCM boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_SCM.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := flash.o smn42.o
SOBJTS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJTS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#address where u-boot will be relocated
-#TEXT_BASE = 0x0
-TEXT_BASE = 0x81500000
+#CONFIG_SYS_TEXT_BASE = 0x0
+CONFIG_SYS_TEXT_BASE = 0x81500000
#define IO0_VALUE 0x4000C
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
MEMMAP_ADR:
.word MEMMAP
BCFG0_ADR:
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Siemens PCU E Boards
-#
-
-TEXT_BASE = 0xFFF00000
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- *
- * The PCU E uses an address map where flash banks are aligned top
- * down, so that the "first" flash bank ends at top of memory, and
- * the monitor entry point is at address (0xFFF00100). The second
- * flash bank is mapped immediately below bank 0.
- *
- * This is NOT in conformance to the "official" memory map!
- *
- */
-
-#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
- - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long base, size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- /*
- * Warning:
- *
- * Since the PCU E memory map assigns flash banks top down,
- * we swap the numbering later if both banks are equipped,
- * so they look like a contiguous area of memory.
- */
- DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
- size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
-
- DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- DEBUGF ("## Before remap: "
- "BR0: 0x%08x OR0: 0x%08x "
- "BR6: 0x%08x OR6: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br6, memctl->memc_or6);
-
- /* Remap FLASH according to real size */
- base = 0 - size_b0;
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
- DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0);
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
- base = 0 - size_b0;
-
- flash_info[0].size = size_b0;
-
- flash_get_offsets (base, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- PCU_MONITOR_BASE,
- PCU_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- flash_info_t tmp_info;
-
- memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
- BR_PS_16 | BR_MS_GPCM | BR_V;
-
- DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
- memctl->memc_br6, memctl->memc_or6);
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(base - size_b1),
- &flash_info[1]);
- base -= size_b1;
-
- flash_get_offsets (base, &flash_info[1]);
-
- flash_info[1].size = size_b1;
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- /*
- * Swap bank numbers so that addresses are in ascending order
- */
- tmp_info = flash_info[0];
- flash_info[0] = flash_info[1];
- flash_info[1] = tmp_info;
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
-
- DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- short n;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
- return;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL322T:
- case FLASH_AMDL323T:
- case FLASH_AMDL324T:
- /* set sector offsets for top boot block type */
-
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- return;
- case FLASH_AMDL322B:
- case FLASH_AMDL323B:
- case FLASH_AMDL324B:
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (base < info->size) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- return;
- case FLASH_AMDL640:
- /* set sector offsets for dual boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- n = info->sector_count - 8;
- while (i < n) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- while (i < info->sector_count) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- ++i;
- }
- return;
- default:
- return;
- }
- /* NOTREACHED */
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
- break;
- default: printf ("Unknown Chip Type 0x%lX\n",
- info->flash_id);
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ushort value;
- vu_short *saddr = (vu_short *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- saddr[0x0555] = 0x00AA;
- saddr[0x02AA] = 0x0055;
- saddr[0x0555] = 0x0090;
-
- value = saddr[0];
-
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
-
- switch (value) {
- case (AMD_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- DEBUGF("Unknown Manufacturer ID\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = saddr[1]; /* device ID */
-
- DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
-
- switch (value) {
-
- case (AMD_ID_DL322T & 0xFFFF):
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL322B & 0xFFFF):
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL323T & 0xFFFF):
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL323B & 0xFFFF):
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL324T & 0xFFFF):
- info->flash_id += FLASH_AMDL324T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL324B & 0xFFFF):
- info->flash_id += FLASH_AMDL324B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
- case (AMD_ID_DL640 & 0xFFFF):
- info->flash_id += FLASH_AMDL640;
- info->sector_count = 142;
- info->size = 0x00800000;
- break;
- default:
- DEBUGF("Unknown Device ID\n");
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- flash_get_offsets ((ulong)addr, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
-#if 0
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- saddr = (vu_short *)(info->start[i]);
- info->protect[i] = saddr[2] & 1;
-#else
- info->protect[i] =0;
-#endif
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- saddr = (vu_short *)info->start[0];
- *saddr = 0x00F0; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0080;
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_short*)(info->start[sect]);
- addr[0] = 0x0030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_short*)(info->start[l_sect]);
- while ((addr[0] & 0x0080) != 0x0080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_short *)info->start[0];
- addr[0] = 0x00F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-#define FLASH_WIDTH 2 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<FLASH_WIDTH && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i=0; i<FLASH_WIDTH; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- vu_short *sdest = (vu_short *)dest;
- ushort sdata = (ushort)data;
- ushort sval;
- ulong start, passed;
- int flag, rc;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*sdest & sdata) != sdata) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x00A0;
-
-#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
- /* work around the timeout bugs */
- udelay(20);
-#endif
-
- *sdest = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- rc = 0;
- /* data polling for D7 */
- start = get_timer (0);
-
- for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
-
- sval = *sdest;
-
- if ((sval & 0x0080) == (sdata & 0x0080))
- break;
-
- if ((sval & 0x0020) == 0) /* DQ5: Timeout? */
- continue;
-
- sval = *sdest;
-
- if ((sval & 0x0080) != (sdata & 0x0080))
- rc = 1;
-
- break;
- }
-
- if (rc) {
- DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
- dest, sval, sdata);
- }
-
- if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
- DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
- dest, sval, sdata);
- rc = 1;
- }
-
- /* reset to read mode */
- addr = (vu_short *)info->start[0];
- addr[0] = 0x00F0; /* reset bank */
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <i2c.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static void puma_status (void);
-static void puma_set_mode (int mode);
-static int puma_init_done (void);
-static void puma_load (ulong addr, ulong len);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * 50 MHz SDRAM access using UPM A
- */
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
- 0x1ffddc47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
- 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * PUMA access using UPM B
- */
-const uint puma_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
- /*
- * Precharge and MRS
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
- puts ("Board: Siemens PCU E\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0, reg;
- int i;
-
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 2 to the SDRAM bank at preliminary address.
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
-#else /* XXX */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-#endif /* XXX */
-
- /* initialize memory address register */
- memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (200); /* 0x8000A105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
-#else /* XXX */
- udelay (200); /* 0x80004105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
-#endif /* XXX */
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (1); /* 0x8000A830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
-#else /* XXX */
- udelay (1); /* 0x80004830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
-#endif /* XXX */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (1); /* 0x8000A106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
-#else /* XXX */
- udelay (1); /* 0x80004106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
-#endif /* XXX */
-
- reg = memctl->memc_mamr;
- reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
- reg |= MAMR_TLFA_4X; /* ... to 4x */
- reg |= MAMR_PTAE; /* enable refresh */
- memctl->memc_mamr = reg;
-
- udelay (200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i = 0; i < 10; ++i) {
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE5_PRELIM;
-#else /* XXX */
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE2_PRELIM;
-#endif /* XXX */
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
-#else /* XXX */
- size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-#endif /* XXX */
-
- memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
-
- /*
- * Final mapping:
- */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#else /* XXX */
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#endif /* XXX */
- udelay (1000);
-
- /*
- * Configure UPMB for PUMA
- */
- upmconfig (UPMB, (uint *) puma_table,
- sizeof (puma_table) / sizeof (uint));
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-#else /* XXX */
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
- CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-#endif /* XXX */
-
-#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
-
-void reset_phy (void)
-{
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong value;
-
- /* Configure all needed port pins for GPIO */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
-# else
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
-# endif
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */
-#endif /* XXX */
- immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
-
- value = immr->im_cpm.cp_pbdat;
-
- /* Assert Powerdown and Reset signals */
- value |= CONFIG_SYS_PB_ETH_POWERDOWN;
- value &= ~(CONFIG_SYS_PB_ETH_RESET);
-
- /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#if !PCU_E_WITH_SWAPPED_CS
-# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- value |= CONFIG_SYS_PB_ETH_MDDIS;
-# else
- value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
-# endif
-#endif
-#ifdef CONFIG_SYS_ETH_CFG1_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG1;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG1);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG2_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG2;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG2);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG3_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG3;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG3);
-#endif
-
- /* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
- immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
- udelay (10000);
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (10000);
-
- /* de-assert RESET signal of PHY */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
- udelay (1000);
-}
-
-/*-----------------------------------------------------------------------
- * Board Special Commands: access functions for "PUMA" FPGA
- */
-#if defined(CONFIG_CMD_BSP)
-
-#define PUMA_READ_MODE 0
-#define PUMA_LOAD_MODE 1
-
-int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr, len;
-
- switch (argc) {
- case 2: /* PUMA reset */
- if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
- puma_status ();
- return 0;
- }
- break;
- case 4: /* PUMA load addr len */
- if (strcmp (argv[1], "load") != 0)
- break;
-
- addr = simple_strtoul (argv[2], NULL, 16);
- len = simple_strtoul (argv[3], NULL, 16);
-
- printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
- addr, len, len);
- puma_load (addr, len);
-
- return 0;
- default:
- break;
- }
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD (puma, 4, 1, do_puma,
- "access PUMA FPGA",
- "status - print PUMA status\n"
- "puma load addr len - load PUMA configuration data"
-);
-#endif
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_set_mode (int mode)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- /* disable PUMA in memory controller */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_br3 = 0;
-#else /* XXX */
- memctl->memc_br4 = 0;
-#endif /* XXX */
-
- switch (mode) {
- case PUMA_READ_MODE:
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or3 = PUMA_CONF_OR_READ;
- memctl->memc_br3 = PUMA_CONF_BR_READ;
-#else /* XXX */
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
- break;
- case PUMA_LOAD_MODE:
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or3 = PUMA_CONF_OR_LOAD;
- memctl->memc_br3 = PUMA_CONF_BR_LOAD;
-#else /* XXX */
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
- break;
- }
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
-
-static void puma_load (ulong addr, ulong len)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
- uchar *data = (uchar *) addr;
- int i;
-
- /* align length */
- if (len & 1)
- ++len;
-
- /* Reset FPGA */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
- immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */
-#else
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */
-#endif /* XXX */
- udelay (100);
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
-#else
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
-#endif /* XXX */
-
- /* wait until INIT indicates completion of reset */
- for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
- udelay (1000);
- if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
- break;
- }
- if (i == PUMA_INIT_TIMEOUT) {
- printf ("*** PUMA init timeout ***\n");
- return;
- }
-
- puma_set_mode (PUMA_LOAD_MODE);
-
- while (len--)
- *fpga_addr = *data++;
-
- puma_set_mode (PUMA_READ_MODE);
-
- puma_status ();
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_status (void)
-{
- /* Check state */
- printf ("PUMA initialization is %scomplete\n",
- puma_init_done ()? "" : "NOT ");
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static int puma_init_done (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* make sure pin is GPIO input */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
- immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
-
- return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
- ulong addr = 0;
- ulong len = 0;
- char *s;
-
- printf ("PUMA: ");
- if (puma_init_done ()) {
- printf ("initialized\n");
- return 0;
- }
-
- if ((s = getenv ("puma_addr")) != NULL)
- addr = simple_strtoul (s, NULL, 16);
-
- if ((s = getenv ("puma_len")) != NULL)
- len = simple_strtoul (s, NULL, 16);
-
- if ((!addr) || (!len)) {
- printf ("net list undefined\n");
- return 0;
- }
-
- printf ("loading... ");
-
- puma_load (addr, len);
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# SIXNET boards
-#
-
-TEXT_BASE = 0xF8000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002-2003
-# Simple Network Magic Corporation, dnevil@snmc.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# QS850
-# Start address of Bootloader in Flash
-#
-
-TEXT_BASE = 0xFFF00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Simple Network Magic Corporation, dnevil@snmc.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# QS860T
-# Start address of 512K Socketed Flash
-#
-
-TEXT_BASE = 0xFFF00000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
#
COBJS-y += $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-#
-# Modified by Sergei Poselenov
-# (C) Copyright 2008, Emcraft Systems.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# socrates board
-# default CCARBAR is at 0xff700000
-#
-TEXT_BASE = 0xfff80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# sorcery board
-#
-
-TEXT_BASE = 0xfff00000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o hpi.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
-# MPC885ADS boards
-#
-
-#TEXT_BASE = 0xFE000000
-TEXT_BASE = 0xFFF00000
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920
-HOSTCFLAGS += -I$(TOPDIR)/board/spc1920
-HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# SPD823TS boards
-#
-
-TEXT_BASE = 0xFF000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ board/spd8xx/libspd8xx.o (.text*)
+ *(.text.v*printf)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)lib$(VENDOR).o
COBJS := spr_misc.o
SOBJS := spr_lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := spear300.o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-TEXT_BASE = 0x00700000
+CONFIG_SYS_TEXT_BASE = 0x00700000
ALL += $(obj)u-boot.img
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := spear310.o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-TEXT_BASE = 0x00700000
+CONFIG_SYS_TEXT_BASE = 0x00700000
ALL += $(obj)u-boot.img
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := spear320.o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-TEXT_BASE = 0x00700000
+CONFIG_SYS_TEXT_BASE = 0x00700000
ALL += $(obj)u-boot.img
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := spear600.o
SOBJS :=
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-TEXT_BASE = 0x00700000
+CONFIG_SYS_TEXT_BASE = 0x00700000
ALL += $(obj)u-boot.img
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := nhk8815.o
SOBJS := platform.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# image should be loaded at 0x01000000
#
-TEXT_BASE = 0x03F80000
+CONFIG_SYS_TEXT_BASE = 0x03F80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# Copied from ADS85xx for STx GP3 - Dan Malek
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-#
-TEXT_BASE = 0xfff80000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += law.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,2003 Motorola Inc.
-#
-# Copied from ADS85xx for STx GP3 - Dan Malek
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 0.5MB
-# U-Boot is less than 256K, so push
-# it further up into the flash
-#
-TEXT_BASE = 0xFFFC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# STx XTc
-#
-
-TEXT_BASE = 0x40F00000
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ lib/libgeneric.o (.text*)
+ net/libnet.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+ board/svm_sc8xx/libsvm_sc8xx.o (.text*)
+ *(.text.*printf)
+ *(.text.do_mem_*)
+ *(.text.flash*)
+ *(.text.run_command)
+ *(.text.main_loop)
+ *(.text.srec_decode)
. = env_offset;
- common/env_embedded.o (.ppcenv)
+ common/env_embedded.o (.ppcenv*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sx1.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#
-TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x11080000
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += jadecpu.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-TEXT_BASE = 0x10000000
+CONFIG_SYS_TEXT_BASE = 0x10000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
#
#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFA0000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
* MA 02111-1307 USA
*/
+#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm/mmu.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
+#include <mtd/cfi_flash.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
{
return board_scan_options;
}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ *
+ * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
+ * can only be read correctly in 16bit mode. We need to emulate
+ * 8bit and 32bit reads here in the board specific code.
+ */
+u8 flash_read8(void *addr)
+{
+ u16 val = __raw_readw((void *)((u32)addr & ~1));
+
+ if ((u32)addr & 1)
+ return val;
+
+ return val >> 8;
+}
+
+u32 flash_read32(void *addr)
+{
+ return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
+}
+
+void flash_cmd_reset(flash_info_t *info)
+{
+ /*
+ * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * needs the Spansion type reset commands. The other flash chip
+ * is located behind a FPGA (Xilinx DS617) and needs the Intel type
+ * reset command.
+ */
+ if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ else
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o vr4131-pci.o
SOBJS = lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
#
# ROM version
-TEXT_BASE = 0xBFC00000
+CONFIG_SYS_TEXT_BASE = 0xBFC00000
# RAM version
-#TEXT_BASE = 0x80400000
+#CONFIG_SYS_TEXT_BASE = 0x80400000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf518-0.0
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o gpio_cfi_flash.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
# This is not actually used for Blackfin boards so do not change it
-#TEXT_BASE = do-not-use-me
+#CONFIG_SYS_TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf537-0.2
CFLAGS_lib += -O2
CFLAGS_lib/lzma += -O2
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-#define GPIO_PIN_1 GPIO_PF4
-#define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2 GPIO_PF5
-#define GPIO_MASK_2 (1 << 22)
-#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
- unsigned long addr = (unsigned long)vaddr;
-
- gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_MASK_2
- gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
- SSYNC();
-
- return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
- __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
- return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
- gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-#ifdef GPIO_MASK_2
- gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
-#endif
- gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
-}
+#define GPIO_PIN_1 GPIO_PF4
+#define GPIO_PIN_2 GPIO_PF5
+#include "../cm-bf537e/gpio_cfi_flash.c"
+++ /dev/null
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
-#include "gpio_cfi_flash.h"
+#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := beagle.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
#include <common.h>
#include <twl4030.h>
#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/gpio.h>
#include <asm/mach-types.h>
#include "beagle.h"
+#define TWL4030_I2C_BUS 0
+#define EXPANSION_EEPROM_I2C_BUS 1
+#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
+
+#define TINCANTOOLS_ZIPPY 0x01000100
+#define TINCANTOOLS_ZIPPY2 0x02000100
+#define TINCANTOOLS_TRAINER 0x04000100
+#define TINCANTOOLS_SHOWDOG 0x03000100
+#define KBADC_BEAGLEFPGA 0x01000600
+
+#define BEAGLE_NO_EEPROM 0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct {
+ unsigned int device_vendor;
+ unsigned char revision;
+ unsigned char content;
+ char fab_revision[8];
+ char env_var[16];
+ char env_setting[64];
+} expansion_config;
+
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
}
/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ * bus 1 for the availability of an AT24C01B serial EEPROM.
+ * returns the device_vendor field from the EEPROM
+ */
+unsigned int get_expansion_id(void)
+{
+ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+ /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
+ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ return BEAGLE_NO_EEPROM;
+ }
+
+ /* read configuration data */
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+
+ return expansion_config.device_vendor;
+}
+
+/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
printf("Beagle unknown 0x%02x\n", get_board_revision());
}
+ switch (get_expansion_id()) {
+ case TINCANTOOLS_ZIPPY:
+ printf("Recognized Tincantools Zippy board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ setenv("buddy", "zippy");
+ break;
+ case TINCANTOOLS_ZIPPY2:
+ printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ setenv("buddy", "zippy2");
+ break;
+ case TINCANTOOLS_TRAINER:
+ printf("Recognized Tincantools Trainer board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ MUX_TINCANTOOLS_TRAINER();
+ setenv("buddy", "trainer");
+ break;
+ case TINCANTOOLS_SHOWDOG:
+ printf("Recognized Tincantools Showdow board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ /* Place holder for DSS2 definition for showdog lcd */
+ setenv("defaultdisplay", "showdoglcd");
+ setenv("buddy", "showdog");
+ break;
+ case KBADC_BEAGLEFPGA:
+ printf("Recognized KBADC Beagle FPGA board\n");
+ MUX_KBADC_BEAGLEFPGA();
+ setenv("buddy", "beaglefpga");
+ break;
+ case BEAGLE_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
+ setenv("buddy", "none");
+ break;
+ default:
+ printf("Unrecognized expansion board: %x\n",
+ expansion_config.device_vendor);
+ setenv("buddy", "unknown");
+ }
+
+ if (expansion_config.content == 1)
+ setenv(expansion_config.env_var, expansion_config.env_setting);
+
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
{
MUX_BEAGLE();
}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+#define MUX_TINCANTOOLS_ZIPPY() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
#endif
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80008000
+CONFIG_SYS_TEXT_BASE = 0x80008000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := evm.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
#include <asm/mach-types.h>
#include "evm.h"
-static u8 omap3_evm_version;
+DECLARE_GLOBAL_DATA_PTR;
-u8 get_omap3_evm_rev(void)
+static u32 omap3_evm_version;
+
+u32 get_omap3_evm_rev(void)
{
return omap3_evm_version;
}
static void omap3_evm_get_revision(void)
{
+#if defined(CONFIG_CMD_NET)
+ /*
+ * Board revision can be ascertained only by identifying
+ * the Ethernet chipset.
+ */
unsigned int smsc_id;
/* Ethernet PHY ID is stored at ID_REV register */
default:
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
}
+#else
+#if defined(CONFIG_STATIC_BOARD_REV)
+ /*
+ * Look for static defintion of the board revision
+ */
+ omap3_evm_version = CONFIG_STATIC_BOARD_REV;
+#else
+ /*
+ * Fallback to the default above.
+ */
+ omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+#endif
+#endif /* CONFIG_CMD_NET */
}
+#ifdef CONFIG_USB_OMAP3
/*
* MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
*/
return retval;
}
+#endif
/*
* Routine: board_init
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
#if defined(CONFIG_CMD_NET)
setup_net_chip();
#endif
+ omap3_evm_get_revision();
dieid_num_r();
writel(GPIO0, &gpio3_base->cleardataout);
udelay(1);
writel(GPIO0, &gpio3_base->setdataout);
-
- /* determine omap3evm revision */
- omap3_evm_get_revision();
}
int board_eth_init(bd_t *bis)
OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
};
-u8 get_omap3_evm_rev(void);
+u32 get_omap3_evm_rev(void);
+#if defined(CONFIG_CMD_NET)
static void setup_net_chip(void);
+#endif
/*
* IEN - Input Enable
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := omap1510innovator.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x11080000
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := omap1610innovator.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x11080000
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := omap2420h4.o mem.o sys_info.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
-#TEXT_BASE = 0x40270000
+#CONFIG_SYS_TEXT_BASE = 0x40270000
# Handy to get symbols to debug ROM version.
-#TEXT_BASE = 0x0
-#TEXT_BASE = 0x08000000
-#TEXT_BASE = 0x04000000
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0x08000000
+#CONFIG_SYS_TEXT_BASE = 0x04000000
#include <asm/arch/clocks.h>
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := omap5912osk.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
-TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x11080000
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := omap730p2.o flash.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
#
#
-TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x11080000
#endif
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := panda.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
-# Let's place u-boot 1MB before the end of SDRAM.
-TEXT_BASE = 0x9ff00000
+CONFIG_SYS_TEXT_BASE = 0x80e80000
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
#include "panda.h"
sizeof(wkup_padconf_array) /
sizeof(struct pad_conf_entry));
}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := sdp.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
# (mem base + reserved)
# For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
#include <asm/mach-types.h>
#include "sdp.h"
+DECLARE_GLOBAL_DATA_PTR;
+
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"OMAP3 SDP3430 board",
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* TODO: Dynamically pop out CS mapping and program accordingly */
/* Configure devices for default ON ON ON settings */
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := sdp.o
+COBJS := sdp.o cmd_bat.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BAT
+#include <twl6030.h>
+
+int do_vbat(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc == 2) {
+ if (strncmp(argv[1], "startcharge", 12) == 0)
+ twl6030_start_usb_charging();
+ else if (strncmp(argv[1], "stopcharge", 11) == 0)
+ twl6030_stop_usb_charging();
+ else if (strncmp(argv[1], "status", 7) == 0) {
+ twl6030_get_battery_voltage();
+ twl6030_get_battery_current();
+ } else {
+ goto bat_cmd_usage;
+ }
+ } else {
+ goto bat_cmd_usage;
+ }
+ return 0;
+
+bat_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ bat, 2, 1, do_vbat,
+ "battery charging, voltage/current measurements",
+ "status - display battery voltage and current\n"
+ "bat startcharge - start charging via USB\n"
+ "bat stopcharge - stop charging\n"
+);
+#endif /* CONFIG_BAT_CMD */
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
-# Let's place u-boot 1MB before the end of SDRAM.
-TEXT_BASE = 0x9ff00000
+CONFIG_SYS_TEXT_BASE = 0x80e80000
* MA 02111-1307 USA
*/
#include <common.h>
+#include <twl6030.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
#include "sdp.h"
*/
int misc_init_r(void)
{
+#ifdef CONFIG_TWL6030_POWER
+ twl6030_init_battery_charging();
+#endif
return 0;
}
sizeof(wkup_padconf_array) /
sizeof(struct pad_conf_entry));
}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS += sdb_board.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
-TEXT_BASE = 0x83FC0000
+CONFIG_SYS_TEXT_BASE = 0x83FC0000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := devkit8000.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Total5200 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFFF00000 boot high (standard configuration)
-# 0xFE000000 boot low
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+ ulong *datap = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+ (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
ulong start;
int i, flag;
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+ ulong *datap = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+ (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
ulong start;
int i;
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM5200 board:
-#
-# Valid values for TEXT_BASE are:
-#
-# 0xFC000000 boot low (standard configuration with room for max 64 MByte
-# Flash ROM)
-# 0xFFF00000 boot high (for a backup copy of U-Boot)
-# 0x00100000 boot from RAM (for testing only)
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot low
-TEXT_BASE = 0xFC000000
-## For a backup copy of U-Boot at the end of flash: boot high
-# TEXT_BASE = 0xFFF00000
-## For testing: boot from RAM
-# TEXT_BASE = 0x00100000
-endif
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
void ps2mult_early_init(void);
#endif
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ *
+ * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ * ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
+ * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
+ * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
+ * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
+ * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
+ * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
+ * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
+};
+#endif
+
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
# define CARRIER_NAME "CAM5200"
#elif defined(CONFIG_FO300)
# define CARRIER_NAME "FO300"
+#elif defined(CONFIG_CHARON)
+# define CARRIER_NAME "CHARON"
#else
# error "UNKNOWN"
#endif
}
#endif /* CONFIG_FO300 */
+#if defined(CONFIG_CHARON)
+#include <i2c.h>
+#include <asm/io.h>
+
+/* The TFP410 registers */
+#define TFP410_REG_VEN_ID_L 0x00
+#define TFP410_REG_VEN_ID_H 0x01
+#define TFP410_REG_DEV_ID_L 0x02
+#define TFP410_REG_DEV_ID_H 0x03
+#define TFP410_REG_REV_ID 0x04
+
+#define TFP410_REG_CTL_1_MODE 0x08
+#define TFP410_REG_CTL_2_MODE 0x09
+#define TFP410_REG_CTL_3_MODE 0x0A
+
+#define TFP410_REG_CFG 0x0B
+
+#define TFP410_REG_DE_DLY 0x32
+#define TFP410_REG_DE_CTL 0x33
+#define TFP410_REG_DE_TOP 0x34
+#define TFP410_REG_DE_CNT_L 0x36
+#define TFP410_REG_DE_CNT_H 0x37
+#define TFP410_REG_DE_LIN_L 0x38
+#define TFP410_REG_DE_LIN_H 0x39
+
+#define TFP410_REG_H_RES_L 0x3A
+#define TFP410_REG_H_RES_H 0x3B
+#define TFP410_REG_V_RES_L 0x3C
+#define TFP410_REG_V_RES_H 0x3D
+
+static int tfp410_read_reg(int reg, uchar *buf)
+{
+ if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
+ puts ("Error reading the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+static int tfp410_write_reg(int reg, uchar buf)
+{
+ if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
+ puts ("Error writing the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+typedef struct _tfp410_config {
+ int reg;
+ uchar val;
+}TFP410_CONFIG;
+
+static TFP410_CONFIG tfp410_configtbl[] = {
+ {TFP410_REG_CTL_1_MODE, 0x37},
+ {TFP410_REG_CTL_2_MODE, 0x20},
+ {TFP410_REG_CTL_3_MODE, 0x80},
+ {TFP410_REG_DE_DLY, 0x90},
+ {TFP410_REG_DE_CTL, 0x00},
+ {TFP410_REG_DE_TOP, 0x23},
+ {TFP410_REG_DE_CNT_H, 0x02},
+ {TFP410_REG_DE_CNT_L, 0x80},
+ {TFP410_REG_DE_LIN_H, 0x01},
+ {TFP410_REG_DE_LIN_L, 0xe0},
+ {-1, 0},
+};
+
+static int charon_last_stage_init(void)
+{
+ volatile struct mpc5xxx_lpb *lpb =
+ (struct mpc5xxx_lpb *) MPC5XXX_LPB;
+ int oldbus = i2c_get_bus_num();
+ uchar buf;
+ int i = 0;
+
+ i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
+
+ /* check version */
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
+ return -1;
+ if (!(buf & 0x04))
+ return -1;
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
+ return -1;
+ if (!(buf & 0x10))
+ return -1;
+ /* OK, now init the chip */
+ while (tfp410_configtbl[i].reg != -1) {
+ int ret;
+
+ ret = tfp410_write_reg(tfp410_configtbl[i].reg,
+ tfp410_configtbl[i].val);
+ if (ret != 0)
+ return -1;
+ i++;
+ }
+ printf("TFP410 initialized.\n");
+ i2c_set_bus_num(oldbus);
+
+ /* set deadcycle for cs3 to 0 */
+ setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
+ return 0;
+}
+#endif
+
int last_stage_init (void)
{
/*
#endif
#endif /* !CONFIG_TQM5200S */
+#if defined(CONFIG_CHARON)
+ charon_last_stage_init();
+#endif
return 0;
}
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
+#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
+ defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
} else if (line_number == 2) {
+#if defined (CONFIG_CHARON)
+ strcpy (info, " on a CHARON carrier board");
+#endif
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#endif
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+#if defined(CONFIG_VIDEO)
+ fdt_add_edid(blob, "smi,sm501", edid_buf);
+#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+ /* init Micrel KSZ8993 PHY */
+ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
+}
+#endif
+
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in FEC comes first */
$(shell mkdir -p $(obj)../tqm8xx/)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8260 boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
$(shell mkdir -p $(obj)../tqm8xx/)
endif
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8272 boards
-#
-
-# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h
-# for the "final" configuration, with U-Boot in flash, or the address
-# in RAM where U-Boot is loaded at for debugging.
-#
-TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_PCI) += pci.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# Copyright 2004 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x80000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += sdram.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
+++ /dev/null
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# tqm85xx board
-#
-ifeq ($(CONFIG_TQM8548_BE),y)
-TEXT_BASE = 0xfff80000
-else
-TEXT_BASE = 0xfffc0000
-endif
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
- SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
#ifdef CONFIG_PCIE1
- SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
#endif /* CONFIG_PCIE */
};
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
*/
set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
- set_lbc_br(0, gd->bd->bi_flashstart |
+ set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
/*
* Initialize PCI Devices, report devices found.
*/
-static int first_free_busno;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-static inline void init_pci1(void)
+void pci_init_board (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_PCI1
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
-
- /* PORDEVSR[15] */
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
- /* PORDEVSR[14] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- /* PORPLLSR[16] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+ struct fsl_pci_info pci_info[2];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
- int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+#ifdef CONFIG_PCI1
+ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
+ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333333) ? "33" :
(pci_speed == 66666666) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
+ pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
-
- /* outbound memory */
- pci_set_region (r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- printf (" PCI on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
ushort reg16 =
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- uint dev = PCI_BDF(hose->first_busno, 0, 0);
+ uint dev = PCI_BDF(0, 0, 0);
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
puts ("PCI-X will only work at 66 MHz\n");
- pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
- reg16);
+ pci_write_config_word(dev, PCIX_COMMAND, reg16);
}
#endif
} else {
- puts ("PCI1: disabled\n");
+ printf("PCI1: disabled\n");
}
-#else /* !CONFIG_PCI1 */
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI1 */
-}
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
-static inline void init_pcie1(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep;
- struct pci_region *r = hose->regions;
-
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR);
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("PCIe: %s, base address %x",
- pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (", with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- puts ("\n");
-
- /* outbound memory */
- pci_set_region (r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf (" PCIe on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
-
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf("PCIE1: connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf ("PCIe: disabled\n");
+ printf("PCIE1: disabled\n");
}
-#else /* !CONFIG_PCIE1 */
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
#endif /* CONFIG_PCIE1 */
}
-void pci_init_board (void)
-{
- init_pci1();
- init_pcie1();
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o load_sernum_ethaddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ arch/powerpc/lib/libpowerpc.o (.text*)
+ board/tqc/tqm8xx/libtqm8xx.o (.text*)
+ disk/libdisk.o (.text*)
+ drivers/net/libnet.o (.text*)
+ drivers/pcmcia/libpcmcia.o (.text*)
+ drivers/rtc/librtc.o (.text*)
+ drivers/misc/libmisc.o (.text*)
+ *(.text.print_buffer)
+ *(.text.print_size)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv)
+ common/env_embedded.o (.ppcenv*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
SOBJS := lowlevel_init.o
all: $(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB)
$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
adc_init ();
- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
- padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
- padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+ padc->adccon &= ~ADC_STDBM; /* select normal mode */
+ padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+ padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
while (j--) {
- if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+ if ((padc->adccon & ADC_ENABLE_START) == 0)
break;
udelay (1);
}
if (j == 0) {
printf("%s: ADC timeout\n", __FUNCTION__);
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
return -1;
}
- result = padc->ADCDAT & 0x3FF;
+ result = padc->adcdat & 0x3FF;
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
- (padc->ADCCON >> 3) & 0x7, result);
+ (padc->adccon >> 3) & 0x7, result);
/*
* Wait for ADC to be ready for next conversion. This delay value was
padc = s3c2400_get_base_adc();
- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
- padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+ padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+ padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
/*
* Wait some time to avoid problem with very first call of
switch (state) {
case 0: /* turn LED off */
- gpio->PADAT |= (1 << 12);
+ gpio->padat |= (1 << 12);
break;
case 1: /* turn LED on */
- gpio->PADAT &= ~(1 << 12);
+ gpio->padat &= ~(1 << 12);
break;
default:
break;
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPA12 as output and set to High -> LED off */
- gpio->PACON &= ~(1 << 12);
- gpio->PADAT |= (1 << 12);
+ gpio->pacon &= ~(1 << 12);
+ gpio->padat |= (1 << 12);
}
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-ifndef TEXT_BASE
-TEXT_BASE = 0x0DF40000
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0x0DF40000
endif
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
_TEXT_BASE:
- .word TEXT_BASE
+ .word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
reg = (33000000 / (16 * 38400)) - 1;
/* FIFO enable, Tx/Rx FIFO clear */
- uart->UFCON = 0x07;
- uart->UMCON = 0x0;
+ uart->ufcon = 0x07;
+ uart->umcon = 0x0;
/* Normal,No parity,1 stop,8 bit */
- uart->ULCON = 0x3;
+ uart->ulcon = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- uart->UCON = 0x245;
- uart->UBRDIV = reg;
+ uart->ucon = 0x245;
+ uart->ubrdiv = reg;
for (i = 0; i < 100; i++);
}
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PFCON &= ~(0x3 << 2);
- gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */
+ gpio->pfcon &= ~(0x3 << 2);
+ gpio->pfcon |= (0x2 << 2); /* configure GPF1 as RXD1 */
- gpio->PFCON &= ~(0x3 << 6);
- gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */
+ gpio->pfcon &= ~(0x3 << 6);
+ gpio->pfcon |= (0x2 << 6); /* configure GPF3 as TXD1 */
- gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
- gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+ gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+ gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
- gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+ gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
}
/*
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
+ while (!(uart->utrstat & 0x1))
+ ;
- return uart->URXH & 0xff;
+ return uart->urxh & 0xff;
}
/*
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
+ while (!(uart->utrstat & 0x2))
+ ;
- uart->UTXH = c;
+ uart->utxh = c;
/* If \n, also do \r */
if (c == '\n')
{
struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
- return uart->UTRSTAT & 0x1;
+ return uart->utrstat & 0x1;
}
void rs485_puts (const char *s)
/* This is on PORT A bit 11 */
if(rs485de_state)
- gpio->PADAT |= (1 << 11);
+ gpio->padat |= (1 << 11);
else
- gpio->PADAT &= ~(1 << 11);
+ gpio->padat &= ~(1 << 11);
}
#ifdef CONFIG_TRAB_50MHZ
/* change the clock to be 50 MHz 1:1:1 */
/* MDIV:0x5c PDIV:4 SDIV:2 */
- clk_power->MPLLCON = 0x5c042;
- clk_power->CLKDIVN = 0;
+ clk_power->mpllcon = 0x5c042;
+ clk_power->clkdivn = 0;
#else
/* change the clock to be 133 MHz 1:2:4 */
/* MDIV:0x7d PDIV:4 SDIV:1 */
- clk_power->MPLLCON = 0x7d041;
- clk_power->CLKDIVN = 3;
+ clk_power->mpllcon = 0x7d041;
+ clk_power->clkdivn = 3;
#endif
/* set up the I/O ports */
- gpio->PACON = 0x3ffff;
- gpio->PBCON = 0xaaaaaaaa;
- gpio->PBUP = 0xffff;
+ gpio->pacon = 0x3ffff;
+ gpio->pbcon = 0xaaaaaaaa;
+ gpio->pbup = 0xffff;
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
/* 00, 10, 10, 10, 10, 10, 10 */
- gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+ gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
#ifdef CONFIG_HWFLOW
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
- gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+ gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
#else
/* do not pull up RXD0, RXD1, TXD0, TXD1 */
- gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+ gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3);
#endif
- gpio->PGCON = 0x0;
- gpio->PGUP = 0x0;
- gpio->OPENCR= 0x0;
+ gpio->pgcon = 0x0;
+ gpio->pgup = 0x0;
+ gpio->opencr = 0x0;
/* suppress flicker of the VFDs */
- gpio->MISCCR = 0x40;
- gpio->PFCON |= (2<<12);
+ gpio->misccr = 0x40;
+ gpio->pfcon |= (2<<12);
gd->bd->bi_arch_number = MACH_TYPE_TRAB;
gd->bd->bi_boot_params = 0x0c000100;
/* Make sure both buzzers are turned off */
- gpio->PDCON |= 0x5400;
- gpio->PDDAT &= ~0xE0;
+ gpio->pdcon |= 0x5400;
+ gpio->pddat &= ~0xE0;
#ifdef CONFIG_VFD
vfd_init_clocks();
#ifdef CONFIG_DRIVER_S3C24X0_I2C
/* Configure I/O ports PG5 und PG6 for I2C */
- gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+ gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
#endif /* CONFIG_DRIVER_S3C24X0_I2C */
return 0;
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT &= 0x5FF;
+ gpio->pddat &= 0x5FF;
}
static inline void CLR_CS_TOUCH(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT |= 0x200;
+ gpio->pddat |= 0x200;
}
static void spi_init(void)
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
- gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
- gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
- gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+ gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+ gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+ gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+ gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
CLR_CS_TOUCH();
- spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
- spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
- spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+ spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+ spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+ spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
}
wait_transmit_done();
}
{
struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
- while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+ while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+ ;
}
static void tsc2000_write(unsigned int page, unsigned int reg,
command |= (page << 11);
command |= (reg << 5);
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (data & 0xFF00) >> 8;
wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0x00FF);
+ spi->ch[0].sptdat = (data & 0x00FF);
wait_transmit_done();
CLR_CS_TOUCH();
padc = s3c2400_get_base_adc();
channel &= 0x7;
- padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
- padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
- padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+ padc->adccon &= ~ADC_STDBM; /* select normal mode */
+ padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+ padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
while (j--) {
- if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+ if ((padc->adccon & ADC_ENABLE_START) == 0)
break;
udelay (1);
}
if (j == 0) {
printf("%s: ADC timeout\n", __FUNCTION__);
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
return -1;
}
- result = padc->ADCDAT & 0x3FF;
+ result = padc->adcdat & 0x3FF;
- padc->ADCCON |= ADC_STDBM; /* select standby mode */
+ padc->adccon |= ADC_STDBM; /* select standby mode */
debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
- (padc->ADCCON >> 3) & 0x7, result);
+ (padc->adccon >> 3) & 0x7, result);
/*
* Wait for ADC to be ready for next conversion. This delay value was
padc = s3c2400_get_base_adc();
- padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
- padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+ padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+ padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
/*
* Wait some time to avoid problem with very first call of
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPE7 as input */
- gpio->PECON &= ~(0x3 << (2 * 7));
+ gpio->pecon &= ~(0x3 << (2 * 7));
/* signal GPE7 from power switch is low active: 0=on , 1=off */
- result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+ result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
print_identifier ();
printf("%d\n", result);
/* try to red vfd board id from the value defined by pull-ups */
- pcup_old = gpio->PCUP;
- pccon_old = gpio->PCCON;
+ pcup_old = gpio->pcup;
+ pccon_old = gpio->pccon;
- gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pull-ups */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+ gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pull-ups */
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
* inputs */
udelay (10); /* allow signals to settle */
- vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
+ vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */
- gpio->PCCON = pccon_old;
- gpio->PCUP = pcup_old;
+ gpio->pccon = pccon_old;
+ gpio->pcup = pcup_old;
/* print vfd_board_id to console */
print_identifier ();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* set prescaler for timer 2, 3 and 4 */
- timers->TCFG0 &= ~0xFF00;
- timers->TCFG0 |= 0x0F00;
+ timers->tcfg0 &= ~0xFF00;
+ timers->tcfg0 |= 0x0F00;
/* set divider for timer 2 */
- timers->TCFG1 &= ~0xF00;
- timers->TCFG1 |= 0x300;
+ timers->tcfg1 &= ~0xF00;
+ timers->tcfg1 |= 0x300;
/* set frequency */
counter = (PCLK / BUZZER_FREQ) >> 9;
- timers->ch[2].TCNTB = counter;
- timers->ch[2].TCMPB = counter / 2;
+ timers->ch[2].tcntb = counter;
+ timers->ch[2].tcmpb = counter / 2;
if (strcmp (argv[2], "on") == 0) {
debug ("%s: frequency: %d\n", __FUNCTION__,
BUZZER_FREQ);
/* configure pin GPD7 as TOUT2 */
- gpio->PDCON &= ~0xC000;
- gpio->PDCON |= 0x8000;
+ gpio->pdcon &= ~0xC000;
+ gpio->pdcon |= 0x8000;
/* start */
- timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+ timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
~INVERT2;
- timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+ timers->tcon = (timers->tcon | START2) & ~UPDATE2;
return (0);
}
else if (strcmp (argv[2], "off") == 0) {
/* stop */
- timers->TCON &= ~(START2 | RELOAD2);
+ timers->tcon &= ~(START2 | RELOAD2);
/* configure GPD7 as output and set to low */
- gpio->PDCON &= ~0xC000;
- gpio->PDCON |= 0x4000;
- gpio->PDDAT &= ~0x80;
+ gpio->pdcon &= ~0xC000;
+ gpio->pdcon |= 0x4000;
+ gpio->pddat &= ~0x80;
return (0);
}
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PC14 and PC15 as output */
- gpio->PCCON &= ~(0xF << 28);
- gpio->PCCON |= (0x5 << 28);
+ gpio->pccon &= ~(0xF << 28);
+ gpio->pccon |= (0x5 << 28);
/* configure PD0 and PD4 as output */
- gpio->PDCON &= ~((0x3 << 8) | 0x3);
- gpio->PDCON |= ((0x1 << 8) | 0x1);
+ gpio->pdcon &= ~((0x3 << 8) | 0x3);
+ gpio->pdcon |= ((0x1 << 8) | 0x1);
switch (simple_strtoul(argv[2], NULL, 10)) {
case 2:
if (strcmp (argv[3], "on") == 0)
- gpio->PCDAT |= (1 << 14);
+ gpio->pcdat |= (1 << 14);
else
- gpio->PCDAT &= ~(1 << 14);
+ gpio->pcdat &= ~(1 << 14);
return 0;
case 3:
if (strcmp (argv[3], "on") == 0)
- gpio->PCDAT |= (1 << 15);
+ gpio->pcdat |= (1 << 15);
else
- gpio->PCDAT &= ~(1 << 15);
+ gpio->pcdat &= ~(1 << 15);
return 0;
case 4:
if (strcmp (argv[3], "on") == 0)
- gpio->PDDAT |= (1 << 0);
+ gpio->pddat |= (1 << 0);
else
- gpio->PDDAT &= ~(1 << 0);
+ gpio->pddat &= ~(1 << 0);
return 0;
case 5:
if (strcmp (argv[3], "on") == 0)
- gpio->PDDAT |= (1 << 4);
+ gpio->pddat |= (1 << 4);
else
- gpio->PDDAT &= ~(1 << 4);
+ gpio->pddat &= ~(1 << 4);
return 0;
default:
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PD5 and PD6 as output */
- gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
- gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+ gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+ gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
if (strcmp (argv[2], "+") == 0) {
- gpio->PDDAT |= (1 << 5);
- gpio->PDDAT |= (1 << 6);
+ gpio->pddat |= (1 << 5);
+ gpio->pddat |= (1 << 6);
return 0;
}
else if (strcmp (argv[2], "-") == 0) {
- gpio->PDDAT &= ~(1 << 5);
- gpio->PDDAT |= (1 << 6);
+ gpio->pddat &= ~(1 << 5);
+ gpio->pddat |= (1 << 6);
return 0;
}
else if (strcmp (argv[2], "off") == 0) {
- gpio->PDDAT &= ~(1 << 5);
- gpio->PDDAT &= ~(1 << 6);
+ gpio->pddat &= ~(1 << 5);
+ gpio->pddat &= ~(1 << 6);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* Configure I/O port */
- gpio->PGCON &= ~(0x3 << 0);
- gpio->PGCON |= (0x1 << 0);
+ gpio->pgcon &= ~(0x3 << 0);
+ gpio->pgcon |= (0x1 << 0);
if (strcmp (argv[2], "on") == 0) {
- gpio->PGDAT &= ~(1 << 0);
+ gpio->pgdat &= ~(1 << 0);
return 0;
}
if (strcmp (argv[2], "off") == 0) {
- gpio->PGDAT |= (1 << 0);
+ gpio->pgdat |= (1 << 0);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
if (strcmp (argv[2], "on") == 0) {
/* configure pin GPD8 as TOUT3 */
- gpio->PDCON &= ~(0x3 << 8*2);
- gpio->PDCON |= (0x2 << 8*2);
+ gpio->pdcon &= ~(0x3 << 8*2);
+ gpio->pdcon |= (0x2 << 8*2);
/* set prescaler for timer 2, 3 and 4 */
- timers->TCFG0 &= ~0xFF00;
- timers->TCFG0 |= 0x0F00;
+ timers->tcfg0 &= ~0xFF00;
+ timers->tcfg0 |= 0x0F00;
/* set divider for timer 3 */
- timers->TCFG1 &= ~(0xf << 12);
- timers->TCFG1 |= (0x3 << 12);
+ timers->tcfg1 &= ~(0xf << 12);
+ timers->tcfg1 |= (0x3 << 12);
/* set frequency */
counter = (PCLK / PWM_FREQ) >> 9;
- timers->ch[3].TCNTB = counter;
- timers->ch[3].TCMPB = counter / 2;
+ timers->ch[3].tcntb = counter;
+ timers->ch[3].tcmpb = counter / 2;
/* start timer */
- timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
- timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+ timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+ timers->tcon = (timers->tcon | START3) & ~UPDATE3;
return 0;
}
if (strcmp (argv[2], "off") == 0) {
/* stop timer */
- timers->TCON &= ~(START2 | RELOAD2);
+ timers->tcon &= ~(START2 | RELOAD2);
/* configure pin GPD8 as output and set to 0 */
- gpio->PDCON &= ~(0x3 << 8*2);
- gpio->PDCON |= (0x1 << 8*2);
- gpio->PDDAT &= ~(1 << 8);
+ gpio->pdcon &= ~(0x3 << 8*2);
+ gpio->pdcon |= (0x1 << 8*2);
+ gpio->pddat &= ~(1 << 8);
return 0;
}
printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
- gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
- gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
- gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+ gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+ gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+ gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+ gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
CLR_CS_TOUCH();
- spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
- spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
- spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+ spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+ spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+ spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
}
spi_wait_transmit_done();
}
{
struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
- while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+ while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+ ;
}
SET_CS_TOUCH();
command = reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (data & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (data & 0x00FF);
+ spi->ch[0].sptdat = (data & 0x00FF);
spi_wait_transmit_done();
CLR_CS_TOUCH();
SET_CS_TOUCH();
command = 0x8000 | reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].sptdat = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = (command & 0x00FF);
+ spi->ch[0].sptdat = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].sptdat = 0xFF;
spi_wait_transmit_done();
- data = spi->ch[0].SPRDAT;
- spi->ch[0].SPTDAT = 0xFF;
+ data = spi->ch[0].sprdat;
+ spi->ch[0].sptdat = 0xFF;
spi_wait_transmit_done();
CLR_CS_TOUCH();
- return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+ return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
}
#define _TSC2000_H_
/* temperature channel multiplexer definitions */
-#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0 (gpio->PCDAT |= 0x00010)
-
-#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1 (gpio->PCDAT |= 0x00020)
-
-#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF)
-
-#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F)
-
-#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF)
-
-#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF)
-
-#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
-#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400)
-
-#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
-#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800)
-
-#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
-#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000)
-
-#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
-#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000)
+#define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0 (gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0 (gpio->pcdat |= 0x00010)
+
+#define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1 (gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1 (gpio->pcdat |= 0x00020)
+
+#define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
+ 0x00100000)
+#define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400)
+
+#define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
+ 0x00400000)
+#define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800)
+
+#define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
+ 0x01000000)
+#define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000)
+
+#define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
+ 0x04000000)
+#define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000)
/* TSC2000 register definition */
#define TSC2000_REG_X ((0 << 11) | (0 << 5))
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT &= 0x5FF;
+ gpio->pddat &= 0x5FF;
}
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- gpio->PDDAT |= 0x200;
+ gpio->pddat |= 0x200;
}
#endif /* _TSC2000_H_ */
/* try to determine display type from the value
* defined by pull-ups
*/
- gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
+ gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pullups */
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
/* allow signals to settle */
for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */
__asm__("NOP");
- vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
+ vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */
VFD_DISABLE; /* activate blank for the vfd */
/* If new board revision, then use PWM 3 as cpld-clock */
/* Enable 500 Hz timer for fill level sensor to operate properly */
/* Configure TOUT3 as functional pin, disable pull-up */
- gpio->PDCON &= ~0x30000;
- gpio->PDCON |= 0x20000;
- gpio->PDUP |= (1 << 8);
+ gpio->pdcon &= ~0x30000;
+ gpio->pdcon |= 0x20000;
+ gpio->pdup |= (1 << 8);
/* Configure the prescaler */
- timers->TCFG0 &= ~0xff00;
- timers->TCFG0 |= 0x0f00;
+ timers->tcfg0 &= ~0xff00;
+ timers->tcfg0 |= 0x0f00;
/* Select MUX input (divider) for timer3 (1/16) */
- timers->TCFG1 &= ~0xf000;
- timers->TCFG1 |= 0x3000;
+ timers->tcfg1 &= ~0xf000;
+ timers->tcfg1 |= 0x3000;
/* Enable autoreload and set the counter and compare
* registers to values for the 500 Hz clock
* (for a given prescaler (15) and divider (16)):
* counter = (66000000 / 500) >> 9;
*/
- timers->ch[3].TCNTB = 0x101;
- timers->ch[3].TCMPB = 0x101 / 2;
+ timers->ch[3].tcntb = 0x101;
+ timers->ch[3].tcmpb = 0x101 / 2;
/* Start timer */
- timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
- timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+ timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+ timers->tcon = (timers->tcon | START3) & ~UPDATE3;
}
#endif
/* If old board revision, then use vm-signal as cpld-clock */
- lcd->LCDCON2 = 0x00FFC000;
- lcd->LCDCON3 = 0x0007FF00;
- lcd->LCDCON4 = 0x00000000;
- lcd->LCDCON5 = 0x00000400;
- lcd->LCDCON1 = 0x00000B75;
+ lcd->lcdcon2 = 0x00FFC000;
+ lcd->lcdcon3 = 0x0007FF00;
+ lcd->lcdcon4 = 0x00000000;
+ lcd->lcdcon5 = 0x00000400;
+ lcd->lcdcon1 = 0x00000B75;
/* VM (GPD1) is used as clock for the CPLD */
- gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+ gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
return 0;
}
* see manual S3C2400
*/
/* Stopp LCD-Controller */
- lcd->LCDCON1 = 0x00000000;
+ lcd->lcdcon1 = 0x00000000;
/* frame buffer startadr */
- lcd->LCDSADDR1 = gd->fb_base >> 1;
+ lcd->lcdsaddr1 = gd->fb_base >> 1;
/* frame buffer endadr */
- lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
- lcd->LCDSADDR3 = ((256/4));
- lcd->LCDCON2 = 0x000DC000;
+ lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+ lcd->lcdsaddr3 = ((256/4));
+ lcd->lcdcon2 = 0x000DC000;
if(gd->vfd_type == VFD_TYPE_MN11236)
- lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */
+ lcd->lcdcon2 = 37 << 14; /* MN11236: 38 lines */
else
- lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */
- lcd->LCDCON3 = 0x0051000A;
- lcd->LCDCON4 = 0x00000001;
+ lcd->lcdcon2 = 55 << 14; /* T119C: 56 lines */
+ lcd->lcdcon3 = 0x0051000A;
+ lcd->lcdcon4 = 0x00000001;
if (gd->vfd_type && vfd_inv_data)
- lcd->LCDCON5 = 0x000004C0;
+ lcd->lcdcon5 = 0x000004C0;
else
- lcd->LCDCON5 = 0x00000440;
+ lcd->lcdcon5 = 0x00000440;
/* Port pins as LCD output */
- gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
- gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+ gpio->pccon = (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
+ gpio->pdcon = (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
/* Synchronize VFD enable with LCD controller to avoid flicker */
- lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */
- while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
- while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
- while((lcd->LCDCON5 & 0x060000)==0x040000);
- while((lcd->LCDCON5 & 0x060000)!=0x000000);
+ lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller */
+ while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
+ ;
+ while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
+ ;
+ while ((lcd->lcdcon5 & 0x060000) == 0x040000)
+ ;
+ while ((lcd->lcdcon5 & 0x060000) != 0x000000)
+ ;
if(gd->vfd_type)
VFD_ENABLE;
- debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
- debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
- debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+ debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+ debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+ debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
return 0;
}
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
VFD_DISABLE;
- gpio->PDCON &= ~0xC;
- gpio->PDUP &= ~0x2;
+ gpio->pdcon &= ~0xC;
+ gpio->pdup &= ~0x2;
}
/************************************************************************/
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := conxs.o eeprom.o
-SOBJS := lowlevel_init.o pxavoltage.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE =0xa1f00000
-# 0xa1700000
-#TEXT_BASE = 0
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
-#if CONFIG_POLARIS
+#if CONFIG_MK_POLARIS
#define BOOT_CONSOLE "serial_stuart"
#else
#define BOOT_CONSOLE "serial_ffuart"
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(RH_A_NPS);
- UHCRHDA |= RH_A_PSM;
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
return 0;
}
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of ConXS Board */
gd->bd->bi_arch_number = 776;
return &serial_ffuart_device;
}
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_DRIVER_DM9000
+++ /dev/null
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPSR3
- ldr r1, =CONFIG_SYS_GPSR3_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR3
- ldr r1, =CONFIG_SYS_GPCR3_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GRER3
- ldr r1, =CONFIG_SYS_GRER3_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER3
- ldr r1, =CONFIG_SYS_GFER3_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR3
- ldr r1, =CONFIG_SYS_GPDR3_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_L
- ldr r1, =CONFIG_SYS_GAFR3_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_U
- ldr r1, =CONFIG_SYS_GAFR3_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
- ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- str r2, [r1, #FLYCNFG_OFFSET]
- str r2, [r1, #FLYCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r4, [r1, #MDREFR_OFFSET]
- ldr r2, =0xFFF
- bic r4, r4, r2
-
- ldr r3, =CONFIG_SYS_MDREFR_VAL
- and r3, r3, r2
-
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
- orr r4, r4, #MDREFR_K0RUN
- orr r4, r4, #MDREFR_K0DB4
- orr r4, r4, #MDREFR_K0FREE
- orr r4, r4, #MDREFR_K0DB2
- orr r4, r4, #MDREFR_K1DB2
- bic r4, r4, #MDREFR_K1FREE
- bic r4, r4, #MDREFR_K2FREE
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- ldr r2, =CONFIG_SYS_SXCNFG_VAL
- str r2, [r1, #SXCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
- orr r4, r4, #MDREFR_K1RUN
- bic r4, r4, #MDREFR_K2DB2
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- bic r4, r4, #MDREFR_SLFRSH
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- orr r4, r4, #MDREFR_E1PIN
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- nop
- nop
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CONFIG_SYS_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- mov r4, r3
- orr r3, r3, #MDCNFG_DE0
- str r3, [r1, #MDCNFG_OFFSET]
- mov r0, r3
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* enable APD */
- ldr r3, [r1, #MDREFR_OFFSET]
- orr r3, r3, #MDREFR_APD
- str r3, [r1, #MDREFR_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-
-
-setvoltage:
-
- mov r10, lr
- bl initPXAvoltage /* In case the board is rebooting with a */
- mov lr, r10 /* low voltage raise it up to a good one. */
-
-#if 1
- b initirqs
-#endif
-
-wakeup:
- /* Are we waking from sleep? */
- ldr r0, =RCSR
- ldr r1, [r0]
- and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r1, [r0]
- teq r1, #RCSR_SMR
-
- bne initirqs
-
- ldr r0, =PSSR
- mov r1, #PSSR_PH
- str r1, [r0]
-
- /* if so, resume at PSPR */
- ldr r0, =PSPR
- ldr r1, [r0]
- mov pc, r1
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off on-chip peripheral clocks (except for memory) */
- /* for re-configuration. */
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN
- str r2, [r1]
-
- /* ... and write the core clock config register */
- ldr r2, =CONFIG_SYS_CCCR
- ldr r1, =CCCR
- str r2, [r1]
-
- /* Turn on turbo mode */
- mrc p14, 0, r2, c6, c0, 0
- orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
- mcr p14, 0, r2, c6, c0, 0
-
- /* Re-write MDREFR */
- ldr r1, =MEMC_BASE
- ldr r2, [r1, #MDREFR_OFFSET]
- str r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#else
-#error "RTC not defined"
-#endif
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
- /* FIXME */
-
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
-COBJS := xsengine.o flash.o
-SOBJS := lowlevel_init.o
+COBJS := vision2.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
+ rm -f $(LIB) core *.bak .depend
#########################################################################
#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
#
# See file CREDITS for list of people who contributed to this
# project.
# MA 02111-1307 USA
#
-#
-# EVB64460 boards
-#
-
-TEXT_BASE = 0xfff00000
+CONFIG_SYS_TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
+ALL += $(obj)u-boot.imx
--- /dev/null
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# (C) Copyright 2010
+# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi, nand, onenand, sd
+
+BOOT_FROM spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+#######################
+### Disable WDOG ###
+#######################
+DATA 2 0x73f98000 0x30
+
+#######################
+### SET DDR Clk ###
+#######################
+
+# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
+DATA 4 0x73FD4018 0x000024C0
+
+# DOUBLE SPI CLK (13MHz->26 MHz Clock)
+DATA 4 0x73FD4038 0x2010241
+
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8600 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8604 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8608 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa860c 0x00000187
+#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
+DATA 4 0x73fa8614 0x00000107
+#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
+DATA 4 0x73fa86a8 0x00000187
+
+#######################
+### Settings IOMUXC ###
+#######################
+
+# DDR IOMUX configuration
+# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+DATA 4 0x73fa84b8 0x000000e7
+# PVTC MAX (at GPC, PGR reg)
+#DATA 4 0x73FD8004 0x1fc00000
+
+#DQM0 DS high slew rate slow
+DATA 4 0x73fa84d4 0x000000e4
+#DQM1 DS high slew rate slow
+DATA 4 0x73fa84d8 0x000000e4
+#DQM2 DS high slew rate slow
+DATA 4 0x73fa84dc 0x000000e4
+#DQM3 DS high slew rate slow
+DATA 4 0x73fa84e0 0x000000e4
+
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
+DATA 4 0x73fa84bc 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
+DATA 4 0x73fa84c0 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
+DATA 4 0x73fa84c4 0x000000c4
+#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
+DATA 4 0x73fa84c8 0x000000c4
+
+#DRAM_DATA B0
+DATA 4 0x73fa88a4 0x00000004
+#DRAM_DATA B1
+DATA 4 0x73fa88ac 0x00000004
+#DRAM_DATA B2
+DATA 4 0x73fa88b8 0x00000004
+#DRAM_DATA B3
+DATA 4 0x73fa882c 0x00000004
+
+#DRAM_DATA B0 slew rate
+DATA 4 0x73fa8878 0x00000000
+#DRAM_DATA B1 slew rate
+DATA 4 0x73fa8880 0x00000000
+#DRAM_DATA B2 slew rate
+DATA 4 0x73fa888c 0x00000000
+#DRAM_DATA B3 slew rate
+DATA 4 0x73fa889c 0x00000000
+
+#######################
+### Configure SDRAM ###
+#######################
+
+# Configure CS0
+#######################
+
+# ESDCTL0: Enable controller
+DATA 4 0x83fd9000 0x83220000
+
+# Init DRAM on CS0
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x04008008
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008010
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x00338018
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801a
+# ESDSCR
+DATA 4 0x83fd9014 0x00008000
+
+# ESDSCR: EMR with full Drive strength
+#DATA 4 0x83fd9014 0x0000801a
+
+# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9000 0xC3220000
+
+# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd9004 0xC33574AA
+
+#micron mDDR
+# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD9004 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD9004 0x704564a8
+
+# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+DATA 4 0x83fd9010 0x000a1700
+
+# Configure CS1
+#######################
+
+# ESDCTL1: Enable controller
+DATA 4 0x83fd9008 0x83220000
+
+# Init DRAM on CS1
+# ESDSCR: Precharge command
+DATA 4 0x83fd9014 0x0400800c
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: Refresh command
+DATA 4 0x83fd9014 0x00008014
+# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DATA 4 0x83fd9014 0x0033801c
+# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
+DATA 4 0x83fd9014 0x0020801e
+# ESDSCR
+DATA 4 0x83fd9014 0x00008004
+
+# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+DATA 4 0x83fd9008 0xC3220000
+
+# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+#DATA 4 0x83fd900c 0xC33574AA
+
+#micron mDDR
+# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+#DATA 4 0x83FD900C 0x101564a8
+
+#hynix mDDR
+# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+DATA 4 0x83FD900C 0x704564a8
+
+# ESDSCR (mDRAM configuration finished)
+DATA 4 0x83FD9014 0x00000004
+
+# ESDSCR - clear "configuration request" bit
+DATA 4 0x83fd9014 0x00000000
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <mxc_gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <linux/fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+extern int mx51_fb_init(struct fb_videomode *mode);
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+static struct fb_videomode nec_nl6448bc26_09c = {
+ "NEC_NL6448BC26-09C",
+ 60, /* Refresh */
+ 640, /* xres */
+ 480, /* yres */
+ 37650, /* pixclock = 26.56Mhz */
+ 48, /* left margin */
+ 16, /* right margin */
+ 31, /* upper margin */
+ 12, /* lower margin */
+ 96, /* hsync-len */
+ 2, /* vsync-len */
+ 0, /* sync */
+ FB_VMODE_NONINTERLACED, /* vmode */
+ 0, /* flag */
+};
+
+void hw_watchdog_reset(void)
+{
+ int val;
+
+ /* toggle watchdog trigger pin */
+ val = mxc_gpio_get(66);
+ val = val ? 0 : 1;
+ mxc_gpio_set(66, val);
+}
+#endif
+
+static void init_drive_strength(void)
+{
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
+
+ /* Setting pad options */
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+}
+
+u32 get_board_rev(void)
+{
+ system_rev = get_cpu_rev();
+
+ return system_rev;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void setup_weim(void)
+{
+ struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
+
+ pweim->csgcr1 = 0x004100b9;
+ pweim->csgcr2 = 0x00000001;
+ pweim->csrcr1 = 0x0a018000;
+ pweim->csrcr2 = 0;
+ pweim->cswcr1 = 0x0704a240;
+}
+
+static void setup_uart(void)
+{
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+ /* console RX on Pin EIM_D25 */
+ mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
+ /* console TX on Pin EIM_D26 */
+ mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+}
+
+#ifdef CONFIG_MXC_SPI
+void spi_io_init(void)
+{
+ /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /*
+ * SS1 will be used as GPIO because of uninterrupted
+ * long SPI transmissions (GPIO4_25)
+ */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+}
+
+static void reset_peripherals(int reset)
+{
+ if (reset) {
+
+ /* reset_n is on NANDF_D15 */
+ mxc_gpio_set(89, 0);
+ mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
+
+#ifdef CONFIG_VISION2_HW_1_0
+ /*
+ * set FEC Configuration lines
+ * set levels of FEC config lines
+ */
+ mxc_gpio_set(75, 0);
+ mxc_gpio_set(74, 1);
+ mxc_gpio_set(95, 1);
+ mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
+
+ /* set direction of FEC config lines */
+ mxc_gpio_set(59, 0);
+ mxc_gpio_set(60, 0);
+ mxc_gpio_set(61, 0);
+ mxc_gpio_set(55, 1);
+ mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
+
+ /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
+ mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+ /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
+ mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
+ /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
+ mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
+ /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
+ mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
+ /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
+ mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
+ /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
+ mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
+ /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
+ mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+#endif
+
+ /*
+ * activate reset_n pin
+ * Select mux mode: ALT3 mux port: NAND D15
+ */
+ mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
+ PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+ } else {
+ /* set FEC Control lines */
+ mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
+ udelay(500);
+
+#ifdef CONFIG_VISION2_HW_1_0
+ /* FEC RDATA[3] */
+ mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+ /* FEC RDATA[2] */
+ mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+ /* FEC RDATA[1] */
+ mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+ /* FEC RDATA[0] */
+ mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+ /* FEC RX_CLK */
+ mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+ /* FEC COL */
+ mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+#endif
+ }
+}
+
+static void power_init_mx51(void)
+{
+ unsigned int val;
+
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg_read(REG_POWER_MISC);
+
+ /* enable VCAM with 2.775V to enable read from PMIC */
+ val = VCAMCONFIG | VCAMEN;
+ pmic_reg_write(REG_MODE_1, val);
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ val = pmic_reg_read(REG_SW_4);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg_read(REG_SW_5);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(REG_SW_5, val);
+
+
+ /* Set VGEN3 to 1.8V, VCAM to 3.0V */
+ val = pmic_reg_read(REG_SETTING_0);
+ val &= ~(VCAM_MASK | VGEN3_MASK);
+ val |= VCAM_3_0;
+ pmic_reg_write(REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
+ val = pmic_reg_read(REG_SETTING_1);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
+ pmic_reg_write(REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(REG_MODE_1, val);
+
+ val = pmic_reg_read(REG_POWER_CTL2);
+ val |= WDIRESET;
+ pmic_reg_write(REG_POWER_CTL2, val);
+
+ udelay(2500);
+
+}
+#endif
+
+static void setup_gpios(void)
+{
+ unsigned int i;
+
+ /* CAM_SUP_DISn, GPIO1_7 */
+ mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
+
+ /* DAB Display EN, GPIO3_1 */
+ mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
+
+ /* WDOG_TRIGGER, GPIO3_2 */
+ mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+
+ /* Now we need to trigger the watchdog */
+ WATCHDOG_RESET();
+
+ /* Display2 TxEN, GPIO3_3 */
+ mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
+
+ /* DAB Light EN, GPIO3_4 */
+ mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
+
+ /* AUDIO_MUTE, GPIO3_5 */
+ mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
+
+ /* SPARE_OUT, GPIO3_6 */
+ mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
+
+ /* BEEPER_EN, GPIO3_26 */
+ mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
+
+ /* POWER_OFF, GPIO3_27 */
+ mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
+
+ /* FRAM_WE, GPIO3_30 */
+ mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
+
+ /* EXPANSION_EN, GPIO4_26 */
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
+
+ /* PWM Output GPIO1_2 */
+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+
+ /*
+ * Set GPIO1_4 to high and output; it is used to reset
+ * the system on reboot
+ */
+ mxc_gpio_set(4, 1);
+ mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
+
+ mxc_gpio_set(7, 0);
+ mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
+ for (i = 65; i < 71; i++) {
+ mxc_gpio_set(i, 0);
+ mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
+ }
+
+ mxc_gpio_set(94, 0);
+ mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
+
+ /* Set POWER_OFF high */
+ mxc_gpio_set(91, 1);
+ mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
+
+ mxc_gpio_set(90, 0);
+ mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
+
+ mxc_gpio_set(122, 0);
+ mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
+
+ mxc_gpio_set(121, 1);
+ mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
+
+ WATCHDOG_RESET();
+}
+
+static void setup_fec(void)
+{
+ /*FEC_MDIO*/
+ mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
+
+ /*FEC_MDC*/
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
+
+ /* FEC RDATA[3] */
+ mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+ /* FEC RDATA[2] */
+ mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+ /* FEC RDATA[1] */
+ mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+ /* FEC RDATA[0] */
+ mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+ /* FEC TDATA[3] */
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
+
+ /* FEC TDATA[2] */
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
+
+ /* FEC TDATA[1] */
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
+
+ /* FEC TDATA[0] */
+ mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
+
+ /* FEC TX_EN */
+ mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
+
+ /* FEC TX_ER */
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
+
+ /* FEC TX_CLK */
+ mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
+
+ /* FEC TX_COL */
+ mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+
+ /* FEC RX_CLK */
+ mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+ /* FEC RX_CRS */
+ mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+ /* FEC RX_DV */
+ mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {MMC_SDHC1_BASE_ADDR, 1},
+};
+
+int get_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *cd = mxc_gpio_get(0);
+ else
+ *cd = 0;
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bis)
+{
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA0,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA1,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA2,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA3,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_GPIO1_0,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+ PAD_CTL_HYS_ENABLE);
+ mxc_request_iomux(MX51_PIN_GPIO1_1,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+ PAD_CTL_HYS_ENABLE);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+
+
+ init_drive_strength();
+
+ /* Setup debug led */
+ mxc_gpio_set(6, 0);
+ mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
+ mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+
+ /* wait a little while to give the pll time to settle */
+ sdelay(100000);
+
+ setup_weim();
+ setup_uart();
+ setup_fec();
+ setup_gpios();
+
+ spi_io_init();
+
+ return 0;
+}
+
+static void backlight(int on)
+{
+ if (on) {
+ mxc_gpio_set(65, 1);
+ udelay(10000);
+ mxc_gpio_set(68, 1);
+ } else {
+ mxc_gpio_set(65, 0);
+ mxc_gpio_set(68, 0);
+ }
+}
+
+void lcd_enable(void)
+{
+ int ret;
+
+ mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+
+ mxc_gpio_set(2, 1);
+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+
+ ret = mx51_fb_init(&nec_nl6448bc26_09c);
+ if (ret)
+ puts("LCD cannot be configured\n");
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ power_init_mx51();
+
+ reset_peripherals(1);
+ udelay(2000);
+ reset_peripherals(0);
+ udelay(2000);
+
+ /* Early revisions require a second reset */
+#ifdef CONFIG_VISION2_HW_1_0
+ reset_peripherals(1);
+ udelay(2000);
+ reset_peripherals(0);
+ udelay(2000);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 system_rev = get_cpu_rev();
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ puts("Board: TTControl Vision II CPU V");
+
+ switch (system_rev & 0xff) {
+ case CHIP_REV_3_0:
+ puts("3.0 [");
+ break;
+ case CHIP_REV_2_5:
+ puts("2.5 [");
+ break;
+ case CHIP_REV_2_0:
+ puts("2.0 [");
+ break;
+ case CHIP_REV_1_1:
+ puts("1.1 [");
+ break;
+ case CHIP_REV_1_0:
+ default:
+ puts("1.0 [");
+ break;
+ }
+
+ cause = src_regs->srsr;
+ switch (cause) {
+ case 0x0001:
+ puts("POR");
+ break;
+ case 0x0009:
+ puts("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ puts("WDOG");
+ break;
+ default:
+ printf("unknown 0x%x", cause);
+ }
+ puts("]\n");
+
+ return 0;
+}
+
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int on;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ on = (strcmp(argv[1], "on") == 0);
+ backlight(on);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+ "Vision2 Backlight",
+ "lcdbl [on|off]\n"
+);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Gregory E. Allen, gallen@arlut.utexas.edu
-# Matthew E. Karger, karger@arlut.utexas.edu
-# Applied Research Laboratories, The University of Texas at Austin
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# UTX8245 boards
-#
-TEXT_BASE = 0xFFF00000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Marel V37 boards
-#
-TEXT_BASE = 0x40000000
/*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
- arch/powerpc/lib/cache.o (.text)
- arch/powerpc/lib/time.o (.text)
-
-/*
- . = env_offset;
-*/
- common/env_embedded.o (.ppcenv)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ethaddr.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MarelV38B board
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-TEXT_BASE = 0xFF000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-ifndef NAND_SPL
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-endif
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xfe000000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := voiceblue.o
SOBJS := setup.o
all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
$(obj)eeprom_start.o:
echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
-TEXT_BASE = 0x13FD0000
+CONFIG_SYS_TEXT_BASE = 0x13FD0000
#include <version.h>
_TEXT_BASE:
- .word TEXT_BASE /* SDRAM load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */
OMAP5910_LPG1_BASE: .word 0xfffbd000
OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
-
#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Voipac PXA270 Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := vpac270.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE = 0xa1000000
/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ * Voipac PXA270 Support
*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-/* ------------------------------------------------------------------------- */
-
/*
* Miscelaneous platform dependent initialisations
*/
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-struct serial_device *default_serial_console (void)
+int board_init(void)
{
- return &serial_ffuart_device;
-}
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
-int board_init (void)
-{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
- /* arch number of vpac270 */
+ /* Arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
/* adress of boot parameters */
return 0;
}
-int dram_init (void)
+struct serial_device *default_serial_console(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ return &serial_ffuart_device;
+}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
+#ifdef CONFIG_RAM_256M
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
}
+#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
+#endif
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
watchdog.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Wave 7 Optics boards
-#
-
-#TEXT_BASE = 0xFFF80000
-TEXT_BASE = 0xFFFC0000
-
-#PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD)
+++ /dev/null
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-TEXT_BASE = 0xa1fe0000
-#TEXT_BASE = 0xa1001000
+++ /dev/null
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- * hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-# define FLASH_BUS vu_char
-# define FLASH_BUS_RET u_char
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# else
-# error "With 8bit bus only one chip is allowed"
-# endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-# define FLASH_BUS vu_short
-# define FLASH_BUS_RET u_short
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( WEP_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 8 )| x )
-# else
-# error "With 16bit bus only 1 or 2 chip(s) are allowed"
-# endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-# define FLASH_BUS vu_long
-# define FLASH_BUS_RET u_long
-# if ( WEP_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( WEP_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 16 )| x )
-# elif ( WEP_FLASH_INTERLEAVE == 4 )
-# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-# else
-# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-# endif
-
-#else
-# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
- FLASH_BUS *addr = (FLASH_BUS *) 0;
-
- *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
- return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
- int ok = 1;
-
- reset_timer_masked ();
- while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
- FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer_masked () > timeout && timeout != 0) {
- ok = 0;
- break;
- }
- }
- return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-# error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
- int i;
- FLASH_BUS address = WEP_FLASH_BASE;
-
- flash_info[0].size = WEP_FLASH_BANK_SIZE;
- flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[0].flash_id = INTEL_MANUFACT;
- memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
- flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
- /* Some devices are hw locked after start. */
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
- flash_ready (0);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
- address += WEP_FLASH_SECT_SIZE;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- printf (" Intel vendor\n");
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if (!(i % 5)) {
- printf ("\n");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, non_protected = 0, sector;
- int rc = ERR_OK;
-
- FLASH_BUS *address;
-
- for (sector = s_first; sector <= s_last; sector++) {
- if (!info->protect[sector]) {
- non_protected++;
- }
- }
-
- if (!non_protected) {
- return ERR_PROTECTED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
-
- /* Start erase on unprotected sectors */
- for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
- if (info->protect[sector]) {
- printf ("Protected sector %2d skipping...\n", sector);
- continue;
- } else {
- printf ("Erasing sector %2d ... ", sector);
- }
-
- address = (FLASH_BUS *) (info->start[sector]);
-
- *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
- *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
- if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- printf ("ok.\n");
- } else {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- break;
- }
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- }
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked (10000);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
- FLASH_BUS *address = (FLASH_BUS *) dest;
- int rc = ERR_OK;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*address & data) != data) {
- return ERR_NOT_ERASED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts ();
-
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
- *address = data;
-
- if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- }
-
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong read_addr, write_addr;
- FLASH_BUS data;
- int i, result = ERR_OK;
-
-
- read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
- write_addr = read_addr;
- if (read_addr != addr) {
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (read_addr < addr || cnt == 0) {
- data |= *((uchar *) read_addr) << i * 8;
- } else {
- data |= (*src++) << i * 8;
- cnt--;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- }
- for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
- if ((result = write_data (info, write_addr,
- *((FLASH_BUS *) src))) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- src += sizeof (FLASH_BUS);
- }
- if (cnt > 0) {
- read_addr = write_addr;
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (cnt > 0) {
- data |= (*src++) << i * 8;
- cnt--;
- } else {
- data |= *((uchar *) read_addr) << i * 8;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != 0) {
- return result;
- }
- }
- return ERR_OK;
-}
+++ /dev/null
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
+++ /dev/null
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- * Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- * Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- * Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* setup memory - see 6.12 in [1]
- * Step 1 - wait 200 us
- */
- mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r0, r0, #1
- bne 1b
-/* TODO: complete step 1 for Synchronous Static memory*/
-
- ldr r0, =0x48000000 /* MC_BASE */
-
-
-/* step 1.a - setup MSCx
- */
- ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
- str r1, [r0, #0x8] /* MSC0_OFFSET */
-
-/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- * see AUTO REFRESH chapter in section D. in [2] and in [3]
- * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- * TODO: complete for Synchronous Static memory
- */
- ldr r1, [r0, #4] /* MDREFR_OFFSET */
- ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
- bic r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
- orr r1, r1, #48 /* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
- orr r1, r1, #24 /* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 2 - only for Synchronous Static memory (TODO)
- *
- * Step 3 - same as step 4
- *
- * Step 4
- *
- * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
- orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
- bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.b - clear MDREFR:SLFRSH */
- bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.c - set MDREFR:E1PIN */
- orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.d - automatically done
- *
- * Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
- ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
- ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 5 - wait at least 200 us for SDRAM
- * see section B. in [2]
- */
- mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r2, r2, #1
- bne 1b
-
-/* Step 6 - after reset dcache is disabled, so automatically done
- *
- * Step 7 - eight refresh cycles
- */
- mov r2, #0xA0000000
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
-
-/* Step 8 - we don't need dcache now
- *
- * Step 9 - enable SDRAM partition 0
- */
- orr r1, r1, #1 /* MDCNFG_DE0 */
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 10 - write MDMRS */
- mov r1, #0
- str r1, [r0, #0x40] /* MDMRS_OFFSET */
-
-/* Step 11 - optional (TODO) */
-
- mov pc,r10
+++ /dev/null
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
- gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
- GPDR1 = 0x80;
- GAFR1_L = 0x8010;
-#elif defined( CONFIG_BTUART )
- GPDR1 = 0x800;
- GAFR1_L = 0x900000;
-#endif
- PSSR = 0x20;
-
- return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
- gd->bd->bi_dram[0].start = WEP_SDRAM_1;
- gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
- gd->bd->bi_dram[1].start = WEP_SDRAM_2;
- gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
- gd->bd->bi_dram[2].start = WEP_SDRAM_3;
- gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
- gd->bd->bi_dram[3].start = WEP_SDRAM_4;
- gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
- return 0;
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#TEXT_BASE = 0xFE000000
-TEXT_BASE = 0x40000000
-OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
*/
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ net/libnet.o (.text*)
+ board/westel/amx860/libamx860.o (.text*)
+ *(.text.*printf)
. = env_offset;
- common/env_embedded.o(.text)
+ common/env_embedded.o (.text*)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.bss*)
+ *(.sbss*)
*(COMMON)
. = ALIGN(4);
}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := xaeniax.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE = 0xa3FB0000
-#TEXT_BASE = 0
+++ /dev/null
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0,=GPSR0
- ldr r1,=CONFIG_SYS_GPSR0_VAL
- str r1,[r0]
-
- ldr r0,=GPSR1
- ldr r1,=CONFIG_SYS_GPSR1_VAL
- str r1,[r0]
-
- ldr r0,=GPSR2
- ldr r1,=CONFIG_SYS_GPSR2_VAL
- str r1,[r0]
-
- ldr r0,=GPCR0
- ldr r1,=CONFIG_SYS_GPCR0_VAL
- str r1,[r0]
-
- ldr r0,=GPCR1
- ldr r1,=CONFIG_SYS_GPCR1_VAL
- str r1,[r0]
-
- ldr r0,=GPCR2
- ldr r1,=CONFIG_SYS_GPCR2_VAL
- str r1,[r0]
-
- ldr r0,=GPDR0
- ldr r1,=CONFIG_SYS_GPDR0_VAL
- str r1,[r0]
-
- ldr r0,=GPDR1
- ldr r1,=CONFIG_SYS_GPDR1_VAL
- str r1,[r0]
-
- ldr r0,=GPDR2
- ldr r1,=CONFIG_SYS_GPDR2_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_L
- ldr r1,=CONFIG_SYS_GAFR0_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_U
- ldr r1,=CONFIG_SYS_GAFR0_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_L
- ldr r1,=CONFIG_SYS_GAFR1_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_U
- ldr r1,=CONFIG_SYS_GAFR1_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_L
- ldr r1,=CONFIG_SYS_GAFR2_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_U
- ldr r1,=CONFIG_SYS_GAFR2_U_VAL
- str r1,[r0]
-
- ldr r0,=PSSR /* enable GPIO pins */
- ldr r1,=CONFIG_SYS_PSSR_VAL
- str r1,[r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1,=MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2,=CONFIG_SYS_MSC0_VAL
- str r2,[r1, #MSC0_OFFSET]
- ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
-
- /* MSC1: nCS(2,3) */
- ldr r2,=CONFIG_SYS_MSC1_VAL
- str r2,[r1, #MSC1_OFFSET]
- ldr r2,[r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2,=CONFIG_SYS_MSC2_VAL
- str r2,[r1, #MSC2_OFFSET]
- ldr r2,[r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2,=CONFIG_SYS_MECR_VAL
- str r2,[r1, #MECR_OFFSET]
- ldr r2,[r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2,=CONFIG_SYS_MCMEM0_VAL
- str r2,[r1, #MCMEM0_OFFSET]
- ldr r2,[r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2,=CONFIG_SYS_MCMEM1_VAL
- str r2,[r1, #MCMEM1_OFFSET]
- ldr r2,[r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2,=CONFIG_SYS_MCATT0_VAL
- str r2,[r1, #MCATT0_OFFSET]
- ldr r2,[r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2,=CONFIG_SYS_MCATT1_VAL
- str r2,[r1, #MCATT1_OFFSET]
- ldr r2,[r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2,=CONFIG_SYS_MCIO0_VAL
- str r2,[r1, #MCIO0_OFFSET]
- ldr r2,[r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2,=CONFIG_SYS_MCIO1_VAL
- str r2,[r1, #MCIO1_OFFSET]
- ldr r2,[r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- @ get the mdrefr settings
- ldr r4,=CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- str r4,[r1, #MDREFR_OFFSET]
- ldr r4,[r1, #MDREFR_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #MDREFR_K1RUN
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #MDREFR_SLFRSH
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
- orr r4, r4, #(MDREFR_E1PIN)
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-
- /* Step 4d: */
- /* fetch platform value of mdcnfg */
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CONFIG_SYS_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* get memory controller base address */
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r1, =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
- ldr r2, =ICMR
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
-test:
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size ?*/
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End lowlevel_init */
- /* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
- mov pc, lr
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of xaeniax */
gd->bd->bi_arch_number = 585;
return 0;
}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- /* gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
- /* gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
- /* gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
- /* gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
- /* gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
- /* gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
- return 0;
}
#ifdef CONFIG_CMD_NET
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
-LIB = $(obj)lib$(VENDOR).a
+LIB = $(obj)lib$(VENDOR).o
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
+COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
+COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
+COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
--- /dev/null
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+ char name[] = CONFIG_SYS_BOARD_NAME;
+ char *s;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+ s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+ s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+ s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+ s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+ s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+ s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+ s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+ s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+ s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+ s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+ s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+ s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+ s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+ s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+ name[strlen(name) - 1] += get_board_derivative();
+ printf("Board: X-ES %s %s SBC\n", name, s);
+
+ /* Display board specific information */
+ puts(" ");
+ if ((s = getenv("board_rev")))
+ printf("Rev %s, ", s);
+ if ((s = getenv("serial#")))
+ printf("Serial# %s, ", s);
+ if ((s = getenv("board_cfg")))
+ printf("Cfg %s", s);
+ puts("\n");
+
+ return 0;
+}
if (in_be32(&gur->gpporcr) & 0x10000)
return 66666666;
else
+#ifdef CONFIG_P2020
+ return 100000000;
+#else
return 50000000;
+#endif
}
#ifdef CONFIG_MPC85xx
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
+#ifdef CONFIG_P2020
+ if (in_be32(&gur->gpporcr) & 0x20000)
+ return 66666666;
+ else
+ return 100000000;
+#else
return 66666666;
+#endif
}
#endif
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+ if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_NVM_WP)
+ return 1;
+
+ return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number. For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+ /*
+ * The top 4 lines of the local bus address are pulled low/high and
+ * can be read to determine the least significant digit of a board's
+ * model number.
+ */
+ return gur->gpporcr >> 28;
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
+
+uint get_board_derivative(void);
+
+#endif /* __FSL_8XXX_MISC_H__ */
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <libfdt.h>
#include <fdt_support.h>
-int first_free_busno = 0;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
static struct pci_controller pcie3_hose;
#endif
-#ifdef CONFIG_MPC8572
-/* Correlate host/agent POR bits to usable info. Table 4-14 */
-struct host_agent_cfg_t {
- uchar pcie_root[3];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{0, 0, 0}, 0},
- {{0, 1, 1}, 1},
- {{1, 0, 1}, 0},
- {{1, 1, 0}, 1},
- {{0, 0, 1}, 0},
- {{0, 1, 0}, 1},
- {{1, 0, 0}, 0},
- {{1, 1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-15 */
-struct io_port_cfg_t {
- uchar pcie_width[3];
- uchar rio_width;
-} io_port_cfg[16] = {
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{4, 0, 0}, 0},
- {{4, 4, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 4},
- {{4, 2, 2}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{0, 0, 0}, 0},
- {{4, 0, 0}, 4},
- {{4, 0, 0}, 4},
- {{0, 0, 0}, 4},
- {{0, 0, 0}, 4},
- {{8, 0, 0}, 0},
-};
-#elif defined CONFIG_MPC8548
-/* Correlate host/agent POR bits to usable info. Table 4-12 */
-struct host_agent_cfg_t {
- uchar pci_host[2];
- uchar pcie_root[1];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{1, 1}, {0}, 0},
- {{1, 1}, {1}, 0},
- {{1, 1}, {0}, 1},
- {{0, 0}, {0}, 0}, /* reserved */
- {{0, 1}, {1}, 0},
- {{1, 1}, {1}, 0},
- {{0, 1}, {1}, 1},
- {{1, 1}, {1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-13 */
-struct io_port_cfg_t {
- uchar pcie_width[1];
- uchar rio_width;
-} io_port_cfg[8] = {
- {{0}, 0},
- {{0}, 0},
- {{0}, 0},
- {{4}, 4},
- {{4}, 4},
- {{0}, 4},
- {{0}, 4},
- {{8}, 0},
-};
-#elif defined CONFIG_MPC86xx
-/* Correlate host/agent POR bits to usable info. Table 4-17 */
-struct host_agent_cfg_t {
- uchar pcie_root[2];
- uchar rio_host;
-} host_agent_cfg[8] = {
- {{0, 0}, 0},
- {{1, 0}, 1},
- {{0, 1}, 0},
- {{1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-16 */
-struct io_port_cfg_t {
- uchar pcie_width[2];
- uchar rio_width;
-} io_port_cfg[16] = {
- {{0, 0}, 0},
- {{0, 0}, 0},
- {{8, 0}, 0},
- {{8, 8}, 0},
- {{0, 0}, 0},
- {{8, 0}, 4},
- {{8, 0}, 4},
- {{8, 0}, 4},
- {{0, 0}, 0},
- {{0, 0}, 4},
- {{0, 0}, 4},
- {{0, 0}, 4},
- {{0, 0}, 0},
- {{0, 0}, 0},
- {{0, 8}, 0},
- {{8, 8}, 0},
-};
-#endif
-
/*
* 85xx and 86xx share naming conventions, but different layout.
* Correlate names to CPU-specific values to share common
void pci_init_board(void)
{
- struct pci_controller *hose;
- volatile ccsr_fsl_pci_t *pci;
- int width;
- int host;
+ struct fsl_pci_info pci_info[3];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
+
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
- uint devdisr = in_be32(&gur->devdisr);
- uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
- uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
- MPC8xxx_PORBMSR_HA_SHIFT;
- struct pci_region *r;
#ifdef CONFIG_PCI1
uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
- width = 0; /* Silence compiler warning... */
- io_sel &= 0xf; /* Silence compiler warning... */
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- hose = &pci1_hose;
- host = host_agent_cfg[host_agent].pci_host[0];
- r = hose->regions;
-
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
pci_32 ? 32 : 64,
pcix ? "PCIX" : "PCI",
pci_spd_norm ? ">=" : "<=",
pcix ? freq * 2 : freq,
- host ? "host" : "agent",
+ pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCI1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
- printf(" PCI1: disabled\n");
+ printf("PCI1: disabled\n");
}
#elif defined CONFIG_MPC8548
/* PCI1 not present on MPC8572 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
-#ifdef CONFIG_PCIE1
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
- host = host_agent_cfg[host_agent].pcie_root[0];
- width = io_port_cfg[io_sel].pcie_width[0];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
- printf("\n PCIE1 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+#ifdef CONFIG_PCIE1
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf("PCIE1: connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf("PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- hose = &pcie2_hose;
- host = host_agent_cfg[host_agent].pcie_root[1];
- width = io_port_cfg[io_sel].pcie_width[1];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
- printf("\n PCIE2 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf("PCIE2: connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+ } else {
+ printf("PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
#endif /* CONFIG_PCIE2 */
#ifdef CONFIG_PCIE3
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- hose = &pcie3_hose;
- host = host_agent_cfg[host_agent].pcie_root[2];
- width = io_port_cfg[io_sel].pcie_width[2];
- r = hose->regions;
-
- if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
- printf("\n PCIE3 connected as %s (x%d)",
- host ? "Root Complex" : "Endpoint", width);
- if (in_be32(&pci->pme_msg_det)) {
- out_be32(&pci->pme_msg_det, 0xffffffff);
- debug(" with errors. Clearing. Now 0x%08x",
- in_be32(&pci->pme_msg_det));
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BASE,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BASE,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- /* Unlock inbound PCI configuration cycles */
- if (!host)
- fsl_pci_config_unlock(hose);
-
- first_free_busno = hose->last_busno + 1;
- printf(" PCIE3 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+ printf("PCIE3: connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
+ } else {
+ printf("PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
# XES XPedite1000 PPC440GX
#
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
+++ /dev/null
-#
-# Copyright 2009 Extreme Engineering Solutions, Inc.
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# XPedite5170
-#
-TEXT_BASE = 0xfff00000
+++ /dev/null
-/*
- * Copyright 2006, 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
#include <asm/io.h>
#include <fdt_support.h>
#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
#endif
-int checkboard(void)
-{
- char *s;
-
- printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- return 0;
-}
/*
* Print out which flash was booted from and if booting from the 2nd flash,
* swap flash chip selects to maintain consistent flash numbering/addresses.
+++ /dev/null
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2004, 2007 Freescale Semiconductor.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# xpedite5200 board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
-int checkboard(void)
-{
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- char *s;
-
- printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
- out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
- out_be32(&ecm->eedr, 0xffffffff); /* Clear ecm errors */
- out_be32(&ecm->eeer, 0xffffffff); /* Enable ecm errors */
-
- return 0;
-}
-
static void flash_cs_fixup(void)
{
int flash_sel;
+++ /dev/null
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# xpedite5370 board
-#
-ifndef TEXT_BASE
-TEXT_BASE = 0xfff80000
-endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
-int checkboard(void)
-{
- char *s;
-
- printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
- printf(" ");
- s = getenv("board_rev");
- if (s)
- printf("Rev %s, ", s);
- s = getenv("serial#");
- if (s)
- printf("Serial# %s, ", s);
- s = getenv("board_cfg");
- if (s)
- printf("Cfg %s", s);
- printf("\n");
-
- return 0;
-}
-
static void flash_cs_fixup(void)
{
int flash_sel;
--- /dev/null
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr3_spd_eeprom_t));
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+/*
+ * There are traditionally three board-specific SDRAM timing parameters
+ * which must be calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 3.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ * The P2020 processor provides an autoleveling option. Setting CPO to
+ * 0x1f enables this auto configuration.
+ */
+
+typedef struct {
+ unsigned short datarate_mhz_low;
+ unsigned short datarate_mhz_high;
+ unsigned char clk_adjust;
+ unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR3-600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ {
+ /* DDR3-800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ ulong ddr_freq;
+
+ /*
+ * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ }
+ }
+ }
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->twoT_en = 0;
+ }
+ pbsp++;
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+
+ /*
+ * Enable on-die termination.
+ * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+ * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
+ * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
+ */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 3;
+}
--- /dev/null
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
#
-TEXT_BASE = 0x29000000
+CONFIG_SYS_TEXT_BASE = 0x29000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
#include <common.h>
#include <config.h>
+#include <netdev.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
-void do_reset (void)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_GPIO_0
*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
puts ("Reseting board\n");
asm ("bra r0");
#endif
+ return 0;
}
int gpio_init (void)
return 0;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ /*
+ * This board either has PCI NICs or uses the CPU's TSECs
+ * pci_eth_init() will return 0 if no NICs found, so in that case
+ * returning -1 will force cpu_eth_init() to be called.
+ */
+#ifdef CONFIG_XILINX_EMACLITE
+ return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR);
+#endif
+}
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
-# Work supported by Qtechnology http://www.qtec.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-
-sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
CFLAGS += $(INCS)
HOSTCFLAGS += $(INCS)
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
-# Work supported by Qtechnology http://www.qtec.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
CFLAGS += $(INCS)
HOSTCFLAGS += $(INCS)
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
+all: $(LIB) $(SOBJS)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $^)
clean:
rm -f $(SOBJS) $(OBJS)
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
-# Work supported by Qtechnology http://www.qtec.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+# need to strip off double quotes
+ifneq ($(CONFIG_SYS_LDSCRIPT),)
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+endif
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start_440)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start_440)
-
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
- _end = . ;
- PROVIDE (end = .);
-}
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := xm250.o flash.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys XM250 board:
-#
-
-
-# This is the address where U-Boot lives in flash:
-#TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-TEXT_BASE = 0xA3F80000
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-/*
- .macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
- ldr r7, =0
- str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
- ldr r7, =\val
- str r7, [r6]
- .endm
-*/
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
- /* SET_LED 1 */
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- * Initlialize Memory Controller
- *
- * See PXA250 Operating System Developer's Guide
- *
- * pause for 200 uSecs- allow internal clocks to settle
- * *Note: only need this if hard reset... doing it anyway for now
- */
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* SET_LED 2 */
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CONFIG_SYS_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CONFIG_SYS_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CONFIG_SYS_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CONFIG_SYS_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CONFIG_SYS_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CONFIG_SYS_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CONFIG_SYS_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CONFIG_SYS_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CONFIG_SYS_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CONFIG_SYS_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CONFIG_SYS_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r4, =CONFIG_SYS_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for FLASH clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank DRAM 0
- @
- orr r4, r4, #0x00010000
-
- @ set K2RUN for bank PLD
- @
- orr r4, r4, #0x00040000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End lowlevel_init
board_init (void)
/**********************************************************/
{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
/* arch number of MicroSys XM250 */
gd->bd->bi_arch_number = MACH_TYPE_XM250;
return 0;
}
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
- return (0);
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
+++ /dev/null
-TEXT_BASE = 0xA3F80000
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define SWAP(x) __swab32(x)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Functions */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors */
- flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
- flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
- break;
- case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case AMD_MANUFACT:
- debug ("Manufacturer: AMD\n");
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- debug ("Manufacturer: FUJITSU\n");
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- debug ("Manufacturer: *** unknown ***\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
-
- case AMD_ID_MIRROR:
- debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
- addr[14], addr[15]);
- switch(addr[14]) {
- case AMD_ID_LV640U_2:
- if (addr[15] != AMD_ID_LV640U_3) {
- debug ("Chip: AMLV640U -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- } else {
- debug ("Chip: AMLV640U\n");
- info->flash_id += FLASH_AMLV640U;
- info->sector_count = 128;
- info->size = 0x01000000;
- }
- break; /* => 16 MB */
- case AMD_ID_GL064MT_2:
- if (addr[15] != AMD_ID_GL064MT_3) {
- debug ("Chip: S29GL064M-R3 -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- } else {
- debug ("Chip: S29GL064M-R3\n");
- info->flash_id += FLASH_S29GL064M;
- info->sector_count = 128;
- info->size = 0x01000000;
- }
- break; /* => 16 MB */
- default:
- debug ("Chip: *** unknown ***\n");
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- switch (value) {
- case AMD_ID_MIRROR:
- switch (info->flash_id & FLASH_TYPEMASK) {
- /* only known types here - no default */
- case FLASH_AMLV128U:
- case FLASH_AMLV640U:
- case FLASH_AMLV320U:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x20000;
- }
- break;
- case FLASH_AMLV320B:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- /*
- * The first 8 sectors are 8 kB,
- * all the other ones are 64 kB
- */
- base += (i < 8)
- ? 2 * ( 8 << 10)
- : 2 * (64 << 10);
- }
- break;
- }
- break;
-
- default:
- return (0);
- break;
- }
-
-#if 0
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-#endif
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 100000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, SWAP(data))) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, SWAP(data))) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, SWAP(data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* ---- GPIO INITIALISATION ---- */
-/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
-
- /* General purpose set registers */
- ldr r0, =GPSR0
- ldr r1, =CONFIG_SYS_GPSR0_VAL
- str r1, [r0]
- ldr r0, =GPSR1
- ldr r1, =CONFIG_SYS_GPSR1_VAL
- str r1, [r0]
- ldr r0, =GPSR2
- ldr r1, =CONFIG_SYS_GPSR2_VAL
- str r1, [r0]
-
- /* General purpose clear registers */
- ldr r0, =GPCR0
- ldr r1, =CONFIG_SYS_GPCR0_VAL
- str r1, [r0]
- ldr r0, =GPCR1
- ldr r1, =CONFIG_SYS_GPCR1_VAL
- str r1, [r0]
- ldr r0, =GPCR2
- ldr r1, =CONFIG_SYS_GPCR2_VAL
- str r1, [r0]
-
- /* General rising edge registers */
- ldr r0, =GRER0
- ldr r1, =CONFIG_SYS_GRER0_VAL
- str r1, [r0]
- ldr r0, =GRER1
- ldr r1, =CONFIG_SYS_GRER1_VAL
- str r1, [r0]
- ldr r0, =GRER2
- ldr r1, =CONFIG_SYS_GRER2_VAL
- str r1, [r0]
-
- /* General falling edge registers */
- ldr r0, =GFER0
- ldr r1, =CONFIG_SYS_GFER0_VAL
- str r1, [r0]
- ldr r0, =GFER1
- ldr r1, =CONFIG_SYS_GFER1_VAL
- str r1, [r0]
- ldr r0, =GFER2
- ldr r1, =CONFIG_SYS_GFER2_VAL
- str r1, [r0]
-
- /* General edge detect registers */
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- /* General alternate function registers */
- ldr r0, =GAFR0_L /* [0:15] */
- ldr r1, =CONFIG_SYS_GAFR0_L_VAL
- str r1, [r0]
- ldr r0, =GAFR0_U /* [31:16] */
- ldr r1, =CONFIG_SYS_GAFR0_U_VAL
- str r1, [r0]
- ldr r0, =GAFR1_L /* [47:32] */
- ldr r1, =CONFIG_SYS_GAFR1_L_VAL
- str r1, [r0]
- ldr r0, =GAFR1_U /* [63:48] */
- ldr r1, =CONFIG_SYS_GAFR1_U_VAL
- str r1, [r0]
- ldr r0, =GAFR2_L /* [79:64] */
- ldr r1, =CONFIG_SYS_GAFR2_L_VAL
- str r1, [r0]
- ldr r0, =GAFR2_U /* [80] */
- ldr r1, =CONFIG_SYS_GAFR2_U_VAL
- str r1, [r0]
-
- /* General purpose direction registers */
- ldr r0, =GPDR0
- ldr r1, =CONFIG_SYS_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CONFIG_SYS_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CONFIG_SYS_GPDR2_VAL
- str r1, [r0]
-
- /* Power manager sleep status */
- ldr r0, =PSSR
- ldr r1, =CONFIG_SYS_PSSR_VAL
- str r1, [r0]
-
-/* ---- MEMORY INITIALISATION ---- */
-/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
-/* pause for 200 uSecs- allow internal clocks to settle */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-/* get memory controller base address */
- ldr r1, =MEMC_BASE
-
-/* ---- FLASH INITIALISATION ---- */
-/* Write MSC0 and read back to ensure data change is accepted by cpu */
- ldr r2, =CONFIG_SYS_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
-/* ---- SDRAM INITIALISATION ---- */
-/* get the MDREFR settings */
- ldr r2, =CONFIG_SYS_MDREFR_VAL
- str r2, [r1, #MDREFR_OFFSET]
-
-/* fetch platform value of MDCNFG */
- ldr r2, =CONFIG_SYS_MDCNFG_VAL
-
-/* disable all sdram banks */
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
-/* write initial value of MDCNFG, w/o enabling sdram banks */
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* pause for 200 uSecs */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* about 200 usec */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-/* Access memory *not yet enabled* for CBR refresh cycles (8) */
-/* CBR is generated for all banks */
-
- ldr r2, =CONFIG_SYS_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
-/* get memory controller base address */
- ldr r2, =MEMC_BASE
-
-/* Enable SDRAM bank 0 in MDCNFG register */
- ldr r2, [r1, #MDCNFG_OFFSET]
- orr r2, r2, #MDCNFG_DE0
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
- ldr r2, =CONFIG_SYS_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-/* ---- INTERRUPT INITIALISATION ---- */
-/* Disable (mask) all interrupts at the interrupt controller */
-/* clear the interrupt level register (use IRQ, not FIQ) */
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
-/* Set interrupt mask register */
- ldr r1, =CONFIG_SYS_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
-/* ---- CLOCK INITIALISATION ---- */
-/* Disable the peripheral clocks, and set the core clock */
-
-/* Turn Off ALL on-chip peripheral clocks for re-configuration */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-/* set core clocks */
- ldr r2, =CONFIG_SYS_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
-/* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
-/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
-/* Turn on needed clocks */
- ldr r1, =CKEN
- ldr r2, =CONFIG_SYS_CKEN_VAL
- str r2, [r1]
-
- mov pc, r10
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o update.o
SOBJS =
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0xFFFC0000
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
static u32 start_time;
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := zipitz2.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
+++ /dev/null
-TEXT_BASE = 0xa1000000
+++ /dev/null
-/*
- * Aeronix Zipit Z2 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
-
- mov pc, lr
#include <serial.h>
#include <asm/arch/hardware.h>
#include <spi.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
- /* arch number of Lubbock-Board */
+ /* arch number of Z2 */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
/* adress of boot parameters */
return 0;
}
-int board_late_init(void)
+struct serial_device *default_serial_console (void)
{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
+ return &serial_stuart_device;
}
-struct serial_device *default_serial_console (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- return &serial_stuart_device;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_SPI
{
/* GPIO 13 */
if (set)
- GPSR0 = (1 << 13);
+ writel((1 << 13), GPSR0);
else
- GPCR0 = (1 << 13);
+ writel((1 << 13), GPCR0);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
- GPCR0 = (1 << 22);
+ writel((1 << 22), GPCR0);
else
- GPSR0 = (1 << 22);
+ writel((1 << 22), GPSR0);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
- return !!(GPLR1 & (1 << 8));
+ return !!(readl(GPLR1) & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
- GPCR2 = (1 << 24);
+ writel((1 << 24), GPCR2);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
- GPSR2 = (1 << 24);
+ writel((1 << 24), GPSR2);
}
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
- GAFR0_L |= 0x00800000;
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
/* Enable clock to all PWM */
- CKEN |= 0x3;
+ writel(readl(CKEN) | 0x3, CKEN);
/* Configure PWM2 */
- PWM_CTRL2 = 0x4f;
- PWM_PWDUTY2 = 0x2ff;
- PWM_PERVAL2 = 792;
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
/* Toggle the reset pin to reset the LCD */
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(100000);
- GPCR0 = (1 << 19);
+ writel((1 << 19), GPCR0);
udelay(20000);
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(20000);
/* Program the LCD init sequence */
udelay(lcd_data[i].mdelay * 1000);
}
- GPSR0 = (1 << 11);
+ writel((1 << 11), GPSR0);
}
#endif
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(SOBJS) $(OBJS)
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# ZPC.1900 board
-#
-
-TEXT_BASE = 0xFE000000
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := zylonite.o nand.o
SOBJS := lowlevel_init.o
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
-#TEXT_BASE = 0x0
-#TEXT_BASE = 0xa1700000
-#TEXT_BASE = 0xa3080000
-TEXT_BASE = 0xa3008000
+#CONFIG_SYS_TEXT_BASE = 0x0
+#CONFIG_SYS_TEXT_BASE = 0xa1700000
+#CONFIG_SYS_TEXT_BASE = 0xa3080000
+CONFIG_SYS_TEXT_BASE = 0xa3008000
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xFFF, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1, GPIO4);
+
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
+
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */
#
# Syntax:
# white-space separated list of entries;
-# each entry has the following fields:
-#
-# Targetname Architecture CPU Boardname Vendor SoC
+# each entry has the fields documented below.
#
# Unused fields can be specified as "-", or omitted if they
# are the last field on the line.
# Lines starting with '#' are comments.
# Blank lines are ignored.
#
+# The options field takes the form:
+# <board config name>[:comma separated config options]
+# Each config option has the form (value defaults to "1"):
+# option[=value]
+# So if you have:
+# FOO:HAS_BAR,BAZ=64
+# The file include/configs/FOO.h will be used, and these defines created:
+# #define CONFIG_HAS_BAR 1
+# #define CONFIG_BAZ 64
+#
+# The list should be ordered according to the following fields,
+# from most to least significant:
+#
+# ARCH, CPU, SoC, Vendor, Target
+#
# To keep the list sorted, use something like
+# :.,$! sort -bdf -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
#
-# :.,$! sort -f -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
+# To reformat the list, use something like
+# :.,$! column -t
#
-# Target ARCH CPU Board name Vendor SoC
-###########################################################################
+# Target ARCH CPU Board name Vendor SoC Options
+###########################################################################################################
-qong arm arm1136 - davedenx mx31
-mx31ads arm arm1136 - freescale mx31
-ep7312 arm arm720t
-impa7 arm arm720t
-SMN42 arm arm720t - siemens lpc2292
-evb4510 arm arm720t - - s3c4510b
-a320evb arm arm920t - faraday a320
-cmc_pu2 arm arm920t - - at91rm9200
-csb637 arm arm920t - - at91rm9200
-kb9202 arm arm920t - - at91rm9200
-m501sk arm arm920t - - at91rm9200
-mp2usb arm arm920t - - at91rm9200
-mx1ads arm arm920t - - imx
-mx1fs2 arm arm920t - - imx
-scb9328 arm arm920t - - imx
-cm4008 arm arm920t - - ks8695
-cm41xx arm arm920t - - ks8695
-VCMA9 arm arm920t vcma9 mpl s3c24x0
-netstar arm arm925t
-meesc arm arm926ejs - esd at91
-otc570 arm arm926ejs - esd at91
-pm9261 arm arm926ejs - ronetix at91
-pm9263 arm arm926ejs - ronetix at91
-jadecpu arm arm926ejs jadecpu syteco mb86r0x
-suen3 arm arm926ejs km_arm keymile kirkwood
-rd6281a arm arm926ejs - Marvell kirkwood
-mx51evk arm armv7 mx51evk freescale mx51
-actux1 arm ixp
-actux2 arm ixp
-actux3 arm ixp
-actux4 arm ixp
-ixdp425 arm ixp
-cerf250 arm pxa
-colibri_pxa270 arm pxa
-cradle arm pxa
-csb226 arm pxa
-delta arm pxa
-innokom arm pxa
-logodl arm pxa
-lubbock arm pxa
-pleb2 arm pxa
-xaeniax arm pxa
-xm250 arm pxa
-zipitz2 arm pxa
-B2 arm s3c44b0 - dave
-assabet arm sa1100
-dnp1110 arm sa1100
-gcplus arm sa1100
-lart arm sa1100
-shannon arm sa1100
-mimc200 avr32 at32ap - mimc at32ap700x
-eNET i386 i386 - - sc520
-idmr m68k mcf52x2
-TASREG m68k mcf52x2 tasreg esd
-M5272C3 m68k mcf52x2 m5272c3 freescale
-EP2500 m68k mcf52x2 ep2500 Mercury
-purple mips mips
-tb0229 mips mips
-PCI5441 nios2 nios2 pci5441 psyent
-PK1C20 nios2 nios2 pk1c20 psyent
-P3G4 powerpc 74xx_7xx evb64260
-ppmc7xx powerpc 74xx_7xx
-ZUMA powerpc 74xx_7xx evb64260
-BAB7xx powerpc 74xx_7xx bab7xx eltec
-ELPPC powerpc 74xx_7xx elppc eltec
-CPCI750 powerpc 74xx_7xx cpci750 esd
-DB64360 powerpc 74xx_7xx db64360 Marvell
-DB64460 powerpc 74xx_7xx db64460 Marvell
-aria powerpc mpc512x - davedenx
-PATI powerpc mpc5xx pati mpl
-BC3450 powerpc mpc5xxx bc3450
-canmb powerpc mpc5xxx
-cm5200 powerpc mpc5xxx
-hmi1001 powerpc mpc5xxx - manroland
-inka4x0 powerpc mpc5xxx
-ipek01 powerpc mpc5xxx
-jupiter powerpc mpc5xxx
-mucmc52 powerpc mpc5xxx - manroland
-munices powerpc mpc5xxx
-o2dnt powerpc mpc5xxx
-uc101 powerpc mpc5xxx - manroland
-v38b powerpc mpc5xxx
-pf5200 powerpc mpc5xxx - esd
-aev powerpc mpc5xxx tqm5200 tqc
-sorcery powerpc mpc8220
-A3000 powerpc mpc824x a3000
-barco powerpc mpc824x
-BMW powerpc mpc824x bmw
-CU824 powerpc mpc824x cu824
-MOUSSE powerpc mpc824x mousse
-MUSENKI powerpc mpc824x musenki
-MVBLUE powerpc mpc824x mvblue
-OXC powerpc mpc824x oxc
-PN62 powerpc mpc824x pn62
-sbc8240 powerpc mpc824x
-utx8245 powerpc mpc824x
-debris powerpc mpc824x - etin
-kvme080 powerpc mpc824x - etin
-atc powerpc mpc8260
-ep8260 powerpc mpc8260
-ep82xxm powerpc mpc8260
-gw8260 powerpc mpc8260
-hymod powerpc mpc8260
-IDS8247 powerpc mpc8260 ids8247
-sacsng powerpc mpc8260
-sbc8260 powerpc mpc8260
-ZPC1900 powerpc mpc8260 zpc1900
-mgcoge powerpc mpc8260 - keymile
-SCM powerpc mpc8260 - siemens
-TQM8272 powerpc mpc8260 tqm8272 tqc
-ve8313 powerpc mpc83xx ve8313
-kmeter1 powerpc mpc83xx kmeter1 keymile
-MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
-TQM834x powerpc mpc83xx tqm834x tqc
-PM854 powerpc mpc85xx pm854
-PM856 powerpc mpc85xx pm856
-stxgp3 powerpc mpc85xx stxgp3 stx
-c2mon powerpc mpc8xx
-EP88x powerpc mpc8xx ep88x
-ETX094 powerpc mpc8xx etx094
-FLAGADM powerpc mpc8xx flagadm
-GENIETV powerpc mpc8xx genietv
-hermes powerpc mpc8xx
-IP860 powerpc mpc8xx ip860
-LANTEC powerpc mpc8xx lantec
-lwmon powerpc mpc8xx
-NX823 powerpc mpc8xx nx823
-quantum powerpc mpc8xx
-R360MPI powerpc mpc8xx r360mpi
-RBC823 powerpc mpc8xx rbc823
-rmu powerpc mpc8xx
-RPXlite powerpc mpc8xx
-spc1920 powerpc mpc8xx
-uc100 powerpc mpc8xx - manroland
-MHPC powerpc mpc8xx mhpc eltec
-TOP860 powerpc mpc8xx top860 emk
-kmsupx4 powerpc mpc8xx km8xx keymile
-mgsuvd powerpc mpc8xx km8xx keymile
-KUP4K powerpc mpc8xx kup4k kup
-KUP4X powerpc mpc8xx kup4x kup
-ELPT860 powerpc mpc8xx elpt860 LEOX
-CCM powerpc mpc8xx - siemens
-IAD210 powerpc mpc8xx - siemens
-pcu_e powerpc mpc8xx - siemens
-QS823 powerpc mpc8xx qs850 snmc
-QS850 powerpc mpc8xx qs850 snmc
-QS860T powerpc mpc8xx qs860t snmc
-stxxtc powerpc mpc8xx stxxtc stx
-SM850 powerpc mpc8xx tqm8xx tqc
-AMX860 powerpc mpc8xx amx860 westel
-csb272 powerpc ppc4xx
-csb472 powerpc ppc4xx
-ERIC powerpc ppc4xx eric
-G2000 powerpc ppc4xx g2000
-JSE powerpc ppc4xx jse
-korat powerpc ppc4xx
-lwmon5 powerpc ppc4xx
-ML2 powerpc ppc4xx ml2
-sbc405 powerpc ppc4xx
-sc3 powerpc ppc4xx
-t3corp powerpc ppc4xx
-zeus powerpc ppc4xx
-acadia powerpc ppc4xx - amcc
-bamboo powerpc ppc4xx - amcc
-bubinga powerpc ppc4xx - amcc
-ebony powerpc ppc4xx - amcc
-katmai powerpc ppc4xx - amcc
-luan powerpc ppc4xx - amcc
-makalu powerpc ppc4xx - amcc
-ocotea powerpc ppc4xx - amcc
-redwood powerpc ppc4xx - amcc
-taihu powerpc ppc4xx - amcc
-taishan powerpc ppc4xx - amcc
-yucca powerpc ppc4xx - amcc
-AP1000 powerpc ppc4xx ap1000 amirix
-CRAYL1 powerpc ppc4xx L1 cray
-ADCIOP powerpc ppc4xx adciop esd
-APC405 powerpc ppc4xx apc405 esd
-AR405 powerpc ppc4xx ar405 esd
-ASH405 powerpc ppc4xx ash405 esd
-CANBT powerpc ppc4xx canbt esd
-CMS700 powerpc ppc4xx cms700 esd
-CPCI2DP powerpc ppc4xx cpci2dp esd
-DP405 powerpc ppc4xx dp405 esd
-DU405 powerpc ppc4xx du405 esd
-DU440 powerpc ppc4xx du440 esd
-HH405 powerpc ppc4xx hh405 esd
-HUB405 powerpc ppc4xx hub405 esd
-PCI405 powerpc ppc4xx pci405 esd
-PLU405 powerpc ppc4xx plu405 esd
-PMC405 powerpc ppc4xx pmc405 esd
-PMC440 powerpc ppc4xx pmc440 esd
-VOH405 powerpc ppc4xx voh405 esd
-VOM405 powerpc ppc4xx vom405 esd
-WUH405 powerpc ppc4xx wuh405 esd
-neo powerpc ppc4xx - gdsys
-icon powerpc ppc4xx - mosaixtech
-MIP405 powerpc ppc4xx mip405 mpl
-PIP405 powerpc ppc4xx pip405 mpl
-alpr powerpc ppc4xx - prodrive
-p3p440 powerpc ppc4xx - prodrive
-KAREF powerpc ppc4xx karef sandburst
-grsim sparc leon3 - gaisler
-imx31_litekit arm arm1136 - logicpd mx31
-omap2420h4 arm arm1136 - ti omap24xx
-tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
-armadillo arm arm720t
-modnet50 arm arm720t
-lpc2292sodimm arm arm720t - - lpc2292
-eb_cpux9k2 arm arm920t - BuS at91
-at91rm9200dk arm arm920t - atmel at91rm9200
-at91rm9200ek arm arm920t - atmel at91rm9200
-sbc2410x arm arm920t - - s3c24x0
-smdk2400 arm arm920t - samsung s3c24x0
-smdk2410 arm arm920t - samsung s3c24x0
-voiceblue arm arm925t
-omap1510inn arm arm925t - ti
-afeb9260 arm arm926ejs - - at91
-at91cap9adk arm arm926ejs - atmel at91
-davinci_dvevm arm arm926ejs dvevm davinci davinci
-davinci_sffsdr arm arm926ejs sffsdr davinci davinci
-davinci_sonata arm arm926ejs sonata davinci davinci
-da830evm arm arm926ejs da8xxevm davinci davinci
-da850evm arm arm926ejs da8xxevm davinci davinci
-guruplug arm arm926ejs - Marvell kirkwood
-mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
-openrd_base arm arm926ejs - Marvell kirkwood
-sheevaplug arm arm926ejs - Marvell kirkwood
-imx27lite arm arm926ejs imx27lite logicpd mx27
-magnesium arm arm926ejs imx27lite logicpd mx27
-omap5912osk arm arm926ejs - ti omap
-edminiv2 arm arm926ejs - LaCie orion5x
-omap3_overo arm armv7 overo - omap3
-omap3_pandora arm armv7 pandora - omap3
-omap3_zoom1 arm armv7 zoom1 logicpd omap3
-omap3_zoom2 arm armv7 zoom2 logicpd omap3
-omap3_beagle arm armv7 beagle ti omap3
-omap3_evm arm armv7 evm ti omap3
-omap3_sdp3430 arm armv7 sdp3430 ti omap3
-omap4_panda arm armv7 panda ti omap4
-omap4_sdp4430 arm armv7 sdp4430 ti omap4
-am3517_evm arm armv7 am3517evm logicpd omap3
-devkit8000 arm armv7 devkit8000 timll omap3
-s5p_goni arm armv7 goni samsung s5pc1xx
-smdkc100 arm armv7 smdkc100 samsung s5pc1xx
-s5pc110_universal arm armv7 universal_c110 samsung s5pc1xx
-s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
-ixdpg425 arm ixp
-lpd7a400 arm lh7a40x lpd7a40x
-lpd7a404 arm lh7a40x lpd7a40x
-pxa255_idp arm pxa
-wepep250 arm pxa
-xsengine arm pxa
-zylonite arm pxa
-atngw100 avr32 at32ap - atmel at32ap700x
-atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
-favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
-hammerhead avr32 at32ap - miromico at32ap700x
-bf518f-ezbrd blackfin blackfin
-bf526-ezbrd blackfin blackfin
-bf527-ad7160-eval blackfin blackfin
-bf527-ezkit blackfin blackfin
-bf533-ezkit blackfin blackfin
-bf533-stamp blackfin blackfin
-bf537-minotaur blackfin blackfin
-bf537-pnav blackfin blackfin
-bf537-srv1 blackfin blackfin
-bf537-stamp blackfin blackfin
-bf538f-ezkit blackfin blackfin
-bf548-ezkit blackfin blackfin
-bf561-acvilon blackfin blackfin
-bf561-ezkit blackfin blackfin
-blackstamp blackfin blackfin
-cm-bf527 blackfin blackfin
-cm-bf533 blackfin blackfin
-cm-bf537e blackfin blackfin
-cm-bf537u blackfin blackfin
-cm-bf548 blackfin blackfin
-cm-bf561 blackfin blackfin
-ibf-dsp561 blackfin blackfin
-ip04 blackfin blackfin
-tcm-bf518 blackfin blackfin
-tcm-bf537 blackfin blackfin
-M5208EVBE m68k mcf52x2 m5208evbe freescale
-M5249EVB m68k mcf52x2 m5249evb freescale
-M5253DEMO m68k mcf52x2 m5253demo freescale
-M5253EVBE m68k mcf52x2 m5253evbe freescale
-M5271EVB m68k mcf52x2 m5271evb freescale
-M5275EVB m68k mcf52x2 m5275evb freescale
-M5282EVB m68k mcf52x2 m5282evb freescale
-M53017EVB m68k mcf52x2 m53017evb freescale
-microblaze-generic microblaze microblaze microblaze-generic xilinx
-mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale
-pdm360ng powerpc mpc512x
-mecp5123 powerpc mpc512x - esd
-cmi_mpc5xx powerpc mpc5xx cmi
-motionpro powerpc mpc5xxx
-cpci5200 powerpc mpc5xxx - esd
-mecp5200 powerpc mpc5xxx - esd
-Alaska8220 powerpc mpc8220 alaska
-Yukon8220 powerpc mpc8220 alaska
-HIDDEN_DRAGON powerpc mpc824x hidden_dragon
-IPHASE4539 powerpc mpc8260 iphase4539
-ppmc8260 powerpc mpc8260
-RPXsuper powerpc mpc8260 rpxsuper
-rsdproto powerpc mpc8260
-MPC8266ADS powerpc mpc8260 mpc8266ads freescale
-mpc8308_p1m powerpc mpc83xx
-MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
-MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
-MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
-MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
-ATUM8548 powerpc mpc85xx atum8548
-socrates powerpc mpc85xx socrates
-MPC8540ADS powerpc mpc85xx mpc8540ads freescale
-MPC8544DS powerpc mpc85xx mpc8544ds freescale
-MPC8560ADS powerpc mpc85xx mpc8560ads freescale
-MPC8568MDS powerpc mpc85xx mpc8568mds freescale
-P4080DS powerpc mpc85xx corenet_ds freescale
-XPEDITE5200 powerpc mpc85xx xpedite5200 xes
-XPEDITE5370 powerpc mpc85xx xpedite5370 xes
-P1022DS powerpc mpc85xx p1022ds freescale
-sbc8641d powerpc mpc86xx
-MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
-XPEDITE5170 powerpc mpc86xx xpedite5170 xes
-cogent_mpc8xx powerpc mpc8xx cogent
-ESTEEM192E powerpc mpc8xx esteem192e
-RPXClassic powerpc mpc8xx
-RRvision powerpc mpc8xx
-svm_sc8xx powerpc mpc8xx
-pcs440ep powerpc ppc4xx
-quad100hd powerpc ppc4xx
-dlvision powerpc ppc4xx - gdsys
-gdppc440etx powerpc ppc4xx - gdsys
-CPCIISER4 powerpc ppc4xx cpciiser4 esd
-DASA_SIM powerpc ppc4xx dasa_sim esd
-PMC405DE powerpc ppc4xx pmc405de esd
-METROBOX powerpc ppc4xx metrobox sandburst
-XPEDITE1000 powerpc ppc4xx xpedite1000 xes
-grsim_leon2 sparc leon2 - gaisler
-gr_cpci_ax2000 sparc leon3 - gaisler
-gr_ep2s60 sparc leon3 - gaisler
-gr_xc3s_1500 sparc leon3 - gaisler
-davinci_dm355evm arm arm926ejs dm355evm davinci davinci
-davinci_dm365evm arm arm926ejs dm365evm davinci davinci
-davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci
-davinci_schmoogie arm arm926ejs schmoogie davinci davinci
-davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
+qong arm arm1136 - davedenx mx31
+mx31ads arm arm1136 - freescale mx31
+imx31_litekit arm arm1136 - logicpd mx31
+omap2420h4 arm arm1136 - ti omap24xx
+tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
+armadillo arm arm720t
+ep7312 arm arm720t
+impa7 arm arm720t
+modnet50 arm arm720t
+lpc2292sodimm arm arm720t - - lpc2292
+SMN42 arm arm720t - siemens lpc2292
+evb4510 arm arm720t - - s3c4510b
+a320evb arm arm920t - faraday a320
+at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
+at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
+eb_cpux9k2 arm arm920t - BuS at91
+cmc_pu2 arm arm920t - - at91rm9200
+csb637 arm arm920t - - at91rm9200
+kb9202 arm arm920t - - at91rm9200
+m501sk arm arm920t - - at91rm9200
+mp2usb arm arm920t - - at91rm9200
+at91rm9200dk arm arm920t - atmel at91rm9200
+mx1ads arm arm920t - - imx
+mx1fs2 arm arm920t - - imx
+scb9328 arm arm920t - - imx
+cm4008 arm arm920t - - ks8695
+cm41xx arm arm920t - - ks8695
+sbc2410x arm arm920t - - s3c24x0
+VCMA9 arm arm920t vcma9 mpl s3c24x0
+smdk2400 arm arm920t - samsung s3c24x0
+smdk2410 arm arm920t - samsung s3c24x0
+netstar arm arm925t
+voiceblue arm arm925t
+omap1510inn arm arm925t - ti
+aspenite arm arm926ejs - Marvell armada100
+afeb9260 arm arm926ejs - - at91
+at91cap9adk arm arm926ejs - atmel at91
+top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
+top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000
+meesc arm arm926ejs - esd at91
+otc570 arm arm926ejs - esd at91
+pm9261 arm arm926ejs - ronetix at91
+pm9263 arm arm926ejs - ronetix at91
+da830evm arm arm926ejs da8xxevm davinci davinci
+da850evm arm arm926ejs da8xxevm davinci davinci
+hawkboard arm arm926ejs da8xxevm davinci davinci
+hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT
+hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT
+ea20 arm arm926ejs ea20 davinci davinci
+davinci_dm355evm arm arm926ejs dm355evm davinci davinci
+davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
+davinci_dm365evm arm arm926ejs dm365evm davinci davinci
+davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci
+davinci_dvevm arm arm926ejs dvevm davinci davinci
+davinci_schmoogie arm arm926ejs schmoogie davinci davinci
+davinci_sffsdr arm arm926ejs sffsdr davinci davinci
+davinci_sonata arm arm926ejs sonata davinci davinci
+suen3 arm arm926ejs km_arm keymile kirkwood
+guruplug arm arm926ejs - Marvell kirkwood
+mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
+openrd_base arm arm926ejs - Marvell kirkwood
+rd6281a arm arm926ejs - Marvell kirkwood
+sheevaplug arm arm926ejs - Marvell kirkwood
+dockstar arm arm926ejs - Seagate kirkwood
+jadecpu arm arm926ejs jadecpu syteco mb86r0x
+imx27lite arm arm926ejs imx27lite logicpd mx27
+magnesium arm arm926ejs imx27lite logicpd mx27
+omap5912osk arm arm926ejs - ti omap
+edminiv2 arm arm926ejs - LaCie orion5x
+ca9x4_ct_vxp arm armv7 vexpress armltd
+mx51evk arm armv7 mx51evk freescale mx5
+vision2 arm armv7 vision2 ttcontrol mx5
+omap3_overo arm armv7 overo - omap3
+omap3_pandora arm armv7 pandora - omap3
+igep0020 arm armv7 igep0020 isee omap3
+igep0030 arm armv7 igep0030 isee omap3
+am3517_evm arm armv7 am3517evm logicpd omap3
+omap3_zoom1 arm armv7 zoom1 logicpd omap3
+omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_beagle arm armv7 beagle ti omap3
+omap3_evm arm armv7 evm ti omap3
+omap3_sdp3430 arm armv7 sdp3430 ti omap3
+devkit8000 arm armv7 devkit8000 timll omap3
+omap4_panda arm armv7 panda ti omap4
+omap4_sdp4430 arm armv7 sdp4430 ti omap4
+s5p_goni arm armv7 goni samsung s5pc1xx
+smdkc100 arm armv7 smdkc100 samsung s5pc1xx
+s5pc110_universal arm armv7 universal_c110 samsung s5pc1xx
+s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
+actux1 arm ixp
+actux2 arm ixp
+actux3 arm ixp
+actux4 arm ixp
+ixdp425 arm ixp
+ixdpg425 arm ixp
+lpd7a400 arm lh7a40x lpd7a40x
+lpd7a404 arm lh7a40x lpd7a40x
+balloon3 arm pxa
+cerf250 arm pxa
+colibri_pxa270 arm pxa
+cradle arm pxa
+csb226 arm pxa
+innokom arm pxa
+lubbock arm pxa
+palmld arm pxa
+palmtc arm pxa
+pleb2 arm pxa
+polaris arm pxa trizepsiv - - trizepsiv:POLARIS
+pxa255_idp arm pxa
+trizepsiv arm pxa
+vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M
+vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M
+vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M
+xaeniax arm pxa
+xm250 arm pxa
+zipitz2 arm pxa
+zylonite arm pxa
+B2 arm s3c44b0 - dave
+assabet arm sa1100
+dnp1110 arm sa1100
+gcplus arm sa1100
+jornada arm sa1100
+lart arm sa1100
+shannon arm sa1100
+atngw100 avr32 at32ap - atmel at32ap700x
+atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
+atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
+atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
+atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
+favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
+mimc200 avr32 at32ap - mimc at32ap700x
+hammerhead avr32 at32ap - miromico at32ap700x
+bct-brettl2 blackfin blackfin
+bf518f-ezbrd blackfin blackfin
+bf526-ezbrd blackfin blackfin
+bf527-ad7160-eval blackfin blackfin
+bf527-ezkit blackfin blackfin
+bf527-ezkit-v2 blackfin blackfin bf527-ezkit - - bf527-ezkit:BF527_EZKIT_REV_2_1
+bf527-sdp blackfin blackfin
+bf533-ezkit blackfin blackfin
+bf533-stamp blackfin blackfin
+bf537-minotaur blackfin blackfin
+bf537-pnav blackfin blackfin
+bf537-srv1 blackfin blackfin
+bf537-stamp blackfin blackfin
+bf538f-ezkit blackfin blackfin
+bf548-ezkit blackfin blackfin
+bf561-acvilon blackfin blackfin
+bf561-ezkit blackfin blackfin
+blackstamp blackfin blackfin
+blackvme blackfin blackfin
+cm-bf527 blackfin blackfin
+cm-bf533 blackfin blackfin
+cm-bf537e blackfin blackfin
+cm-bf537u blackfin blackfin
+cm-bf548 blackfin blackfin
+cm-bf561 blackfin blackfin
+ibf-dsp561 blackfin blackfin
+ip04 blackfin blackfin
+tcm-bf518 blackfin blackfin
+tcm-bf537 blackfin blackfin
+eNET i386 i386 - - sc520
+idmr m68k mcf52x2
+TASREG m68k mcf52x2 tasreg esd
+M5208EVBE m68k mcf52x2 m5208evbe freescale
+M5249EVB m68k mcf52x2 m5249evb freescale
+M5253DEMO m68k mcf52x2 m5253demo freescale
+M5253EVBE m68k mcf52x2 m5253evbe freescale
+M5271EVB m68k mcf52x2 m5271evb freescale
+M5272C3 m68k mcf52x2 m5272c3 freescale
+M5275EVB m68k mcf52x2 m5275evb freescale
+M5282EVB m68k mcf52x2 m5282evb freescale
+M53017EVB m68k mcf52x2 m53017evb freescale
+EP2500 m68k mcf52x2 ep2500 Mercury
+microblaze-generic microblaze microblaze microblaze-generic xilinx
+purple mips mips
+tb0229 mips mips
+PCI5441 nios2 nios2 pci5441 psyent
+PK1C20 nios2 nios2 pk1c20 psyent
+EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
+EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260
+P3G4 powerpc 74xx_7xx evb64260
+PCIPPC2 powerpc 74xx_7xx pcippc2
+PCIPPC6 powerpc 74xx_7xx pcippc2
+ppmc7xx powerpc 74xx_7xx
+ZUMA powerpc 74xx_7xx evb64260
+BAB7xx powerpc 74xx_7xx bab7xx eltec
+ELPPC powerpc 74xx_7xx elppc eltec
+CPCI750 powerpc 74xx_7xx cpci750 esd
+mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale
+DB64360 powerpc 74xx_7xx db64360 Marvell
+DB64460 powerpc 74xx_7xx db64460 Marvell
+p3m7448 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M7448
+p3m750 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M750
+pdm360ng powerpc mpc512x
+aria powerpc mpc512x - davedenx
+mecp5123 powerpc mpc512x - esd
+mpc5121ads powerpc mpc512x mpc5121ads freescale
+mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
+cmi_mpc5xx powerpc mpc5xx cmi
+PATI powerpc mpc5xx pati mpl
+a4m072 powerpc mpc5xxx a4m072
+BC3450 powerpc mpc5xxx bc3450
+canmb powerpc mpc5xxx
+cm5200 powerpc mpc5xxx
+digsy_mtc powerpc mpc5xxx digsy_mtc
+digsy_mtc_LOWBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0xFF000000
+digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000
+galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
+galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
+icecube_5200 powerpc mpc5xxx icecube - - IceCube
+icecube_5200_DDR powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR
+icecube_5200_DDR_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR
+icecube_5200_DDR_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR
+icecube_5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000
+icecube_5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000
+inka4x0 powerpc mpc5xxx
+ipek01 powerpc mpc5xxx
+jupiter powerpc mpc5xxx
+Lite5200 powerpc mpc5xxx icecube - - IceCube
+lite5200b powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B
+lite5200b_LOWBOOT powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000
+lite5200b_PM powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM
+Lite5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000
+Lite5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000
+mcc200 powerpc mpc5xxx mcc200 - - mcc200
+mcc200_COM12 powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12
+mcc200_COM12_highboot powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000
+mcc200_COM12_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
+mcc200_COM12_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,MCC200_SDRAM
+mcc200_highboot powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000
+mcc200_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
+mcc200_SDRAM powerpc mpc5xxx mcc200 - - mcc200:MCC200_SDRAM
+motionpro powerpc mpc5xxx
+munices powerpc mpc5xxx
+o2dnt powerpc mpc5xxx
+PM520 powerpc mpc5xxx pm520
+PM520_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR
+PM520_ROMBOOT powerpc mpc5xxx pm520 - - PM520:BOOT_ROM
+PM520_ROMBOOT_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR,BOOT_ROM
+prs200 powerpc mpc5xxx mcc200 - - mcc200:PRS200,MCC200_SDRAM
+prs200_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200
+prs200_highboot powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
+prs200_highboot_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000
+Total5200 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1
+Total5200_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000
+Total5200_Rev2 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2
+Total5200_Rev2_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000
+v38b powerpc mpc5xxx
+EVAL5200 powerpc mpc5xxx top5200 emk - TOP5200:EVAL5200
+MINI5200 powerpc mpc5xxx top5200 emk - TOP5200:MINI5200
+TOP5200 powerpc mpc5xxx top5200 emk - TOP5200:TOP5200
+cpci5200 powerpc mpc5xxx - esd
+mecp5200 powerpc mpc5xxx - esd
+pf5200 powerpc mpc5xxx - esd
+hmi1001 powerpc mpc5xxx - manroland
+mucmc52 powerpc mpc5xxx - manroland
+uc101 powerpc mpc5xxx - manroland
+MVBC_P powerpc mpc5xxx mvbc_p matrix_vision - MVBC_P:MVBC_P
+MVSMR powerpc mpc5xxx mvsmr matrix_vision
+pcm030 powerpc mpc5xxx pcm030 phytec - pcm030
+pcm030_LOWBOOT powerpc mpc5xxx pcm030 phytec - pcm030:SYS_TEXT_BASE=0xFF000000
+aev powerpc mpc5xxx tqm5200 tqc
+cam5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B
+cam5200_niosflash powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH
+charon powerpc mpc5xxx tqm5200 tqc - charon
+fo300 powerpc mpc5xxx tqm5200 tqc - TQM5200:FO300
+MiniFAP powerpc mpc5xxx tqm5200 tqc - TQM5200:MINIFAP
+TB5200 powerpc mpc5xxx tqm5200 tqc
+TB5200_B powerpc mpc5xxx tqm5200 tqc - TB5200:TQM5200_B
+TQM5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:
+TQM5200_B powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B
+TQM5200_B_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000
+TQM5200S powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S
+TQM5200S_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000
+TQM5200_STK100 powerpc mpc5xxx tqm5200 tqc - TQM5200:STK52XX_REV100
+Alaska8220 powerpc mpc8220 alaska
+sorcery powerpc mpc8220
+Yukon8220 powerpc mpc8220 alaska
+A3000 powerpc mpc824x a3000
+BMW powerpc mpc824x bmw
+CPC45 powerpc mpc824x cpc45 - - CPC45
+CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM
+CU824 powerpc mpc824x cu824
+eXalion powerpc mpc824x eXalion
+HIDDEN_DRAGON powerpc mpc824x hidden_dragon
+linkstation_HGLAN powerpc mpc824x linkstation - - linkstation:HGLAN=1
+MOUSSE powerpc mpc824x mousse
+MUSENKI powerpc mpc824x musenki
+MVBLUE powerpc mpc824x mvblue
+OXC powerpc mpc824x oxc
+PN62 powerpc mpc824x pn62
+Sandpoint8240 powerpc mpc824x sandpoint
+Sandpoint8245 powerpc mpc824x sandpoint
+sbc8240 powerpc mpc824x
+utx8245 powerpc mpc824x
+debris powerpc mpc824x - etin
+kvme080 powerpc mpc824x - etin
+atc powerpc mpc8260
+cogent_mpc8260 powerpc mpc8260 cogent
+CPU86 powerpc mpc8260 cpu86 - - CPU86
+CPU86_ROMBOOT powerpc mpc8260 cpu86 - - CPU86:BOOT_ROM
+CPU87 powerpc mpc8260 cpu87 - - CPU87
+CPU87_ROMBOOT powerpc mpc8260 cpu87 - - CPU87:BOOT_ROM
+ep8248 powerpc mpc8260 ep8248
+ep8248E powerpc mpc8260 ep8248 - - ep8248
+ep8260 powerpc mpc8260
+ep82xxm powerpc mpc8260
+gw8260 powerpc mpc8260
+hymod powerpc mpc8260
+IDS8247 powerpc mpc8260 ids8247
+IPHASE4539 powerpc mpc8260 iphase4539
+ISPAN powerpc mpc8260 ispan
+ISPAN_REVB powerpc mpc8260 ispan - - ISPAN:SYS_REV_B
+muas3001 powerpc mpc8260 muas3001
+muas3001_dev powerpc mpc8260 muas3001 - - muas3001:MUAS_DEV_BOARD
+PM825 powerpc mpc8260 pm826 - - PM826:PCI,SYS_TEXT_BASE=0xFF000000
+PM825_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000
+PM825_ROMBOOT powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000
+PM825_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000
+PM826 powerpc mpc8260 pm826 - - PM826:SYS_TEXT_BASE=0xFF000000
+PM826_BIGFLASH powerpc mpc8260 pm826 - - PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000
+PM826_ROMBOOT powerpc mpc8260 pm826 - - PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000
+PM826_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000
+PM828 powerpc mpc8260 pm828 - - PM828
+PM828_PCI powerpc mpc8260 pm828 - - PM828:PCI
+PM828_ROMBOOT powerpc mpc8260 pm828 - - PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000
+PM828_ROMBOOT_PCI powerpc mpc8260 pm828 - - PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000
+ppmc8260 powerpc mpc8260
+Rattler powerpc mpc8260 rattler - - Rattler
+Rattler8248 powerpc mpc8260 rattler - - Rattler:MPC8248
+RPXsuper powerpc mpc8260 rpxsuper
+rsdproto powerpc mpc8260
+sacsng powerpc mpc8260
+sbc8260 powerpc mpc8260
+ZPC1900 powerpc mpc8260 zpc1900
+MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS
+MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000
+MPC8260ADS_33MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000
+MPC8260ADS_40MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000
+MPC8260ADS_40MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000
+MPC8260ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000
+MPC8266ADS powerpc mpc8260 mpc8266ads freescale
+MPC8272ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS
+MPC8272ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000
+PQ2FADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS
+PQ2FADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
+PQ2FADS-VR powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000
+PQ2FADS-VR_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000
+PQ2FADS-ZU powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS
+PQ2FADS-ZU_66MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000
+PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000
+PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
+VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz
+mgcoge powerpc mpc8260 - keymile
+SCM powerpc mpc8260 - siemens
+TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz
+TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz
+TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
+TQM8260_AC powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
+TQM8260_AD powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
+TQM8260_AE powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,266MHz
+TQM8260_AF powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
+TQM8260_AG powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz
+TQM8260_AH powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x
+TQM8260_AI powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
+TQM8265_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8265,300MHz,BUSMODE_60x
+TQM8272 powerpc mpc8260 tqm8272 tqc
+mpc8308_p1m powerpc mpc83xx
+sbc8349 powerpc mpc83xx sbc8349 - - sbc8349
+sbc8349_PCI_33 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_33M
+sbc8349_PCI_66 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_66M
+ve8313 powerpc mpc83xx ve8313
+caddy2 powerpc mpc83xx vme8349 esd - vme8349:CADDY2
+vme8349 powerpc mpc83xx vme8349 esd - vme8349
+MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
+MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ
+MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ
+MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND_U_BOOT
+MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND_U_BOOT
+MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB
+MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT
+MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
+MPC832XEMDS powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:
+MPC832XEMDS_ATM powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
+MPC832XEMDS_HOST_33 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1
+MPC832XEMDS_HOST_66 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1
+MPC832XEMDS_SLAVE powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCISLAVE
+MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
+MPC8349ITX powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX
+MPC8349ITXGP powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000
+MPC8349ITX_LOWBOOT powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000
+MPC8360EMDS powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:
+MPC8360EMDS_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
+MPC8360EMDS_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCI_33M,PQ_MDS_PIB=1
+MPC8360EMDS_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCI_66M,PQ_MDS_PIB=1
+MPC8360EMDS_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:PCI,PCISLAVE
+MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
+MPC8360ERDK_33 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK:CLKIN_33MHZ
+MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
+MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
+MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
+MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
+kmeter1 powerpc mpc83xx kmeter1 keymile
+MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
+SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
+SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
+TQM834x powerpc mpc83xx tqm834x tqc
+ATUM8548 powerpc mpc85xx atum8548
+MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
+MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL
+MPC8540EVAL_33_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:PCI_SLAVE
+MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
+MPC8540EVAL_66_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M,PCI_SLAVE
+PM854 powerpc mpc85xx pm854
+PM856 powerpc mpc85xx pm856
+sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
+sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
+sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
+sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
+sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
+sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
+sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66
+sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE
+sbc8560 powerpc mpc85xx sbc8560 - - sbc8560
+sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560
+sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560
+socrates powerpc mpc85xx socrates
+MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
+MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT
+MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND
+MPC8536DS_SDCARD powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SDCARD
+MPC8536DS_SPIFLASH powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SPIFLASH
+MPC8540ADS powerpc mpc85xx mpc8540ads freescale
+MPC8541CDS powerpc mpc85xx mpc8541cds freescale - MPC8541CDS
+MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY
+MPC8544DS powerpc mpc85xx mpc8544ds freescale
+MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS
+MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY
+MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS
+MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY
+MPC8560ADS powerpc mpc85xx mpc8560ads freescale
+MPC8568MDS powerpc mpc85xx mpc8568mds freescale
+MPC8569MDS powerpc mpc85xx mpc8569mds freescale - MPC8569MDS
+MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:ATM
+MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND
+MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
+MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
+P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011
+P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND
+P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD
+P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SPIFLASH
+P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB
+P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
+P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
+P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH
+P1022DS powerpc mpc85xx p1022ds freescale
+P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
+P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
+P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD
+P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SPIFLASH
+P2020DS powerpc mpc85xx p2020ds freescale
+P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
+P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
+P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020
+P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
+P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
+P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH
+P4080DS powerpc mpc85xx corenet_ds freescale
+stxgp3 powerpc mpc85xx stxgp3 stx
+stxssa powerpc mpc85xx stxssa stx - stxssa
+stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
+TQM8540 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540"
+TQM8541 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541"
+TQM8548 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548"
+TQM8548_AG powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_AG=y,HOSTNAME=tqm8485,BOARDNAME="TQM8548_AG"
+TQM8548_BE powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8548,TQM8548_BE=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548_BE"
+TQM8555 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8555,TQM8555=y,HOSTNAME=tqm8555,BOARDNAME="TQM8555"
+TQM8560 powerpc mpc85xx tqm85xx tqc - TQM85xx:MPC8560,TQM8560=y,HOSTNAME=tqm8560,BOARDNAME="TQM8560"
+xpedite520x powerpc mpc85xx - xes
+xpedite537x powerpc mpc85xx - xes
+xpedite550x powerpc mpc85xx - xes
+sbc8641d powerpc mpc86xx
+MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
+MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN
+MPC8641HPCN_36BIT powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN:PHYS_64BIT
+xpedite517x powerpc mpc86xx - xes
+Adder powerpc mpc8xx adder
+Adder87x powerpc mpc8xx adder - - Adder
+AdderII powerpc mpc8xx adder - - Adder:MPC852T
+AdderUSB powerpc mpc8xx adder - - Adder
+ADS860 powerpc mpc8xx fads
+c2mon powerpc mpc8xx
+cogent_mpc8xx powerpc mpc8xx cogent
+EP88x powerpc mpc8xx ep88x
+ESTEEM192E powerpc mpc8xx esteem192e
+ETX094 powerpc mpc8xx etx094
+FADS823 powerpc mpc8xx fads
+FADS850SAR powerpc mpc8xx fads
+FADS860T powerpc mpc8xx fads
+FLAGADM powerpc mpc8xx flagadm
+GEN860T powerpc mpc8xx gen860t
+GEN860T_SC powerpc mpc8xx gen860t - - GEN860T:SC
+GENIETV powerpc mpc8xx genietv
+hermes powerpc mpc8xx
+ICU862 powerpc mpc8xx icu862
+ICU862_100MHz powerpc mpc8xx icu862 - - ICU862:100MHz
+IP860 powerpc mpc8xx ip860
+IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M
+IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M
+IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M
+IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M
+IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M
+IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M
+LANTEC powerpc mpc8xx lantec
+lwmon powerpc mpc8xx
+MBX powerpc mpc8xx mbx8xx
+MBX860T powerpc mpc8xx mbx8xx
+MPC86xADS powerpc mpc8xx fads
+MPC885ADS powerpc mpc8xx fads
+NETPHONE powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=1
+NETPHONE_V2 powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=2
+NETTA powerpc mpc8xx netta - - NETTA
+NETTA2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=1
+NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2
+NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1
+NETTA_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1
+NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1
+NETTA_ISDN_6412 powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1
+NETTA_ISDN_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1
+NETTA_ISDN_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1
+NETTA_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_SWAPHOOK=1
+NETVIA powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=1
+NETVIA_V2 powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=2
+NX823 powerpc mpc8xx nx823
+quantum powerpc mpc8xx
+R360MPI powerpc mpc8xx r360mpi
+RBC823 powerpc mpc8xx rbc823
+rmu powerpc mpc8xx
+RPXClassic powerpc mpc8xx
+RPXlite powerpc mpc8xx
+RPXlite_DW powerpc mpc8xx RPXlite_dw - - RPXlite_DW
+RPXlite_DW_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz
+RPXlite_DW_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20
+RPXlite_DW_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20
+RPXlite_DW_NVRAM powerpc mpc8xx RPXlite_dw - - RPXlite_DW:ENV_IS_IN_NVRAM
+RPXlite_DW_NVRAM_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM
+RPXlite_DW_NVRAM_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM
+RPXlite_DW_NVRAM_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM
+RRvision powerpc mpc8xx
+RRvision_LCD powerpc mpc8xx RRvision - - RRvision:LCD,SHARP_LQ104V7DS01
+spc1920 powerpc mpc8xx
+SPD823TS powerpc mpc8xx spd8xx
+svm_sc8xx powerpc mpc8xx
+SXNI855T powerpc mpc8xx sixnet
+v37 powerpc mpc8xx
+MHPC powerpc mpc8xx mhpc eltec
+TOP860 powerpc mpc8xx top860 emk
+kmsupx4 powerpc mpc8xx km8xx keymile
+mgsuvd powerpc mpc8xx km8xx keymile
+KUP4K powerpc mpc8xx kup4k kup
+KUP4X powerpc mpc8xx kup4x kup
+ELPT860 powerpc mpc8xx elpt860 LEOX
+uc100 powerpc mpc8xx - manroland
+IAD210 powerpc mpc8xx - siemens
+QS823 powerpc mpc8xx qs850 snmc
+QS850 powerpc mpc8xx qs850 snmc
+QS860T powerpc mpc8xx qs860t snmc
+stxxtc powerpc mpc8xx stxxtc stx
+FPS850L powerpc mpc8xx tqm8xx tqc
+FPS860L powerpc mpc8xx tqm8xx tqc
+NSCU powerpc mpc8xx tqm8xx tqc
+SM850 powerpc mpc8xx tqm8xx tqc
+TK885D powerpc mpc8xx tqm8xx tqc
+TQM823L powerpc mpc8xx tqm8xx tqc
+TQM823L_LCD powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,NEC_NL6448BC20
+TQM823M powerpc mpc8xx tqm8xx tqc
+TQM850L powerpc mpc8xx tqm8xx tqc
+TQM850M powerpc mpc8xx tqm8xx tqc
+TQM855L powerpc mpc8xx tqm8xx tqc
+TQM855M powerpc mpc8xx tqm8xx tqc
+TQM860L powerpc mpc8xx tqm8xx tqc
+TQM860M powerpc mpc8xx tqm8xx tqc
+TQM862L powerpc mpc8xx tqm8xx tqc
+TQM862M powerpc mpc8xx tqm8xx tqc
+TQM866M powerpc mpc8xx tqm8xx tqc
+TQM885D powerpc mpc8xx tqm8xx tqc
+TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01
+virtlab2 powerpc mpc8xx tqm8xx tqc
+wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U
+AMX860 powerpc mpc8xx amx860 westel
+csb272 powerpc ppc4xx
+csb472 powerpc ppc4xx
+G2000 powerpc ppc4xx g2000
+JSE powerpc ppc4xx jse
+korat powerpc ppc4xx
+korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
+lwmon5 powerpc ppc4xx
+ML2 powerpc ppc4xx ml2
+pcs440ep powerpc ppc4xx
+quad100hd powerpc ppc4xx
+sbc405 powerpc ppc4xx
+sc3 powerpc ppc4xx
+t3corp powerpc ppc4xx
+W7OLMC powerpc ppc4xx w7o
+W7OLMG powerpc ppc4xx w7o
+zeus powerpc ppc4xx
+acadia powerpc ppc4xx - amcc
+acadia_nand powerpc ppc4xx acadia amcc - acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+arches powerpc ppc4xx canyonlands amcc - canyonlands:ARCHES
+bamboo powerpc ppc4xx - amcc
+bamboo_nand powerpc ppc4xx bamboo amcc - bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+bluestone powerpc ppc4xx - amcc
+bubinga powerpc ppc4xx - amcc
+canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS
+canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+ebony powerpc ppc4xx - amcc
+glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER
+glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA
+haleakala_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+katmai powerpc ppc4xx - amcc
+kilauea powerpc ppc4xx kilauea amcc - kilauea:KILAUEA
+kilauea_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+luan powerpc ppc4xx - amcc
+makalu powerpc ppc4xx - amcc
+ocotea powerpc ppc4xx - amcc
+rainier powerpc ppc4xx sequoia amcc - sequoia:RAINIER
+rainier_nand powerpc ppc4xx sequoia amcc - sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+rainier_ramboot powerpc ppc4xx sequoia amcc - sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds
+redwood powerpc ppc4xx - amcc
+sequoia powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA
+sequoia_nand powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
+sequoia_ramboot powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds
+sycamore powerpc ppc4xx walnut amcc - walnut
+taihu powerpc ppc4xx - amcc
+taishan powerpc ppc4xx - amcc
+walnut powerpc ppc4xx walnut amcc
+yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE
+yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
+yucca powerpc ppc4xx - amcc
+AP1000 powerpc ppc4xx ap1000 amirix
+fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
+fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
+v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
+v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
+CRAYL1 powerpc ppc4xx L1 cray
+CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1
+CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
+CATcenter_33 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
+PPChameleonEVB powerpc ppc4xx PPChameleonEVB dave
+PPChameleonEVB_BA_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25
+PPChameleonEVB_BA_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33
+PPChameleonEVB_HI_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25
+PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33
+PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
+PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
+ADCIOP powerpc ppc4xx adciop esd
+APC405 powerpc ppc4xx apc405 esd
+AR405 powerpc ppc4xx ar405 esd
+ASH405 powerpc ppc4xx ash405 esd
+CANBT powerpc ppc4xx canbt esd
+CMS700 powerpc ppc4xx cms700 esd
+CPCI2DP powerpc ppc4xx cpci2dp esd
+CPCI405 powerpc ppc4xx cpci405 esd
+CPCI4052 powerpc ppc4xx cpci405 esd
+CPCI405AB powerpc ppc4xx cpci405 esd
+CPCI405DT powerpc ppc4xx cpci405 esd
+CPCIISER4 powerpc ppc4xx cpciiser4 esd
+DASA_SIM powerpc ppc4xx dasa_sim esd
+DP405 powerpc ppc4xx dp405 esd
+DU405 powerpc ppc4xx du405 esd
+DU440 powerpc ppc4xx du440 esd
+HH405 powerpc ppc4xx hh405 esd
+HUB405 powerpc ppc4xx hub405 esd
+OCRTC powerpc ppc4xx ocrtc esd
+PCI405 powerpc ppc4xx pci405 esd
+PLU405 powerpc ppc4xx plu405 esd
+PMC405 powerpc ppc4xx pmc405 esd
+PMC405DE powerpc ppc4xx pmc405de esd
+PMC440 powerpc ppc4xx pmc440 esd
+VOH405 powerpc ppc4xx voh405 esd
+VOM405 powerpc ppc4xx vom405 esd
+WUH405 powerpc ppc4xx wuh405 esd
+devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER
+dlvision powerpc ppc4xx - gdsys
+gdppc440etx powerpc ppc4xx - gdsys
+intip powerpc ppc4xx intip gdsys - intip:INTIB
+io powerpc ppc4xx 405ep gdsys
+iocon powerpc ppc4xx 405ep gdsys
+neo powerpc ppc4xx - gdsys
+icon powerpc ppc4xx - mosaixtech
+MIP405 powerpc ppc4xx mip405 mpl
+MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
+PIP405 powerpc ppc4xx pip405 mpl
+hcu4 powerpc ppc4xx hcu4 netstal
+hcu5 powerpc ppc4xx hcu5 netstal
+mcu25 powerpc ppc4xx mcu25 netstal
+alpr powerpc ppc4xx - prodrive
+p3p440 powerpc ppc4xx - prodrive
+KAREF powerpc ppc4xx karef sandburst
+METROBOX powerpc ppc4xx metrobox sandburst
+xpedite1000 powerpc ppc4xx - xes
+ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
+ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
+xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC
+xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
+xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1
+xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
+rsk7203 sh sh2 rsk7203 renesas -
+mpr2 sh sh3 mpr2 - -
+ms7720se sh sh3 ms7720se - -
+espt sh sh4 espt - -
+ms7722se sh sh4 ms7722se - -
+ms7750se sh sh4 ms7750se - -
+ap325rxa sh sh4 ap325rxa renesas -
+r2dplus sh sh4 r2dplus renesas -
+r7780mp sh sh4 r7780mp renesas -
+sh7763rdp sh sh4 sh7763rdp renesas -
+sh7785lcr sh sh4 sh7785lcr renesas -
+sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
+MigoRsh sh4 MigoR renesas -
+grsim_leon2 sparc leon2 - gaisler
+gr_cpci_ax2000 sparc leon3 - gaisler
+gr_ep2s60 sparc leon3 - gaisler
+grsim sparc leon3 - gaisler
+gr_xc3s_1500 sparc leon3 - gaisler
+# Target ARCH CPU Board name Vendor SoC Options
+########################################################################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libcommon.a
-
-AOBJS =
+LIB = $(obj)libcommon.o
# core
COBJS-y += main.o
COBJS-y += env_common.o
COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
-COBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
+XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
+XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
COBJS-$(CONFIG_ENV_IS_IN_MG_DISK) += env_mgdisk.o
COBJS := $(sort $(COBJS-y))
-SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
+XCOBJS := $(sort $(XCOBJS-y))
+SRCS := $(COBJS:.o=.c) $(XCOBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+XOBJS := $(addprefix $(obj),$(XCOBJS))
CPPFLAGS += -I..
-all: $(LIB) $(AOBJS)
+all: $(LIB) $(XOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
$(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc
$(CC) $(AFLAGS) -Wa,--no-warn \
printf("CONFIG_SYS_PROM_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
CONFIG_SYS_PROM_SIZE);
printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
- CONFIG_SYS_GBL_DATA_SIZE);
+ GENERATED_GBL_DATA_SIZE);
#if defined(CONFIG_CMD_NET)
print_eth(0);
printf ("ip_addr = %pI4\n", &bd->bi_ip_addr);
#endif
printf ("baudrate = %d bps\n", bd->bi_baudrate);
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
print_num ("TLB addr", gd->tlb_addr);
#endif
print_num ("irq_sp", gd->irq_sp); /* irq stack pointer */
print_num ("sp start ", gd->start_addr_sp);
print_num ("FB base ", gd->fb_base);
-#endif
return 0;
}
bd_t *bd = gd->bd;
char buf[32];
- print_num ("env_t", (ulong)bd->bi_env);
print_num ("boot_params", (ulong)bd->bi_boot_params);
print_num ("bi_memstart", bd->bi_memstart);
print_num ("bi_memsize", bd->bi_memsize);
U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
};
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void bmp_reloc(void) {
fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
}
" passing 'arg' as arguments"
);
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
U_BOOT_CMD(
reset, 1, 0, do_reset,
"Perform RESET of the CPU",
static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag,int argc, char * const argv[],
bootm_headers_t *images, ulong *os_data, ulong *os_len);
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Continue booting an OS image; caller already has:
}
#if defined(CONFIG_OF_LIBFDT)
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
/* find flattened device tree */
ret = boot_get_fdt (flag, argc, argv, &images,
&images.ft_addr, &images.ft_len);
set_working_fdt_addr(images.ft_addr);
#endif
-#endif
}
images.os.start = (ulong)os_hdr;
static cmd_tbl_t cmd_bootm_sub[] = {
U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""),
U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""),
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
U_BOOT_CMD_MKENT(ramdisk, 0, 1, (void *)BOOTM_STATE_RAMDISK, "", ""),
#endif
#ifdef CONFIG_OF_LIBFDT
lmb_reserve(&images.lmb, images.os.load,
(load_end - images.os.load));
break;
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
case BOOTM_STATE_RAMDISK:
{
ulong rd_len = images.rd_end - images.rd_start;
ulong load_end = 0;
int ret;
boot_os_fn *boot_fn;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
static int relocated = 0;
/* relocate boot function table */
DECLARE_GLOBAL_DATA_PTR;
-const char *weekdays[] = {
+static const char * const weekdays[] = {
"Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",
};
-#ifdef CONFIG_RELOC_FIXUP_WORKS
-#define RELOC(a) a
-#else
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
#define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off))
+#else
+#define RELOC(a) a
#endif
-int mk_date (char *, struct rtc_time *);
+int mk_date (const char *, struct rtc_time *);
int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/*
* simple conversion of two-digit string with error checking
*/
-static int cnvrt2 (char *str, int *valp)
+static int cnvrt2 (const char *str, int *valp)
{
int val;
* Some basic checking for valid values is done, but this will not catch
* all possible error conditions.
*/
-int mk_date (char *datestr, struct rtc_time *tmp)
+int mk_date (const char *datestr, struct rtc_time *tmp)
{
int len, val;
char *ptr;
#include <common.h>
#include <command.h>
+#include <led-display.h>
#undef DEBUG_DISP
-#define DISP_SIZE 8
-#define CWORD_CLEAR 0x80
-#define CLEAR_DELAY (110 * 2)
-
int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
- int pos;
/* Clear display */
- *((volatile char*)(CONFIG_SYS_DISP_CWORD)) = CWORD_CLEAR;
- udelay(1000 * CLEAR_DELAY);
+ display_set(DISPLAY_CLEAR | DISPLAY_HOME);
if (argc < 2)
return (0);
- for (pos = 0, i = 1; i < argc && pos < DISP_SIZE; i++) {
- char *p = argv[i], c;
+ for (i = 1; i < argc; i++) {
+ char *p = argv[i];
- if (i > 1) {
- *((volatile uchar *) (CONFIG_SYS_DISP_CHR_RAM + pos++)) = ' ';
-#ifdef DEBUG_DISP
- putc(' ');
-#endif
+ if (i > 1) { /* Insert a space between strings */
+ display_putc(' ');
}
- while ((c = *p++) != '\0' && pos < DISP_SIZE) {
- *((volatile uchar *) (CONFIG_SYS_DISP_CHR_RAM + pos++)) = c;
+ while ((*p)) {
#ifdef DEBUG_DISP
- putc(c);
+ putc(*p);
#endif
+ display_putc(*p++);
}
}
#endif
int valid_elf_image (unsigned long addr);
-unsigned long load_elf_image (unsigned long addr);
+static unsigned long load_elf_image_phdr(unsigned long addr);
+static unsigned long load_elf_image_shdr(unsigned long addr);
/* Allow ports to override the default behavior */
__attribute__((weak))
{
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
+ char *sload, *saddr;
/* -------------------------------------------------- */
int rcode = 0;
- if (argc < 2)
- addr = load_addr;
+ sload = saddr = NULL;
+ if (argc == 3) {
+ sload = argv[1];
+ saddr = argv[2];
+ } else if (argc == 2) {
+ if (argv[1][0] == '-')
+ sload = argv[1];
+ else
+ saddr = argv[1];
+ }
+
+ if (saddr)
+ addr = simple_strtoul(saddr, NULL, 16);
else
- addr = simple_strtoul (argv[1], NULL, 16);
+ addr = load_addr;
if (!valid_elf_image (addr))
return 1;
- addr = load_elf_image (addr);
+ if (sload && sload[1] == 'p')
+ addr = load_elf_image_phdr(addr);
+ else
+ addr = load_elf_image_shdr(addr);
printf ("## Starting application at 0x%08lx ...\n", addr);
*/
if (valid_elf_image (addr)) {
- addr = load_elf_image (addr);
+ addr = load_elf_image_shdr (addr);
} else {
puts ("## Not an ELF image, assuming binary\n");
/* leave addr as load_addr */
* A very simple elf loader, assumes the image is valid, returns the
* entry point address.
* ====================================================================== */
-unsigned long load_elf_image (unsigned long addr)
+static unsigned long load_elf_image_phdr(unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Phdr *phdr; /* Program header structure pointer */
+ int i;
+
+ ehdr = (Elf32_Ehdr *) addr;
+ phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff);
+
+ /* Load each program header */
+ for (i = 0; i < ehdr->e_phnum; ++i) {
+ void *dst = (void *) phdr->p_paddr;
+ void *src = (void *) addr + phdr->p_offset;
+ debug("Loading phdr %i to 0x%p (%i bytes)\n",
+ i, dst, phdr->p_filesz);
+ if (phdr->p_filesz)
+ memcpy(dst, src, phdr->p_filesz);
+ if (phdr->p_filesz != phdr->p_memsz)
+ memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz);
+ flush_cache((unsigned long)dst, phdr->p_filesz);
+ ++phdr;
+ }
+
+ return ehdr->e_entry;
+}
+
+static unsigned long load_elf_image_shdr(unsigned long addr)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Shdr *shdr; /* Section header structure pointer */
/* ====================================================================== */
U_BOOT_CMD(
- bootelf, 2, 0, do_bootelf,
+ bootelf, 3, 0, do_bootelf,
"Boot from an ELF image in memory",
- " [address] - load address of ELF image."
+ "[-p|-s] [address]\n"
+ "\t- load ELF image at [address] via program headers (-p)\n"
+ "\t or via section headers (-s)"
);
U_BOOT_CMD(
"<interface> <dev[:part]>\n"
" - print information about filesystem from 'dev' on 'interface'"
);
-
image_header_t *hdr; /* used for fdc boot */
unsigned char boot_drive;
int i,nrofblk;
- char *ep;
int rcode = 0;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
size, load_addr);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
#include <dataflash.h>
#endif
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
#include <jffs2/jffs2.h>
/* partition handling routines */
flash_info_t *info;
ulong bank, addr_first, addr_last;
int n, sect_first, sect_last;
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
u8 dev_type, dev_num, pnum;
return rcode;
}
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
/* erase <part-id> - erase partition */
if ((argc == 2) && (mtd_id_parse(argv[1], NULL, &dev_type, &dev_num) == 0)) {
mtdparts_init();
#if !defined(CONFIG_SYS_NO_FLASH) || defined(CONFIG_HAS_DATAFLASH)
ulong addr_first, addr_last;
#endif
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
u8 dev_type, dev_num, pnum;
return rcode;
}
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
/* protect on/off <part-id> */
if ((argc == 3) && (mtd_id_parse(argv[2], NULL, &dev_type, &dev_num) == 0)) {
mtdparts_init();
/**************************************************/
-#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS)
+#if defined(CONFIG_CMD_MTDPARTS)
# define TMP_ERASE "erase <part-id>\n - erase partition\n"
# define TMP_PROT_ON "protect on <part-id>\n - protect partition\n"
# define TMP_PROT_OFF "protect off <part-id>\n - make partition writable\n"
char *devstr = getenv ("fpga");
char *datastr = getenv ("fpgadata");
int rc = FPGA_FAIL;
+ int wrong_parms = 0;
#if defined (CONFIG_FIT)
const char *fit_uname = NULL;
ulong fit_addr;
break;
}
+ if (dev == FPGA_INVALID_DEVICE) {
+ puts("FPGA device not specified\n");
+ op = FPGA_NONE;
+ }
+
+ switch (op) {
+ case FPGA_NONE:
+ case FPGA_INFO:
+ break;
+ case FPGA_LOAD:
+ case FPGA_LOADB:
+ case FPGA_DUMP:
+ if (!fpga_data || !data_size)
+ wrong_parms = 1;
+ break;
+ case FPGA_LOADMK:
+ if (!fpga_data)
+ wrong_parms = 1;
+ break;
+ }
+
+ if (wrong_parms) {
+ puts("Wrong parameters for FPGA request\n");
+ op = FPGA_NONE;
+ }
+
switch (op) {
case FPGA_NONE:
return cmd_usage(cmdtp);
}
U_BOOT_CMD (fpga, 6, 1, do_fpga,
- "loadable FPGA image support",
- "fpga [operation type] [device number] [image address] [image size]\n"
- "fpga operations:\n"
- "\tinfo\tlist known device information\n"
- "\tload\tLoad device from memory buffer\n"
- "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
- "\tloadmk\tLoad device generated with mkimage\n"
- "\tdump\tLoad device to memory buffer"
+ "loadable FPGA image support",
+ "[operation type] [device number] [image address] [image size]\n"
+ "fpga operations:\n"
+ " dump\t[dev]\t\t\tLoad device to memory buffer\n"
+ " info\t[dev]\t\t\tlist known device information\n"
+ " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
+ " loadb\t[dev] [address] [size]\t"
+ "Load device from bitstream buffer (Xilinx only)\n"
+ " loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
- "\n"
- "\tFor loadmk operating on FIT format uImage address must include\n"
- "\tsubimage unit name in the form of addr:<subimg_uname>"
+ "\n"
+ "\tFor loadmk operating on FIT format uImage address must include\n"
+ "\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
);
U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
};
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void i2c_reloc(void) {
fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
}
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
typedef struct op_tbl_s op_tbl_t;
-op_tbl_t op_table [] = {
+static const op_tbl_t op_table [] = {
{ "-lt", LT },
{ "<" , LT },
{ "-gt", GT },
{ "<=" , LE },
};
-#define op_tbl_size (sizeof(op_table)/sizeof(op_table[0]))
-
static long evalexp(char *s, int w)
{
long l = 0;
int binary_test (char *op, char *arg1, char *arg2, int w)
{
int len, i;
- op_tbl_t *optp;
+ const op_tbl_t *optp;
len = strlen(op);
for (optp = (op_tbl_t *)&op_table, i = 0;
- i < op_tbl_size;
+ i < ARRAY_SIZE(op_table);
optp++, i++) {
if ((strncmp (op, optp->op, len) == 0) && (len == strlen (optp->op))) {
ngood++;
addr1 += size;
addr2 += size;
+
+ /* reset watchdog from time to time */
+ if ((count % (64 << 10)) == 0)
+ WATCHDOG_RESET();
}
printf("Total of %ld %s%s were the same\n",
*((u_char *)dest) = *((u_char *)addr);
addr += size;
dest += size;
+
+ /* reset watchdog from time to time */
+ if ((count % (64 << 10)) == 0)
+ WATCHDOG_RESET();
}
return 0;
}
char * name;
} MII_reg_desc_t;
-MII_reg_desc_t reg_0_5_desc_tbl[] = {
+static const MII_reg_desc_t reg_0_5_desc_tbl[] = {
{ 0, "PHY control register" },
{ 1, "PHY status register" },
{ 2, "PHY ID 1 register" },
char * name;
} MII_field_desc_t;
-MII_field_desc_t reg_0_desc_tbl[] = {
+static const MII_field_desc_t reg_0_desc_tbl[] = {
{ 15, 15, 0x01, "reset" },
{ 14, 14, 0x01, "loopback" },
{ 13, 6, 0x81, "speed selection" }, /* special */
{ 5, 0, 0x3f, "(reserved)" }
};
-MII_field_desc_t reg_1_desc_tbl[] = {
+static const MII_field_desc_t reg_1_desc_tbl[] = {
{ 15, 15, 0x01, "100BASE-T4 able" },
{ 14, 14, 0x01, "100BASE-X full duplex able" },
{ 13, 13, 0x01, "100BASE-X half duplex able" },
{ 0, 0, 0x01, "extended capabilities" },
};
-MII_field_desc_t reg_2_desc_tbl[] = {
+static const MII_field_desc_t reg_2_desc_tbl[] = {
{ 15, 0, 0xffff, "OUI portion" },
};
-MII_field_desc_t reg_3_desc_tbl[] = {
+static const MII_field_desc_t reg_3_desc_tbl[] = {
{ 15, 10, 0x3f, "OUI portion" },
{ 9, 4, 0x3f, "manufacturer part number" },
{ 3, 0, 0x0f, "manufacturer rev. number" },
};
-MII_field_desc_t reg_4_desc_tbl[] = {
+static const MII_field_desc_t reg_4_desc_tbl[] = {
{ 15, 15, 0x01, "next page able" },
{ 14, 14, 0x01, "reserved" },
{ 13, 13, 0x01, "remote fault" },
{ 4, 0, 0x1f, "xxx to do" },
};
-MII_field_desc_t reg_5_desc_tbl[] = {
+static const MII_field_desc_t reg_5_desc_tbl[] = {
{ 15, 15, 0x01, "next page able" },
{ 14, 14, 0x01, "acknowledge" },
{ 13, 13, 0x01, "remote fault" },
{ 5, 5, 0x01, "10BASE-T able" },
{ 4, 0, 0x1f, "xxx to do" },
};
-
-#define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0]))
-#define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0]))
-#define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0]))
-#define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0]))
-#define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0]))
-#define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0]))
-
typedef struct _MII_field_desc_and_len_t {
- MII_field_desc_t * pdesc;
+ const MII_field_desc_t *pdesc;
ushort len;
} MII_field_desc_and_len_t;
-MII_field_desc_and_len_t desc_and_len_tbl[] = {
- { reg_0_desc_tbl, DESC0LEN },
- { reg_1_desc_tbl, DESC1LEN },
- { reg_2_desc_tbl, DESC2LEN },
- { reg_3_desc_tbl, DESC3LEN },
- { reg_4_desc_tbl, DESC4LEN },
- { reg_5_desc_tbl, DESC5LEN },
+static const MII_field_desc_and_len_t desc_and_len_tbl[] = {
+ { reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl) },
+ { reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl) },
+ { reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl) },
+ { reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl) },
+ { reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl) },
+ { reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl) },
};
static void dump_reg(
ushort regval,
- MII_reg_desc_t * prd,
- MII_field_desc_and_len_t * pdl);
+ const MII_reg_desc_t *prd,
+ const MII_field_desc_and_len_t *pdl);
static int special_field(
ushort regno,
- MII_field_desc_t * pdesc,
+ const MII_field_desc_t *pdesc,
ushort regval);
-void MII_dump_0_to_5(
+static void MII_dump_0_to_5(
ushort regvals[6],
uchar reglo,
uchar reghi)
static void dump_reg(
ushort regval,
- MII_reg_desc_t * prd,
- MII_field_desc_and_len_t * pdl)
+ const MII_reg_desc_t *prd,
+ const MII_field_desc_and_len_t *pdl)
{
ulong i;
ushort mask_in_place;
- MII_field_desc_t * pdesc;
+ const MII_field_desc_t *pdesc;
printf("%u. (%04hx) -- %s --\n",
prd->regno, regval, prd->name);
static int special_field(
ushort regno,
- MII_field_desc_t * pdesc,
+ const MII_field_desc_t *pdesc,
ushort regval)
{
if ((regno == 0) && (pdesc->lo == 6)) {
return 0;
}
-char last_op[2];
-uint last_data;
-uint last_addr_lo;
-uint last_addr_hi;
-uint last_reg_lo;
-uint last_reg_hi;
+static char last_op[2];
+static uint last_data;
+static uint last_addr_lo;
+static uint last_addr_hi;
+static uint last_reg_lo;
+static uint last_reg_hi;
static void extract_range(
char * input,
}
/* ---------------------------------------------------------------- */
-int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char op[2];
unsigned char addrlo, addrhi, reglo, reghi;
* Parsing routines are based on driver/mtd/cmdline.c from the linux 2.4
* kernel tree.
*
+ * (C) Copyright 2008
+ * Harald Welte, OpenMoko, Inc., Harald Welte <laforge@openmoko.org>
+ *
* $Id: cmdlinepart.c,v 1.17 2004/11/26 11:18:47 lavinen Exp $
* Copyright 2002 SYSGO Real-Time Solutions GmbH
*
index_partitions();
}
+
+/**
+ * Produce a mtd_info given a type and num.
+ *
+ * @param type mtd type
+ * @param num mtd number
+ * @param mtd a pointer to an mtd_info instance (output)
+ * @return 0 if device is valid, 1 otherwise
+ */
+static int get_mtd_info(u8 type, u8 num, struct mtd_info **mtd)
+{
+ char mtd_dev[16];
+
+ sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(type), num);
+ *mtd = get_mtd_device_nm(mtd_dev);
+ if (IS_ERR(*mtd)) {
+ printf("Device %s not found!\n", mtd_dev);
+ return 1;
+ }
+
+ return 0;
+}
+
/**
* Performs sanity check for supplied flash partition.
* Table of existing MTD flash devices is searched and partition device
*/
static int part_validate_eraseblock(struct mtdids *id, struct part_info *part)
{
- struct mtd_info *mtd;
- char mtd_dev[16];
+ struct mtd_info *mtd = NULL;
int i, j;
ulong start;
- sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(id->type), id->num);
- mtd = get_mtd_device_nm(mtd_dev);
- if (IS_ERR(mtd)) {
- printf("Partition %s not found on device %s!\n", part->name, mtd_dev);
+ if (get_mtd_info(id->type, id->num, &mtd))
return 1;
- }
part->sector_size = mtd->erasesize;
/**
* Check device number to be within valid range for given device type.
*
- * @param dev device to validate
+ * @param type mtd type
+ * @param num mtd number
+ * @param size a pointer to the size of the mtd device (output)
* @return 0 if device is valid, 1 otherwise
*/
int mtd_device_validate(u8 type, u8 num, u32 *size)
{
- struct mtd_info *mtd;
- char mtd_dev[16];
+ struct mtd_info *mtd = NULL;
- sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(type), num);
- mtd = get_mtd_device_nm(mtd_dev);
- if (IS_ERR(mtd)) {
- printf("Device %s not found!\n", mtd_dev);
+ if (get_mtd_info(type, num, &mtd))
return 1;
- }
*size = mtd->size;
}
#endif
+#if defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES)
/**
- * Format and print out a partition list for each device from global device
- * list.
+ * Get the net size (w/o bad blocks) of the given partition.
+ *
+ * @param mtd the mtd info
+ * @param part the partition
+ * @return the calculated net size of this partition
*/
-static void list_partitions(void)
+static uint64_t net_part_size(struct mtd_info *mtd, struct part_info *part)
+{
+ uint64_t i, net_size = 0;
+
+ if (!mtd->block_isbad)
+ return part->size;
+
+ for (i = 0; i < part->size; i += mtd->erasesize) {
+ if (!mtd->block_isbad(mtd, part->offset + i))
+ net_size += mtd->erasesize;
+ }
+
+ return net_size;
+}
+#endif
+
+static void print_partition_table(void)
{
struct list_head *dentry, *pentry;
struct part_info *part;
struct mtd_device *dev;
int part_num;
- debug("\n---list_partitions---\n");
list_for_each(dentry, &devices) {
dev = list_entry(dentry, struct mtd_device, link);
+ /* list partitions for given device */
+ part_num = 0;
+#if defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES)
+ struct mtd_info *mtd;
+
+ if (get_mtd_info(dev->id->type, dev->id->num, &mtd))
+ return;
+
+ printf("\ndevice %s%d <%s>, # parts = %d\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num,
+ dev->id->mtd_id, dev->num_parts);
+ printf(" #: name\t\tsize\t\tnet size\toffset\t\tmask_flags\n");
+
+ list_for_each(pentry, &dev->parts) {
+ u32 net_size;
+ char *size_note;
+
+ part = list_entry(pentry, struct part_info, link);
+ net_size = net_part_size(mtd, part);
+ size_note = part->size == net_size ? " " : " (!)";
+ printf("%2d: %-20s0x%08x\t0x%08x%s\t0x%08x\t%d\n",
+ part_num, part->name, part->size,
+ net_size, size_note, part->offset,
+ part->mask_flags);
+#else /* !defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */
printf("\ndevice %s%d <%s>, # parts = %d\n",
MTD_DEV_TYPE(dev->id->type), dev->id->num,
dev->id->mtd_id, dev->num_parts);
printf(" #: name\t\tsize\t\toffset\t\tmask_flags\n");
- /* list partitions for given device */
- part_num = 0;
list_for_each(pentry, &dev->parts) {
part = list_entry(pentry, struct part_info, link);
printf("%2d: %-20s0x%08x\t0x%08x\t%d\n",
part_num, part->name, part->size,
part->offset, part->mask_flags);
-
+#endif /* defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */
part_num++;
}
}
+
if (list_empty(&devices))
printf("no partitions defined\n");
+}
+
+/**
+ * Format and print out a partition list for each device from global device
+ * list.
+ */
+static void list_partitions(void)
+{
+ struct part_info *part;
+
+ debug("\n---list_partitions---\n");
+ print_partition_table();
/* current_mtd_dev is not NULL only when we have non empty device list */
if (current_mtd_dev) {
}
#endif
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+/**
+ * Increase the size of the given partition so that it's net size is at least
+ * as large as the size member and such that the next partition would start on a
+ * good block if it were adjacent to this partition.
+ *
+ * @param mtd the mtd device
+ * @param part the partition
+ * @param next_offset pointer to the offset of the next partition after this
+ * partition's size has been modified (output)
+ */
+static void spread_partition(struct mtd_info *mtd, struct part_info *part,
+ uint64_t *next_offset)
+{
+ uint64_t net_size, padding_size = 0;
+ int truncated;
+
+ mtd_get_len_incl_bad(mtd, part->offset, part->size, &net_size,
+ &truncated);
+
+ /*
+ * Absorb bad blocks immediately following this
+ * partition also into the partition, such that
+ * the next partition starts with a good block.
+ */
+ if (!truncated) {
+ mtd_get_len_incl_bad(mtd, part->offset + net_size,
+ mtd->erasesize, &padding_size, &truncated);
+ if (truncated)
+ padding_size = 0;
+ else
+ padding_size -= mtd->erasesize;
+ }
+
+ if (truncated) {
+ printf("truncated partition %s to %lld bytes\n", part->name,
+ (uint64_t) net_size + padding_size);
+ }
+
+ part->size = net_size + padding_size;
+ *next_offset = part->offset + part->size;
+}
+
+/**
+ * Adjust all of the partition sizes, such that all partitions are at least
+ * as big as their mtdparts environment variable sizes and they each start
+ * on a good block.
+ *
+ * @return 0 on success, 1 otherwise
+ */
+static int spread_partitions(void)
+{
+ struct list_head *dentry, *pentry;
+ struct mtd_device *dev;
+ struct part_info *part;
+ struct mtd_info *mtd;
+ int part_num;
+ uint64_t cur_offs;
+
+ list_for_each(dentry, &devices) {
+ dev = list_entry(dentry, struct mtd_device, link);
+
+ if (get_mtd_info(dev->id->type, dev->id->num, &mtd))
+ return 1;
+
+ part_num = 0;
+ cur_offs = 0;
+ list_for_each(pentry, &dev->parts) {
+ part = list_entry(pentry, struct part_info, link);
+
+ debug("spread_partitions: device = %s%d, partition %d ="
+ " (%s) 0x%08x@0x%08x\n",
+ MTD_DEV_TYPE(dev->id->type), dev->id->num,
+ part_num, part->name, part->size,
+ part->offset);
+
+ if (cur_offs > part->offset)
+ part->offset = cur_offs;
+
+ spread_partition(mtd, part, &cur_offs);
+
+ part_num++;
+ }
+ }
+
+ index_partitions();
+
+ if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
+ printf("generated mtdparts too long, reseting to null\n");
+ return 1;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MTDPARTS_SPREAD */
+
/**
* Accept character string describing mtd partitions and call device_parse()
* for each entry. Add created devices to the global devices list.
#ifndef CONFIG_CMD_MTDPARTS_LITE
/* mtdparts add <mtd-dev> <size>[@<offset>] <name> [ro] */
- if (((argc == 5) || (argc == 6)) && (strcmp(argv[1], "add") == 0)) {
+ if (((argc == 5) || (argc == 6)) && (strncmp(argv[1], "add", 3) == 0)) {
#define PART_ADD_DESC_MAXLEN 64
char tmpbuf[PART_ADD_DESC_MAXLEN];
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+ struct mtd_info *mtd;
+ uint64_t next_offset;
+#endif
u8 type, num, len;
struct mtd_device *dev;
struct mtd_device *dev_tmp;
debug("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type),
dev->id->num, dev->id->mtd_id);
- if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) {
+ p = list_entry(dev->parts.next, struct part_info, link);
+
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+ if (get_mtd_info(dev->id->type, dev->id->num, &mtd))
+ return 1;
+
+ if (!strcmp(&argv[1][3], ".spread")) {
+ spread_partition(mtd, p, &next_offset);
+ debug("increased %s to %d bytes\n", p->name, p->size);
+ }
+#endif
+
+ dev_tmp = device_find(dev->id->type, dev->id->num);
+ if (dev_tmp == NULL) {
device_add(dev);
- } else {
+ } else if (part_add(dev_tmp, p) != 0) {
/* merge new partition with existing ones*/
- p = list_entry(dev->parts.next, struct part_info, link);
- if (part_add(dev_tmp, p) != 0) {
- device_del(dev);
- return 1;
- }
+ device_del(dev);
+ return 1;
}
if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) {
}
#endif
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+ if ((argc == 2) && (strcmp(argv[1], "spread") == 0))
+ return spread_partitions();
+#endif /* CONFIG_CMD_MTDPARTS_SPREAD */
+
return cmd_usage(cmdtp);
}
" - delete partition (e.g. part-id = nand0,1)\n"
"mtdparts add <mtd-dev> <size>[@<offset>] [<name>] [ro]\n"
" - add partition\n"
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+ "mtdparts add.spread <mtd-dev> <size>[@<offset>] [<name>] [ro]\n"
+ " - add partition, padding size by skipping bad blocks\n"
+#endif
"mtdparts default\n"
- " - reset partition table to defaults\n\n"
+ " - reset partition table to defaults\n"
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+ "mtdparts spread\n"
+ " - adjust the sizes of the partitions so they are\n"
+ " at least as big as the mtdparts variable specifies\n"
+ " and they each start on a good block\n\n"
+#else
+ "\n"
+#endif /* CONFIG_CMD_MTDPARTS_SPREAD */
"-----\n\n"
"this command uses three environment variables:\n\n"
"'partition' - keeps current partition identifier\n\n"
* (C) Copyright 2006-2007 OpenMoko, Inc.
* Added 16-bit nand support
* (C) 2004 Texas Instruments
+ *
+ * Copyright 2010 Freescale Semiconductor
+ * The portions of this file whose copyright is held by Freescale and which
+ * are not considered a derived work of GPL v2-only code may be distributed
+ * and/or modified under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
*/
#include <common.h>
u8 *part_num, struct part_info **part);
#endif
-static int nand_dump(nand_info_t *nand, ulong off, int only_oob)
+static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
{
int i;
u_char *datbuf, *oobbuf, *p;
+ static loff_t last;
+
+ if (repeat)
+ off = last + nand->writesize;
+
+ last = off;
datbuf = malloc(nand->writesize + nand->oobsize);
oobbuf = malloc(nand->oobsize);
/* ------------------------------------------------------------------------- */
-static inline int str2long(char *p, ulong *num)
+static int set_dev(int dev)
+{
+ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[dev].name) {
+ puts("No such device\n");
+ return -1;
+ }
+
+ if (nand_curr_device == dev)
+ return 0;
+
+ printf("Device %d: %s", dev, nand_info[dev].name);
+ puts("... is now current device\n");
+ nand_curr_device = dev;
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
+ board_nand_select_device(nand_info[dev].priv, dev);
+#endif
+
+ return 0;
+}
+
+static inline int str2off(const char *p, loff_t *num)
+{
+ char *endptr;
+
+ *num = simple_strtoull(p, &endptr, 16);
+ return *p != '\0' && *endptr == '\0';
+}
+
+static inline int str2long(const char *p, ulong *num)
{
char *endptr;
*num = simple_strtoul(p, &endptr, 16);
- return (*p != '\0' && *endptr == '\0') ? 1 : 0;
+ return *p != '\0' && *endptr == '\0';
}
-static int
-arg_off_size(int argc, char * const argv[], nand_info_t *nand, ulong *off, size_t *size)
+static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size)
{
- int idx = nand_curr_device;
-#if defined(CONFIG_CMD_MTDPARTS)
+#ifdef CONFIG_CMD_MTDPARTS
struct mtd_device *dev;
struct part_info *part;
u8 pnum;
+ int ret;
- if (argc >= 1 && !(str2long(argv[0], off))) {
- if ((mtdparts_init() == 0) &&
- (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) {
- if (dev->id->type != MTD_DEV_TYPE_NAND) {
- puts("not a NAND device\n");
- return -1;
- }
- *off = part->offset;
- if (argc >= 2) {
- if (!(str2long(argv[1], (ulong *)size))) {
- printf("'%s' is not a number\n", argv[1]);
- return -1;
- }
- if (*size > part->size)
- *size = part->size;
- } else {
- *size = part->size;
- }
- idx = dev->id->num;
- *nand = nand_info[idx];
- goto out;
- }
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ ret = find_dev_and_part(partname, &dev, &pnum, &part);
+ if (ret)
+ return ret;
+
+ if (dev->id->type != MTD_DEV_TYPE_NAND) {
+ puts("not a NAND device\n");
+ return -1;
}
+
+ *off = part->offset;
+ *size = part->size;
+ *idx = dev->id->num;
+
+ ret = set_dev(*idx);
+ if (ret)
+ return ret;
+
+ return 0;
+#else
+ puts("offset is not a number\n");
+ return -1;
#endif
+}
- if (argc >= 1) {
- if (!(str2long(argv[0], off))) {
- printf("'%s' is not a number\n", argv[0]);
- return -1;
- }
- } else {
+static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize)
+{
+ if (!str2off(arg, off))
+ return get_part(arg, idx, off, maxsize);
+
+ if (*off >= nand_info[*idx].size) {
+ puts("Offset exceeds device limit\n");
+ return -1;
+ }
+
+ *maxsize = nand_info[*idx].size - *off;
+ return 0;
+}
+
+static int arg_off_size(int argc, char *const argv[], int *idx,
+ loff_t *off, loff_t *size)
+{
+ int ret;
+ loff_t maxsize;
+
+ if (argc == 0) {
*off = 0;
+ *size = nand_info[*idx].size;
+ goto print;
}
- if (argc >= 2) {
- if (!(str2long(argv[1], (ulong *)size))) {
- printf("'%s' is not a number\n", argv[1]);
- return -1;
- }
- } else {
- *size = nand->size - *off;
+ ret = arg_off(argv[0], idx, off, &maxsize);
+ if (ret)
+ return ret;
+
+ if (argc == 1) {
+ *size = maxsize;
+ goto print;
}
-#if defined(CONFIG_CMD_MTDPARTS)
-out:
-#endif
- printf("device %d ", idx);
- if (*size == nand->size)
+ if (!str2off(argv[1], size)) {
+ printf("'%s' is not a number\n", argv[1]);
+ return -1;
+ }
+
+ if (*size > maxsize) {
+ puts("Size exceeds partition or device limit\n");
+ return -1;
+ }
+
+print:
+ printf("device %d ", *idx);
+ if (*size == nand_info[*idx].size)
puts("whole chip\n");
else
- printf("offset 0x%lx, size 0x%zx\n", *off, *size);
+ printf("offset 0x%llx, size 0x%llx\n",
+ (unsigned long long)*off, (unsigned long long)*size);
return 0;
}
#ifdef CONFIG_ENV_OFFSET_OOB
unsigned long nand_env_oob_offset;
-int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand,
- int argc, char * const argv[])
+int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
{
int ret;
uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
-
+ nand_info_t *nand = &nand_info[0];
char *cmd = argv[1];
+ if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+ puts("no devices available\n");
+ return 1;
+ }
+
+ set_dev(0);
+
if (!strcmp(cmd, "get")) {
ret = get_nand_env_oob(nand, &nand_env_oob_offset);
if (ret)
printf("0x%08lx\n", nand_env_oob_offset);
} else if (!strcmp(cmd, "set")) {
- ulong addr;
- size_t dummy_size;
+ loff_t addr;
+ loff_t maxsize;
struct mtd_oob_ops ops;
+ int idx = 0;
if (argc < 3)
goto usage;
- if (arg_off_size(argc - 2, argv + 2, nand, &addr,
- &dummy_size) < 0) {
- printf("Offset or partition name expected\n");
+ if (arg_off(argv[2], &idx, &addr, &maxsize)) {
+ puts("Offset or partition name expected\n");
+ return 1;
+ }
+
+ if (idx != 0) {
+ puts("Partition not on first NAND device\n");
return 1;
}
if (addr != nand_env_oob_offset) {
printf("Verification of env offset in OOB failed: "
- "0x%08lx expected but got 0x%08lx\n",
- addr, nand_env_oob_offset);
+ "0x%08llx expected but got 0x%08lx\n",
+ (unsigned long long)addr, nand_env_oob_offset);
return 1;
}
} else {
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- int i, dev, ret = 0;
- ulong addr, off;
- size_t size;
+ int i, ret = 0;
+ ulong addr;
+ loff_t off, size;
char *cmd, *s;
nand_info_t *nand;
#ifdef CONFIG_SYS_NAND_QUIET
int quiet = 0;
#endif
const char *quiet_str = getenv("quiet");
+ int dev = nand_curr_device;
+ int repeat = flag & CMD_FLAG_REPEAT;
/* at least two arguments please */
if (argc < 2)
cmd = argv[1];
+ /* Only "dump" is repeatable. */
+ if (repeat && strcmp(cmd, "dump"))
+ return 0;
+
if (strcmp(cmd, "info") == 0) {
putc('\n');
}
if (strcmp(cmd, "device") == 0) {
-
if (argc < 3) {
putc('\n');
- if ((nand_curr_device < 0) ||
- (nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE))
+ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE)
puts("no devices available\n");
else
- nand_print_info(nand_curr_device);
+ nand_print_info(dev);
return 0;
}
- dev = (int)simple_strtoul(argv[2], NULL, 10);
- if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev].name) {
- puts("No such device\n");
- return 1;
- }
- printf("Device %d: %s", dev, nand_info[dev].name);
- puts("... is now current device\n");
- nand_curr_device = dev;
-#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
- /*
- * Select the chip in the board/cpu specific driver
- */
- board_nand_select_device(nand_info[dev].priv, dev);
-#endif
+ dev = (int)simple_strtoul(argv[2], NULL, 10);
+ set_dev(dev);
return 0;
}
- if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
- strncmp(cmd, "dump", 4) != 0 &&
- strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
- strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
- strcmp(cmd, "biterr") != 0 &&
- strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0
-#ifdef CONFIG_ENV_OFFSET_OOB
- && strcmp(cmd, "env.oob") != 0
-#endif
- )
- goto usage;
-
#ifdef CONFIG_ENV_OFFSET_OOB
/* this command operates only on the first nand device */
- if (strcmp(cmd, "env.oob") == 0) {
- return do_nand_env_oob(cmdtp, &nand_info[0],
- argc - 1, argv + 1);
- }
+ if (strcmp(cmd, "env.oob") == 0)
+ return do_nand_env_oob(cmdtp, argc - 1, argv + 1);
#endif
- /* the following commands operate on the current device */
- if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
- !nand_info[nand_curr_device].name) {
+ /* The following commands operate on the current device, unless
+ * overridden by a partition specifier. Note that if somehow the
+ * current device is invalid, it will have to be changed to a valid
+ * one before these commands can run, even if a partition specifier
+ * for another device is to be used.
+ */
+ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[dev].name) {
puts("\nno devices available\n");
return 1;
}
- nand = &nand_info[nand_curr_device];
+ nand = &nand_info[dev];
if (strcmp(cmd, "bad") == 0) {
- printf("\nDevice %d bad blocks:\n", nand_curr_device);
+ printf("\nDevice %d bad blocks:\n", dev);
for (off = 0; off < nand->size; off += nand->erasesize)
if (nand_block_isbad(nand, off))
- printf(" %08lx\n", off);
+ printf(" %08llx\n", (unsigned long long)off);
return 0;
}
* 0 1 2 3 4
* nand erase [clean] [off size]
*/
- if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+ if (strncmp(cmd, "erase", 5) == 0 || strncmp(cmd, "scrub", 5) == 0) {
nand_erase_options_t opts;
/* "clean" at index 2 means request to write cleanmarker */
int clean = argc > 2 && !strcmp("clean", argv[2]);
int o = clean ? 3 : 2;
- int scrub = !strcmp(cmd, "scrub");
+ int scrub = !strncmp(cmd, "scrub", 5);
+ int part = 0;
+ int chip = 0;
+ int spread = 0;
+ int args = 2;
+
+ if (cmd[5] != 0) {
+ if (!strcmp(&cmd[5], ".spread")) {
+ spread = 1;
+ } else if (!strcmp(&cmd[5], ".part")) {
+ part = 1;
+ args = 1;
+ } else if (!strcmp(&cmd[5], ".chip")) {
+ chip = 1;
+ args = 0;
+ } else {
+ goto usage;
+ }
+ }
+
+ /*
+ * Don't allow missing arguments to cause full chip/partition
+ * erases -- easy to do accidentally, e.g. with a misspelled
+ * variable name.
+ */
+ if (argc != o + args)
+ goto usage;
- printf("\nNAND %s: ", scrub ? "scrub" : "erase");
+ printf("\nNAND %s: ", cmd);
/* skip first two or three arguments, look for offset and size */
- if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0)
+ if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
return 1;
+ nand = &nand_info[dev];
+
memset(&opts, 0, sizeof(opts));
opts.offset = off;
opts.length = size;
opts.jffs2 = clean;
opts.quiet = quiet;
+ opts.spread = spread;
if (scrub) {
puts("Warning: "
if (argc < 3)
goto usage;
- s = strchr(cmd, '.');
off = (int)simple_strtoul(argv[2], NULL, 16);
-
- if (s != NULL && strcmp(s, ".oob") == 0)
- ret = nand_dump(nand, off, 1);
- else
- ret = nand_dump(nand, off, 0);
+ ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
return ret == 0 ? 1 : 0;
-
}
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+ size_t rwsize;
int read;
if (argc < 4)
read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
printf("\nNAND %s: ", read ? "read" : "write");
- if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0)
+ if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0)
return 1;
+ nand = &nand_info[dev];
+ rwsize = size;
+
s = strchr(cmd, '.');
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
- ret = nand_read_skip_bad(nand, off, &size,
+ ret = nand_read_skip_bad(nand, off, &rwsize,
(u_char *)addr);
else
- ret = nand_write_skip_bad(nand, off, &size,
+ ret = nand_write_skip_bad(nand, off, &rwsize,
(u_char *)addr);
} else if (!strcmp(s, ".oob")) {
/* out-of-band data */
mtd_oob_ops_t ops = {
.oobbuf = (u8 *)addr,
- .ooblen = size,
+ .ooblen = rwsize,
.mode = MTD_OOB_RAW
};
return 1;
}
- printf(" %zu bytes %s: %s\n", size,
+ printf(" %zu bytes %s: %s\n", rwsize,
read ? "read" : "written", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
if (strcmp(cmd, "unlock") == 0) {
- if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
+ if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0)
return 1;
- if (!nand_unlock(nand, off, size)) {
+ if (!nand_unlock(&nand_info[dev], off, size)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
"nand write - addr off|partition size\n"
" read/write 'size' bytes starting at offset 'off'\n"
" to/from memory address 'addr', skipping bad blocks.\n"
- "nand erase [clean] [off size] - erase 'size' bytes from\n"
- " offset 'off' (entire device if not specified)\n"
+ "nand erase[.spread] [clean] [off [size]] - erase 'size' bytes "
+ "from offset 'off'\n"
+ " With '.spread', erase enough for given file size, otherwise,\n"
+ " 'size' includes skipped bad blocks.\n"
+ "nand erase.part [clean] partition - erase entire mtd partition'\n"
+ "nand erase.chip [clean] - erase entire chip'\n"
"nand bad - show bad blocks\n"
"nand dump[.oob] off - dump page\n"
- "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
+ "nand scrub off size | scrub.part partition | scrub.chip\n"
+ " really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n"
"nand biterr off - make a bit error at offset (UNSAFE)"
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
ulong offset, ulong addr, char *cmd)
{
int r;
- char *ep, *s;
+ char *s;
size_t cnt;
image_header_t *hdr;
#if defined(CONFIG_FIT)
load_addr = addr;
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = cmd;
local_args[1] = NULL;
#include <command.h>
#include <net.h>
-extern int do_bootm (cmd_tbl_t *, int, int, char * const []);
-
static int netboot_common (proto_t, cmd_tbl_t *, int , char * const []);
int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+#ifdef CONFIG_CMD_RARP
int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return netboot_common (RARP, cmdtp, argc, argv);
"boot image via network using RARP/TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+#endif
#if defined(CONFIG_CMD_DHCP)
int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
flush_cache(load_addr, size);
/* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
local_args[0] = argv[0];
local_args[1] = NULL;
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
if (ep == NULL)
return 0;
len = printf ("%s=%s\n", ep->key, ep->data);
}
/* print whole list */
- len = hexport('\n', &res, 0);
+ len = hexport_r(&env_htab, '\n', &res, 0);
if (len > 0) {
puts(res);
*/
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
/* Check for console redirection */
if (strcmp(name,"stdin") == 0) {
/* Delete only ? */
if ((argc < 3) || argv[2] == NULL) {
- int rc = hdelete(name);
+ int rc = hdelete_r(name, &env_htab);
return !rc;
}
e.key = name;
e.data = value;
- ep = hsearch(e, ENTER);
+ hsearch_r(e, ENTER, &ep, &env_htab);
free(value);
if (!ep) {
printf("## Error inserting \"%s\" variable, errno=%d\n",
e.key = name;
e.data = NULL;
- ep = hsearch (e, FIND);
+ hsearch_r(e, FIND, &ep, &env_htab);
return (ep ? ep->data : NULL);
}
static int do_env_default(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if ((argc != 2) || (strcmp(argv[1], "-f") != 0)) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
set_default_env("## Resetting to default environment\n");
return 0;
sep = '\n';
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
}
}
if (argc < 1) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
addr = (char *)simple_strtoul(argv[0], NULL, 16);
}
if (sep) { /* export as text file */
- len = hexport(sep, &addr, size);
+ len = hexport_r(&env_htab, sep, &addr, size);
if (len < 0) {
error("Cannot export environment: errno = %d\n",
errno);
else /* export as raw binary data */
res = addr;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n",
errno);
del = 1;
break;
default:
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
}
}
if (argc < 1) {
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
if (!fmt)
addr = (char *)ep->data;
}
- if (himport(addr, size, sep, del ? 0 : H_NOCLEAR) == 0) {
+ if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
};
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+void env_reloc(void)
+{
+ fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub));
+}
+#endif
+
static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *cp;
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
/* drop initial "env" arg */
argc--;
argv++;
if (cp)
return cp->cmd(cmdtp, flag, argc, argv);
- cmd_usage(cmdtp);
- return 1;
+ return cmd_usage(cmdtp);
}
U_BOOT_CMD(
*/
#if defined(CONFIG_CMD_EDITENV)
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
editenv, 2, 0, do_env_edit,
"edit environment variable",
"name\n"
- " - edit environment variable 'name'"
+ " - edit environment variable 'name'",
+ var_complete
);
#endif
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
printenv, CONFIG_SYS_MAXARGS, 1, do_env_print,
"print environment variables",
"\n - print values of all environment variables\n"
"printenv name ...\n"
- " - print value of environment variable 'name'"
+ " - print value of environment variable 'name'",
+ var_complete
);
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
"name value ...\n"
" - set environment variable 'name' to 'value ...'\n"
"setenv name\n"
- " - delete environment variable 'name'"
+ " - delete environment variable 'name'",
+ var_complete
);
#if defined(CONFIG_CMD_ASKENV)
#endif
#if defined(CONFIG_CMD_RUN)
-U_BOOT_CMD(
+U_BOOT_CMD_COMPLETE(
run, CONFIG_SYS_MAXARGS, 1, do_run,
"run commands in an environment variable",
"var [...]\n"
- " - run the commands in the environment variable(s) 'var'"
+ " - run the commands in the environment variable(s) 'var'",
+ var_complete
);
#endif
return 0;
}
-static int onenand_block_write(loff_t to, ssize_t len,
- ssize_t *retlen, const u_char * buf)
+static int onenand_write_oneblock_withoob(loff_t to, const u_char * buf,
+ size_t *retlen)
+{
+ struct mtd_oob_ops ops = {
+ .len = mtd->writesize,
+ .ooblen = mtd->oobsize,
+ .mode = MTD_OOB_AUTO,
+ };
+ int page, ret = 0;
+ for (page = 0; page < (mtd->erasesize / mtd->writesize); page ++) {
+ ops.datbuf = (u_char *)buf;
+ buf += mtd->writesize;
+ ops.oobbuf = (u_char *)buf;
+ buf += mtd->oobsize;
+ ret = mtd->write_oob(mtd, to, &ops);
+ if (ret)
+ break;
+ to += mtd->writesize;
+ }
+
+ *retlen = (ret) ? 0 : mtd->erasesize;
+ return ret;
+}
+
+static int onenand_block_write(loff_t to, size_t len,
+ size_t *retlen, const u_char * buf, int withoob)
{
struct onenand_chip *this = mtd->priv;
int blocksize = (1 << this->erase_shift);
};
loff_t ofs;
size_t thislen;
+ size_t _retlen = 0;
int ret;
if (to == next_ofs) {
goto next;
}
- ops.datbuf = (u_char *) buf;
- ops.len = thislen;
- ops.retlen = 0;
- ret = mtd->write_oob(mtd, ofs, &ops);
+ if (!withoob)
+ ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf);
+ else
+ ret = onenand_write_oneblock_withoob(ofs, buf, &_retlen);
if (ret) {
printk("Write failed 0x%x, %d", (u32)ofs, ret);
skip_ofs += thislen;
addr = (loff_t) off;
memset(&ops, 0, sizeof(ops));
ops.datbuf = datbuf;
- ops.oobbuf = oobbuf; /* must exist, but oob data will be appended to ops.datbuf */
+ ops.oobbuf = oobbuf;
ops.len = mtd->writesize;
ops.ooblen = mtd->oobsize;
ops.retlen = 0;
p += 16;
}
puts("OOB:\n");
- p = oobbuf;
i = mtd->oobsize >> 3;
+ p = oobbuf;
+
while (i--) {
printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
static int do_onenand_write(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, ofs;
- ssize_t len;
- int ret = 0;
- ssize_t retlen = 0;
+ size_t len;
+ int ret = 0, withoob = 0;
+ size_t retlen = 0;
if (argc < 3)
return cmd_usage(cmdtp);
+ if (strncmp(argv[0] + 6, "yaffs", 5) == 0)
+ withoob = 1;
+
addr = (ulong)simple_strtoul(argv[1], NULL, 16);
printf("\nOneNAND write: ");
if (arg_off_size(argc - 2, argv + 2, &ofs, &len) != 0)
return 1;
- ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr);
+ ret = onenand_block_write(ofs, len, &retlen, (u8 *)addr, withoob);
printf(" %d bytes written: %s\n", retlen, ret ? "ERROR" : "OK");
U_BOOT_CMD_MKENT(bad, 1, 0, do_onenand_bad, "", ""),
U_BOOT_CMD_MKENT(read, 4, 0, do_onenand_read, "", ""),
U_BOOT_CMD_MKENT(write, 4, 0, do_onenand_write, "", ""),
+ U_BOOT_CMD_MKENT(write.yaffs, 4, 0, do_onenand_write, "", ""),
U_BOOT_CMD_MKENT(erase, 3, 0, do_onenand_erase, "", ""),
U_BOOT_CMD_MKENT(test, 3, 0, do_onenand_test, "", ""),
U_BOOT_CMD_MKENT(dump, 2, 0, do_onenand_dump, "", ""),
U_BOOT_CMD_MKENT(lock, 3, 0, do_onenand_lock, "", ""),
};
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void onenand_reloc(void) {
fixup_cmdtable(cmd_onenand_sub, ARRAY_SIZE(cmd_onenand_sub));
}
{
cmd_tbl_t *c;
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
mtd = &onenand_mtd;
/* Strip off leading 'onenand' command argument */
"info - show available OneNAND devices\n"
"onenand bad - show bad blocks\n"
"onenand read[.oob] addr off size\n"
- "onenand write addr off size\n"
+ "onenand write[.yaffs] addr off size\n"
" read/write 'size' bytes starting at offset 'off'\n"
" to/from memory address 'addr', skipping bad blocks.\n"
"onenand erase [force] [off size] - erase 'size' bytes from\n"
int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ char *cmd;
uint32_t ret, base_flags;
bool prompt_user, force_read;
uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content);
prompt_user = false;
base_flags = 0;
- if (!strcmp(argv[1], "read"))
+ cmd = argv[1];
+ if (!strcmp(cmd, "read"))
otp_func = bfrom_OtpRead;
- else if (!strcmp(argv[1], "dump")) {
+ else if (!strcmp(cmd, "dump")) {
otp_func = bfrom_OtpRead;
force_read = true;
- } else if (!strcmp(argv[1], "write")) {
+ } else if (!strcmp(cmd, "write")) {
otp_func = bfrom_OtpWrite;
base_flags = OTP_CHECK_FOR_PREV_WRITE;
if (!strcmp(argv[2], "--force")) {
- argv[2] = argv[1];
argv++;
--argc;
} else
prompt_user = false;
- } else if (!strcmp(argv[1], "lock")) {
+ } else if (!strcmp(cmd, "lock")) {
if (argc != 4)
goto usage;
otp_func = bfrom_OtpWrite;
}
printf("OTP memory %s: addr 0x%p page 0x%03X count %zu ... ",
- argv[1], addr, page, count);
+ cmd, addr, page, count);
set_otp_timing(otp_func == bfrom_OtpWrite);
if (otp_func == bfrom_OtpWrite && check_voltage()) {
}
}
-static char *pci_classes_str(u8 class)
-{
- switch (class) {
- case PCI_CLASS_NOT_DEFINED:
- return "Build before PCI Rev2.0";
- break;
- case PCI_BASE_CLASS_STORAGE:
- return "Mass storage controller";
- break;
- case PCI_BASE_CLASS_NETWORK:
- return "Network controller";
- break;
- case PCI_BASE_CLASS_DISPLAY:
- return "Display controller";
- break;
- case PCI_BASE_CLASS_MULTIMEDIA:
- return "Multimedia device";
- break;
- case PCI_BASE_CLASS_MEMORY:
- return "Memory controller";
- break;
- case PCI_BASE_CLASS_BRIDGE:
- return "Bridge device";
- break;
- case PCI_BASE_CLASS_COMMUNICATION:
- return "Simple comm. controller";
- break;
- case PCI_BASE_CLASS_SYSTEM:
- return "Base system peripheral";
- break;
- case PCI_BASE_CLASS_INPUT:
- return "Input device";
- break;
- case PCI_BASE_CLASS_DOCKING:
- return "Docking station";
- break;
- case PCI_BASE_CLASS_PROCESSOR:
- return "Processor";
- break;
- case PCI_BASE_CLASS_SERIAL:
- return "Serial bus controller";
- break;
- case PCI_BASE_CLASS_INTELLIGENT:
- return "Intelligent controller";
- break;
- case PCI_BASE_CLASS_SATELLITE:
- return "Satellite controller";
- break;
- case PCI_BASE_CLASS_CRYPT:
- return "Cryptographic device";
- break;
- case PCI_BASE_CLASS_SIGNAL_PROCESSING:
- return "DSP";
- break;
- case PCI_CLASS_OTHERS:
- return "Does not fit any class";
- break;
- default:
- return "???";
- break;
- };
-}
/*
* Subroutine: pci_header_show_brief
printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
vendor, device,
- pci_classes_str(class), subclass);
+ pci_class_str(class), subclass);
}
/*
PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
- pci_classes_str);
+ pci_class_str);
PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
if ((bdf = get_pci_dev(argv[2])) == -1)
return 1;
break;
+#ifdef CONFIG_CMD_PCI_ENUM
+ case 'e':
+ break;
+#endif
default: /* scan bus */
value = 1; /* short listing */
bdf = 0; /* bus number */
return 0;
case 'd': /* display */
return pci_cfg_display(bdf, addr, size, value);
+#ifdef CONFIG_CMD_PCI_ENUM
+ case 'e':
+ pci_init();
+ return 0;
+#endif
case 'n': /* next */
if (argc < 4)
goto usage;
"list and access PCI Configuration Space",
"[bus] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
+#ifdef CONFIG_CMD_PCI_ENUM
+ "pci enum\n"
+ " - re-enumerate PCI buses\n"
+#endif
"pci header b.d.f\n"
" - show header of PCI device 'bus.device.function'\n"
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
flush_cache (addr, (cnt+1)*info.blksz);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
/*
* Values from last command.
*/
-static unsigned int device;
+static unsigned int bus;
+static unsigned int cs;
+static unsigned int mode;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
if ((flag & CMD_FLAG_REPEAT) == 0)
{
- if (argc >= 2)
- device = simple_strtoul(argv[1], NULL, 10);
+ if (argc >= 2) {
+ mode = CONFIG_DEFAULT_SPI_MODE;
+ bus = simple_strtoul(argv[1], &cp, 10);
+ if (*cp == ':') {
+ cs = simple_strtoul(cp+1, &cp, 10);
+ } else {
+ cs = bus;
+ bus = CONFIG_DEFAULT_SPI_BUS;
+ }
+ if (*cp == '.');
+ mode = simple_strtoul(cp+1, NULL, 10);
+ }
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
if (argc >= 4) {
if(tmp > 15)
tmp -= ('a' - 'A');
if(tmp > 15) {
- printf("Hex conversion error on %c, giving up.\n", *cp);
+ printf("Hex conversion error on %c\n", *cp);
return 1;
}
if((j % 2) == 0)
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
- printf("Invalid bitlen %d, giving up.\n", bitlen);
+ printf("Invalid bitlen %d\n", bitlen);
return 1;
}
- /* FIXME: Make these parameters run-time configurable */
- slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000,
- CONFIG_DEFAULT_SPI_MODE);
+ slave = spi_setup_slave(bus, cs, 1000000, mode);
if (!slave) {
- printf("Invalid device %d, giving up.\n", device);
+ printf("Invalid device %d:%d\n", bus, cs);
return 1;
}
- debug ("spi chipsel = %08X\n", device);
-
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
- printf("Error with the SPI transaction.\n");
+ printf("Error during SPI transaction\n");
rcode = 1;
} else {
for(j = 0; j < ((bitlen + 7) / 8); j++) {
U_BOOT_CMD(
sspi, 5, 1, do_spi,
- "SPI utility commands",
- "<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
- "<device> - Identifies the chip select of the device\n"
+ "SPI utility command",
+ "[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n"
+ "<bus> - Identifies the SPI bus\n"
+ "<cs> - Identifies the chip select\n"
+ "<mode> - Identifies the SPI mode to use\n"
"<bit_len> - Number of bits to send (base 10)\n"
"<dout> - Hexadecimal string that gets sent"
);
if (argc > 5)
vam = simple_strtoul(argv[5], NULL, 16);
if (argc > 6)
- vdw = simple_strtoul(argv[7], NULL, 16);
+ vdw = simple_strtoul(argv[6], NULL, 16);
switch (cmd) {
case 'c':
}
U_BOOT_CMD(
- tsi148, 8, 1, do_tsi148,
+ tsi148, 7, 1, do_tsi148,
"initialize and configure Turndra Tsi148\n",
"init\n"
" - initialize tsi148\n"
static struct selected_dev ubi_dev;
+#ifdef CONFIG_CMD_UBIFS
+int ubifs_is_mounted(void);
+void cmd_ubifs_umount(void);
+#endif
+
static void ubi_dump_vol_info(const struct ubi_volume *vol)
{
ubi_msg("volume information dump:");
if (argc < 3)
return cmd_usage(cmdtp);
+#ifdef CONFIG_CMD_UBIFS
+ /*
+ * Automatically unmount UBIFS partition when user
+ * changes the UBI device. Otherwise the following
+ * UBIFS commands will crash.
+ */
+ if (ubifs_is_mounted())
+ cmd_ubifs_umount();
+#endif
+
/* todo: get dev number for NAND... */
ubi_dev.nr = 0;
#include <config.h>
#include <command.h>
+#include "../fs/ubifs/ubifs.h"
+
static int ubifs_initialized;
static int ubifs_mounted;
+extern struct super_block *ubifs_sb;
+
/* Prototypes */
int ubifs_init(void);
int ubifs_mount(char *vol_name);
+void ubifs_umount(struct ubifs_info *c);
int ubifs_ls(char *dir_name);
int ubifs_load(char *filename, u32 addr, u32 size);
return 0;
}
+int ubifs_is_mounted(void)
+{
+ return ubifs_mounted;
+}
+
+void cmd_ubifs_umount(void)
+{
+
+ if (ubifs_sb) {
+ printf("Unmounting UBIFS volume %s!\n",
+ ((struct ubifs_info *)(ubifs_sb->s_fs_info))->vi.name);
+ ubifs_umount(ubifs_sb->s_fs_info);
+ }
+
+ ubifs_sb = NULL;
+ ubifs_mounted = 0;
+ ubifs_initialized = 0;
+}
+
+int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 1)
+ return cmd_usage(cmdtp);
+
+ if (ubifs_initialized == 0) {
+ printf("No UBIFS volume mounted!\n");
+ return -1;
+ }
+
+ cmd_ubifs_umount();
+
+ return 0;
+}
+
int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *filename = "/";
int ret;
if (!ubifs_mounted) {
- printf("UBIFS not mounted, use ubifs mount to mount volume first!\n");
+ printf("UBIFS not mounted, use ubifsmount to mount volume first!\n");
return -1;
}
);
U_BOOT_CMD(
+ ubifsumount, 1, 0, do_ubifs_umount,
+ "unmount UBIFS volume",
+ " - unmount current volume"
+);
+
+U_BOOT_CMD(
ubifsls, 2, 0, do_ubifs_ls,
"list files in a directory",
"[directory]\n"
flush_cache(addr, (cnt+1)*info.blksz);
/* Check if we should attempt an auto-start */
- if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+ if (getenv_yesno("autostart")) {
char *local_args[2];
- extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
local_args[0] = argv[0];
local_args[1] = NULL;
printf("Automatic boot of image at addr 0x%08lX ...\n", addr);
static int down_mode;
-/* cpu/${CPU} dependent */
-extern void do_reset(void);
-
/* common commands */
-extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int do_run(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+#ifdef CONFIG_CMD_UBI
+static int check_ubi_mode(void)
+{
+ char *env_ubifs;
+ int ubi_mode;
+
+ env_ubifs = getenv("ubi");
+ ubi_mode = !strcmp(env_ubifs, "enabled");
+
+ return ubi_mode;
+}
+#else
+#define check_ubi_mode() 0
+#endif
+
+#ifdef CONFIG_CMD_MTDPARTS
int mtdparts_init(void);
int find_dev_and_part(const char*, struct mtd_device**, u8*, struct part_info**);
return part_num;
}
-#ifdef CONFIG_CMD_UBI
-static int check_ubi_mode(void)
-{
- char *env_ubifs;
- int ubi_mode;
-
- env_ubifs = getenv("ubi");
- ubi_mode = !strcmp(env_ubifs, "enabled");
-
- return ubi_mode;
-}
-#else
-#define check_ubi_mode() 0
-#endif
-
-#ifdef CONFIG_MTD_PARTITIONS
static int get_part_info(void)
{
struct mtd_device *dev;
{
int ret = 0;
+#ifdef CONFIG_CMD_MTDPARTS
#ifdef CONFIG_CMD_UBI
/* UBI Update */
if (ubi_update) {
fs_offset += len;
ret = nand_cmd(1, ramaddr, offset, length);
+#endif
return ret;
}
/* Erase the qboot */
static void erase_qboot_area(void)
{
+#ifdef CONFIG_CMD_MTDPARTS
char offset[12], length[12];
int qboot_id;
nand_cmd(0, offset, length, NULL);
qboot_erase = 1;
}
+#endif
}
/* Erase the environment */
static int write_mtd_image(struct usbd_ops *usbd, int img_type,
unsigned int len, unsigned int arg)
{
+ int ret = -1;
+#ifdef CONFIG_CMD_MTDPARTS
unsigned int ofs = 0;
char offset[12], length[12], ramaddr[12];
- int ret;
sprintf(ramaddr, "0x%x", (uint) down_ram_addr);
/* Retry? */
write_part--;
}
-
+#endif
return ret;
}
#endif
printf("COMMAND_PARTITION_SYNC - Part%d\n", part_id);
+#ifdef CONFIG_CMD_MTDPARTS
blocks = parts[part_id]->size / 1024 / 128;
+#endif
printf("COMMAND_PARTITION_SYNC - Part%d, %d blocks\n",
part_id, blocks);
if (usbd->cpu_reset)
usbd->cpu_reset();
else
- do_reset();
+ run_command("reset", 0);
return 0;
usbd_path_change();
- do_reset();
+ run_command("reset", 0);
return 0;
#endif
case COMMAND_CSA_CLEAR:
int len;
int n_found = 0;
+ if (!cmd)
+ return NULL;
/*
* Some commands allow length modifiers (like "cp.b");
* compare command name only until first dot.
return 0;
}
-static void install_auto_complete_handler(const char *cmd,
- int (*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]))
-{
- cmd_tbl_t *cmdtp;
-
- cmdtp = find_cmd(cmd);
- if (cmdtp == NULL)
- return;
-
- cmdtp->complete = complete;
-}
-
-void install_auto_complete(void)
-{
-#if defined(CONFIG_CMD_EDITENV)
- install_auto_complete_handler("editenv", var_complete);
-#endif
- install_auto_complete_handler("printenv", var_complete);
- install_auto_complete_handler("setenv", var_complete);
-#if defined(CONFIG_CMD_RUN)
- install_auto_complete_handler("run", var_complete);
-#endif
-}
-
/*************************************************************************************/
static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
}
#endif
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
DECLARE_GLOBAL_DATA_PTR;
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size)
/** U-Boot INIT FUNCTIONS *************************************************/
-struct stdio_dev *search_device(int flags, char *name)
+struct stdio_dev *search_device(int flags, const char *name)
{
struct stdio_dev *dev;
return NULL;
}
-int console_assign(int file, char *devname)
+int console_assign(int file, const char *devname)
{
int flag;
struct stdio_dev *dev;
INTERNAL_SIZE_T size; /* Size in bytes, including overhead. */
struct malloc_chunk* fd; /* double links -- used only if free. */
struct malloc_chunk* bk;
-};
+} __attribute__((__may_alias__)) ;
typedef struct malloc_chunk* mchunkptr;
IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127)
};
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void malloc_bin_reloc (void)
{
unsigned long *p = (unsigned long *)(&av_[2]);
ulong old = mem_malloc_brk;
ulong new = old + increment;
+ /*
+ * if we are giving memory back make sure we clear it out since
+ * we set MORECORE_CLEARS to 1
+ */
+ if (increment < 0)
+ memset((void *)new, 0, -increment);
+
if ((new < mem_malloc_start) || (new > mem_malloc_end))
return (void *)MORECORE_FAILURE;
"\0"
};
+struct hsearch_data env_htab;
+
static uchar env_get_char_init (int index)
{
uchar c;
puts("Using default environment\n\n");
}
- if (himport((char *)default_environment,
+ if (himport_r(&env_htab, (char *)default_environment,
sizeof(default_environment), '\0', 0) == 0) {
error("Environment import failed: errno = %d\n", errno);
}
}
}
- if (himport((char *)ep->data, ENV_SIZE, '\0', 0)) {
+ if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) {
gd->flags |= GD_FLG_ENV_READY;
return 1;
}
void env_relocate (void)
{
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+ extern void env_reloc(void);
+
+ env_reloc();
+#endif
if (gd->env_valid == 0) {
#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
set_default_env(NULL);
#else
show_boot_progress (-60);
-#endif
set_default_env("!bad CRC");
+#endif
} else {
env_relocate_spec ();
}
char *res;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
BUG_ON(env_ptr != NULL);
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return (*((uchar *)(gd->env_addr + index)));
}
-#undef debug
-#define debug printf
-
#ifdef CONFIG_ENV_ADDR_REDUND
int env_init(void)
}
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
goto done;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
goto done;
#endif /* ENV_IS_EMBEDDED */
/* local functions */
+#if !defined(ENV_IS_EMBEDDED)
+static void use_default(void);
+#endif
DECLARE_GLOBAL_DATA_PTR;
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)&env_new)) {
puts("failed\n");
return (n == blk_cnt) ? 0 : -1;
}
-#if !defined(ENV_IS_EMBEDDED)
-static void use_default()
-{
- set_default_env(NULL);
-}
-#endif
-
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
- char buf[CONFIG_ENV_SIZE];
+ char buf[CONFIG_ENV_SIZE];
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
env_import(buf, 1);
#endif
}
+
+#if !defined(ENV_IS_EMBEDDED)
+static void use_default()
+{
+ set_default_env(NULL);
+}
+#endif
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
return 1;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
offset += blocksize;
} else {
char_ptr = &buf[amount_loaded];
- if (nand_read(&nand_info[0], offset, &len, char_ptr))
+ if (nand_read_skip_bad(&nand_info[0], offset, &len, char_ptr))
return 1;
offset += blocksize;
amount_loaded += len;
int rcode = 0;
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
};
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
#define ACTIVE_FLAG 1
#define OBSOLETE_FLAG 0
-#endif /* CONFIG_ENV_ADDR_REDUND */
+#endif /* CONFIG_ENV_OFFSET_REDUND */
DECLARE_GLOBAL_DATA_PTR;
}
#if defined(CONFIG_ENV_OFFSET_REDUND)
-void swap_env(void)
-{
- ulong tmp_offset = env_offset;
-
- env_offset = env_new_offset;
- env_new_offset = tmp_offset;
-}
int saveenv(void)
{
char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG;
if (!env_flash) {
- puts("Environment SPI flash not initialized\n");
- return 1;
+ env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (!env_flash) {
+ set_default_env("!spi_flash_probe() failed");
+ return 1;
+ }
}
res = (char *)&env_new.data;
- len = hexport('\0', &res, ENV_SIZE);
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
env_new.crc = crc32(0, env_new.data, ENV_SIZE);
env_new.flags = ACTIVE_FLAG;
+ if (gd->env_valid == 1) {
+ env_new_offset = CONFIG_ENV_OFFSET_REDUND;
+ env_offset = CONFIG_ENV_OFFSET;
+ } else {
+ env_new_offset = CONFIG_ENV_OFFSET;
+ env_offset = CONFIG_ENV_OFFSET_REDUND;
+ }
+
/* Is the sector larger than the env (i.e. embedded) */
if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE;
goto done;
puts("Writing to SPI flash...");
- ret = spi_flash_write(env_flash,
- env_new_offset + offsetof(env_t, data),
- sizeof(env_new.data), env_new.data);
- if (ret)
- goto done;
-
- ret = spi_flash_write(env_flash,
- env_new_offset + offsetof(env_t, crc),
- sizeof(env_new.crc), &env_new.crc);
- if (ret)
- goto done;
- ret = spi_flash_write(env_flash,
- env_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag);
- if (ret)
- goto done;
-
- ret = spi_flash_write(env_flash,
- env_new_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &new_flag);
+ ret = spi_flash_write(env_flash, env_new_offset,
+ CONFIG_ENV_SIZE, &env_new);
if (ret)
goto done;
goto done;
}
- swap_env();
+ ret = spi_flash_write(env_flash,
+ env_offset + offsetof(env_t, flags),
+ sizeof(env_new.flags), &flag);
+ if (ret)
+ goto done;
- ret = 0;
puts("done\n");
+ gd->env_valid = (gd->env_valid == 2 ? 1 : 2);
+
+ printf("Valid environment: %d\n", gd->env_valid);
+
done:
if (saved_buffer)
free(saved_buffer);
int crc1_ok = 0, crc2_ok = 0;
env_t *tmp_env1 = NULL;
env_t *tmp_env2 = NULL;
- env_t ep;
+ env_t *ep = NULL;
uchar flag1, flag2;
/* current_env is set only in case both areas are valid! */
int current_env = 0;
flag2 = tmp_env2->flags;
}
- if (!crc1_ok && !crc2_ok)
- goto err_crc;
- else if (crc1_ok && !crc2_ok) {
+ if (!crc1_ok && !crc2_ok) {
+ free(tmp_env1);
+ free(tmp_env2);
+ set_default_env("!bad CRC");
+ return;
+ } else if (crc1_ok && !crc2_ok) {
gd->env_valid = 1;
ep = tmp_env1;
} else if (!crc1_ok && crc2_ok) {
gd->env_valid = 1;
- ep = tmp_env2;
- swap_env();
} else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) {
gd->env_valid = 1;
- ep = tmp_env1;
} else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) {
- gd->env_valid = 1;
- ep = tmp_env2;
- swap_env();
+ gd->env_valid = 2;
} else if (flag1 == flag2) {
gd->env_valid = 2;
- ep = tmp_env1;
- current_env = 1;
} else if (flag1 == 0xFF) {
gd->env_valid = 2;
- ep = tmp_env1;
- current_env = 1;
} else {
/*
* this differs from code in env_flash.c, but I think a sane
* default path is desirable.
*/
gd->env_valid = 2;
- ep = tmp_env2;
- swap_env();
- current_env = 2;
}
- rc = env_import((char *)ep, 0);
- if (!rc) {
- error("Cannot import environment: errno = %d\n", errno);
- goto out;
- }
+ free(env_ptr);
- if (current_env == 1) {
- if (flag2 != OBSOLETE_FLAG) {
- flag2 = OBSOLETE_FLAG;
- spi_flash_write(env_flash,
- env_new_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag2);
- }
- if (flag1 != ACTIVE_FLAG) {
- flag1 = ACTIVE_FLAG;
- spi_flash_write(env_flash,
- env_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag1);
- }
- } else if (current_env == 2) {
- if (flag1 != OBSOLETE_FLAG) {
- flag1 = OBSOLETE_FLAG;
- spi_flash_write(env_flash,
- env_new_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag1);
- }
- if (flag2 != ACTIVE_FLAG) {
- flag2 = ACTIVE_FLAG;
- spi_flash_write(env_flash,
- env_offset + offsetof(env_t, flags),
- sizeof(env_new.flags), &flag2);
- }
- }
- if (gd->env_valid == 2) {
- puts("*** Warning - some problems detected "
- "reading environment; recovered successfully\n\n");
+ if (gd->env_valid == 1)
+ ep = tmp_env1;
+ else
+ ep = tmp_env2;
+
+ ret = env_import((char *)ep, 0);
+ if (!ret) {
+ error("Cannot import environment: errno = %d\n", errno);
+ set_default_env("env_import failed");
}
- if (tmp_env1)
- free(tmp_env1);
- if (tmp_env2)
- free(tmp_env2);
- return;
err_read:
spi_flash_free(env_flash);
env_flash = NULL;
out:
+ if (tmp_env1)
+ free(tmp_env1);
+ if (tmp_env2)
+ free(tmp_env2);
free(tmp_env1);
free(tmp_env2);
+
+ return;
}
#else
int saveenv(void)
u32 saved_size, saved_offset;
char *saved_buffer = NULL;
u32 sector = 1;
- int ret;
+ int ret = 1;
+ env_t env_new;
+ char *res;
+ ssize_t len;
if (!env_flash) {
- puts("Environment SPI flash not initialized\n");
- return 1;
+ env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (!env_flash) {
+ set_default_env("!spi_flash_probe() failed");
+ return 1;
+ }
}
/* Is the sector larger than the env (i.e. embedded) */
saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE;
saved_buffer = malloc(saved_size);
if (!saved_buffer) {
- ret = 1;
goto done;
}
- ret = spi_flash_read(env_flash, saved_offset, saved_size, saved_buffer);
+ ret = spi_flash_read(env_flash, saved_offset,
+ saved_size, saved_buffer);
if (ret)
goto done;
}
sector++;
}
+ res = (char *)&env_new.data;
+ len = hexport_r(&env_htab, '\0', &res, ENV_SIZE);
+ if (len < 0) {
+ error("Cannot export environment: errno = %d\n", errno);
+ goto done;
+ }
+ env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+
puts("Erasing SPI flash...");
- ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE);
+ ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET,
+ sector * CONFIG_ENV_SECT_SIZE);
if (ret)
goto done;
puts("Writing to SPI flash...");
- ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr);
+ ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET,
+ CONFIG_ENV_SIZE, &env_new);
if (ret)
goto done;
if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
- ret = spi_flash_write(env_flash, saved_offset, saved_size, saved_buffer);
+ ret = spi_flash_write(env_flash, saved_offset,
+ saved_size, saved_buffer);
if (ret)
goto done;
}
do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
}
-int fdt_fixup_memory(void *blob, u64 start, u64 size)
+/*
+ * Get cells len in bytes
+ * if #NNNN-cells property is 2 then len is 8
+ * otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+ const u32 *cell;
+
+ cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ if (cell && *cell == 2)
+ return 8;
+
+ return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+ int shift = (size - 1) * 8;
+ while (size-- > 0) {
+ *addr++ = (val >> shift) & 0xff;
+ shift -= 8;
+ }
+}
+
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
- int err, nodeoffset, len = 0;
- u8 tmp[16];
- const u32 *addrcell, *sizecell;
+ int err, nodeoffset;
+ int addr_cell_len, size_cell_len, len;
+ u8 tmp[banks * 8];
+ int bank;
err = fdt_check_header(blob);
if (err < 0) {
return err;
}
- addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
- /* use shifts and mask to ensure endianness */
- if ((addrcell) && (*addrcell == 2)) {
- tmp[0] = (start >> 56) & 0xff;
- tmp[1] = (start >> 48) & 0xff;
- tmp[2] = (start >> 40) & 0xff;
- tmp[3] = (start >> 32) & 0xff;
- tmp[4] = (start >> 24) & 0xff;
- tmp[5] = (start >> 16) & 0xff;
- tmp[6] = (start >> 8) & 0xff;
- tmp[7] = (start ) & 0xff;
- len = 8;
- } else {
- tmp[0] = (start >> 24) & 0xff;
- tmp[1] = (start >> 16) & 0xff;
- tmp[2] = (start >> 8) & 0xff;
- tmp[3] = (start ) & 0xff;
- len = 4;
- }
+ addr_cell_len = get_cells_len(blob, "#address-cells");
+ size_cell_len = get_cells_len(blob, "#size-cells");
+
+ for (bank = 0, len = 0; bank < banks; bank++) {
+ write_cell(tmp + len, start[bank], addr_cell_len);
+ len += addr_cell_len;
- sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
- /* use shifts and mask to ensure endianness */
- if ((sizecell) && (*sizecell == 2)) {
- tmp[0+len] = (size >> 56) & 0xff;
- tmp[1+len] = (size >> 48) & 0xff;
- tmp[2+len] = (size >> 40) & 0xff;
- tmp[3+len] = (size >> 32) & 0xff;
- tmp[4+len] = (size >> 24) & 0xff;
- tmp[5+len] = (size >> 16) & 0xff;
- tmp[6+len] = (size >> 8) & 0xff;
- tmp[7+len] = (size ) & 0xff;
- len += 8;
- } else {
- tmp[0+len] = (size >> 24) & 0xff;
- tmp[1+len] = (size >> 16) & 0xff;
- tmp[2+len] = (size >> 8) & 0xff;
- tmp[3+len] = (size ) & 0xff;
- len += 4;
+ write_cell(tmp + len, size[bank], size_cell_len);
+ len += size_cell_len;
}
err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
return 0;
}
+int fdt_fixup_memory(void *blob, u64 start, u64 size)
+{
+ return fdt_fixup_memory_banks(blob, &start, &size, 1);
+}
+
void fdt_fixup_ethernet(void *fdt)
{
int node, i, j;
int off;
int len;
struct fdt_property *prop;
- u32 *reg;
+ u32 *reg, *reg2;
int i;
for (i = 0; i < 2; i++) {
* There might be multiple reg-tuples,
* so loop through them all
*/
- len /= tuple_size;
- reg = (u32 *)&prop->data[0];
- for (idx = 0; idx < len; idx++) {
+ reg = reg2 = (u32 *)&prop->data[0];
+ for (idx = 0; idx < (len / tuple_size); idx++) {
/*
* Update size in reg property
*/
reg[2] = flash_get_bank_size(reg[0],
idx);
- fdt_setprop(blob, off, "reg", reg,
- tuple_size);
- reg += tuple_size;
+
+ /*
+ * Point to next reg tuple
+ */
+ reg += 3;
}
+
+ fdt_setprop(blob, off, "reg", reg2, len);
}
/* Move to next compatible node */
}
#endif
+int fdt_increase_size(void *fdt, int add_len)
+{
+ int newlen;
+
+ newlen = fdt_totalsize(fdt) + add_len;
+
+ /* Open in place with a new len */
+ return fdt_open_into(fdt, fdt, newlen);
+}
+
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
return 0;
}
-int fdt_increase_size(void *fdt, int add_len)
-{
- int newlen;
-
- newlen = fdt_totalsize(fdt) + add_len;
-
- /* Open in place with a new len */
- return fdt_open_into(fdt, fdt, newlen);
-}
-
int fdt_del_partitions(void *blob, int parent_offset)
{
const void *prop;
if (addrc) {
prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
if (prop)
- *addrc = be32_to_cpup(prop);
+ *addrc = be32_to_cpup((u32 *)prop);
else
*addrc = 2;
}
if (sizec) {
prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
if (prop)
- *sizec = be32_to_cpup(prop);
+ *sizec = be32_to_cpup((u32 *)prop);
else
*sizec = 1;
}
return phandle + 1;
}
+
+#if defined(CONFIG_VIDEO)
+int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf)
+{
+ int noff;
+ int ret;
+
+ noff = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (noff != -FDT_ERR_NOTFOUND) {
+ debug("%s: %s\n", fdt_get_name(blob, noff, 0), compat);
+add_edid:
+ ret = fdt_setprop(blob, noff, "edid", edid_buf, 128);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(blob, 512);
+ if (!ret)
+ goto add_edid;
+ else
+ goto err_size;
+ } else if (ret < 0) {
+ printf("Can't add property: %s\n", fdt_strerror(ret));
+ return ret;
+ }
+ }
+ return 0;
+err_size:
+ printf("Can't increase blob size: %s\n", fdt_strerror(ret));
+ return ret;
+}
+#endif
#include <common.h> /* readline */
#include <hush.h>
#include <command.h> /* find_cmd */
-/*cmd_boot.c*/
-extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* do_bootd */
#endif
#ifndef __U_BOOT__
#include <ctype.h> /* isalpha, isdigit */
static char the_command[CONFIG_SYS_CBSIZE];
#ifdef CONFIG_BOOT_RETRY_TIME
-# ifdef CONFIG_RESET_TO_RETRY
- extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-# else
+# ifndef CONFIG_RESET_TO_RETRY
# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
# endif
reset_cmd_timeout();
} else {
int rcode;
#if defined(CONFIG_CMD_BOOTD)
- extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
/* avoid "bootd" recursion */
if (cmdtp->cmd == do_bootd) {
if (flag & CMD_FLAG_BOOTD) {
}
#ifdef __U_BOOT__
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
static void u_boot_hush_reloc(void)
{
unsigned long addr;
top_vars->next = 0;
top_vars->flg_export = 0;
top_vars->flg_read_only = 1;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
u_boot_hush_reloc();
#endif
}
#define min(a, b) (((a) < (b)) ? (a) : (b))
#endif /* HWCONFIG_TEST */
+DECLARE_GLOBAL_DATA_PTR;
+
static const char *hwconfig_parse(const char *opts, size_t maxlen,
const char *opt, char *stopchs, char eqch,
size_t *arglen)
return NULL;
}
-const char *cpu_hwconfig __attribute__((weak));
-const char *board_hwconfig __attribute__((weak));
+const char cpu_hwconfig[] __attribute__((weak)) = "";
+const char board_hwconfig[] __attribute__((weak)) = "";
+
+#define HWCONFIG_PRE_RELOC_BUF_SIZE 128
static const char *__hwconfig(const char *opt, size_t *arglen)
{
- const char *env_hwconfig = getenv("hwconfig");
-
- if (env_hwconfig)
- return hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
- opt, ";", ':', arglen);
+ const char *env_hwconfig = NULL, *ret;
+ char buf[HWCONFIG_PRE_RELOC_BUF_SIZE];
+
+ if (gd->flags & GD_FLG_ENV_READY) {
+ env_hwconfig = getenv("hwconfig");
+ } else {
+ /*
+ * Use our own on stack based buffer before relocation to allow
+ * accessing longer hwconfig strings that might be in the
+ * environment before we've relocated. This is pretty fragile
+ * on both the use of stack and if the buffer is big enough.
+ * However we will get a warning from getenv_f for the later.
+ */
+ if ((getenv_f("hwconfig", buf, sizeof(buf))) > 0)
+ env_hwconfig = buf;
+ }
- if (board_hwconfig)
- return hwconfig_parse(board_hwconfig, strlen(board_hwconfig),
+ if (env_hwconfig) {
+ ret = hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
opt, ";", ':', arglen);
+ if (ret)
+ return ret;
+ }
- if (cpu_hwconfig)
- return hwconfig_parse(cpu_hwconfig, strlen(cpu_hwconfig),
- opt, ";", ':', arglen);
+ ret = hwconfig_parse(board_hwconfig, strlen(board_hwconfig),
+ opt, ";", ':', arglen);
+ if (ret)
+ return ret;
- return NULL;
+ return hwconfig_parse(cpu_hwconfig, strlen(cpu_hwconfig),
+ opt, ";", ':', arglen);
}
/*
#include <image.h>
#endif /* !USE_HOSTCC*/
-static table_entry_t uimage_arch[] = {
+static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, NULL, "Invalid ARCH", },
{ IH_ARCH_ALPHA, "alpha", "Alpha", },
{ IH_ARCH_ARM, "arm", "ARM", },
{ -1, "", "", },
};
-static table_entry_t uimage_os[] = {
+static const table_entry_t uimage_os[] = {
{ IH_OS_INVALID, NULL, "Invalid OS", },
{ IH_OS_LINUX, "linux", "Linux", },
#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
{ -1, "", "", },
};
-static table_entry_t uimage_type[] = {
+static const table_entry_t uimage_type[] = {
{ IH_TYPE_INVALID, NULL, "Invalid Image", },
{ IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", },
{ IH_TYPE_FIRMWARE, "firmware", "Firmware", },
{ -1, "", "", },
};
-static table_entry_t uimage_comp[] = {
+static const table_entry_t uimage_comp[] = {
{ IH_COMP_NONE, "none", "uncompressed", },
{ IH_COMP_BZIP2, "bzip2", "bzip2 compressed", },
{ IH_COMP_GZIP, "gzip", "gzip compressed", },
* long entry name if translation succeeds
* msg otherwise
*/
-char *get_table_entry_name (table_entry_t *table, char *msg, int id)
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id)
{
for (; table->id >= 0; ++table) {
if (table->id == id)
-#if defined(USE_HOSTCC) || defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
return table->lname;
#else
return table->lname + gd->reloc_off;
* entry id if translation succeeds
* -1 otherwise
*/
-int get_table_entry_id (table_entry_t *table,
+int get_table_entry_id(const table_entry_t *table,
const char *table_name, const char *name)
{
- table_entry_t *t;
+ const table_entry_t *t;
#ifdef USE_HOSTCC
int first = 1;
fprintf (stderr, "\n");
#else
for (t = table; t->id >= 0; ++t) {
-#ifdef CONFIG_RELOC_FIXUP_WORKS
- if (t->sname && strcmp(t->sname, name) == 0)
-#else
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
if (t->sname && strcmp(t->sname + gd->reloc_off, name) == 0)
+#else
+ if (t->sname && strcmp(t->sname, name) == 0)
#endif
return (t->id);
}
return 0;
}
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
/**
* boot_ramdisk_high - relocate init ramdisk
* @lmb: pointer to lmb handle, will be used for memory mgmt
error:
return -1;
}
-#endif /* defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) */
+#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
#ifdef CONFIG_OF_LIBFDT
static void fdt_error (const char *msg)
* @of_flat_tree: pointer to a char* variable, will hold fdt start address
* @of_size: pointer to a ulong variable, will hold fdt length
*
- * boot_relocate_fdt() determines if the of_flat_tree address is within
- * the bootmap and if not relocates it into that region
+ * boot_relocate_fdt() allocates a region of memory within the bootmap and
+ * relocates the of_flat_tree into that region, even if the fdt is already in
+ * the bootmap. It also expands the size of the fdt by CONFIG_SYS_FDT_PAD
+ * bytes.
*
* of_flat_tree and of_size are set to final (after relocation) values
*
int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base,
char **of_flat_tree, ulong *of_size)
{
- char *fdt_blob = *of_flat_tree;
- ulong relocate = 0;
+ void *fdt_blob = *of_flat_tree;
+ void *of_start = 0;
ulong of_len = 0;
+ int err;
/* nothing to do */
if (*of_size == 0)
goto error;
}
-#ifndef CONFIG_SYS_NO_FLASH
- /* move the blob if it is in flash (set relocate) */
- if (addr2info ((ulong)fdt_blob) != NULL)
- relocate = 1;
-#endif
-
- /*
- * The blob needs to be inside the boot mapping.
- */
- if (fdt_blob < (char *)bootmap_base)
- relocate = 1;
-
- if ((fdt_blob + *of_size + CONFIG_SYS_FDT_PAD) >=
- ((char *)CONFIG_SYS_BOOTMAPSZ + bootmap_base))
- relocate = 1;
-
- /* move flattend device tree if needed */
- if (relocate) {
- int err;
- ulong of_start = 0;
-
- /* position on a 4K boundary before the alloc_current */
- /* Pad the FDT by a specified amount */
- of_len = *of_size + CONFIG_SYS_FDT_PAD;
- of_start = (unsigned long)lmb_alloc_base(lmb, of_len, 0x1000,
- (CONFIG_SYS_BOOTMAPSZ + bootmap_base));
-
- if (of_start == 0) {
- puts("device tree - allocation error\n");
- goto error;
- }
-
- debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
- (ulong)fdt_blob, (ulong)fdt_blob + *of_size - 1,
- of_len, of_len);
+ /* position on a 4K boundary before the alloc_current */
+ /* Pad the FDT by a specified amount */
+ of_len = *of_size + CONFIG_SYS_FDT_PAD;
+ of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000,
+ (CONFIG_SYS_BOOTMAPSZ + bootmap_base));
- printf (" Loading Device Tree to %08lx, end %08lx ... ",
- of_start, of_start + of_len - 1);
+ if (of_start == 0) {
+ puts("device tree - allocation error\n");
+ goto error;
+ }
- err = fdt_open_into (fdt_blob, (void *)of_start, of_len);
- if (err != 0) {
- fdt_error ("fdt move failed");
- goto error;
- }
- puts ("OK\n");
+ debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n",
+ fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
- *of_flat_tree = (char *)of_start;
- *of_size = of_len;
- } else {
- *of_flat_tree = fdt_blob;
- of_len = (CONFIG_SYS_BOOTMAPSZ + bootmap_base) - (ulong)fdt_blob;
- lmb_reserve(lmb, (ulong)fdt_blob, of_len);
- fdt_set_totalsize(*of_flat_tree, of_len);
+ printf (" Loading Device Tree to %p, end %p ... ",
+ of_start, of_start + of_len - 1);
- *of_size = of_len;
+ err = fdt_open_into (fdt_blob, of_start, of_len);
+ if (err != 0) {
+ fdt_error ("fdt move failed");
+ goto error;
}
+ puts ("OK\n");
+
+ *of_flat_tree = of_start;
+ *of_size = of_len;
set_working_fdt_addr(*of_flat_tree);
return 0;
goto error;
}
- if (be32_to_cpu (fdt_totalsize (fdt_blob)) != fdt_len) {
+ if (fdt_totalsize(fdt_blob) != fdt_len) {
fdt_error ("fdt size != image size");
goto error;
}
}
*of_flat_tree = fdt_blob;
- *of_size = be32_to_cpu (fdt_totalsize (fdt_blob));
+ *of_size = fdt_totalsize(fdt_blob);
debug (" of_flat_tree at 0x%08lx size 0x%08lx\n",
(ulong)*of_flat_tree, *of_size);
}
#endif /* CONFIG_OF_LIBFDT */
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
/**
* boot_get_cmdline - allocate and initialize kernel cmdline
* @lmb: pointer to lmb handle, will be used for memory mgmt
return 0;
}
+#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
+#ifdef CONFIG_SYS_BOOT_GET_KBD
/**
* boot_get_kbd - allocate and initialize kernel copy of board info
* @lmb: pointer to lmb handle, will be used for memory mgmt
return 0;
}
-#endif /* CONFIG_PPC || CONFIG_M68K */
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
#endif /* !USE_HOSTCC */
#if defined(CONFIG_FIT)
void inline __show_boot_progress (int val) {}
void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
-#if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* for do_reset() prototype */
-#endif
-
-extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
#if defined(CONFIG_UPDATE_TFTP)
void update_tftp (void);
#endif /* CONFIG_UPDATE_TFTP */
hush_init_var ();
#endif
-#ifdef CONFIG_AUTO_COMPLETE
- install_auto_complete();
-#endif
-
#ifdef CONFIG_PREBOOT
if ((p = getenv ("preboot")) != NULL) {
# ifdef CONFIG_AUTOBOOT_KEYED
} while (0)
#define CTL_CH(c) ((c) - 'a' + 1)
-
-#define MAX_CMDBUF_SIZE CONFIG_SYS_CBSIZE
-
#define CTL_BACKSPACE ('\b')
#define DEL ((char)255)
#define DEL7 ((char)127)
#define getcmd_cbeep() getcmd_putch('\a')
#define HIST_MAX 20
-#define HIST_SIZE MAX_CMDBUF_SIZE
+#define HIST_SIZE CONFIG_SYS_CBSIZE
static int hist_max = 0;
static int hist_add_idx = 0;
{
char *p = buffer;
#ifdef CONFIG_CMDLINE_EDITING
- unsigned int len=MAX_CMDBUF_SIZE;
+ unsigned int len = CONFIG_SYS_CBSIZE;
int rc;
static int initted = 0;
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
-#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA250) && !defined(CONFIG_PXA27X)
struct serial_device *__default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
+#else
return &serial0_device;
#endif
#elif defined(CONFIG_MPC512X)
int serial_register (struct serial_device *dev)
{
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
dev->init += gd->reloc_off;
dev->setbrg += gd->reloc_off;
dev->getc += gd->reloc_off;
return &(devs.list);
}
-struct stdio_dev* stdio_get_by_name(char* name)
+struct stdio_dev* stdio_get_by_name(const char *name)
{
struct list_head *pos;
struct stdio_dev *dev;
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(char *devname)
+int stdio_deregister(const char *devname)
{
int l;
struct list_head *pos;
int stdio_init (void)
{
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* already relocated for current ARM implementation */
ulong relocation_offset = gd->reloc_off;
int i;
stdio_names[i] = (char *) (((ulong) stdio_names[i]) +
relocation_offset);
}
-#endif /* !CONFIG_RELOC_FIXUP_WORKS */
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
/* Initialize the list */
INIT_LIST_HEAD(&(devs.list));
/* direction table -- this indicates the direction of the data
* transfer for each command code -- a 1 indicates input
*/
-unsigned char us_direction[256/8] = {
+static const unsigned char us_direction[256/8] = {
0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77,
0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01,
return 1;
}
+static unsigned int usb_get_max_lun(struct us_data *us)
+{
+ int len;
+ unsigned char result;
+ len = usb_control_msg(us->pusb_dev,
+ usb_rcvctrlpipe(us->pusb_dev, 0),
+ US_BBB_GET_MAX_LUN,
+ USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
+ 0, us->ifnum,
+ &result, sizeof(result),
+ USB_CNTL_TIMEOUT * 5);
+ USB_STOR_PRINTF("Get Max LUN -> len = %i, result = %i\n",
+ len, (int) result);
+ return (len > 0) ? result : 0;
+}
+
/*******************************************************************************
* scan the usb and reports device info
* to the user if mode = 1
break; /* no more devices avaiable */
if (usb_storage_probe(dev, 0, &usb_stor[usb_max_devs])) {
- /* ok, it is a storage devices
- * get info and fill it in
+ /* OK, it's a storage device. Iterate over its LUNs
+ * and populate `usb_dev_desc'.
*/
- if (usb_stor_get_info(dev, &usb_stor[usb_max_devs],
- &usb_dev_desc[usb_max_devs]) == 1)
+ int lun, max_lun, start = usb_max_devs;
+
+ max_lun = usb_get_max_lun(&usb_stor[usb_max_devs]);
+ for (lun = 0;
+ lun <= max_lun && usb_max_devs < USB_MAX_STOR_DEV;
+ lun++) {
+ usb_dev_desc[usb_max_devs].lun = lun;
+ if (usb_stor_get_info(dev, &usb_stor[start],
+ &usb_dev_desc[usb_max_devs]) == 1) {
usb_max_devs++;
}
+ }
+ }
/* if storage device */
if (usb_max_devs == USB_MAX_STOR_DEV) {
printf("max USB Storage Device reached: %d stopping\n",
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_INQUIRY;
+ srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 36;
srb->datalen = 36;
srb->cmdlen = 12;
ptr = (char *)srb->pdata;
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_REQ_SENSE;
+ srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 18;
srb->datalen = 18;
srb->pdata = &srb->sense_buf[0];
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_TST_U_RDY;
+ srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
srb->cmdlen = 12;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
do {
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_RD_CAPAC;
+ srb->cmd[1] = srb->lun << 5;
srb->datalen = 8;
srb->cmdlen = 12;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
{
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_READ10;
+ srb->cmd[1] = srb->lun << 5;
srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
{
memset(&srb->cmd[0], 0, 12);
srb->cmd[0] = SCSI_WRITE10;
+ srb->cmd[1] = srb->lun << 5;
srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
# Mac OS X / Darwin's C preprocessor is Apple specific. It
# generates numerous errors and warnings. We want to bypass it
-# and use GNU C's cpp. To do this we pass the -traditional-cpp
+# and use GNU C's cpp. To do this we pass the -traditional-cpp
# option to the compiler. Note that the -traditional-cpp flag
# DOES NOT have the same semantics as GNU C's flag, all it does
# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
-D__KERNEL__
-ifneq ($(TEXT_BASE),)
-CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
ifneq ($(RESET_VECTOR_ADDRESS),)
AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
LDFLAGS += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS)
-ifneq ($(TEXT_BASE),)
-LDFLAGS += -Ttext $(TEXT_BASE)
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+LDFLAGS += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
# Location of a usable BFD library, where we define "usable" as
export HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \
AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE
-export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
+export CONFIG_SYS_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
#########################################################################
# Allow boards to use custom optimize flags on a per dir/file basis
BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
+ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR))
+ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR))
$(obj)%.s: %.S
- $(CPP) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
- -o $@ $<
+ $(CPP) $(ALL_AFLAGS) -o $@ $<
$(obj)%.o: %.S
- $(CC) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CC) $(ALL_AFLAGS) -o $@ $< -c
$(obj)%.o: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CC) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.i: %.c
- $(CPP) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c
+ $(CPP) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.s: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ $< -c -S
+ $(CC) $(ALL_CFLAGS) -o $@ $< -c -S
+
+#########################################################################
+
+# If the list of objects to link is empty, just create an empty built-in.o
+cmd_link_o_target = $(if $(strip $1),\
+ $(LD) -r -o $@ $1 ,\
+ rm -f $@; $(AR) rcs $@ )
#########################################################################
#CFLAGS += -DET_DEBUG -DDEBUG
-LIB = $(obj)libdisk.a
+LIB = $(obj)libdisk.o
COBJS-y += part.o
COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
char *name;
name = drvr->name;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd->reloc_off;
#endif
while (name) {
name = drvr->name;
reloc_get_dev = drvr->get_dev;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
name += gd->reloc_off;
reloc_get_dev += gd->reloc_off;
#endif
>
>How are they (should they be) set in your memory map above?
-_armboot_start contains the value of TEXT_BASE (0xA07E0000); it seems
-TEXT_BASE and _armboot_start are both used for the same purpose in
+_armboot_start contains the value of CONFIG_SYS_TEXT_BASE (0xA07E0000); it seems
+CONFIG_SYS_TEXT_BASE and _armboot_start are both used for the same purpose in
different parts of the (ARM) code.
Furthermore, the startup code (cpu/<arm>/start.S) internally uses
another variable (_TEXT_BASE) with the same content as _armboot_start.
=> u-boot as single bootloader starting from flash
- in board/cobra5272/config.mk TEXT_BASE should be
+ in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
- TEXT_BASE = 0xffe00000
+ CONFIG_SYS_TEXT_BASE = 0xffe00000
=> linking address for u-boot as single bootloader stored in flash
=> u-boot as RAM version, chainloaded by another bootloader or using bdm cable
- in board/cobra5272/config.mk TEXT_BASE should be
+ in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
- TEXT_BASE = 0x00020000
+ CONFIG_SYS_TEXT_BASE = 0x00020000
=> target linking address for RAM
--- /dev/null
+LED display internal API
+=======================================
+
+This README describes the LED display API.
+
+The API is defined by the include file include/led-display.h
+
+The first step in to define CONFIG_CMD_DISPLAY in the board config file.
+Then you need to provide the following functions to access LED display:
+
+void display_set(int cmd);
+
+This function should control the state of the LED display. Argument is
+an ORed combination of the following values:
+ DISPLAY_CLEAR -- clear the display
+ DISPLAY_HOME -- set the position to the beginning of display
+
+int display_putc(char c);
+
+This function should display it's parameter on the LED display in the
+current position. Returns the displayed character on success or -1 in
+case of failure.
+
+With this functions defined 'display' command will display it's
+arguments on the LED display (or clear the display if called without
+arguments).
2.2.2.1. I2C test
For verifying the I2C bus, a full I2C bus scanning will be performed
-using the i2c_probe() routine. If any I2C device is found, the test
-will be considered as passed, otherwise failed. This particular way
-will be used because it provides the most common method of testing.
-For example, using the internal loopback mode of the CPM I2C
-controller for testing would not work on boards where the software
-I2C driver (also known as bit-banged driver) is used.
+using the i2c_probe() routine. If a board defines
+CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices
+listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional
+devices are detected. If CONFIG_SYS_POST_I2C_ADDRS is not defined
+the test will pass if any I2C device is found.
+
+The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C
+devices which may or may not be present when using
+CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless
+if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not.
+This is useful in cases when I2C devices are optional (eg on a
+daughtercard that may or may not be present) or not critical
+to board operation.
2.2.2.2. Watchdog timer test
To make relocation on arm working, the following changes are done:
-Add new compilerflag:
+At arch level: add linker flag -pie
--fPIC
+ This causes the linker to generate fixup tables .rel.dyn and .dynsym,
+ which must be applied to the relocated image before transferring
+ control to it.
- -> compiler generates position independent code
+ These fixups are described in the ARM ELF documentation as type 23
+ (program-base-relative) and 2 (symbol-relative)
-changes in board code:
+At cpu level: modify linker file and add a relocation and fixup loop
-- dram_init:
- - bd pointer is now at this point not accessible, so only
- detect the real dramsize, and store it in gd->ram_size.
- best detected with get_ram_size();
- ToDo: move there also the dram initialization on boards where
- it is possible.
- - setup the bd_t dram bank info in the new function
- dram_init_banksize().
+ the linker file must be modified to include the .rel.dyn and .dynsym
+ tables in the binary image, and to provide symbols for the relocation
+ code to access these tables
-- board.c code is adapted from ppc code
+ The relocation and fixup loop must be executed after executing
+ board_init_f at initial location and before executing board_init_r
+ at final location.
-- undef CONFIG_RELOC_FIXUP_WORKS
+At board level:
- -> cmdtabl, and subcommand table must be handled from "hand"
- collected in section "__datarellocal_start".
+ dram_init(): bd pointer is now at this point not accessible, so only
+ detect the real dramsize, and store it in gd->ram_size. Bst detected
+ with get_ram_size().
- - How To fixup the sections:
+TODO: move also dram initialization there on boards where it is possible.
- __datarel_start, __datarelrolocal_start, __datarellocal_start and
- __datarelro_start
+ Setup of the the bd_t dram bank info is done in the new function
+ dram_init_banksize() called after bd is accessible.
- automatically? Then it should be possible to define again
- CONFIG_RELOC_FIXUP_WORKS
+At lib level:
-- irq stack setup is now not longer on a fix position, instead it is
- calculated in board_init_f, and stored in gd->irq_sp
+ Board.c code is adapted from ppc code
--------------------------------------------------------------------------------------
+* WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING *
-To compile a board without relocation, define CONFIG_SYS_ARM_WITHOUT_RELOC
-This possibility will removed!! So please fix your board to compile without
-CONFIG_SYS_ARM_WITHOUT_RELOC defined!!!
+Boards which are not fixed to support relocation will be REMOVED!
--------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
-For boards which boot from nand_spl, it is possible to save a copy
-if TEXT_BASE == relocation address! This prevents that uboot code
+For boards which boot from nand_spl, it is possible to save one copy
+if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
is copied again in relocate_code().
example for the tx25 board:
f) u-boot code steps through board_init_f() and calculates
the relocation address and copy itself to it
-If TEXT_BASE == relocation address, the copying of u-boot
+If CONFIG_SYS_TEXT_BASE == relocation address, the copying of u-boot
in f) could be saved.
--------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
-ToDo:
+TODO
- fill in bd_t infos (check)
- adapt all boards
-- maybe adapt TEXT_BASE (this must be checked from board maintainers)
+- maybe adapt CONFIG_SYS_TEXT_BASE (this must be checked from board maintainers)
This *must* be done for boards, which boot from NOR flash
- on other boards if TEXT_BASE = relocation baseaddr, this saves
+ on other boards if CONFIG_SYS_TEXT_BASE = relocation baseaddr, this saves
one copying from u-boot code.
- new function dram_init_banksize() is actual board specific. Maybe
we make a weak default function in arch/arm/lib/board.c ?
--------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
Relocation with NAND_SPL (example for the tx25):
and start with code execution on this address.
- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c
- which inits the dram, cpu registers, reloacte itself to TEXT_BASE and loads
+ which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
-- This u-boot does no ram int, nor cpu register setup. Just looks
- where it have to relocate and relocate itself to this address.
- If relocate address = TEXT_BASE(not the same, as the TEXT_BASE
- from the nand_spl code), no need to copy, just go on with bss clear
- and jump to board_init_r.
-
--------------------------------------------------------------------------------------
-
-Relocation:
-How to translate flash addresses in GOT to ram addresses.
-This is automagically done from code, but this example
-shows, how this magic code works ;-)
-(example on the qong board)
-
-Find a variable:
-
-a) search it in System.map
-(for example flash_info)
-
-a005b4c0 B BootpID
-a005b4c4 B BootpTry
-a005b4c8 b slave
-a005b4cc B flash_info
-^^^^^^^^
-a005c908 b saved_sector.4002
-a005c910 b cfi_mtd_info
-a005c9c0 b cfi_mtd_names
-a005c9d0 B mtd_table
-
----------------------------------------
-
-b) create hexdump from u-boot code:
-
-hexdump -C u-boot > gnlmpfhex
-
----------------------------------------
-
-c) search the variables address in the hexdump
-
-
-*
-0005fc80 00 00 00 00 00 00 00 00 2c 06 01 a0 18 cd 05 a0 |........,.......|
-0005fc90 9c d4 05 a0 bc b4 05 a0 1c 7f 05 a0 f0 05 01 a0 |................|
-0005fca0 08 5a 04 a0 1c ab 05 a0 ec a4 05 a0 98 c3 01 a0 |.Z..............|
-0005fcb0 a0 d6 05 a0 04 71 05 a0 c0 f9 00 a0 3c cd 05 a0 |.....q......<...|
-0005fcc0 cc b4 05 a0 f0 fa 00 a0 f0 d6 05 a0 10 86 05 a0 |................|
- ^^^^^^^^^^^
-0005fcd0 a4 16 06 a0 dc 64 05 a0 18 86 05 a0 52 48 05 a0 |.....d......RH..|
-0005fce0 c0 86 05 a0 24 6e 02 a0 b4 6c 05 a0 b0 94 01 a0 |....$n...l......|
-0005fcf0 1c 86 05 a0 50 85 05 a0 d4 0c 06 a0 bc 0b 06 a0 |....P...........|
-
-
--> 0005fcc0
-
-----------------------------------------
-
-d) know we calculate this address in RAM
-
-
- 8ff08000 (new address of code in RAM *1)
-
-+ 0005fcc0
-
-- 00008000 (offset of text *2)
-
-----------
-
- 8ff5fcc0 -> Addr GOT in RAM
-
-*1:
-activate debug and look for the line:
-Now running in RAM - U-Boot at: 8ff08000
- ^^^^^^^^
- new address of u-boot code in RAM
-
-*2:
-Section Headers:
- [Nr] Name Type Addr Off Size ES Flg Lk Inf Al
- [ 0] NULL 00000000 000000 000000 00 0 0 0
- [ 1] .text PROGBITS a0000000 008000 04599c 00 AX 0 0 32
- ^^^^^^
- Offset of text
-
-----------------------------------------
+- This u-boot does no RAM init, nor CPU register setup. Just look
+ where it has to copy and relocate itself to this address. If
+ relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
+ CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need
+ to copy, just go on with bss clear and jump to board_init_r.
-e) now we look in 8ff5fcc0 (RAM)
+-----------------------------------------------------------------------------
+How ELF relocations 23 and 2 work.
-QongEVB>md 0x8ff5fcc0
-8ff5fcc0 : a005b4cc a000faf0 a005d6f0 a0058610 ................
- ^^^^^^^^
- Bingo, here we have the old flash address (when relocation
- is working, here is the fixed ram address. see @ f, how
- it gets calculated)
-
-
-----------------------------------------
-
-f) now translate it in the new RAM address
-
- a005b4cc
-
-- a0000000 TextBase
-
-+ 8ff08000 new address of u-boot in ram
-----------
- 8ff634cc
-
-QongEVB>mm 0x8ff5fcc0 0x8ff634cc 1
-QongEVB>md 0x8ff5fcc0
-8ff5fcc0 : 8ff634cc a000faf0 a005d6f0 a0058610 .4..............
-8ff5fcd0 : a00616a4 a00564dc a0058618 a0054852 .....d......RH..
-
-As this must be done for all address in the GOT, the u-boot
-code did this automagically ... :-)
-
-----------------------------------------------
-
-g) check if the new address is really in the bss section:
-
-bss start:
-8ff6054c (8ff08000 + 0005854C monitorlen)
-
-bss end:
-8ff698ac (8ff08000 + 618AC)
-
-8ff634cc is in bss :-)
-
-----------------------------------------------
-
-h) u-boot prints:
-
-important addresses:
-
-U-Boot code: A0000000 -> A005854C BSS: -> A00618AC TextBase 0xa0000000
-Now running in RAM - U-Boot at: 8ff08000 relocBase 0x8ff08000
-
-
----------
-
-U-Boot 2010.06-rc2-00002-gf8fbb25-dirty (Jun 18 2010 - 17:07:19)
-
-U-Boot code: A0000000 -> A005854C BSS: -> A00618AC
-CPU: Freescale i.MX31 at 398 MHz
-Board: DAVE/DENX Qong
-mon: FFFFFFFF gd->monLen: 000618AC
-Top of RAM usable for U-Boot at: 90000000
-LCD panel info: 640 x 480, 16 bit/pix
-Reserving 600k for LCD Framebuffer at: 8ff6a000
-Reserving 390k for U-Boot at: 8ff08000
-Reserving 1280k for malloc() at: 8fdc8000
-Reserving 28 Bytes for Board Info at: 8fdc7fe4
-Reserving 48 Bytes for Global Data at: 8fdc7fb4
-New Stack Pointer is: 8fdc7fb0
-RAM Configuration:
-Bank #0: 80000000 256 MiB
-mon: 0005854C gd->monLen: 000618AC
-Now running in RAM - U-Boot at: 8ff08000
+TBC
-------------------------------------------------------------------------------------
(gdb) add-symbol-file u-boot 0x8ff08000
add symbol table from file "u-boot" at
- .text_addr = 0x8ff08000
+ .text_addr = 0x8ff08000
(y or n) y
Reading symbols from /home/hs/celf/u-boot/u-boot...done.
(gdb) c
^C
Program received signal SIGSTOP, Stopped (signal).
0x8ff17f18 in serial_getc () at serial_mxc.c:192
-192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
(gdb)
add-symbol-file u-boot 0x8ff08000
- ^^^^^^^^^^
- get this address from u-boot debug printfs
+ ^^^^^^^^^^
+ get this address from u-boot debug printfs
U-Boot 2010.06-rc2-00009-gf77b8b8-dirty (Jun 22 2010 - 09:43:46)
LCD panel info: 640 x 480, 16 bit/pix
Reserving 600k for LCD Framebuffer at: 8ff6a000
Reserving 391k for U-Boot at: 8ff08000
- ^^^^^^^^
+ ^^^^^^^^
Reserving 1280k for malloc() at: 8fdc8000
Reserving 24 Bytes for Board Info at: 8fdc7fe8
Reserving 52 Bytes for Global Data at: 8fdc7fb4
relocation Offset is: eff08000
mon: 00058BAC gd->monLen: 00061F10
Now running in RAM - U-Boot at: 8ff08000
- ^^^^^^^^
+ ^^^^^^^^
Now you can use gdb as usual :-)
* TI DA830 EVM
+* TI DA850 EVM
+
* DM355 based Leopard board
* DM644x based schmoogie board
make da830evm_config
make
+* TI DA850 EVM:
+
+make da850evm_config
+make
+
* DM355 based Leopard board:
make davinci_dm355leopard_config
The programmers and UBL are always released as part of any standard TI
software release associated with an SOC.
+Environment Variables
+=====================
+
+The DA850 EVM allows the user to specify the maximum cpu clock allowed by the
+silicon, in Hz, via an environment variable "maxcpuclk".
+
+The maximum clock rate allowed depends on the silicon populated on the EVM.
+Please make sure you understand the restrictions placed on this clock in the
+device specific datasheet before setting up this variable. This information is
+passed to the Linux kernel using the ATAG_REVISION atag.
+
+If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK
+is used to obtain this information.
+
Links
=====
6) TI DA830 EVM
http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385
http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214
+
+7) TI DA850 EVM
+http://focus.ti.com/docs/prod/folders/print/omap-l138.html
+http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
Syntax is:
hwconfig=fsl_ddr:addr_hash=true
+
+Memory testing options for mpc85xx
+==================================
+1. Memory test can be done once U-boot prompt comes up using mtest, or
+2. Memory test can be done with Power-On-Self-Test function, activated at
+ compile time.
+
+ In order to enable the POST memory test, CONFIG_POST needs to be
+ defined in board configuraiton header file. By default, POST memory test
+ performs a fast test. A slow test can be enabled by changing the flag at
+ compiling time. To test memory bigger than 2GB, 36BIT support is needed.
+ Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
+ window to physical address so that all physical memory can be tested.
+
Combination of hwconfig
=======================
Hwconfig can be combined with multiple parameters, for example, on a supported
--- /dev/null
+Freescale-specific 'hwconfig' options.
+
+This file documents Freescale-specific key:value pairs for the 'hwconfig'
+option. See README.hwconfig for general information about 'hwconfig'.
+
+audclk
+ Specific to the P1022DS reference board.
+
+ This option specifies which of the two oscillator frequencies should be
+ routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to
+ route either a 11.2896MHz or a 12.288MHz clock. The default is
+ 12.288MHz. This option has two effects. First, the MUX on the board
+ will be programmed accordingly. Second, the clock-frequency property
+ in the codec node in the device tree will be updated to the correct
+ value.
+
+ 'audclk:11'
+ Select the 11.2896MHz clock
+
+ 'audclk:12'
+ Select the 12.288MHz clock
--- /dev/null
+Summary
+=======
+The README is for the boot procedure used for TI's OMAP-L138 based
+hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
+DDR SDRAM along with a host of other controllers.
+
+The hawkboard is booted in three stages. The initial bootloader which
+executes upon reset is the Rom Boot Loader(RBL) which sits in the
+internal ROM of the omap. The RBL initialises the memory and the nand
+controller, and copies the image stored at a predefined location(block
+1) of the nand flash. The image loaded by the RBL to the memory is the
+AIS signed nand_spl image. This, in turns copies the u-boot binary
+from the nand flash to the memory and jumps to the u-boot entry point.
+
+AIS is an image format defined by TI for the images that are to be
+loaded to memory by the RBL. The image is divided into a series of
+sections and the image's entry point is specified. Each section comes
+with meta data like the target address the section is to be copied to
+and the size of the section, which is used by the RBL to load the
+image. At the end of the image the RBL jumps to the image entry
+point.
+
+The secondary stage bootloader(nand_spl) which is loaded by the RBL
+then loads the u-boot from a predefined location in the nand to the
+memory and jumps to the u-boot entry point.
+
+The reason a secondary stage bootloader is used is because the ECC
+layout expected by the RBL is not the same as that used by
+u-boot/linux. This also implies that for flashing the nand_spl image,
+we need to use the u-boot which uses the ECC layout expected by the
+RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
+
+
+Compilation
+===========
+Three images might be needed
+
+* nand_spl - This is the secondary bootloader which boots the u-boot
+ binary.
+
+ hawkboard_nand_config
+
+ The nand_spl ELF gets generated under nand_spl/u-boot-spl. This
+ needs to be processed with the AISGen tool for generating the AIS
+ signed image to be flashed. Steps for generating the AIS image are
+ explained here[3].
+
+* u-boot binary - This is the image flashed to the nand and copied to
+ the memory by the nand_spl.
+
+ hawkboard_config
+
+* u-boot for uart boot - This is same as the u-boot binary generated
+ above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
+ 0xc1080000, as expected by the RBL.
+
+ hawkboard_uart_config
+
+
+Flashing the images to Nand
+===========================
+The nand_spl AIS image needs to be flashed to the block 1 of the
+Nand flash, as that is the location the RBL expects the image[4]. For
+flashing the nand_spl, boot over the u-boot specified in [1], and
+flash the image
+
+=> tftpboot 0xc0700000 <nand_spl_ais.bin>
+=> nand erase 0x20000 0x20000
+=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
+
+The u-boot binary is flashed at location 0xe0000(block 6) of the nand
+flash. The nand_spl loader expects the u-boot at this location. For
+flashing the u-boot binary
+
+=> tftpboot 0xc0700000 u-boot.bin
+=> nand erase 0xe0000 0x40000
+=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
+
+
+Links
+=====
+
+[1]
+ http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
+
+[2]
+ http://elinux.org/Hawkboard#Booting_u-boot_over_UART
+
+[3]
+ http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
+
+[4]
+ http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
The build sequence:
- make korat_config
- make all perm=1
+ make korat_perm_config
+ make all
builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
make korat_config
make all
-creates the upgradable U-Boot but selecting loader file "u-boot-F7FC.lds" and
+creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
2008-02-22, Larry Johnson <lrj@acm.org>
http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
U-boot is configured to run at 0x20000 at default. This can be configured by
-change TEXT_BASE in board/m5282evb/config.mk and CONFIG_SYS_MONITOR_BASE in
+change CONFIG_SYS_TEXT_BASE in board/m5282evb/config.mk and CONFIG_SYS_MONITOR_BASE in
include/configs/M5282EVB.h.
3.2 BuS EB+MCF-EV123
initial vector table and basic processor initialization will not
be compiled in. The start address of u-boot must be adjusted in
the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile
-(TEXT_BASE) to the load address.
+(CONFIG_SYS_TEXT_BASE) to the load address.
4.1 MCF5272 specific Options/Settings
-------------------------------------
pcm030_LOWBOOT_config: unconfig
@ >include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
- { echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \
+ { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
}
@[ -z "$(findstring RAMBOOT_,$@)" ] || \
- { echo "TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
+ { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
config.tmp ; \
echo "... with RAMBOOT configuration" ; \
echo "... remember to make sure that MBAR is already \
--- /dev/null
+Over time, support for more and more boards gets added to U-Boot -
+while other board support code dies a silent death caused by
+negligence in combination with ordinary bitrot. Sometimes this goes
+by unnoticed, but often build errors will result. If nobody cares any
+more to resolve such problems, then the code is really dead and will
+be removed from the U-Boot source tree. The remainders rest in piece
+in the imperishable depths of the git history. This document tries to
+maintain a list of such former fellows, so archeologists can check
+easily if here is something they might want to dig for...
+
+
+Board Arch CPU removed Commit last known maintainer/contact
+=============================================================================
+barco powerpc MPC8245 - 2010-11-23 Marc Leeman <marc.leeman@barco.com>
+ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson <sand@peppercon.de>
+VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de>
+NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
+CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
+logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl <august.hoerandl@gmx.at>
+CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger <wg@denx.de>
+PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk <wd@denx.de>
+spieval powerpc MPC5200 69434e4 2010-09-19
+smmaco4 powerpc MPC5200 9ddc3af 2010-09-19
+HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk <wd@denx.de>
+GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange <thomas@corelatus.se>
+AmigaOneG3SE 953b7e6 2010-06-23
+suzaku microblaze 4f18060 2009-10-03 Yasushi Shoji <yashi@atmark-techno.com>
+XUPV2P microblaze 8fab49e 2008-12-10 Michal Simek <monstr@monstr.eu>
+MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz <andre.schwarz@matrix-vision.de>
+adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
+R5200 ColdFire 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
+CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
--- /dev/null
+-------------------
+UBI usage in U-Boot
+-------------------
+
+Here the list of the currently implemented UBI commands:
+
+=> help ubi
+ubi - ubi commands
+
+Usage:
+ubi part [part] [offset]
+ - Show or set current partition (with optional VID header offset)
+ubi info [l[ayout]] - Display volume and ubi layout information
+ubi create[vol] volume [size] [type] - create volume name with size
+ubi write[vol] address volume size - Write volume from address with size
+ubi read[vol] address volume [size] - Read volume to address with size
+ubi remove[vol] volume - Remove volume
+[Legends]
+ volume: character name
+ size: specified in bytes
+ type: s[tatic] or d[ynamic] (default=dynamic)
+
+
+The first command that is needed to be issues is "ubi part" to connect
+one mtd partition to the UBI subsystem. This command will either create
+a new UBI device on the requested MTD partition. Or it will attach a
+previously created UBI device. The other UBI commands will only work
+when such a UBI device is attached (via "ubi part"). Here an example:
+
+=> mtdparts
+
+device nor0 <1fc000000.nor_flash>, # parts = 6
+ #: name size offset mask_flags
+ 0: kernel 0x00200000 0x00000000 0
+ 1: dtb 0x00040000 0x00200000 0
+ 2: root 0x00200000 0x00240000 0
+ 3: user 0x01ac0000 0x00440000 0
+ 4: env 0x00080000 0x01f00000 0
+ 5: u-boot 0x00080000 0x01f80000 0
+
+active partition: nor0,0 - (kernel) 0x00200000 @ 0x00000000
+
+defaults:
+mtdids : nor0=1fc000000.nor_flash
+mtdparts: mtdparts=1fc000000.nor_flash:2m(kernel),256k(dtb),2m(root),27392k(user),512k(env),512k(u-boot)
+
+=> ubi part root
+Creating 1 MTD partitions on "nor0":
+0x000000240000-0x000000440000 : "mtd=2"
+UBI: attaching mtd1 to ubi0
+UBI: physical eraseblock size: 262144 bytes (256 KiB)
+UBI: logical eraseblock size: 262016 bytes
+UBI: smallest flash I/O unit: 1
+UBI: VID header offset: 64 (aligned 64)
+UBI: data offset: 128
+UBI: attached mtd1 to ubi0
+UBI: MTD device name: "mtd=2"
+UBI: MTD device size: 2 MiB
+UBI: number of good PEBs: 8
+UBI: number of bad PEBs: 0
+UBI: max. allowed volumes: 128
+UBI: wear-leveling threshold: 4096
+UBI: number of internal volumes: 1
+UBI: number of user volumes: 1
+UBI: available PEBs: 0
+UBI: total number of reserved PEBs: 8
+UBI: number of PEBs reserved for bad PEB handling: 0
+UBI: max/mean erase counter: 2/1
+
+
+Now that the UBI device is attached, this device can be modified
+using the following commands:
+
+ubi info Display volume and ubi layout information
+ubi createvol Create UBI volume on UBI device
+ubi removevol Remove UBI volume from UBI device
+ubi read Read data from UBI volume to memory
+ubi write Write data from memory to UBI volume
+
+
+Here a few examples on the usage:
+
+=> ubi create testvol
+Creating dynamic volume testvol of size 1048064
+
+=> ubi info l
+UBI: volume information dump:
+UBI: vol_id 0
+UBI: reserved_pebs 4
+UBI: alignment 1
+UBI: data_pad 0
+UBI: vol_type 3
+UBI: name_len 7
+UBI: usable_leb_size 262016
+UBI: used_ebs 4
+UBI: used_bytes 1048064
+UBI: last_eb_bytes 262016
+UBI: corrupted 0
+UBI: upd_marker 0
+UBI: name testvol
+
+UBI: volume information dump:
+UBI: vol_id 2147479551
+UBI: reserved_pebs 2
+UBI: alignment 1
+UBI: data_pad 0
+UBI: vol_type 3
+UBI: name_len 13
+UBI: usable_leb_size 262016
+UBI: used_ebs 2
+UBI: used_bytes 524032
+UBI: last_eb_bytes 2
+UBI: corrupted 0
+UBI: upd_marker 0
+UBI: name layout volume
+
+=> ubi info
+UBI: MTD device name: "mtd=2"
+UBI: MTD device size: 2 MiB
+UBI: physical eraseblock size: 262144 bytes (256 KiB)
+UBI: logical eraseblock size: 262016 bytes
+UBI: number of good PEBs: 8
+UBI: number of bad PEBs: 0
+UBI: smallest flash I/O unit: 1
+UBI: VID header offset: 64 (aligned 64)
+UBI: data offset: 128
+UBI: max. allowed volumes: 128
+UBI: wear-leveling threshold: 4096
+UBI: number of internal volumes: 1
+UBI: number of user volumes: 1
+UBI: available PEBs: 0
+UBI: total number of reserved PEBs: 8
+UBI: number of PEBs reserved for bad PEB handling: 0
+UBI: max/mean erase counter: 4/1
+
+=> ubi write 800000 testvol 80000
+Volume "testvol" found at volume id 0
+
+=> ubi read 900000 testvol 80000
+Volume testvol found at volume id 0
+read 524288 bytes from volume 0 to 900000(buf address)
+
+=> cmp.b 800000 900000 80000
+Total of 524288 bytes were the same
file.
---------------------------
-What: CONFIG_SYS_ARM_WITHOUT_RELOC option
-When: After Release 2011.03
-
-Why: The implementation of U-Boot for the ARM architecture has
- been reworked to support relocation. This allows to
- efficiently use the same U-Boot binary image on systems with
- different RAM sizes, and brings the implementation much more
- in line with the code used for example on Power Architecture
- systems (eventually allowing to merge into common code). This
- seems especailly interesting now that ARM is getting Device
- Tree support as well.
-
- All ARM boards need to be adapted to this new code, which
- requires testing on the actual hardware, so this is a task
- for the respective board maintainers or other users.
-
- Please see the commit message of commit f1d2b31 for details:
-
- http://git.denx.de/?p=u-boot.git;a=commit;h=f1d2b31
-
- Support for CONFIG_SYS_ARM_WITHOUT_RELOC will be removed
- after release v2011.03; all boards that have not been
- converted by then, i. e. that are still broken then, are
- considered unmaintained and without interest for the
- community and will be removed as well.
-
----------------------------
What: CONFIG_NET_MULTI option
When: Release 2009-11
include $(TOPDIR)/config.mk
-LIB := $(obj)libatibiosemu.a
+LIB := $(obj)libatibiosemu.o
X86DIR = x86emu
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libblock.a
+LIB := $(obj)libblock.o
COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
/*
+ * Status codes to return to client callers. Currently, callers ignore
+ * exact value and only care for zero or nonzero, so no need to make this
+ * public, it is only #define'd for clarity.
+ * If/when standard negative codes are implemented in U-boot, then these
+ * #defines should be moved to, or replaced by ones from, the common list
+ * of status codes.
+ */
+
+#define MVSATA_STATUS_OK 0
+#define MVSATA_STATUS_TIMEOUT -1
+
+/*
* Initialize one MVSATAHC port: set SControl's IPM to "always active"
* and DET to "reset", then wait for SStatus's DET to become "device and
* comm ok" (or time out after 50 us if no device), then set SControl's
* DET back to "no action".
*/
-static void mvsata_ide_initialize_port(struct mvsata_port_registers *port)
+static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
{
u32 control;
u32 status;
- u32 tout = 50; /* wait at most 50 us for SATA reset to complete */
+ u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
+ /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
control = readl(&port->scontrol);
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
writel(control, &port->scontrol);
- while (--tout) {
+ /* Toggle control DET back to 0 (normal operation) */
+ control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
+ writel(control, &port->scontrol);
+ /* wait for status DET to become 3 (device and communication OK) */
+ while (--timeleft) {
status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
if (status == MVSATA_SSTATUS_DET_DEVCOMM)
break;
udelay(1);
}
- control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
- writel(control, &port->scontrol);
+ /* return success or time-out error depending on time left */
+ if (!timeleft)
+ return MVSATA_STATUS_TIMEOUT;
+ return MVSATA_STATUS_OK;
}
/*
int ide_preinit(void)
{
+ int status;
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
- mvsata_ide_initialize_port(
+ status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
+ if (status)
+ return status;
#endif
/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
- mvsata_ide_initialize_port(
+ status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
+ if (status)
+ return status;
#endif
- /* return 0 as we always succeed */
- return 0;
+ /* return success if all ports initializations succeeded */
+ return MVSATA_STATUS_OK;
}
include $(TOPDIR)/config.mk
-LIB := $(obj)libdma.a
+LIB := $(obj)libdma.o
COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libfpga.a
+LIB := $(obj)libfpga.o
ifdef CONFIG_FPGA
COBJS-y += fpga.o
COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
+COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
COBJS-y += altera.o
COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h> /* core U-Boot definitions */
#include <xilinx.h> /* xilinx specific definitions */
#include <altera.h> /* altera specific definitions */
+#include <lattice.h>
#if 0
#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
+ case fpga_lattice:
+#if defined(CONFIG_FPGA_LATTICE)
+ printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
+ ret_val = lattice_info(desc->devdesc);
+#else
+ fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+#endif
+ break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
+ case fpga_lattice:
+#if defined(CONFIG_FPGA_LATTICE)
+ ret_val = lattice_load(desc->devdesc, buf, bsize);
+#else
+ fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+#endif
+ break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
+ case fpga_lattice:
+#if defined(CONFIG_FPGA_LATTICE)
+ ret_val = lattice_dump(desc->devdesc, buf, bsize);
+#else
+ fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+#endif
+ break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Lattice ispVME Embedded code to load Lattice's FPGA:
+ *
+ * Copyright 2009 Lattice Semiconductor Corp.
+ *
+ * ispVME Embedded allows programming of Lattice's suite of FPGA
+ * devices on embedded systems through the JTAG port. The software
+ * is distributed in source code form and is open to re - distribution
+ * and modification where applicable.
+ *
+ * Revision History of ivm_core.c module:
+ * 4/25/06 ht Change some variables from unsigned short or int
+ * to long int to make the code compiler independent.
+ * 5/24/06 ht Support using RESET (TRST) pin as a special purpose
+ * control pin such as triggering the loading of known
+ * state exit.
+ * 3/6/07 ht added functions to support output to terminals
+ *
+ * 09/11/07 NN Type cast mismatch variables
+ * Moved the sclock() function to hardware.c
+ * 08/28/08 NN Added Calculate checksum support.
+ * 4/1/09 Nguyen replaced the recursive function call codes on
+ * the ispVMLCOUNT function
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/string.h>
+#include <malloc.h>
+#include <lattice.h>
+
+#define vme_out_char(c) printf("%c", c)
+#define vme_out_hex(c) printf("%x", c)
+#define vme_out_string(s) printf("%s", s)
+
+/*
+ *
+ * Global variables used to specify the flow control and data type.
+ *
+ * g_usFlowControl: flow control register. Each bit in the
+ * register can potentially change the
+ * personality of the embedded engine.
+ * g_usDataType: holds the data type of the current row.
+ *
+ */
+
+static unsigned short g_usFlowControl;
+unsigned short g_usDataType;
+
+/*
+ *
+ * Global variables used to specify the ENDDR and ENDIR.
+ *
+ * g_ucEndDR: the state that the device goes to after SDR.
+ * g_ucEndIR: the state that the device goes to after SIR.
+ *
+ */
+
+unsigned char g_ucEndDR = DRPAUSE;
+unsigned char g_ucEndIR = IRPAUSE;
+
+/*
+ *
+ * Global variables used to support header/trailer.
+ *
+ * g_usHeadDR: the number of lead devices in bypass.
+ * g_usHeadIR: the sum of IR length of lead devices.
+ * g_usTailDR: the number of tail devices in bypass.
+ * g_usTailIR: the sum of IR length of tail devices.
+ *
+ */
+
+static unsigned short g_usHeadDR;
+static unsigned short g_usHeadIR;
+static unsigned short g_usTailDR;
+static unsigned short g_usTailIR;
+
+/*
+ *
+ * Global variable to store the number of bits of data or instruction
+ * to be shifted into or out from the device.
+ *
+ */
+
+static unsigned short g_usiDataSize;
+
+/*
+ *
+ * Stores the frequency. Default to 1 MHz.
+ *
+ */
+
+static int g_iFrequency = 1000;
+
+/*
+ *
+ * Stores the maximum amount of ram needed to hold a row of data.
+ *
+ */
+
+static unsigned short g_usMaxSize;
+
+/*
+ *
+ * Stores the LSH or RSH value.
+ *
+ */
+
+static unsigned short g_usShiftValue;
+
+/*
+ *
+ * Stores the current repeat loop value.
+ *
+ */
+
+static unsigned short g_usRepeatLoops;
+
+/*
+ *
+ * Stores the current vendor.
+ *
+ */
+
+static signed char g_cVendor = LATTICE;
+
+/*
+ *
+ * Stores the VME file CRC.
+ *
+ */
+
+unsigned short g_usCalculatedCRC;
+
+/*
+ *
+ * Stores the Device Checksum.
+ *
+ */
+/* 08/28/08 NN Added Calculate checksum support. */
+unsigned long g_usChecksum;
+static unsigned int g_uiChecksumIndex;
+
+/*
+ *
+ * Stores the current state of the JTAG state machine.
+ *
+ */
+
+static signed char g_cCurrentJTAGState;
+
+/*
+ *
+ * Global variables used to support looping.
+ *
+ * g_pucHeapMemory: holds the entire repeat loop.
+ * g_iHeapCounter: points to the current byte in the repeat loop.
+ * g_iHEAPSize: the current size of the repeat in bytes.
+ *
+ */
+
+unsigned char *g_pucHeapMemory;
+unsigned short g_iHeapCounter;
+unsigned short g_iHEAPSize;
+static unsigned short previous_size;
+
+/*
+ *
+ * Global variables used to support intelligent programming.
+ *
+ * g_usIntelDataIndex: points to the current byte of the
+ * intelligent buffer.
+ * g_usIntelBufferSize: holds the size of the intelligent
+ * buffer.
+ *
+ */
+
+unsigned short g_usIntelDataIndex;
+unsigned short g_usIntelBufferSize;
+
+/*
+ *
+ * Supported VME versions.
+ *
+ */
+
+const char *const g_szSupportedVersions[] = {
+ "__VME2.0", "__VME3.0", "____12.0", "____12.1", 0};
+
+/*
+ *
+ * Holds the maximum size of each respective buffer. These variables are used
+ * to write the HEX files when converting VME to HEX.
+ *
+*/
+
+static unsigned short g_usTDOSize;
+static unsigned short g_usMASKSize;
+static unsigned short g_usTDISize;
+static unsigned short g_usDMASKSize;
+static unsigned short g_usLCOUNTSize;
+static unsigned short g_usHDRSize;
+static unsigned short g_usTDRSize;
+static unsigned short g_usHIRSize;
+static unsigned short g_usTIRSize;
+static unsigned short g_usHeapSize;
+
+/*
+ *
+ * Global variables used to store data.
+ *
+ * g_pucOutMaskData: local RAM to hold one row of MASK data.
+ * g_pucInData: local RAM to hold one row of TDI data.
+ * g_pucOutData: local RAM to hold one row of TDO data.
+ * g_pucHIRData: local RAM to hold the current SIR header.
+ * g_pucTIRData: local RAM to hold the current SIR trailer.
+ * g_pucHDRData: local RAM to hold the current SDR header.
+ * g_pucTDRData: local RAM to hold the current SDR trailer.
+ * g_pucIntelBuffer: local RAM to hold the current intelligent buffer
+ * g_pucOutDMaskData: local RAM to hold one row of DMASK data.
+ *
+ */
+
+unsigned char *g_pucOutMaskData = NULL,
+ *g_pucInData = NULL,
+ *g_pucOutData = NULL,
+ *g_pucHIRData = NULL,
+ *g_pucTIRData = NULL,
+ *g_pucHDRData = NULL,
+ *g_pucTDRData = NULL,
+ *g_pucIntelBuffer = NULL,
+ *g_pucOutDMaskData = NULL;
+
+/*
+ *
+ * JTAG state machine transition table.
+ *
+ */
+
+struct {
+ unsigned char CurState; /* From this state */
+ unsigned char NextState; /* Step to this state */
+ unsigned char Pattern; /* The tragetory of TMS */
+ unsigned char Pulses; /* The number of steps */
+} g_JTAGTransistions[25] = {
+{ RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */
+{ RESET, IDLE, 0x00, 1 },
+{ RESET, DRPAUSE, 0x50, 5 },
+{ RESET, IRPAUSE, 0x68, 6 },
+{ IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */
+{ IDLE, DRPAUSE, 0xA0, 4 },
+{ IDLE, IRPAUSE, 0xD0, 5 },
+{ DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */
+{ DRPAUSE, IDLE, 0xC0, 3 },
+{ DRPAUSE, IRPAUSE, 0xF4, 7 },
+{ DRPAUSE, DRPAUSE, 0xE8, 6 },/* 06/14/06 Support POLL STATUS LOOP*/
+{ IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */
+{ IRPAUSE, IDLE, 0xC0, 3 },
+{ IRPAUSE, DRPAUSE, 0xE8, 6 },
+{ DRPAUSE, SHIFTDR, 0x80, 2 }, /* Extra transitions using SHIFTDR */
+{ IRPAUSE, SHIFTDR, 0xE0, 5 },
+{ SHIFTDR, DRPAUSE, 0x80, 2 },
+{ SHIFTDR, IDLE, 0xC0, 3 },
+{ IRPAUSE, SHIFTIR, 0x80, 2 },/* Extra transitions using SHIFTIR */
+{ SHIFTIR, IRPAUSE, 0x80, 2 },
+{ SHIFTIR, IDLE, 0xC0, 3 },
+{ DRPAUSE, DRCAPTURE, 0xE0, 4 }, /* 11/15/05 Support DRCAPTURE*/
+{ DRCAPTURE, DRPAUSE, 0x80, 2 },
+{ IDLE, DRCAPTURE, 0x80, 2 },
+{ IRPAUSE, DRCAPTURE, 0xE0, 4 }
+};
+
+/*
+ *
+ * List to hold all LVDS pairs.
+ *
+ */
+
+LVDSPair *g_pLVDSList;
+unsigned short g_usLVDSPairCount;
+
+/*
+ *
+ * Function prototypes.
+ *
+ */
+
+static signed char ispVMDataCode(void);
+static long int ispVMDataSize(void);
+static void ispVMData(unsigned char *Data);
+static signed char ispVMShift(signed char Code);
+static signed char ispVMAmble(signed char Code);
+static signed char ispVMLoop(unsigned short a_usLoopCount);
+static signed char ispVMBitShift(signed char mode, unsigned short bits);
+static void ispVMComment(unsigned short a_usCommentSize);
+static void ispVMHeader(unsigned short a_usHeaderSize);
+static signed char ispVMLCOUNT(unsigned short a_usCountSize);
+static void ispVMClocks(unsigned short Clocks);
+static void ispVMBypass(signed char ScanType, unsigned short Bits);
+static void ispVMStateMachine(signed char NextState);
+static signed char ispVMSend(unsigned short int);
+static signed char ispVMRead(unsigned short int);
+static signed char ispVMReadandSave(unsigned short int);
+static signed char ispVMProcessLVDS(unsigned short a_usLVDSCount);
+static void ispVMMemManager(signed char types, unsigned short size);
+
+/*
+ *
+ * External variables and functions in hardware.c module
+ *
+ */
+static signed char g_cCurrentJTAGState;
+
+#ifdef DEBUG
+
+/*
+ *
+ * GetState
+ *
+ * Returns the state as a string based on the opcode. Only used
+ * for debugging purposes.
+ *
+ */
+
+const char *GetState(unsigned char a_ucState)
+{
+ switch (a_ucState) {
+ case RESET:
+ return "RESET";
+ case IDLE:
+ return "IDLE";
+ case IRPAUSE:
+ return "IRPAUSE";
+ case DRPAUSE:
+ return "DRPAUSE";
+ case SHIFTIR:
+ return "SHIFTIR";
+ case SHIFTDR:
+ return "SHIFTDR";
+ case DRCAPTURE:/* 11/15/05 support DRCAPTURE*/
+ return "DRCAPTURE";
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ *
+ * PrintData
+ *
+ * Prints the data. Only used for debugging purposes.
+ *
+ */
+
+void PrintData(unsigned short a_iDataSize, unsigned char *a_pucData)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short usByteSize = 0;
+ unsigned short usBitIndex = 0;
+ signed short usByteIndex = 0;
+ unsigned char ucByte = 0;
+ unsigned char ucFlipByte = 0;
+
+ if (a_iDataSize % 8) {
+ /* 09/11/07 NN Type cast mismatch variables */
+ usByteSize = (unsigned short)(a_iDataSize / 8 + 1);
+ } else {
+ /* 09/11/07 NN Type cast mismatch variables */
+ usByteSize = (unsigned short)(a_iDataSize / 8);
+ }
+ puts("(");
+ /* 09/11/07 NN Type cast mismatch variables */
+ for (usByteIndex = (signed short)(usByteSize - 1);
+ usByteIndex >= 0; usByteIndex--) {
+ ucByte = a_pucData[usByteIndex];
+ ucFlipByte = 0x00;
+
+ /*
+ *
+ * Flip each byte.
+ *
+ */
+
+ for (usBitIndex = 0; usBitIndex < 8; usBitIndex++) {
+ ucFlipByte <<= 1;
+ if (ucByte & 0x1) {
+ ucFlipByte |= 0x1;
+ }
+
+ ucByte >>= 1;
+ }
+
+ /*
+ *
+ * Print the flipped byte.
+ *
+ */
+
+ printf("%.02X", ucFlipByte);
+ if ((usByteSize - usByteIndex) % 40 == 39) {
+ puts("\n\t\t");
+ }
+ if (usByteIndex < 0)
+ break;
+ }
+ puts(")");
+}
+#endif /* DEBUG */
+
+void ispVMMemManager(signed char cTarget, unsigned short usSize)
+{
+ switch (cTarget) {
+ case XTDI:
+ case TDI:
+ if (g_pucInData != NULL) {
+ if (previous_size == usSize) {/*memory exist*/
+ break;
+ } else {
+ free(g_pucInData);
+ g_pucInData = NULL;
+ }
+ }
+ g_pucInData = (unsigned char *) malloc(usSize / 8 + 2);
+ previous_size = usSize;
+ case XTDO:
+ case TDO:
+ if (g_pucOutData != NULL) {
+ if (previous_size == usSize) { /*already exist*/
+ break;
+ } else {
+ free(g_pucOutData);
+ g_pucOutData = NULL;
+ }
+ }
+ g_pucOutData = (unsigned char *) malloc(usSize / 8 + 2);
+ previous_size = usSize;
+ break;
+ case MASK:
+ if (g_pucOutMaskData != NULL) {
+ if (previous_size == usSize) {/*already allocated*/
+ break;
+ } else {
+ free(g_pucOutMaskData);
+ g_pucOutMaskData = NULL;
+ }
+ }
+ g_pucOutMaskData = (unsigned char *) malloc(usSize / 8 + 2);
+ previous_size = usSize;
+ break;
+ case HIR:
+ if (g_pucHIRData != NULL) {
+ free(g_pucHIRData);
+ g_pucHIRData = NULL;
+ }
+ g_pucHIRData = (unsigned char *) malloc(usSize / 8 + 2);
+ break;
+ case TIR:
+ if (g_pucTIRData != NULL) {
+ free(g_pucTIRData);
+ g_pucTIRData = NULL;
+ }
+ g_pucTIRData = (unsigned char *) malloc(usSize / 8 + 2);
+ break;
+ case HDR:
+ if (g_pucHDRData != NULL) {
+ free(g_pucHDRData);
+ g_pucHDRData = NULL;
+ }
+ g_pucHDRData = (unsigned char *) malloc(usSize / 8 + 2);
+ break;
+ case TDR:
+ if (g_pucTDRData != NULL) {
+ free(g_pucTDRData);
+ g_pucTDRData = NULL;
+ }
+ g_pucTDRData = (unsigned char *) malloc(usSize / 8 + 2);
+ break;
+ case HEAP:
+ if (g_pucHeapMemory != NULL) {
+ free(g_pucHeapMemory);
+ g_pucHeapMemory = NULL;
+ }
+ g_pucHeapMemory = (unsigned char *) malloc(usSize + 2);
+ break;
+ case DMASK:
+ if (g_pucOutDMaskData != NULL) {
+ if (previous_size == usSize) { /*already allocated*/
+ break;
+ } else {
+ free(g_pucOutDMaskData);
+ g_pucOutDMaskData = NULL;
+ }
+ }
+ g_pucOutDMaskData = (unsigned char *) malloc(usSize / 8 + 2);
+ previous_size = usSize;
+ break;
+ case LHEAP:
+ if (g_pucIntelBuffer != NULL) {
+ free(g_pucIntelBuffer);
+ g_pucIntelBuffer = NULL;
+ }
+ g_pucIntelBuffer = (unsigned char *) malloc(usSize + 2);
+ break;
+ case LVDS:
+ if (g_pLVDSList != NULL) {
+ free(g_pLVDSList);
+ g_pLVDSList = NULL;
+ }
+ g_pLVDSList = (LVDSPair *) malloc(usSize * sizeof(LVDSPair));
+ if (g_pLVDSList)
+ memset(g_pLVDSList, 0, usSize * sizeof(LVDSPair));
+ break;
+ default:
+ return;
+ }
+}
+
+void ispVMFreeMem(void)
+{
+ if (g_pucHeapMemory != NULL) {
+ free(g_pucHeapMemory);
+ g_pucHeapMemory = NULL;
+ }
+
+ if (g_pucOutMaskData != NULL) {
+ free(g_pucOutMaskData);
+ g_pucOutMaskData = NULL;
+ }
+
+ if (g_pucInData != NULL) {
+ free(g_pucInData);
+ g_pucInData = NULL;
+ }
+
+ if (g_pucOutData != NULL) {
+ free(g_pucOutData);
+ g_pucOutData = NULL;
+ }
+
+ if (g_pucHIRData != NULL) {
+ free(g_pucHIRData);
+ g_pucHIRData = NULL;
+ }
+
+ if (g_pucTIRData != NULL) {
+ free(g_pucTIRData);
+ g_pucTIRData = NULL;
+ }
+
+ if (g_pucHDRData != NULL) {
+ free(g_pucHDRData);
+ g_pucHDRData = NULL;
+ }
+
+ if (g_pucTDRData != NULL) {
+ free(g_pucTDRData);
+ g_pucTDRData = NULL;
+ }
+
+ if (g_pucOutDMaskData != NULL) {
+ free(g_pucOutDMaskData);
+ g_pucOutDMaskData = NULL;
+ }
+
+ if (g_pucIntelBuffer != NULL) {
+ free(g_pucIntelBuffer);
+ g_pucIntelBuffer = NULL;
+ }
+
+ if (g_pLVDSList != NULL) {
+ free(g_pLVDSList);
+ g_pLVDSList = NULL;
+ }
+}
+
+
+/*
+ *
+ * ispVMDataSize
+ *
+ * Returns a VME-encoded number, usually used to indicate the
+ * bit length of an SIR/SDR command.
+ *
+ */
+
+long int ispVMDataSize()
+{
+ /* 09/11/07 NN added local variables initialization */
+ long int iSize = 0;
+ signed char cCurrentByte = 0;
+ signed char cIndex = 0;
+ cIndex = 0;
+ while ((cCurrentByte = GetByte()) & 0x80) {
+ iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex;
+ cIndex += 7;
+ }
+ iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex;
+ return iSize;
+}
+
+/*
+ *
+ * ispVMCode
+ *
+ * This is the heart of the embedded engine. All the high-level opcodes
+ * are extracted here. Once they have been identified, then it
+ * will call other functions to handle the processing.
+ *
+ */
+
+signed char ispVMCode()
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short iRepeatSize = 0;
+ signed char cOpcode = 0;
+ signed char cRetCode = 0;
+ unsigned char ucState = 0;
+ unsigned short usDelay = 0;
+ unsigned short usToggle = 0;
+ unsigned char usByte = 0;
+
+ /*
+ *
+ * Check the compression flag only if this is the first time
+ * this function is entered. Do not check the compression flag if
+ * it is being called recursively from other functions within
+ * the embedded engine.
+ *
+ */
+
+ if (!(g_usDataType & LHEAP_IN) && !(g_usDataType & HEAP_IN)) {
+ usByte = GetByte();
+ if (usByte == 0xf1) {
+ g_usDataType |= COMPRESS;
+ } else if (usByte == 0xf2) {
+ g_usDataType &= ~COMPRESS;
+ } else {
+ return VME_INVALID_FILE;
+ }
+ }
+
+ /*
+ *
+ * Begin looping through all the VME opcodes.
+ *
+ */
+
+ while ((cOpcode = GetByte()) >= 0) {
+
+ switch (cOpcode) {
+ case STATE:
+
+ /*
+ * Step the JTAG state machine.
+ */
+
+ ucState = GetByte();
+
+ /*
+ * Step the JTAG state machine to DRCAPTURE
+ * to support Looping.
+ */
+
+ if ((g_usDataType & LHEAP_IN) &&
+ (ucState == DRPAUSE) &&
+ (g_cCurrentJTAGState == ucState)) {
+ ispVMStateMachine(DRCAPTURE);
+ }
+
+ ispVMStateMachine(ucState);
+
+#ifdef DEBUG
+ if (g_usDataType & LHEAP_IN) {
+ debug("LDELAY %s ", GetState(ucState));
+ } else {
+ debug("STATE %s;\n", GetState(ucState));
+ }
+#endif /* DEBUG */
+ break;
+ case SIR:
+ case SDR:
+ case XSDR:
+
+#ifdef DEBUG
+ switch (cOpcode) {
+ case SIR:
+ puts("SIR ");
+ break;
+ case SDR:
+ case XSDR:
+ if (g_usDataType & LHEAP_IN) {
+ puts("LSDR ");
+ } else {
+ puts("SDR ");
+ }
+ break;
+ }
+#endif /* DEBUG */
+ /*
+ *
+ * Shift in data into the device.
+ *
+ */
+
+ cRetCode = ispVMShift(cOpcode);
+ if (cRetCode != 0) {
+ return cRetCode;
+ }
+ break;
+ case WAIT:
+
+ /*
+ *
+ * Observe delay.
+ *
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ usDelay = (unsigned short) ispVMDataSize();
+ ispVMDelay(usDelay);
+
+#ifdef DEBUG
+ if (usDelay & 0x8000) {
+
+ /*
+ * Since MSB is set, the delay time must be
+ * decoded to millisecond. The SVF2VME encodes
+ * the MSB to represent millisecond.
+ */
+
+ usDelay &= ~0x8000;
+ if (g_usDataType & LHEAP_IN) {
+ printf("%.2E SEC;\n",
+ (float) usDelay / 1000);
+ } else {
+ printf("RUNTEST %.2E SEC;\n",
+ (float) usDelay / 1000);
+ }
+ } else {
+ /*
+ * Since MSB is not set, the delay time
+ * is given as microseconds.
+ */
+
+ if (g_usDataType & LHEAP_IN) {
+ printf("%.2E SEC;\n",
+ (float) usDelay / 1000000);
+ } else {
+ printf("RUNTEST %.2E SEC;\n",
+ (float) usDelay / 1000000);
+ }
+ }
+#endif /* DEBUG */
+ break;
+ case TCK:
+
+ /*
+ * Issue clock toggles.
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ usToggle = (unsigned short) ispVMDataSize();
+ ispVMClocks(usToggle);
+
+#ifdef DEBUG
+ printf("RUNTEST %d TCK;\n", usToggle);
+#endif /* DEBUG */
+ break;
+ case ENDDR:
+
+ /*
+ *
+ * Set the ENDDR.
+ *
+ */
+
+ g_ucEndDR = GetByte();
+
+#ifdef DEBUG
+ printf("ENDDR %s;\n", GetState(g_ucEndDR));
+#endif /* DEBUG */
+ break;
+ case ENDIR:
+
+ /*
+ *
+ * Set the ENDIR.
+ *
+ */
+
+ g_ucEndIR = GetByte();
+
+#ifdef DEBUG
+ printf("ENDIR %s;\n", GetState(g_ucEndIR));
+#endif /* DEBUG */
+ break;
+ case HIR:
+ case TIR:
+ case HDR:
+ case TDR:
+
+#ifdef DEBUG
+ switch (cOpcode) {
+ case HIR:
+ puts("HIR ");
+ break;
+ case TIR:
+ puts("TIR ");
+ break;
+ case HDR:
+ puts("HDR ");
+ break;
+ case TDR:
+ puts("TDR ");
+ break;
+ }
+#endif /* DEBUG */
+ /*
+ * Set the header/trailer of the device in order
+ * to bypass
+ * successfully.
+ */
+
+ cRetCode = ispVMAmble(cOpcode);
+ if (cRetCode != 0) {
+ return cRetCode;
+ }
+
+#ifdef DEBUG
+ puts(";\n");
+#endif /* DEBUG */
+ break;
+ case MEM:
+
+ /*
+ * The maximum RAM required to support
+ * processing one row of the VME file.
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usMaxSize = (unsigned short) ispVMDataSize();
+
+#ifdef DEBUG
+ printf("// MEMSIZE %d\n", g_usMaxSize);
+#endif /* DEBUG */
+ break;
+ case VENDOR:
+
+ /*
+ *
+ * Set the VENDOR type.
+ *
+ */
+
+ cOpcode = GetByte();
+ switch (cOpcode) {
+ case LATTICE:
+#ifdef DEBUG
+ puts("// VENDOR LATTICE\n");
+#endif /* DEBUG */
+ g_cVendor = LATTICE;
+ break;
+ case ALTERA:
+#ifdef DEBUG
+ puts("// VENDOR ALTERA\n");
+#endif /* DEBUG */
+ g_cVendor = ALTERA;
+ break;
+ case XILINX:
+#ifdef DEBUG
+ puts("// VENDOR XILINX\n");
+#endif /* DEBUG */
+ g_cVendor = XILINX;
+ break;
+ default:
+ break;
+ }
+ break;
+ case SETFLOW:
+
+ /*
+ * Set the flow control. Flow control determines
+ * the personality of the embedded engine.
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usFlowControl |= (unsigned short) ispVMDataSize();
+ break;
+ case RESETFLOW:
+
+ /*
+ *
+ * Unset the flow control.
+ *
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usFlowControl &= (unsigned short) ~(ispVMDataSize());
+ break;
+ case HEAP:
+
+ /*
+ *
+ * Allocate heap size to store loops.
+ *
+ */
+
+ cRetCode = GetByte();
+ if (cRetCode != SECUREHEAP) {
+ return VME_INVALID_FILE;
+ }
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_iHEAPSize = (unsigned short) ispVMDataSize();
+
+ /*
+ * Store the maximum size of the HEAP buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_iHEAPSize > g_usHeapSize) {
+ g_usHeapSize = g_iHEAPSize;
+ }
+
+ ispVMMemManager(HEAP, (unsigned short) g_iHEAPSize);
+ break;
+ case REPEAT:
+
+ /*
+ *
+ * Execute loops.
+ *
+ */
+
+ g_usRepeatLoops = 0;
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ iRepeatSize = (unsigned short) ispVMDataSize();
+
+ cRetCode = ispVMLoop((unsigned short) iRepeatSize);
+ if (cRetCode != 0) {
+ return cRetCode;
+ }
+ break;
+ case ENDLOOP:
+
+ /*
+ *
+ * Exit point from processing loops.
+ *
+ */
+
+ return cRetCode;
+ case ENDVME:
+
+ /*
+ * The only valid exit point that indicates
+ * end of programming.
+ */
+
+ return cRetCode;
+ case SHR:
+
+ /*
+ *
+ * Right-shift address.
+ *
+ */
+
+ g_usFlowControl |= SHIFTRIGHT;
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usShiftValue = (unsigned short) (g_usRepeatLoops *
+ (unsigned short)GetByte());
+ break;
+ case SHL:
+
+ /*
+ * Left-shift address.
+ */
+
+ g_usFlowControl |= SHIFTLEFT;
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usShiftValue = (unsigned short) (g_usRepeatLoops *
+ (unsigned short)GetByte());
+ break;
+ case FREQUENCY:
+
+ /*
+ *
+ * Set the frequency.
+ *
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_iFrequency = (int) (ispVMDataSize() / 1000);
+ if (g_iFrequency == 1)
+ g_iFrequency = 1000;
+
+#ifdef DEBUG
+ printf("FREQUENCY %.2E HZ;\n",
+ (float) g_iFrequency * 1000);
+#endif /* DEBUG */
+ break;
+ case LCOUNT:
+
+ /*
+ *
+ * Process LCOUNT command.
+ *
+ */
+
+ cRetCode = ispVMLCOUNT((unsigned short)ispVMDataSize());
+ if (cRetCode != 0) {
+ return cRetCode;
+ }
+ break;
+ case VUES:
+
+ /*
+ *
+ * Set the flow control to verify USERCODE.
+ *
+ */
+
+ g_usFlowControl |= VERIFYUES;
+ break;
+ case COMMENT:
+
+ /*
+ *
+ * Display comment.
+ *
+ */
+
+ ispVMComment((unsigned short) ispVMDataSize());
+ break;
+ case LVDS:
+
+ /*
+ *
+ * Process LVDS command.
+ *
+ */
+
+ ispVMProcessLVDS((unsigned short) ispVMDataSize());
+ break;
+ case HEADER:
+
+ /*
+ *
+ * Discard header.
+ *
+ */
+
+ ispVMHeader((unsigned short) ispVMDataSize());
+ break;
+ /* 03/14/06 Support Toggle ispENABLE signal*/
+ case ispEN:
+ ucState = GetByte();
+ if ((ucState == ON) || (ucState == 0x01))
+ writePort(g_ucPinENABLE, 0x01);
+ else
+ writePort(g_ucPinENABLE, 0x00);
+ ispVMDelay(1);
+ break;
+ /* 05/24/06 support Toggle TRST pin*/
+ case TRST:
+ ucState = GetByte();
+ if (ucState == 0x01)
+ writePort(g_ucPinTRST, 0x01);
+ else
+ writePort(g_ucPinTRST, 0x00);
+ ispVMDelay(1);
+ break;
+ default:
+
+ /*
+ *
+ * Invalid opcode encountered.
+ *
+ */
+
+#ifdef DEBUG
+ printf("\nINVALID OPCODE: 0x%.2X\n", cOpcode);
+#endif /* DEBUG */
+
+ return VME_INVALID_FILE;
+ }
+ }
+
+ /*
+ *
+ * Invalid exit point. Processing the token 'ENDVME' is the only
+ * valid way to exit the embedded engine.
+ *
+ */
+
+ return VME_INVALID_FILE;
+}
+
+/*
+ *
+ * ispVMDataCode
+ *
+ * Processes the TDI/TDO/MASK/DMASK etc of an SIR/SDR command.
+ *
+ */
+
+signed char ispVMDataCode()
+{
+ /* 09/11/07 NN added local variables initialization */
+ signed char cDataByte = 0;
+ signed char siDataSource = 0; /*source of data from file by default*/
+
+ if (g_usDataType & HEAP_IN) {
+ siDataSource = 1; /*the source of data from memory*/
+ }
+
+ /*
+ *
+ * Clear the data type register.
+ *
+ **/
+
+ g_usDataType &= ~(MASK_DATA + TDI_DATA +
+ TDO_DATA + DMASK_DATA + CMASK_DATA);
+
+ /*
+ * Iterate through SIR/SDR command and look for TDI,
+ * TDO, MASK, etc.
+ */
+
+ while ((cDataByte = GetByte()) >= 0) {
+ ispVMMemManager(cDataByte, g_usMaxSize);
+ switch (cDataByte) {
+ case TDI:
+
+ /*
+ * Store the maximum size of the TDI buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usTDISize) {
+ g_usTDISize = g_usiDataSize;
+ }
+ /*
+ * Updated data type register to indicate that
+ * TDI data is currently being used. Process the
+ * data in the VME file into the TDI buffer.
+ */
+
+ g_usDataType |= TDI_DATA;
+ ispVMData(g_pucInData);
+ break;
+ case XTDO:
+
+ /*
+ * Store the maximum size of the TDO buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usTDOSize) {
+ g_usTDOSize = g_usiDataSize;
+ }
+
+ /*
+ * Updated data type register to indicate that
+ * TDO data is currently being used.
+ */
+
+ g_usDataType |= TDO_DATA;
+ break;
+ case TDO:
+
+ /*
+ * Store the maximum size of the TDO buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usTDOSize) {
+ g_usTDOSize = g_usiDataSize;
+ }
+
+ /*
+ * Updated data type register to indicate
+ * that TDO data is currently being used.
+ * Process the data in the VME file into the
+ * TDO buffer.
+ */
+
+ g_usDataType |= TDO_DATA;
+ ispVMData(g_pucOutData);
+ break;
+ case MASK:
+
+ /*
+ * Store the maximum size of the MASK buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usMASKSize) {
+ g_usMASKSize = g_usiDataSize;
+ }
+
+ /*
+ * Updated data type register to indicate that
+ * MASK data is currently being used. Process
+ * the data in the VME file into the MASK buffer
+ */
+
+ g_usDataType |= MASK_DATA;
+ ispVMData(g_pucOutMaskData);
+ break;
+ case DMASK:
+
+ /*
+ * Store the maximum size of the DMASK buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usDMASKSize) {
+ g_usDMASKSize = g_usiDataSize;
+ }
+
+ /*
+ * Updated data type register to indicate that
+ * DMASK data is currently being used. Process
+ * the data in the VME file into the DMASK
+ * buffer.
+ */
+
+ g_usDataType |= DMASK_DATA;
+ ispVMData(g_pucOutDMaskData);
+ break;
+ case CMASK:
+
+ /*
+ * Updated data type register to indicate that
+ * MASK data is currently being used. Process
+ * the data in the VME file into the MASK buffer
+ */
+
+ g_usDataType |= CMASK_DATA;
+ ispVMData(g_pucOutMaskData);
+ break;
+ case CONTINUE:
+ return 0;
+ default:
+ /*
+ * Encountered invalid opcode.
+ */
+ return VME_INVALID_FILE;
+ }
+
+ switch (cDataByte) {
+ case TDI:
+
+ /*
+ * Left bit shift. Used when performing
+ * algorithm looping.
+ */
+
+ if (g_usFlowControl & SHIFTLEFT) {
+ ispVMBitShift(SHL, g_usShiftValue);
+ g_usFlowControl &= ~SHIFTLEFT;
+ }
+
+ /*
+ * Right bit shift. Used when performing
+ * algorithm looping.
+ */
+
+ if (g_usFlowControl & SHIFTRIGHT) {
+ ispVMBitShift(SHR, g_usShiftValue);
+ g_usFlowControl &= ~SHIFTRIGHT;
+ }
+ default:
+ break;
+ }
+
+ if (siDataSource) {
+ g_usDataType |= HEAP_IN; /*restore from memory*/
+ }
+ }
+
+ if (siDataSource) { /*fetch data from heap memory upon return*/
+ g_usDataType |= HEAP_IN;
+ }
+
+ if (cDataByte < 0) {
+
+ /*
+ * Encountered invalid opcode.
+ */
+
+ return VME_INVALID_FILE;
+ } else {
+ return 0;
+ }
+}
+
+/*
+ *
+ * ispVMData
+ * Extract one row of data operand from the current data type opcode. Perform
+ * the decompression if necessary. Extra RAM is not required for the
+ * decompression process. The decompression scheme employed in this module
+ * is on row by row basis. The format of the data stream:
+ * [compression code][compressed data stream]
+ * 0x00 --No compression
+ * 0x01 --Compress by 0x00.
+ * Example:
+ * Original stream: 0x000000000000000000000001
+ * Compressed stream: 0x01000901
+ * Detail: 0x01 is the code, 0x00 is the key,
+ * 0x09 is the count of 0x00 bytes,
+ * 0x01 is the uncompressed byte.
+ * 0x02 --Compress by 0xFF.
+ * Example:
+ * Original stream: 0xFFFFFFFFFFFFFFFFFFFFFF01
+ * Compressed stream: 0x02FF0901
+ * Detail: 0x02 is the code, 0xFF is the key,
+ * 0x09 is the count of 0xFF bytes,
+ * 0x01 is the uncompressed byte.
+ * 0x03
+ * : :
+ * 0xFE -- Compress by nibble blocks.
+ * Example:
+ * Original stream: 0x84210842108421084210
+ * Compressed stream: 0x0584210
+ * Detail: 0x05 is the code, means 5 nibbles block.
+ * 0x84210 is the 5 nibble blocks.
+ * The whole row is 80 bits given by g_usiDataSize.
+ * The number of times the block repeat itself
+ * is found by g_usiDataSize/(4*0x05) which is 4.
+ * 0xFF -- Compress by the most frequently happen byte.
+ * Example:
+ * Original stream: 0x04020401030904040404
+ * Compressed stream: 0xFF04(0,1,0x02,0,1,0x01,1,0x03,1,0x09,0,0,0)
+ * or: 0xFF044090181C240
+ * Detail: 0xFF is the code, 0x04 is the key.
+ * a bit of 0 represent the key shall be put into
+ * the current bit position and a bit of 1
+ * represent copying the next of 8 bits of data
+ * in.
+ *
+ */
+
+void ispVMData(unsigned char *ByteData)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short size = 0;
+ unsigned short i, j, m, getData = 0;
+ unsigned char cDataByte = 0;
+ unsigned char compress = 0;
+ unsigned short FFcount = 0;
+ unsigned char compr_char = 0xFF;
+ unsigned short index = 0;
+ signed char compression = 0;
+
+ /*convert number in bits to bytes*/
+ if (g_usiDataSize % 8 > 0) {
+ /* 09/11/07 NN Type cast mismatch variables */
+ size = (unsigned short)(g_usiDataSize / 8 + 1);
+ } else {
+ /* 09/11/07 NN Type cast mismatch variables */
+ size = (unsigned short)(g_usiDataSize / 8);
+ }
+
+ /*
+ * If there is compression, then check if compress by key
+ * of 0x00 or 0xFF or by other keys or by nibble blocks
+ */
+
+ if (g_usDataType & COMPRESS) {
+ compression = 1;
+ compress = GetByte();
+ if ((compress == VAR) && (g_usDataType & HEAP_IN)) {
+ getData = 1;
+ g_usDataType &= ~(HEAP_IN);
+ compress = GetByte();
+ }
+
+ switch (compress) {
+ case 0x00:
+ /* No compression */
+ compression = 0;
+ break;
+ case 0x01:
+ /* Compress by byte 0x00 */
+ compr_char = 0x00;
+ break;
+ case 0x02:
+ /* Compress by byte 0xFF */
+ compr_char = 0xFF;
+ break;
+ case 0xFF:
+ /* Huffman encoding */
+ compr_char = GetByte();
+ i = 8;
+ for (index = 0; index < size; index++) {
+ ByteData[index] = 0x00;
+ if (i > 7) {
+ cDataByte = GetByte();
+ i = 0;
+ }
+ if ((cDataByte << i++) & 0x80)
+ m = 8;
+ else {
+ ByteData[index] = compr_char;
+ m = 0;
+ }
+
+ for (j = 0; j < m; j++) {
+ if (i > 7) {
+ cDataByte = GetByte();
+ i = 0;
+ }
+ ByteData[index] |=
+ ((cDataByte << i++) & 0x80) >> j;
+ }
+ }
+ size = 0;
+ break;
+ default:
+ for (index = 0; index < size; index++)
+ ByteData[index] = 0x00;
+ for (index = 0; index < compress; index++) {
+ if (index % 2 == 0)
+ cDataByte = GetByte();
+ for (i = 0; i < size * 2 / compress; i++) {
+ j = (unsigned short)(index +
+ (i * (unsigned short)compress));
+ /*clear the nibble to zero first*/
+ if (j%2) {
+ if (index % 2)
+ ByteData[j/2] |=
+ cDataByte & 0xF;
+ else
+ ByteData[j/2] |=
+ cDataByte >> 4;
+ } else {
+ if (index % 2)
+ ByteData[j/2] |=
+ cDataByte << 4;
+ else
+ ByteData[j/2] |=
+ cDataByte & 0xF0;
+ }
+ }
+ }
+ size = 0;
+ break;
+ }
+ }
+
+ FFcount = 0;
+
+ /* Decompress by byte 0x00 or 0xFF */
+ for (index = 0; index < size; index++) {
+ if (FFcount <= 0) {
+ cDataByte = GetByte();
+ if ((cDataByte == VAR) && (g_usDataType&HEAP_IN) &&
+ !getData && !(g_usDataType&COMPRESS)) {
+ getData = 1;
+ g_usDataType &= ~(HEAP_IN);
+ cDataByte = GetByte();
+ }
+ ByteData[index] = cDataByte;
+ if ((compression) && (cDataByte == compr_char))
+ /* 09/11/07 NN Type cast mismatch variables */
+ FFcount = (unsigned short) ispVMDataSize();
+ /*The number of 0xFF or 0x00 bytes*/
+ } else {
+ FFcount--; /*Use up the 0xFF chain first*/
+ ByteData[index] = compr_char;
+ }
+ }
+
+ if (getData) {
+ g_usDataType |= HEAP_IN;
+ getData = 0;
+ }
+}
+
+/*
+ *
+ * ispVMShift
+ *
+ * Processes the SDR/XSDR/SIR commands.
+ *
+ */
+
+signed char ispVMShift(signed char a_cCode)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short iDataIndex = 0;
+ unsigned short iReadLoop = 0;
+ signed char cRetCode = 0;
+
+ cRetCode = 0;
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usiDataSize = (unsigned short) ispVMDataSize();
+
+ /*clear the flags first*/
+ g_usDataType &= ~(SIR_DATA + EXPRESS + SDR_DATA);
+ switch (a_cCode) {
+ case SIR:
+ g_usDataType |= SIR_DATA;
+ /*
+ * 1/15/04 If performing cascading, then go directly to SHIFTIR.
+ * Else, go to IRPAUSE before going to SHIFTIR
+ */
+ if (g_usFlowControl & CASCADE) {
+ ispVMStateMachine(SHIFTIR);
+ } else {
+ ispVMStateMachine(IRPAUSE);
+ ispVMStateMachine(SHIFTIR);
+ if (g_usHeadIR > 0) {
+ ispVMBypass(HIR, g_usHeadIR);
+ sclock();
+ }
+ }
+ break;
+ case XSDR:
+ g_usDataType |= EXPRESS; /*mark simultaneous in and out*/
+ case SDR:
+ g_usDataType |= SDR_DATA;
+ /*
+ * 1/15/04 If already in SHIFTDR, then do not move state or
+ * shift in header. This would imply that the previously
+ * shifted frame was a cascaded frame.
+ */
+ if (g_cCurrentJTAGState != SHIFTDR) {
+ /*
+ * 1/15/04 If performing cascading, then go directly
+ * to SHIFTDR. Else, go to DRPAUSE before going
+ * to SHIFTDR
+ */
+ if (g_usFlowControl & CASCADE) {
+ if (g_cCurrentJTAGState == DRPAUSE) {
+ ispVMStateMachine(SHIFTDR);
+ /*
+ * 1/15/04 If cascade flag has been seat
+ * and the current state is DRPAUSE,
+ * this implies that the first cascaded
+ * frame is about to be shifted in. The
+ * header must be shifted prior to
+ * shifting the first cascaded frame.
+ */
+ if (g_usHeadDR > 0) {
+ ispVMBypass(HDR, g_usHeadDR);
+ sclock();
+ }
+ } else {
+ ispVMStateMachine(SHIFTDR);
+ }
+ } else {
+ ispVMStateMachine(DRPAUSE);
+ ispVMStateMachine(SHIFTDR);
+ if (g_usHeadDR > 0) {
+ ispVMBypass(HDR, g_usHeadDR);
+ sclock();
+ }
+ }
+ }
+ break;
+ default:
+ return VME_INVALID_FILE;
+ }
+
+ cRetCode = ispVMDataCode();
+
+ if (cRetCode != 0) {
+ return VME_INVALID_FILE;
+ }
+
+#ifdef DEBUG
+ printf("%d ", g_usiDataSize);
+
+ if (g_usDataType & TDI_DATA) {
+ puts("TDI ");
+ PrintData(g_usiDataSize, g_pucInData);
+ }
+
+ if (g_usDataType & TDO_DATA) {
+ puts("\n\t\tTDO ");
+ PrintData(g_usiDataSize, g_pucOutData);
+ }
+
+ if (g_usDataType & MASK_DATA) {
+ puts("\n\t\tMASK ");
+ PrintData(g_usiDataSize, g_pucOutMaskData);
+ }
+
+ if (g_usDataType & DMASK_DATA) {
+ puts("\n\t\tDMASK ");
+ PrintData(g_usiDataSize, g_pucOutDMaskData);
+ }
+
+ puts(";\n");
+#endif /* DEBUG */
+
+ if (g_usDataType & TDO_DATA || g_usDataType & DMASK_DATA) {
+ if (g_usDataType & DMASK_DATA) {
+ cRetCode = ispVMReadandSave(g_usiDataSize);
+ if (!cRetCode) {
+ if (g_usTailDR > 0) {
+ sclock();
+ ispVMBypass(TDR, g_usTailDR);
+ }
+ ispVMStateMachine(DRPAUSE);
+ ispVMStateMachine(SHIFTDR);
+ if (g_usHeadDR > 0) {
+ ispVMBypass(HDR, g_usHeadDR);
+ sclock();
+ }
+ for (iDataIndex = 0;
+ iDataIndex < g_usiDataSize / 8 + 1;
+ iDataIndex++)
+ g_pucInData[iDataIndex] =
+ g_pucOutData[iDataIndex];
+ g_usDataType &= ~(TDO_DATA + DMASK_DATA);
+ cRetCode = ispVMSend(g_usiDataSize);
+ }
+ } else {
+ cRetCode = ispVMRead(g_usiDataSize);
+ if (cRetCode == -1 && g_cVendor == XILINX) {
+ for (iReadLoop = 0; iReadLoop < 30;
+ iReadLoop++) {
+ cRetCode = ispVMRead(g_usiDataSize);
+ if (!cRetCode) {
+ break;
+ } else {
+ /* Always DRPAUSE */
+ ispVMStateMachine(DRPAUSE);
+ /*
+ * Bypass other devices
+ * when appropriate
+ */
+ ispVMBypass(TDR, g_usTailDR);
+ ispVMStateMachine(g_ucEndDR);
+ ispVMStateMachine(IDLE);
+ ispVMDelay(1000);
+ }
+ }
+ }
+ }
+ } else { /*TDI only*/
+ cRetCode = ispVMSend(g_usiDataSize);
+ }
+
+ /*transfer the input data to the output buffer for the next verify*/
+ if ((g_usDataType & EXPRESS) || (a_cCode == SDR)) {
+ if (g_pucOutData) {
+ for (iDataIndex = 0; iDataIndex < g_usiDataSize / 8 + 1;
+ iDataIndex++)
+ g_pucOutData[iDataIndex] =
+ g_pucInData[iDataIndex];
+ }
+ }
+
+ switch (a_cCode) {
+ case SIR:
+ /* 1/15/04 If not performing cascading, then shift ENDIR */
+ if (!(g_usFlowControl & CASCADE)) {
+ if (g_usTailIR > 0) {
+ sclock();
+ ispVMBypass(TIR, g_usTailIR);
+ }
+ ispVMStateMachine(g_ucEndIR);
+ }
+ break;
+ case XSDR:
+ case SDR:
+ /* 1/15/04 If not performing cascading, then shift ENDDR */
+ if (!(g_usFlowControl & CASCADE)) {
+ if (g_usTailDR > 0) {
+ sclock();
+ ispVMBypass(TDR, g_usTailDR);
+ }
+ ispVMStateMachine(g_ucEndDR);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return cRetCode;
+}
+
+/*
+ *
+ * ispVMAmble
+ *
+ * This routine is to extract Header and Trailer parameter for SIR and
+ * SDR operations.
+ *
+ * The Header and Trailer parameter are the pre-amble and post-amble bit
+ * stream need to be shifted into TDI or out of TDO of the devices. Mostly
+ * is for the purpose of bypassing the leading or trailing devices. ispVM
+ * supports only shifting data into TDI to bypass the devices.
+ *
+ * For a single device, the header and trailer parameters are all set to 0
+ * as default by ispVM. If it is for multiple devices, the header and trailer
+ * value will change as specified by the VME file.
+ *
+ */
+
+signed char ispVMAmble(signed char Code)
+{
+ signed char compress = 0;
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_usiDataSize = (unsigned short)ispVMDataSize();
+
+#ifdef DEBUG
+ printf("%d", g_usiDataSize);
+#endif /* DEBUG */
+
+ if (g_usiDataSize) {
+
+ /*
+ * Discard the TDI byte and set the compression bit in the data
+ * type register to false if compression is set because TDI data
+ * after HIR/HDR/TIR/TDR is not compressed.
+ */
+
+ GetByte();
+ if (g_usDataType & COMPRESS) {
+ g_usDataType &= ~(COMPRESS);
+ compress = 1;
+ }
+ }
+
+ switch (Code) {
+ case HIR:
+
+ /*
+ * Store the maximum size of the HIR buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usHIRSize) {
+ g_usHIRSize = g_usiDataSize;
+ }
+
+ /*
+ * Assign the HIR value and allocate memory.
+ */
+
+ g_usHeadIR = g_usiDataSize;
+ if (g_usHeadIR) {
+ ispVMMemManager(HIR, g_usHeadIR);
+ ispVMData(g_pucHIRData);
+
+#ifdef DEBUG
+ puts(" TDI ");
+ PrintData(g_usHeadIR, g_pucHIRData);
+#endif /* DEBUG */
+ }
+ break;
+ case TIR:
+
+ /*
+ * Store the maximum size of the TIR buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usTIRSize) {
+ g_usTIRSize = g_usiDataSize;
+ }
+
+ /*
+ * Assign the TIR value and allocate memory.
+ */
+
+ g_usTailIR = g_usiDataSize;
+ if (g_usTailIR) {
+ ispVMMemManager(TIR, g_usTailIR);
+ ispVMData(g_pucTIRData);
+
+#ifdef DEBUG
+ puts(" TDI ");
+ PrintData(g_usTailIR, g_pucTIRData);
+#endif /* DEBUG */
+ }
+ break;
+ case HDR:
+
+ /*
+ * Store the maximum size of the HDR buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usHDRSize) {
+ g_usHDRSize = g_usiDataSize;
+ }
+
+ /*
+ * Assign the HDR value and allocate memory.
+ *
+ */
+
+ g_usHeadDR = g_usiDataSize;
+ if (g_usHeadDR) {
+ ispVMMemManager(HDR, g_usHeadDR);
+ ispVMData(g_pucHDRData);
+
+#ifdef DEBUG
+ puts(" TDI ");
+ PrintData(g_usHeadDR, g_pucHDRData);
+#endif /* DEBUG */
+ }
+ break;
+ case TDR:
+
+ /*
+ * Store the maximum size of the TDR buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usiDataSize > g_usTDRSize) {
+ g_usTDRSize = g_usiDataSize;
+ }
+
+ /*
+ * Assign the TDR value and allocate memory.
+ *
+ */
+
+ g_usTailDR = g_usiDataSize;
+ if (g_usTailDR) {
+ ispVMMemManager(TDR, g_usTailDR);
+ ispVMData(g_pucTDRData);
+
+#ifdef DEBUG
+ puts(" TDI ");
+ PrintData(g_usTailDR, g_pucTDRData);
+#endif /* DEBUG */
+ }
+ break;
+ default:
+ break;
+ }
+
+ /*
+ *
+ * Re-enable compression if it was previously set.
+ *
+ **/
+
+ if (compress) {
+ g_usDataType |= COMPRESS;
+ }
+
+ if (g_usiDataSize) {
+ Code = GetByte();
+ if (Code == CONTINUE) {
+ return 0;
+ } else {
+
+ /*
+ * Encountered invalid opcode.
+ */
+
+ return VME_INVALID_FILE;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ *
+ * ispVMLoop
+ *
+ * Perform the function call upon by the REPEAT opcode.
+ * Memory is to be allocated to store the entire loop from REPEAT to ENDLOOP.
+ * After the loop is stored then execution begin. The REPEATLOOP flag is set
+ * on the g_usFlowControl register to indicate the repeat loop is in session
+ * and therefore fetch opcode from the memory instead of from the file.
+ *
+ */
+
+signed char ispVMLoop(unsigned short a_usLoopCount)
+{
+ /* 09/11/07 NN added local variables initialization */
+ signed char cRetCode = 0;
+ unsigned short iHeapIndex = 0;
+ unsigned short iLoopIndex = 0;
+
+ g_usShiftValue = 0;
+ for (iHeapIndex = 0; iHeapIndex < g_iHEAPSize; iHeapIndex++) {
+ g_pucHeapMemory[iHeapIndex] = GetByte();
+ }
+
+ if (g_pucHeapMemory[iHeapIndex - 1] != ENDLOOP) {
+ return VME_INVALID_FILE;
+ }
+
+ g_usFlowControl |= REPEATLOOP;
+ g_usDataType |= HEAP_IN;
+
+ for (iLoopIndex = 0; iLoopIndex < a_usLoopCount; iLoopIndex++) {
+ g_iHeapCounter = 0;
+ cRetCode = ispVMCode();
+ g_usRepeatLoops++;
+ if (cRetCode < 0) {
+ break;
+ }
+ }
+
+ g_usDataType &= ~(HEAP_IN);
+ g_usFlowControl &= ~(REPEATLOOP);
+ return cRetCode;
+}
+
+/*
+ *
+ * ispVMBitShift
+ *
+ * Shift the TDI stream left or right by the number of bits. The data in
+ * *g_pucInData is of the VME format, so the actual shifting is the reverse of
+ * IEEE 1532 or SVF format.
+ *
+ */
+
+signed char ispVMBitShift(signed char mode, unsigned short bits)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short i = 0;
+ unsigned short size = 0;
+ unsigned short tmpbits = 0;
+
+ if (g_usiDataSize % 8 > 0) {
+ /* 09/11/07 NN Type cast mismatch variables */
+ size = (unsigned short)(g_usiDataSize / 8 + 1);
+ } else {
+ /* 09/11/07 NN Type cast mismatch variables */
+ size = (unsigned short)(g_usiDataSize / 8);
+ }
+
+ switch (mode) {
+ case SHR:
+ for (i = 0; i < size; i++) {
+ if (g_pucInData[i] != 0) {
+ tmpbits = bits;
+ while (tmpbits > 0) {
+ g_pucInData[i] <<= 1;
+ if (g_pucInData[i] == 0) {
+ i--;
+ g_pucInData[i] = 1;
+ }
+ tmpbits--;
+ }
+ }
+ }
+ break;
+ case SHL:
+ for (i = 0; i < size; i++) {
+ if (g_pucInData[i] != 0) {
+ tmpbits = bits;
+ while (tmpbits > 0) {
+ g_pucInData[i] >>= 1;
+ if (g_pucInData[i] == 0) {
+ i--;
+ g_pucInData[i] = 8;
+ }
+ tmpbits--;
+ }
+ }
+ }
+ break;
+ default:
+ return VME_INVALID_FILE;
+ }
+
+ return 0;
+}
+
+/*
+ *
+ * ispVMComment
+ *
+ * Displays the SVF comments.
+ *
+ */
+
+void ispVMComment(unsigned short a_usCommentSize)
+{
+ char cCurByte = 0;
+ for (; a_usCommentSize > 0; a_usCommentSize--) {
+ /*
+ *
+ * Print character to the terminal.
+ *
+ **/
+ cCurByte = GetByte();
+ vme_out_char(cCurByte);
+ }
+ cCurByte = '\n';
+ vme_out_char(cCurByte);
+}
+
+/*
+ *
+ * ispVMHeader
+ *
+ * Iterate the length of the header and discard it.
+ *
+ */
+
+void ispVMHeader(unsigned short a_usHeaderSize)
+{
+ for (; a_usHeaderSize > 0; a_usHeaderSize--) {
+ GetByte();
+ }
+}
+
+/*
+ *
+ * ispVMCalculateCRC32
+ *
+ * Calculate the 32-bit CRC.
+ *
+ */
+
+void ispVMCalculateCRC32(unsigned char a_ucData)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned char ucIndex = 0;
+ unsigned char ucFlipData = 0;
+ unsigned short usCRCTableEntry = 0;
+ unsigned int crc_table[16] = {
+ 0x0000, 0xCC01, 0xD801,
+ 0x1400, 0xF001, 0x3C00,
+ 0x2800, 0xE401, 0xA001,
+ 0x6C00, 0x7800, 0xB401,
+ 0x5000, 0x9C01, 0x8801,
+ 0x4400
+ };
+
+ for (ucIndex = 0; ucIndex < 8; ucIndex++) {
+ ucFlipData <<= 1;
+ if (a_ucData & 0x01) {
+ ucFlipData |= 0x01;
+ }
+ a_ucData >>= 1;
+ }
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]);
+ g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF);
+ g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^
+ usCRCTableEntry ^ crc_table[ucFlipData & 0xF]);
+ usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]);
+ g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF);
+ g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^
+ usCRCTableEntry ^ crc_table[(ucFlipData >> 4) & 0xF]);
+}
+
+/*
+ *
+ * ispVMLCOUNT
+ *
+ * Process the intelligent programming loops.
+ *
+ */
+
+signed char ispVMLCOUNT(unsigned short a_usCountSize)
+{
+ unsigned short usContinue = 1;
+ unsigned short usIntelBufferIndex = 0;
+ unsigned short usCountIndex = 0;
+ signed char cRetCode = 0;
+ signed char cRepeatHeap = 0;
+ signed char cOpcode = 0;
+ unsigned char ucState = 0;
+ unsigned short usDelay = 0;
+ unsigned short usToggle = 0;
+ unsigned char usByte = 0;
+
+ g_usIntelBufferSize = (unsigned short)ispVMDataSize();
+
+ /*
+ * Allocate memory for intel buffer.
+ *
+ */
+
+ ispVMMemManager(LHEAP, g_usIntelBufferSize);
+
+ /*
+ * Store the maximum size of the intelligent buffer.
+ * Used to convert VME to HEX.
+ */
+
+ if (g_usIntelBufferSize > g_usLCOUNTSize) {
+ g_usLCOUNTSize = g_usIntelBufferSize;
+ }
+
+ /*
+ * Copy intel data to the buffer.
+ */
+
+ for (usIntelBufferIndex = 0; usIntelBufferIndex < g_usIntelBufferSize;
+ usIntelBufferIndex++) {
+ g_pucIntelBuffer[usIntelBufferIndex] = GetByte();
+ }
+
+ /*
+ * Set the data type register to get data from the intelligent
+ * data buffer.
+ */
+
+ g_usDataType |= LHEAP_IN;
+
+ /*
+ *
+ * If the HEAP_IN flag is set, temporarily unset the flag so data will be
+ * retrieved from the status buffer.
+ *
+ **/
+
+ if (g_usDataType & HEAP_IN) {
+ g_usDataType &= ~HEAP_IN;
+ cRepeatHeap = 1;
+ }
+
+#ifdef DEBUG
+ printf("LCOUNT %d;\n", a_usCountSize);
+#endif /* DEBUG */
+
+ /*
+ * Iterate through the intelligent programming command.
+ */
+
+ for (usCountIndex = 0; usCountIndex < a_usCountSize; usCountIndex++) {
+
+ /*
+ *
+ * Initialize the intel data index to 0 before each iteration.
+ *
+ **/
+
+ g_usIntelDataIndex = 0;
+ cOpcode = 0;
+ ucState = 0;
+ usDelay = 0;
+ usToggle = 0;
+ usByte = 0;
+ usContinue = 1;
+
+ /*
+ *
+ * Begin looping through all the VME opcodes.
+ *
+ */
+ /*
+ * 4/1/09 Nguyen replaced the recursive function call codes on
+ * the ispVMLCOUNT function
+ *
+ */
+ while (usContinue) {
+ cOpcode = GetByte();
+ switch (cOpcode) {
+ case HIR:
+ case TIR:
+ case HDR:
+ case TDR:
+ /*
+ * Set the header/trailer of the device in order
+ * to bypass successfully.
+ */
+
+ ispVMAmble(cOpcode);
+ break;
+ case STATE:
+
+ /*
+ * Step the JTAG state machine.
+ */
+
+ ucState = GetByte();
+ /*
+ * Step the JTAG state machine to DRCAPTURE
+ * to support Looping.
+ */
+
+ if ((g_usDataType & LHEAP_IN) &&
+ (ucState == DRPAUSE) &&
+ (g_cCurrentJTAGState == ucState)) {
+ ispVMStateMachine(DRCAPTURE);
+ }
+ ispVMStateMachine(ucState);
+#ifdef DEBUG
+ printf("LDELAY %s ", GetState(ucState));
+#endif /* DEBUG */
+ break;
+ case SIR:
+#ifdef DEBUG
+ printf("SIR ");
+#endif /* DEBUG */
+ /*
+ * Shift in data into the device.
+ */
+
+ cRetCode = ispVMShift(cOpcode);
+ break;
+ case SDR:
+
+#ifdef DEBUG
+ printf("LSDR ");
+#endif /* DEBUG */
+ /*
+ * Shift in data into the device.
+ */
+
+ cRetCode = ispVMShift(cOpcode);
+ break;
+ case WAIT:
+
+ /*
+ *
+ * Observe delay.
+ *
+ */
+
+ usDelay = (unsigned short)ispVMDataSize();
+ ispVMDelay(usDelay);
+
+#ifdef DEBUG
+ if (usDelay & 0x8000) {
+
+ /*
+ * Since MSB is set, the delay time must
+ * be decoded to millisecond. The
+ * SVF2VME encodes the MSB to represent
+ * millisecond.
+ */
+
+ usDelay &= ~0x8000;
+ printf("%.2E SEC;\n",
+ (float) usDelay / 1000);
+ } else {
+ /*
+ * Since MSB is not set, the delay time
+ * is given as microseconds.
+ */
+
+ printf("%.2E SEC;\n",
+ (float) usDelay / 1000000);
+ }
+#endif /* DEBUG */
+ break;
+ case TCK:
+
+ /*
+ * Issue clock toggles.
+ */
+
+ usToggle = (unsigned short)ispVMDataSize();
+ ispVMClocks(usToggle);
+
+#ifdef DEBUG
+ printf("RUNTEST %d TCK;\n", usToggle);
+#endif /* DEBUG */
+ break;
+ case ENDLOOP:
+
+ /*
+ * Exit point from processing loops.
+ */
+ usContinue = 0;
+ break;
+
+ case COMMENT:
+
+ /*
+ * Display comment.
+ */
+
+ ispVMComment((unsigned short) ispVMDataSize());
+ break;
+ case ispEN:
+ ucState = GetByte();
+ if ((ucState == ON) || (ucState == 0x01))
+ writePort(g_ucPinENABLE, 0x01);
+ else
+ writePort(g_ucPinENABLE, 0x00);
+ ispVMDelay(1);
+ break;
+ case TRST:
+ if (GetByte() == 0x01)
+ writePort(g_ucPinTRST, 0x01);
+ else
+ writePort(g_ucPinTRST, 0x00);
+ ispVMDelay(1);
+ break;
+ default:
+
+ /*
+ * Invalid opcode encountered.
+ */
+
+ debug("\nINVALID OPCODE: 0x%.2X\n", cOpcode);
+
+ return VME_INVALID_FILE;
+ }
+ }
+ if (cRetCode >= 0) {
+ /*
+ * Break if intelligent programming is successful.
+ */
+
+ break;
+ }
+
+ }
+ /*
+ * If HEAP_IN flag was temporarily disabled,
+ * re-enable it before exiting
+ */
+
+ if (cRepeatHeap) {
+ g_usDataType |= HEAP_IN;
+ }
+
+ /*
+ * Set the data type register to not get data from the
+ * intelligent data buffer.
+ */
+
+ g_usDataType &= ~LHEAP_IN;
+ return cRetCode;
+}
+/*
+ *
+ * ispVMClocks
+ *
+ * Applies the specified number of pulses to TCK.
+ *
+ */
+
+void ispVMClocks(unsigned short Clocks)
+{
+ unsigned short iClockIndex = 0;
+ for (iClockIndex = 0; iClockIndex < Clocks; iClockIndex++) {
+ sclock();
+ }
+}
+
+/*
+ *
+ * ispVMBypass
+ *
+ * This procedure takes care of the HIR, HDR, TIR, TDR for the
+ * purpose of putting the other devices into Bypass mode. The
+ * current state is checked to find out if it is at DRPAUSE or
+ * IRPAUSE. If it is at DRPAUSE, perform bypass register scan.
+ * If it is at IRPAUSE, scan into instruction registers the bypass
+ * instruction.
+ *
+ */
+
+void ispVMBypass(signed char ScanType, unsigned short Bits)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short iIndex = 0;
+ unsigned short iSourceIndex = 0;
+ unsigned char cBitState = 0;
+ unsigned char cCurByte = 0;
+ unsigned char *pcSource = NULL;
+
+ if (Bits <= 0) {
+ return;
+ }
+
+ switch (ScanType) {
+ case HIR:
+ pcSource = g_pucHIRData;
+ break;
+ case TIR:
+ pcSource = g_pucTIRData;
+ break;
+ case HDR:
+ pcSource = g_pucHDRData;
+ break;
+ case TDR:
+ pcSource = g_pucTDRData;
+ break;
+ default:
+ break;
+ }
+
+ iSourceIndex = 0;
+ cBitState = 0;
+ for (iIndex = 0; iIndex < Bits - 1; iIndex++) {
+ /* Scan instruction or bypass register */
+ if (iIndex % 8 == 0) {
+ cCurByte = pcSource[iSourceIndex++];
+ }
+ cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
+ ? 0x01 : 0x00);
+ writePort(g_ucPinTDI, cBitState);
+ sclock();
+ }
+
+ if (iIndex % 8 == 0) {
+ cCurByte = pcSource[iSourceIndex++];
+ }
+
+ cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
+ ? 0x01 : 0x00);
+ writePort(g_ucPinTDI, cBitState);
+}
+
+/*
+ *
+ * ispVMStateMachine
+ *
+ * This procedure steps all devices in the daisy chain from a given
+ * JTAG state to the next desirable state. If the next state is TLR,
+ * the JTAG state machine is brute forced into TLR by driving TMS
+ * high and pulse TCK 6 times.
+ *
+ */
+
+void ispVMStateMachine(signed char cNextJTAGState)
+{
+ /* 09/11/07 NN added local variables initialization */
+ signed char cPathIndex = 0;
+ signed char cStateIndex = 0;
+
+ if ((g_cCurrentJTAGState == cNextJTAGState) &&
+ (cNextJTAGState != RESET)) {
+ return;
+ }
+
+ for (cStateIndex = 0; cStateIndex < 25; cStateIndex++) {
+ if ((g_cCurrentJTAGState ==
+ g_JTAGTransistions[cStateIndex].CurState) &&
+ (cNextJTAGState ==
+ g_JTAGTransistions[cStateIndex].NextState)) {
+ break;
+ }
+ }
+
+ g_cCurrentJTAGState = cNextJTAGState;
+ for (cPathIndex = 0;
+ cPathIndex < g_JTAGTransistions[cStateIndex].Pulses;
+ cPathIndex++) {
+ if ((g_JTAGTransistions[cStateIndex].Pattern << cPathIndex)
+ & 0x80) {
+ writePort(g_ucPinTMS, (unsigned char) 0x01);
+ } else {
+ writePort(g_ucPinTMS, (unsigned char) 0x00);
+ }
+ sclock();
+ }
+
+ writePort(g_ucPinTDI, 0x00);
+ writePort(g_ucPinTMS, 0x00);
+}
+
+/*
+ *
+ * ispVMStart
+ *
+ * Enable the port to the device and set the state to RESET (TLR).
+ *
+ */
+
+void ispVMStart()
+{
+#ifdef DEBUG
+ printf("// ISPVM EMBEDDED ADDED\n");
+ printf("STATE RESET;\n");
+#endif
+ g_usFlowControl = 0;
+ g_usDataType = g_uiChecksumIndex = g_cCurrentJTAGState = 0;
+ g_usHeadDR = g_usHeadIR = g_usTailDR = g_usTailIR = 0;
+ g_usMaxSize = g_usShiftValue = g_usRepeatLoops = 0;
+ g_usTDOSize = g_usMASKSize = g_usTDISize = 0;
+ g_usDMASKSize = g_usLCOUNTSize = g_usHDRSize = 0;
+ g_usTDRSize = g_usHIRSize = g_usTIRSize = g_usHeapSize = 0;
+ g_pLVDSList = NULL;
+ g_usLVDSPairCount = 0;
+ previous_size = 0;
+
+ ispVMStateMachine(RESET); /*step devices to RESET state*/
+}
+
+/*
+ *
+ * ispVMEnd
+ *
+ * Set the state of devices to RESET to enable the devices and disable
+ * the port.
+ *
+ */
+
+void ispVMEnd()
+{
+#ifdef DEBUG
+ printf("// ISPVM EMBEDDED ADDED\n");
+ printf("STATE RESET;\n");
+ printf("RUNTEST 1.00E-001 SEC;\n");
+#endif
+
+ ispVMStateMachine(RESET); /*step devices to RESET state */
+ ispVMDelay(1000); /*wake up devices*/
+}
+
+/*
+ *
+ * ispVMSend
+ *
+ * Send the TDI data stream to devices. The data stream can be
+ * instructions or data.
+ *
+ */
+
+signed char ispVMSend(unsigned short a_usiDataSize)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short iIndex = 0;
+ unsigned short iInDataIndex = 0;
+ unsigned char cCurByte = 0;
+ unsigned char cBitState = 0;
+
+ for (iIndex = 0; iIndex < a_usiDataSize - 1; iIndex++) {
+ if (iIndex % 8 == 0) {
+ cCurByte = g_pucInData[iInDataIndex++];
+ }
+ cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80)
+ ? 0x01 : 0x00);
+ writePort(g_ucPinTDI, cBitState);
+ sclock();
+ }
+
+ if (iIndex % 8 == 0) {
+ /* Take care of the last bit */
+ cCurByte = g_pucInData[iInDataIndex];
+ }
+
+ cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
+ ? 0x01 : 0x00);
+
+ writePort(g_ucPinTDI, cBitState);
+ if (g_usFlowControl & CASCADE) {
+ /*1/15/04 Clock in last bit for the first n-1 cascaded frames */
+ sclock();
+ }
+
+ return 0;
+}
+
+/*
+ *
+ * ispVMRead
+ *
+ * Read the data stream from devices and verify.
+ *
+ */
+
+signed char ispVMRead(unsigned short a_usiDataSize)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short usDataSizeIndex = 0;
+ unsigned short usErrorCount = 0;
+ unsigned short usLastBitIndex = 0;
+ unsigned char cDataByte = 0;
+ unsigned char cMaskByte = 0;
+ unsigned char cInDataByte = 0;
+ unsigned char cCurBit = 0;
+ unsigned char cByteIndex = 0;
+ unsigned short usBufferIndex = 0;
+ unsigned char ucDisplayByte = 0x00;
+ unsigned char ucDisplayFlag = 0x01;
+ char StrChecksum[256] = {0};
+ unsigned char g_usCalculateChecksum = 0x00;
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ usLastBitIndex = (unsigned short)(a_usiDataSize - 1);
+
+#ifndef DEBUG
+ /*
+ * If mask is not all zeros, then set the display flag to 0x00,
+ * otherwise it shall be set to 0x01 to indicate that data read
+ * from the device shall be displayed. If DEBUG is defined,
+ * always display data.
+ */
+
+ for (usDataSizeIndex = 0; usDataSizeIndex < (a_usiDataSize + 7) / 8;
+ usDataSizeIndex++) {
+ if (g_usDataType & MASK_DATA) {
+ if (g_pucOutMaskData[usDataSizeIndex] != 0x00) {
+ ucDisplayFlag = 0x00;
+ break;
+ }
+ } else if (g_usDataType & CMASK_DATA) {
+ g_usCalculateChecksum = 0x01;
+ ucDisplayFlag = 0x00;
+ break;
+ } else {
+ ucDisplayFlag = 0x00;
+ break;
+ }
+ }
+#endif /* DEBUG */
+
+ /*
+ *
+ * Begin shifting data in and out of the device.
+ *
+ **/
+
+ for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize;
+ usDataSizeIndex++) {
+ if (cByteIndex == 0) {
+
+ /*
+ * Grab byte from TDO buffer.
+ */
+
+ if (g_usDataType & TDO_DATA) {
+ cDataByte = g_pucOutData[usBufferIndex];
+ }
+
+ /*
+ * Grab byte from MASK buffer.
+ */
+
+ if (g_usDataType & MASK_DATA) {
+ cMaskByte = g_pucOutMaskData[usBufferIndex];
+ } else {
+ cMaskByte = 0xFF;
+ }
+
+ /*
+ * Grab byte from CMASK buffer.
+ */
+
+ if (g_usDataType & CMASK_DATA) {
+ cMaskByte = 0x00;
+ g_usCalculateChecksum = 0x01;
+ }
+
+ /*
+ * Grab byte from TDI buffer.
+ */
+
+ if (g_usDataType & TDI_DATA) {
+ cInDataByte = g_pucInData[usBufferIndex];
+ }
+
+ usBufferIndex++;
+ }
+
+ cCurBit = readPort();
+
+ if (ucDisplayFlag) {
+ ucDisplayByte <<= 1;
+ ucDisplayByte |= cCurBit;
+ }
+
+ /*
+ * Check if data read from port matches with expected TDO.
+ */
+
+ if (g_usDataType & TDO_DATA) {
+ /* 08/28/08 NN Added Calculate checksum support. */
+ if (g_usCalculateChecksum) {
+ if (cCurBit == 0x01)
+ g_usChecksum +=
+ (1 << (g_uiChecksumIndex % 8));
+ g_uiChecksumIndex++;
+ } else {
+ if ((((cMaskByte << cByteIndex) & 0x80)
+ ? 0x01 : 0x00)) {
+ if (cCurBit != (unsigned char)
+ (((cDataByte << cByteIndex) & 0x80)
+ ? 0x01 : 0x00)) {
+ usErrorCount++;
+ }
+ }
+ }
+ }
+
+ /*
+ * Write TDI data to the port.
+ */
+
+ writePort(g_ucPinTDI,
+ (unsigned char)(((cInDataByte << cByteIndex) & 0x80)
+ ? 0x01 : 0x00));
+
+ if (usDataSizeIndex < usLastBitIndex) {
+
+ /*
+ * Clock data out from the data shift register.
+ */
+
+ sclock();
+ } else if (g_usFlowControl & CASCADE) {
+
+ /*
+ * Clock in last bit for the first N - 1 cascaded frames
+ */
+
+ sclock();
+ }
+
+ /*
+ * Increment the byte index. If it exceeds 7, then reset it back
+ * to zero.
+ */
+
+ cByteIndex++;
+ if (cByteIndex >= 8) {
+ if (ucDisplayFlag) {
+
+ /*
+ * Store displayed data in the TDO buffer. By reusing
+ * the TDO buffer to store displayed data, there is no
+ * need to allocate a buffer simply to hold display
+ * data. This will not cause any false verification
+ * errors because the true TDO byte has already
+ * been consumed.
+ */
+
+ g_pucOutData[usBufferIndex - 1] = ucDisplayByte;
+ ucDisplayByte = 0;
+ }
+
+ cByteIndex = 0;
+ }
+ /* 09/12/07 Nguyen changed to display the 1 bit expected data */
+ else if (a_usiDataSize == 1) {
+ if (ucDisplayFlag) {
+
+ /*
+ * Store displayed data in the TDO buffer.
+ * By reusing the TDO buffer to store displayed
+ * data, there is no need to allocate
+ * a buffer simply to hold display data. This
+ * will not cause any false verification errors
+ * because the true TDO byte has already
+ * been consumed.
+ */
+
+ /*
+ * Flip ucDisplayByte and store it in cDataByte.
+ */
+ cDataByte = 0x00;
+ for (usBufferIndex = 0; usBufferIndex < 8;
+ usBufferIndex++) {
+ cDataByte <<= 1;
+ if (ucDisplayByte & 0x01) {
+ cDataByte |= 0x01;
+ }
+ ucDisplayByte >>= 1;
+ }
+ g_pucOutData[0] = cDataByte;
+ ucDisplayByte = 0;
+ }
+
+ cByteIndex = 0;
+ }
+ }
+
+ if (ucDisplayFlag) {
+
+#ifdef DEBUG
+ debug("RECEIVED TDO (");
+#else
+ vme_out_string("Display Data: 0x");
+#endif /* DEBUG */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ for (usDataSizeIndex = (unsigned short)
+ ((a_usiDataSize + 7) / 8);
+ usDataSizeIndex > 0 ; usDataSizeIndex--) {
+ cMaskByte = g_pucOutData[usDataSizeIndex - 1];
+ cDataByte = 0x00;
+
+ /*
+ * Flip cMaskByte and store it in cDataByte.
+ */
+
+ for (usBufferIndex = 0; usBufferIndex < 8;
+ usBufferIndex++) {
+ cDataByte <<= 1;
+ if (cMaskByte & 0x01) {
+ cDataByte |= 0x01;
+ }
+ cMaskByte >>= 1;
+ }
+#ifdef DEBUG
+ printf("%.2X", cDataByte);
+ if ((((a_usiDataSize + 7) / 8) - usDataSizeIndex)
+ % 40 == 39) {
+ printf("\n\t\t");
+ }
+#else
+ vme_out_hex(cDataByte);
+#endif /* DEBUG */
+ }
+
+#ifdef DEBUG
+ printf(")\n\n");
+#else
+ vme_out_string("\n\n");
+#endif /* DEBUG */
+ /* 09/02/08 Nguyen changed to display the data Checksum */
+ if (g_usChecksum != 0) {
+ g_usChecksum &= 0xFFFF;
+ sprintf(StrChecksum, "Data Checksum: %.4lX\n\n",
+ g_usChecksum);
+ vme_out_string(StrChecksum);
+ g_usChecksum = 0;
+ }
+ }
+
+ if (usErrorCount > 0) {
+ if (g_usFlowControl & VERIFYUES) {
+ vme_out_string(
+ "USERCODE verification failed. "
+ "Continue programming......\n\n");
+ g_usFlowControl &= ~(VERIFYUES);
+ return 0;
+ } else {
+
+#ifdef DEBUG
+ printf("TOTAL ERRORS: %d\n", usErrorCount);
+#endif /* DEBUG */
+
+ return VME_VERIFICATION_FAILURE;
+ }
+ } else {
+ if (g_usFlowControl & VERIFYUES) {
+ vme_out_string("USERCODE verification passed. "
+ "Programming aborted.\n\n");
+ g_usFlowControl &= ~(VERIFYUES);
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+}
+
+/*
+ *
+ * ispVMReadandSave
+ *
+ * Support dynamic I/O.
+ *
+ */
+
+signed char ispVMReadandSave(unsigned short int a_usiDataSize)
+{
+ /* 09/11/07 NN added local variables initialization */
+ unsigned short int usDataSizeIndex = 0;
+ unsigned short int usLastBitIndex = 0;
+ unsigned short int usBufferIndex = 0;
+ unsigned short int usOutBitIndex = 0;
+ unsigned short int usLVDSIndex = 0;
+ unsigned char cDataByte = 0;
+ unsigned char cDMASKByte = 0;
+ unsigned char cInDataByte = 0;
+ unsigned char cCurBit = 0;
+ unsigned char cByteIndex = 0;
+ signed char cLVDSByteIndex = 0;
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ usLastBitIndex = (unsigned short) (a_usiDataSize - 1);
+
+ /*
+ *
+ * Iterate through the data bits.
+ *
+ */
+
+ for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize;
+ usDataSizeIndex++) {
+ if (cByteIndex == 0) {
+
+ /*
+ * Grab byte from DMASK buffer.
+ */
+
+ if (g_usDataType & DMASK_DATA) {
+ cDMASKByte = g_pucOutDMaskData[usBufferIndex];
+ } else {
+ cDMASKByte = 0x00;
+ }
+
+ /*
+ * Grab byte from TDI buffer.
+ */
+
+ if (g_usDataType & TDI_DATA) {
+ cInDataByte = g_pucInData[usBufferIndex];
+ }
+
+ usBufferIndex++;
+ }
+
+ cCurBit = readPort();
+ cDataByte = (unsigned char)(((cInDataByte << cByteIndex) & 0x80)
+ ? 0x01 : 0x00);
+
+ /*
+ * Initialize the byte to be zero.
+ */
+
+ if (usOutBitIndex % 8 == 0) {
+ g_pucOutData[usOutBitIndex / 8] = 0x00;
+ }
+
+ /*
+ * Use TDI, DMASK, and device TDO to create new TDI (actually
+ * stored in g_pucOutData).
+ */
+
+ if ((((cDMASKByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) {
+
+ if (g_pLVDSList) {
+ for (usLVDSIndex = 0;
+ usLVDSIndex < g_usLVDSPairCount;
+ usLVDSIndex++) {
+ if (g_pLVDSList[usLVDSIndex].
+ usNegativeIndex ==
+ usDataSizeIndex) {
+ g_pLVDSList[usLVDSIndex].
+ ucUpdate = 0x01;
+ break;
+ }
+ }
+ }
+
+ /*
+ * DMASK bit is 1, use TDI.
+ */
+
+ g_pucOutData[usOutBitIndex / 8] |= (unsigned char)
+ (((cDataByte & 0x1) ? 0x01 : 0x00) <<
+ (7 - usOutBitIndex % 8));
+ } else {
+
+ /*
+ * DMASK bit is 0, use device TDO.
+ */
+
+ g_pucOutData[usOutBitIndex / 8] |= (unsigned char)
+ (((cCurBit & 0x1) ? 0x01 : 0x00) <<
+ (7 - usOutBitIndex % 8));
+ }
+
+ /*
+ * Shift in TDI in order to get TDO out.
+ */
+
+ usOutBitIndex++;
+ writePort(g_ucPinTDI, cDataByte);
+ if (usDataSizeIndex < usLastBitIndex) {
+ sclock();
+ }
+
+ /*
+ * Increment the byte index. If it exceeds 7, then reset it back
+ * to zero.
+ */
+
+ cByteIndex++;
+ if (cByteIndex >= 8) {
+ cByteIndex = 0;
+ }
+ }
+
+ /*
+ * If g_pLVDSList exists and pairs need updating, then update
+ * the negative-pair to receive the flipped positive-pair value.
+ */
+
+ if (g_pLVDSList) {
+ for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount;
+ usLVDSIndex++) {
+ if (g_pLVDSList[usLVDSIndex].ucUpdate) {
+
+ /*
+ * Read the positive value and flip it.
+ */
+
+ cDataByte = (unsigned char)
+ (((g_pucOutData[g_pLVDSList[usLVDSIndex].
+ usPositiveIndex / 8]
+ << (g_pLVDSList[usLVDSIndex].
+ usPositiveIndex % 8)) & 0x80) ?
+ 0x01 : 0x00);
+ /* 09/11/07 NN Type cast mismatch variables */
+ cDataByte = (unsigned char) (!cDataByte);
+
+ /*
+ * Get the byte that needs modification.
+ */
+
+ cInDataByte =
+ g_pucOutData[g_pLVDSList[usLVDSIndex].
+ usNegativeIndex / 8];
+
+ if (cDataByte) {
+
+ /*
+ * Copy over the current byte and
+ * set the negative bit to 1.
+ */
+
+ cDataByte = 0x00;
+ for (cLVDSByteIndex = 7;
+ cLVDSByteIndex >= 0;
+ cLVDSByteIndex--) {
+ cDataByte <<= 1;
+ if (7 -
+ (g_pLVDSList[usLVDSIndex].
+ usNegativeIndex % 8) ==
+ cLVDSByteIndex) {
+
+ /*
+ * Set negative bit to 1
+ */
+
+ cDataByte |= 0x01;
+ } else if (cInDataByte & 0x80) {
+ cDataByte |= 0x01;
+ }
+
+ cInDataByte <<= 1;
+ }
+
+ /*
+ * Store the modified byte.
+ */
+
+ g_pucOutData[g_pLVDSList[usLVDSIndex].
+ usNegativeIndex / 8] = cDataByte;
+ } else {
+
+ /*
+ * Copy over the current byte and set
+ * the negative bit to 0.
+ */
+
+ cDataByte = 0x00;
+ for (cLVDSByteIndex = 7;
+ cLVDSByteIndex >= 0;
+ cLVDSByteIndex--) {
+ cDataByte <<= 1;
+ if (7 -
+ (g_pLVDSList[usLVDSIndex].
+ usNegativeIndex % 8) ==
+ cLVDSByteIndex) {
+
+ /*
+ * Set negative bit to 0
+ */
+
+ cDataByte |= 0x00;
+ } else if (cInDataByte & 0x80) {
+ cDataByte |= 0x01;
+ }
+
+ cInDataByte <<= 1;
+ }
+
+ /*
+ * Store the modified byte.
+ */
+
+ g_pucOutData[g_pLVDSList[usLVDSIndex].
+ usNegativeIndex / 8] = cDataByte;
+ }
+
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+signed char ispVMProcessLVDS(unsigned short a_usLVDSCount)
+{
+ unsigned short usLVDSIndex = 0;
+
+ /*
+ * Allocate memory to hold LVDS pairs.
+ */
+
+ ispVMMemManager(LVDS, a_usLVDSCount);
+ g_usLVDSPairCount = a_usLVDSCount;
+
+#ifdef DEBUG
+ printf("LVDS %d (", a_usLVDSCount);
+#endif /* DEBUG */
+
+ /*
+ * Iterate through each given LVDS pair.
+ */
+
+ for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) {
+
+ /*
+ * Assign the positive and negative indices of the LVDS pair.
+ */
+
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_pLVDSList[usLVDSIndex].usPositiveIndex =
+ (unsigned short) ispVMDataSize();
+ /* 09/11/07 NN Type cast mismatch variables */
+ g_pLVDSList[usLVDSIndex].usNegativeIndex =
+ (unsigned short)ispVMDataSize();
+
+#ifdef DEBUG
+ if (usLVDSIndex < g_usLVDSPairCount - 1) {
+ printf("%d:%d, ",
+ g_pLVDSList[usLVDSIndex].usPositiveIndex,
+ g_pLVDSList[usLVDSIndex].usNegativeIndex);
+ } else {
+ printf("%d:%d",
+ g_pLVDSList[usLVDSIndex].usPositiveIndex,
+ g_pLVDSList[usLVDSIndex].usNegativeIndex);
+ }
+#endif /* DEBUG */
+
+ }
+
+#ifdef DEBUG
+ printf(");\n", a_usLVDSCount);
+#endif /* DEBUG */
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * ispVM functions adapted from Lattice's ispmVMEmbedded code:
+ * Copyright 2009 Lattice Semiconductor Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <fpga.h>
+#include <lattice.h>
+
+static lattice_board_specific_func *pfns;
+static char *fpga_image;
+static unsigned long read_bytes;
+static unsigned long bufsize;
+static unsigned short expectedCRC;
+
+/*
+ * External variables and functions declared in ivm_core.c module.
+ */
+extern unsigned short g_usCalculatedCRC;
+extern unsigned short g_usDataType;
+extern unsigned char *g_pucIntelBuffer;
+extern unsigned char *g_pucHeapMemory;
+extern unsigned short g_iHeapCounter;
+extern unsigned short g_iHEAPSize;
+extern unsigned short g_usIntelDataIndex;
+extern unsigned short g_usIntelBufferSize;
+extern char *const g_szSupportedVersions[];
+
+
+/*
+ * ispVMDelay
+ *
+ * Users must implement a delay to observe a_usTimeDelay, where
+ * bit 15 of the a_usTimeDelay defines the unit.
+ * 1 = milliseconds
+ * 0 = microseconds
+ * Example:
+ * a_usTimeDelay = 0x0001 = 1 microsecond delay.
+ * a_usTimeDelay = 0x8001 = 1 millisecond delay.
+ *
+ * This subroutine is called upon to provide a delay from 1 millisecond to a few
+ * hundreds milliseconds each time.
+ * It is understood that due to a_usTimeDelay is defined as unsigned short, a 16
+ * bits integer, this function is restricted to produce a delay to 64000
+ * micro-seconds or 32000 milli-second maximum. The VME file will never pass on
+ * to this function a delay time > those maximum number. If it needs more than
+ * those maximum, the VME file will launch the delay function several times to
+ * realize a larger delay time cummulatively.
+ * It is perfectly alright to provide a longer delay than required. It is not
+ * acceptable if the delay is shorter.
+ */
+void ispVMDelay(unsigned short delay)
+{
+ if (delay & 0x8000)
+ delay = (delay & ~0x8000) * 1000;
+ udelay(delay);
+}
+
+void writePort(unsigned char a_ucPins, unsigned char a_ucValue)
+{
+ a_ucValue = a_ucValue ? 1 : 0;
+
+ switch (a_ucPins) {
+ case g_ucPinTDI:
+ pfns->jtag_set_tdi(a_ucValue);
+ break;
+ case g_ucPinTCK:
+ pfns->jtag_set_tck(a_ucValue);
+ break;
+ case g_ucPinTMS:
+ pfns->jtag_set_tms(a_ucValue);
+ break;
+ default:
+ printf("%s: requested unknown pin\n", __func__);
+ }
+}
+
+unsigned char readPort(void)
+{
+ return pfns->jtag_get_tdo();
+}
+
+void sclock(void)
+{
+ writePort(g_ucPinTCK, 0x01);
+ writePort(g_ucPinTCK, 0x00);
+}
+
+void calibration(void)
+{
+ /* Apply 2 pulses to TCK. */
+ writePort(g_ucPinTCK, 0x00);
+ writePort(g_ucPinTCK, 0x01);
+ writePort(g_ucPinTCK, 0x00);
+ writePort(g_ucPinTCK, 0x01);
+ writePort(g_ucPinTCK, 0x00);
+
+ ispVMDelay(0x8001);
+
+ /* Apply 2 pulses to TCK. */
+ writePort(g_ucPinTCK, 0x01);
+ writePort(g_ucPinTCK, 0x00);
+ writePort(g_ucPinTCK, 0x01);
+ writePort(g_ucPinTCK, 0x00);
+}
+
+/*
+ * GetByte
+ *
+ * Returns a byte to the caller. The returned byte depends on the
+ * g_usDataType register. If the HEAP_IN bit is set, then the byte
+ * is returned from the HEAP. If the LHEAP_IN bit is set, then
+ * the byte is returned from the intelligent buffer. Otherwise,
+ * the byte is returned directly from the VME file.
+ */
+unsigned char GetByte(void)
+{
+ unsigned char ucData;
+ unsigned int block_size = 4 * 1024;
+
+ if (g_usDataType & HEAP_IN) {
+
+ /*
+ * Get data from repeat buffer.
+ */
+
+ if (g_iHeapCounter > g_iHEAPSize) {
+
+ /*
+ * Data over-run.
+ */
+
+ return 0xFF;
+ }
+
+ ucData = g_pucHeapMemory[g_iHeapCounter++];
+ } else if (g_usDataType & LHEAP_IN) {
+
+ /*
+ * Get data from intel buffer.
+ */
+
+ if (g_usIntelDataIndex >= g_usIntelBufferSize) {
+ return 0xFF;
+ }
+
+ ucData = g_pucIntelBuffer[g_usIntelDataIndex++];
+ } else {
+ if (read_bytes == bufsize) {
+ return 0xFF;
+ }
+ ucData = *fpga_image++;
+ read_bytes++;
+
+ if (!(read_bytes % block_size)) {
+ printf("Downloading FPGA %ld/%ld completed\r",
+ read_bytes,
+ bufsize);
+ }
+
+ if (expectedCRC != 0) {
+ ispVMCalculateCRC32(ucData);
+ }
+ }
+
+ return ucData;
+}
+
+signed char ispVM(void)
+{
+ char szFileVersion[9] = { 0 };
+ signed char cRetCode = 0;
+ signed char cIndex = 0;
+ signed char cVersionIndex = 0;
+ unsigned char ucReadByte = 0;
+ unsigned short crc;
+
+ g_pucHeapMemory = NULL;
+ g_iHeapCounter = 0;
+ g_iHEAPSize = 0;
+ g_usIntelDataIndex = 0;
+ g_usIntelBufferSize = 0;
+ g_usCalculatedCRC = 0;
+ expectedCRC = 0;
+ ucReadByte = GetByte();
+ switch (ucReadByte) {
+ case FILE_CRC:
+ crc = (unsigned char)GetByte();
+ crc <<= 8;
+ crc |= GetByte();
+ expectedCRC = crc;
+
+ for (cIndex = 0; cIndex < 8; cIndex++)
+ szFileVersion[cIndex] = GetByte();
+
+ break;
+ default:
+ szFileVersion[0] = (signed char) ucReadByte;
+ for (cIndex = 1; cIndex < 8; cIndex++)
+ szFileVersion[cIndex] = GetByte();
+
+ break;
+ }
+
+ /*
+ *
+ * Compare the VME file version against the supported version.
+ *
+ */
+
+ for (cVersionIndex = 0; g_szSupportedVersions[cVersionIndex] != 0;
+ cVersionIndex++) {
+ for (cIndex = 0; cIndex < 8; cIndex++) {
+ if (szFileVersion[cIndex] !=
+ g_szSupportedVersions[cVersionIndex][cIndex]) {
+ cRetCode = VME_VERSION_FAILURE;
+ break;
+ }
+ cRetCode = 0;
+ }
+
+ if (cRetCode == 0) {
+ break;
+ }
+ }
+
+ if (cRetCode < 0) {
+ return VME_VERSION_FAILURE;
+ }
+
+ printf("VME file checked: starting downloading to FPGA\n");
+
+ ispVMStart();
+
+ cRetCode = ispVMCode();
+
+ ispVMEnd();
+ ispVMFreeMem();
+ puts("\n");
+
+ if (cRetCode == 0 && expectedCRC != 0 &&
+ (expectedCRC != g_usCalculatedCRC)) {
+ printf("Expected CRC: 0x%.4X\n", expectedCRC);
+ printf("Calculated CRC: 0x%.4X\n", g_usCalculatedCRC);
+ return VME_CRC_FAILURE;
+ }
+ return cRetCode;
+}
+
+static int lattice_validate(Lattice_desc *desc, const char *fn)
+{
+ int ret_val = FALSE;
+
+ if (desc) {
+ if ((desc->family > min_lattice_type) &&
+ (desc->family < max_lattice_type)) {
+ if ((desc->iface > min_lattice_iface_type) &&
+ (desc->iface < max_lattice_iface_type)) {
+ if (desc->size) {
+ ret_val = TRUE;
+ } else {
+ printf("%s: NULL part size\n", fn);
+ }
+ } else {
+ printf("%s: Invalid Interface type, %d\n",
+ fn, desc->iface);
+ }
+ } else {
+ printf("%s: Invalid family type, %d\n",
+ fn, desc->family);
+ }
+ } else {
+ printf("%s: NULL descriptor!\n", fn);
+ }
+
+ return ret_val;
+}
+
+int lattice_load(Lattice_desc *desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+
+ if (!lattice_validate(desc, (char *)__func__)) {
+ printf("%s: Invalid device descriptor\n", __func__);
+ } else {
+ pfns = desc->iface_fns;
+
+ switch (desc->family) {
+ case Lattice_XP2:
+ fpga_image = buf;
+ read_bytes = 0;
+ bufsize = bsize;
+ debug("%s: Launching the Lattice ISPVME Loader:"
+ " addr 0x%x size 0x%x...\n",
+ __func__, fpga_image, bufsize);
+ ret_val = ispVM();
+ if (ret_val)
+ printf("%s: error %d downloading FPGA image\n",
+ __func__, ret_val);
+ else
+ puts("FPGA downloaded successfully\n");
+ break;
+ default:
+ printf("%s: Unsupported family type, %d\n",
+ __func__, desc->family);
+ }
+ }
+
+ return ret_val;
+}
+
+int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize)
+{
+ puts("Dump not supported for Lattice FPGA\n");
+
+ return FPGA_FAIL;
+
+}
+
+int lattice_info(Lattice_desc *desc)
+{
+ int ret_val = FPGA_FAIL;
+
+ if (lattice_validate(desc, (char *)__func__)) {
+ printf("Family: \t");
+ switch (desc->family) {
+ case Lattice_XP2:
+ puts("XP2\n");
+ break;
+ /* Add new family types here */
+ default:
+ printf("Unknown family type, %d\n", desc->family);
+ }
+
+ puts("Interface type:\t");
+ switch (desc->iface) {
+ case lattice_jtag_mode:
+ puts("JTAG Mode\n");
+ break;
+ /* Add new interface types here */
+ default:
+ printf("Unsupported interface type, %d\n", desc->iface);
+ }
+
+ printf("Device Size: \t%d bytes\n",
+ desc->size);
+
+ if (desc->iface_fns) {
+ printf("Device Function Table @ 0x%p\n",
+ desc->iface_fns);
+ switch (desc->family) {
+ case Lattice_XP2:
+ break;
+ /* Add new family types here */
+ default:
+ break;
+ }
+ } else {
+ puts("No Device Function Table.\n");
+ }
+
+ if (desc->desc)
+ printf("Model: \t%s\n", desc->desc);
+
+ ret_val = FPGA_SUCCESS;
+ } else {
+ printf("%s: Invalid device descriptor\n", __func__);
+ }
+
+ return ret_val;
+}
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return FPGA_FAIL;
}
} while ((*fn->init) (cookie));
while DONE is low (inactive) */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
+ if (*fn->abort)
+ (*fn->abort) (cookie);
return (FPGA_FAIL);
}
val = data [bytecount ++];
include $(TOPDIR)/config.mk
-LIB := $(obj)libgpio.a
+LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
-COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o
+COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
+COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#ifdef CONFIG_ARMADA100
+#include <asm/arch/armada100.h>
+#else
+#error Unsupported SoC...
+#endif
+
+/*
+ * mfp_config
+ *
+ * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
+ * configuration registers to configure each GPIO/Function pin on the
+ * SoC.
+ *
+ * This function reads the array of values for
+ * MFPR_X registers and programms them into respective
+ * Multi-Function Pin registers.
+ * It supports - Alternate Function Selection programming.
+ *
+ * Whereas,
+ * The Configureation value is constructed using MFP()
+ * array consists of 32bit values as defined in MFP(xx,xx..) macro
+ */
+void mfp_config(u32 *mfp_cfgs)
+{
+ u32 *p_mfpr = NULL;
+ u32 cfg_val, val;
+
+ do {
+ cfg_val = *mfp_cfgs++;
+ /* exit if End of configuration table detected */
+ if (cfg_val == MFP_EOC)
+ break;
+
+ p_mfpr = (u32 *)(MV_MFPR_BASE
+ + MFP_REG_GET_OFFSET(cfg_val));
+
+ /* Write a mfg register as per configuration */
+ val = 0;
+ if (cfg_val & MFP_AF_FLAG)
+ /* Abstract and program Afternate-Func Selection */
+ val |= cfg_val & MFP_AF_MASK;
+ if (cfg_val & MFP_EDGE_FLAG)
+ /* Abstract and program Edge configuration */
+ val |= cfg_val & MFP_LPM_EDGE_MASK;
+ if (cfg_val & MFP_DRIVE_FLAG)
+ /* Abstract and program Drive configuration */
+ val |= cfg_val & MFP_DRIVE_MASK;
+ if (cfg_val & MFP_PULL_FLAG)
+ /* Abstract and program Pullup/down configuration */
+ val |= cfg_val & MFP_PULL_MASK;
+
+ writel(val, p_mfpr);
+ } while (1);
+ /*
+ * perform a read-back of any MFPR register to make sure the
+ * previous writings are finished
+ */
+ readl(p_mfpr);
+}
* MA 02111-1307 USA
*/
#include <common.h>
-#include <asm/arch/mx31.h>
+#ifdef CONFIG_MX31
#include <asm/arch/mx31-regs.h>
+#endif
+#ifdef CONFIG_MX51
+#include <asm/arch/imx-regs.h>
+#endif
+#include <asm/io.h>
+#include <mxc_gpio.h>
/* GPIO port description */
static unsigned long gpio_ports[] = {
- [0] = GPIO1_BASE,
- [1] = GPIO2_BASE,
- [2] = GPIO3_BASE,
+ [0] = GPIO1_BASE_ADDR,
+ [1] = GPIO2_BASE_ADDR,
+ [2] = GPIO3_BASE_ADDR,
+#ifdef CONFIG_MX51
+ [3] = GPIO4_BASE_ADDR,
+#endif
};
-int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
gpio &= 0x1f;
- l = __REG(gpio_ports[port] + GPIO_GDIR);
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = readl(®s->gpio_dir);
+
switch (direction) {
- case MX31_GPIO_DIRECTION_OUT:
+ case MXC_GPIO_DIRECTION_OUT:
l |= 1 << gpio;
break;
- case MX31_GPIO_DIRECTION_IN:
+ case MXC_GPIO_DIRECTION_IN:
l &= ~(1 << gpio);
}
- __REG(gpio_ports[port] + GPIO_GDIR) = l;
+ writel(l, ®s->gpio_dir);
return 0;
}
-void mx31_gpio_set(unsigned int gpio, unsigned int value)
+void mxc_gpio_set(unsigned int gpio, unsigned int value)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
gpio &= 0x1f;
- l = __REG(gpio_ports[port] + GPIO_DR);
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = readl(®s->gpio_dr);
if (value)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- __REG(gpio_ports[port] + GPIO_DR) = l;
+ writel(l, ®s->gpio_dr);
}
-int mx31_gpio_get(unsigned int gpio)
+int mxc_gpio_get(unsigned int gpio)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
gpio &= 0x1f;
- l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01;
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = (readl(®s->gpio_dr) >> gpio) & 0x01;
return l;
}
#CFLAGS += -DDEBUG
-LIB = $(obj)libhwmon.a
+LIB = $(obj)libhwmon.o
COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
*/
/*
- * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat.
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
*/
#include <common.h>
/*
* Device code
*/
-#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
+#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
+/*
+ * Config register bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_POLARITY 0x02
+#define DTT_CONFIG_R0 0x04 /* ds1631 only */
+#define DTT_CONFIG_R1 0x08 /* ds1631 only */
+#define DTT_CONFIG_NVB 0x10
+#define DTT_CONFIG_TLF 0x20
+#define DTT_CONFIG_THF 0x40
+#define DTT_CONFIG_DONE 0x80
+
+
int dtt_read(int sensor, int reg)
{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and command.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
-
- /*
- * Prepare to handle 2 byte result.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW))
- dlen = 2;
- else
- dlen = 1;
-
- /*
- * Now try to read the register.
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- /*
- * Handle 2 byte result.
- */
- if (dlen == 2)
- return ((int)((short)data[1] + (((short)data[0]) << 8)));
-
- return (int)data[0];
-} /* dtt_read() */
+ int dlen;
+ uchar data[2];
+
+ /* Calculate sensor address and command */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
+
+ /* Prepare to handle 2 byte result */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ break;
+ default:
+ dlen = 1;
+ }
+
+ /* Now try to read the register */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /* Handle 2 byte result */
+ if (dlen == 2)
+ return (short)((data[0] << 8) | data[1]);
+
+ return (int)data[0];
+}
int dtt_write(int sensor, int reg, int val)
{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and register.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /*
- * Handle various data sizes.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) {
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- }
- else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) {
- dlen = 0;
- data[0] = (char)0;
- data[1] = (char)0;
- }
- else {
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
-
- /*
- * Write value to device.
- */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
+ int dlen;
+ uchar data[2];
+
+ /* Calculate sensor address and register */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
+
+ /* Handle various data sizes. */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ break;
+ case DTT_WRITE_START_CONV:
+ case DTT_WRITE_STOP_CONV:
+ dlen = 0;
+ data[0] = (char)0;
+ data[1] = (char)0;
+ break;
+ default:
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ }
+
+ /* Write value to device */
+ if (i2c_write(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /* Poll NV memory busy bit in case write was to register stored in EEPROM */
+ while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB)
+ ;
+
+ return 0;
+}
static int _dtt_init(int sensor)
{
- int val;
-
- /*
- * Setup High Temp.
- */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup Low Temp - hysteresis.
- */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup configuraton register
- *
- * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
- *
- * We run in polled mode, since there isn't any way to know if this
- * lousy device is ready to provide temperature readings on power up.
- */
- val = 0x9;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- return 0;
-} /* _dtt_init() */
+ int val;
+
+ /* Setup High Temp */
+ val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
+ return 1;
+
+ /* Setup Low Temp - hysteresis */
+ val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
+ return 1;
+
+ /*
+ * Setup configuraton register
+ *
+ * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
+ *
+ * We run in polled mode, since there isn't any way to know if this
+ * lousy device is ready to provide temperature readings on power up.
+ */
+ val = 0x9;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+
+ return 0;
+}
int dtt_init (void)
{
- int i;
- unsigned char sensors[] = CONFIG_DTT_SENSORS;
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
- for (i = 0; i < sizeof(sensors); i++) {
- if (_dtt_init(sensors[i]) != 0)
- printf("DTT%d: FAILED\n", i+1);
- else
- printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
- }
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i + 1);
+ else
+ printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
+ }
- return (0);
-} /* dtt_init() */
+ return (0);
+}
int dtt_get_temp(int sensor)
{
- int i;
-
- /*
- * Start a conversion, may take up to 1 second.
- */
- dtt_write(sensor, DTT_WRITE_START_CONV, 0);
- for (i = 0; i <= 10; i++) {
- udelay(100000);
- if (dtt_read(sensor, DTT_CONFIG) & 0x80)
- break;
- }
-
- return (dtt_read(sensor, DTT_READ_TEMP) / 256);
-} /* dtt_get_temp() */
+ int i;
+
+ /* Start a conversion, may take up to 1 second. */
+ dtt_write(sensor, DTT_WRITE_START_CONV, 0);
+ for (i = 0; i <= 10; i++) {
+ udelay(100000);
+ if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE)
+ break;
+ }
+
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+}
include $(TOPDIR)/config.mk
-LIB := $(obj)libi2c.a
+LIB := $(obj)libi2c.o
COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include "omap24xx_i2c.h"
-#define I2C_TIMEOUT 10
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_TIMEOUT 1000
static void wait_for_bb (void);
static u16 wait_for_pin (void);
void i2c_init (int speed, int slaveadd)
{
- DECLARE_GLOBAL_DATA_PTR;
int psc, fsscll, fssclh;
int hsscll = 0, hssclh = 0;
u32 scll, sclh;
/* no stop bit needed here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* Important: have to use byte access */
- writeb (regoffset, &i2c_base->data);
- udelay (20000);
- if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
+ /* send register offset */
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
+ goto read_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ /* Important: have to use byte access */
+ writeb(regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
}
- } else {
- i2c_error = 1;
}
- if (!i2c_error) {
- writew (I2C_CON_EN, &i2c_base->con);
- while (readw(&i2c_base->stat) &
- (I2C_STAT_XRDY | I2C_STAT_ARDY)) {
- udelay (10000);
- /* Have to clear pending interrupt to clear I2C_STAT */
- writew (0xFFFF, &i2c_base->stat);
+ /* set slave address */
+ writew(devaddr, &i2c_base->sa);
+ /* read one byte from slave */
+ writew(1, &i2c_base->cnt);
+ /* need stop bit here */
+ writew(I2C_CON_EN | I2C_CON_MST |
+ I2C_CON_STT | I2C_CON_STP,
+ &i2c_base->con);
+
+ /* receive data */
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ goto read_exit;
}
-
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* read one byte from slave */
- writew (1, &i2c_base->cnt);
- /* need stop bit here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- &i2c_base->con);
-
- status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
defined(CONFIG_OMAP44XX)
- *value = readb (&i2c_base->data);
+ *value = readb(&i2c_base->data);
#else
- *value = readw (&i2c_base->data);
+ *value = readw(&i2c_base->data);
#endif
- udelay (20000);
- } else {
- i2c_error = 1;
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
}
-
- if (!i2c_error) {
- writew (I2C_CON_EN, &i2c_base->con);
- while (readw (&i2c_base->stat) &
- (I2C_STAT_RRDY | I2C_STAT_ARDY)) {
- udelay (10000);
- writew (0xFFFF, &i2c_base->stat);
- }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
}
}
+
+read_exit:
flush_fifo();
writew (0xFFFF, &i2c_base->stat);
writew (0, &i2c_base->cnt);
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
{
int i2c_error = 0;
- u16 status, stat;
+ u16 status;
/* wait until bus not busy */
wait_for_bb ();
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
- /* wait until state change */
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send out 1 byte */
- writeb (regoffset, &i2c_base->data);
- writew (I2C_STAT_XRDY, &i2c_base->stat);
-
- status = wait_for_pin ();
- if ((status & I2C_STAT_XRDY)) {
- /* send out next 1 byte */
- writeb (value, &i2c_base->data);
- writew (I2C_STAT_XRDY, &i2c_base->stat);
- } else {
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
+ goto write_exit;
}
+ if (status & I2C_STAT_XRDY) {
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
+ /* send register offset */
+ writeb(regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ goto write_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ /* send data */
+ writeb(value, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ }
+ break;
#else
- /* send out two bytes */
- writew ((value << 8) + regoffset, &i2c_base->data);
+ /* send out two bytes */
+ writew((value << 8) + regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
#endif
- /* must have enough delay to allow BB bit to go low */
- udelay (50000);
- if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
- i2c_error = 1;
}
- } else {
- i2c_error = 1;
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
}
- if (!i2c_error) {
- int eout = 200;
+ wait_for_bb();
- writew (I2C_CON_EN, &i2c_base->con);
- while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
- udelay (1000);
- /* have to read to clear intrrupt */
- writew (0xFFFF, &i2c_base->stat);
- if(--eout == 0) /* better leave with error than hang */
- break;
- }
- }
+ status = readw(&i2c_base->stat);
+ if (status & I2C_STAT_NACK)
+ i2c_error = 1;
+
+write_exit:
flush_fifo();
writew (0xFFFF, &i2c_base->stat);
writew (0, &i2c_base->cnt);
int i2c_probe (uchar chip)
{
+ u16 status;
int res = 1; /* default = fail */
if (chip == readw (&i2c_base->oa)) {
writew (chip, &i2c_base->sa);
/* stop bit needed here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
- /* enough delay for the NACK bit set */
- udelay (50000);
- if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
- res = 0; /* success case */
- flush_fifo();
- writew(0xFFFF, &i2c_base->stat);
- } else {
- writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
- writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
- udelay(20000);
- wait_for_bb ();
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_AL) {
+ res = 1;
+ goto probe_exit;
+ }
+ if (status & I2C_STAT_NACK) {
+ res = 1;
+ writew(0xff, &i2c_base->stat);
+ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
+ wait_for_bb ();
+ break;
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ if (status & I2C_STAT_RRDY) {
+ res = 0;
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
+ readb(&i2c_base->data);
+#else
+ readw(&i2c_base->data);
+#endif
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
+ }
}
+
+probe_exit:
flush_fifo();
writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
writew(0xFFFF, &i2c_base->stat);
static void wait_for_bb (void)
{
- int timeout = 10;
+ int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
writew (stat, &i2c_base->stat);
- udelay (50000);
+ udelay(1000);
}
if (timeout <= 0) {
static u16 wait_for_pin (void)
{
u16 status;
- int timeout = 10;
+ int timeout = I2C_TIMEOUT;
do {
udelay (1000);
if (timeout <= 0) {
printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
readw (&i2c_base->stat));
- writew(0xFFFF, &i2c_base->stat);
-}
+ writew(0xFFFF, &i2c_base->stat);
+ status = 0;
+ }
+
return status;
}
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
+ return (readl(&gpio->gpedat) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
- return (readl(&gpio->PGDAT) & 0x0020) >> 5;
+ return (readl(&gpio->pgdat) & 0x0020) >> 5;
#endif
}
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
+ writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
#endif
#ifdef CONFIG_S3C2400
- writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
+ writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
#endif
}
int i;
i = I2C_TIMEOUT * 10000;
- while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
+ while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
udelay(100);
i--;
}
- return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+ return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
static int IsACK(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
+ return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
}
static void ReadWriteByte(void)
{
struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
+ writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
void i2c_init(int speed, int slaveadd)
/* wait for some time to give previous transfer a chance to finish */
i = I2C_TIMEOUT * 1000;
- while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
+ while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
- if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+ if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
#ifdef CONFIG_S3C2410
- ulong old_gpecon = readl(&gpio->GPECON);
+ ulong old_gpecon = readl(&gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
- ulong old_gpecon = readl(&gpio->PGCON);
+ ulong old_gpecon = readl(&gpio->pgcon);
#endif
/* bus still busy probably by (most) previously interrupted
transfer */
#ifdef CONFIG_S3C2410
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
- writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
- &gpio->GPECON);
+ writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
+ &gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
- writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
- &gpio->PGCON);
+ writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
+ &gpio->pgcon);
#endif
/* toggle I2CSCL until bus idle */
/* restore pin functions */
#ifdef CONFIG_S3C2410
- writel(old_gpecon, &gpio->GPECON);
+ writel(old_gpecon, &gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
- writel(old_gpecon, &gpio->PGCON);
+ writel(old_gpecon, &gpio->pgcon);
#endif
}
/* set prescaler, divisor according to freq, also set
* ACKGEN, IRQ */
- writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
+ writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */
- writel(0, &i2c->IICSTAT);
- writel(slaveadd, &i2c->IICADD);
+ writel(0, &i2c->iicstat);
+ writel(slaveadd, &i2c->iicadd);
/* program Master Transmit (and implicit STOP) */
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
/* Check I2C bus idle */
i = I2C_TIMEOUT * 1000;
- while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
+ while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
udelay(1000);
i--;
}
- if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
+ if (readl(&i2c->iicstat) & I2CSTAT_BSY)
return I2C_NOK_TOUT;
- writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
+ writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
result = I2C_OK;
switch (cmd_type) {
case I2C_WRITE:
if (addr && addr_len) {
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
- &i2c->IICSTAT);
+ &i2c->iicstat);
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
result = WaitForXfer();
- writel(addr[i], &i2c->IICDS);
+ writel(addr[i], &i2c->iicds);
ReadWriteByte();
i++;
}
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
result = WaitForXfer();
- writel(data[i], &i2c->IICDS);
+ writel(data[i], &i2c->iicds);
ReadWriteByte();
i++;
}
} else {
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* send START */
writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
- &i2c->IICSTAT);
+ &i2c->iicstat);
i = 0;
while ((i < data_len) && (result = I2C_OK)) {
result = WaitForXfer();
- writel(data[i], &i2c->IICDS);
+ writel(data[i], &i2c->iicds);
ReadWriteByte();
i++;
}
result = WaitForXfer();
/* send STOP */
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
break;
case I2C_READ:
if (addr && addr_len) {
- writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
- writel(chip, &i2c->IICDS);
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
+ writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
- &i2c->IICSTAT);
+ writel(readl(&i2c->iicstat) | I2C_START_STOP,
+ &i2c->iicstat);
result = WaitForXfer();
if (IsACK()) {
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
- writel(addr[i], &i2c->IICDS);
+ writel(addr[i], &i2c->iicds);
ReadWriteByte();
result = WaitForXfer();
i++;
}
- writel(chip, &i2c->IICDS);
+ writel(chip, &i2c->iicds);
/* resend START */
writel(I2C_MODE_MR | I2C_TXRX_ENA |
- I2C_START_STOP, &i2c->IICSTAT);
+ I2C_START_STOP, &i2c->iicstat);
ReadWriteByte();
result = WaitForXfer();
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- writel(readl(&i2c->IICCON)
- & ~0x80, &i2c->IICCON);
+ writel(readl(&i2c->iiccon)
+ & ~0x80, &i2c->iiccon);
ReadWriteByte();
result = WaitForXfer();
- data[i] = readl(&i2c->IICDS);
+ data[i] = readl(&i2c->iicds);
i++;
}
} else {
}
} else {
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
- writel(chip, &i2c->IICDS);
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ writel(chip, &i2c->iicds);
/* send START */
- writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
- &i2c->IICSTAT);
+ writel(readl(&i2c->iicstat) | I2C_START_STOP,
+ &i2c->iicstat);
result = WaitForXfer();
if (IsACK()) {
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- writel(readl(&i2c->IICCON) &
- ~0x80, &i2c->IICCON);
+ writel(readl(&i2c->iiccon) &
+ ~0x80, &i2c->iiccon);
ReadWriteByte();
result = WaitForXfer();
- data[i] = readl(&i2c->IICDS);
+ data[i] = readl(&i2c->iicds);
i++;
}
} else {
}
/* send STOP */
- writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
ReadWriteByte();
break;
include $(TOPDIR)/config.mk
-LIB := $(obj)libinput.a
+LIB := $(obj)libinput.o
COBJS-$(CONFIG_I8042_KBD) += i8042.o
ifdef CONFIG_PS2KBD
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libmisc.a
+LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
+COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_CMD_RAMOOPS) += ramoops.o
COBJS-$(CONFIG_CMD_MBR) += mbr.o
COBJS-$(CONFIG_INFO_ACTION) += info_action.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
u32 pmic_reg(u32 reg, u32 val, u32 write)
{
u32 pmic_tx, pmic_rx;
+ u32 tmp;
if (!slave) {
slave = pmic_spi_probe();
pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
- if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ tmp = cpu_to_be32(pmic_tx);
+
+ if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx,
SPI_XFER_BEGIN | SPI_XFER_END)) {
spi_release_bus(slave);
return -1;
if (write) {
pmic_tx &= ~(1 << 31);
- if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ tmp = cpu_to_be32(pmic_tx);
+ if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx,
SPI_XFER_BEGIN | SPI_XFER_END)) {
spi_release_bus(slave);
return -1;
}
spi_release_bus(slave);
- return pmic_rx;
+ return cpu_to_be32(pmic_rx);
}
void pmic_reg_write(u32 reg, u32 value)
--- /dev/null
+/*
+ * Copyright 2010 Sergey Poselenov, Emcraft Systems, <sposelenov@emcraft.com>
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <led-display.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CMD_DISPLAY
+#define CWORD_CLEAR 0x80
+#define CLEAR_DELAY (110 * 2)
+#define DISPLAY_SIZE 8
+
+static int pos; /* Current display position */
+
+/* Handle different display commands */
+void display_set(int cmd)
+{
+ if (cmd & DISPLAY_CLEAR) {
+ out_8((unsigned char *)CONFIG_SYS_DISP_CWORD, CWORD_CLEAR);
+ udelay(1000 * CLEAR_DELAY);
+ }
+
+ if (cmd & DISPLAY_HOME) {
+ pos = 0;
+ }
+}
+
+/*
+ * Display a character at the current display position.
+ * Characters beyond the display size are ignored.
+ */
+int display_putc(char c)
+{
+ if (pos >= DISPLAY_SIZE)
+ return -1;
+
+ out_8((unsigned char *)CONFIG_SYS_DISP_CHR_RAM + pos++, c);
+
+ return c;
+}
+#endif
include $(TOPDIR)/config.mk
-LIB := $(obj)libmmc.a
+LIB := $(obj)libmmc.o
COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
+COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
static int
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
- unsigned int sdh_cmd;
- unsigned int status;
+ unsigned int status, timeout;
int cmd = mmc_cmd->cmdidx;
int flags = mmc_cmd->resp_type;
int arg = mmc_cmd->cmdarg;
- int ret = 0;
- sdh_cmd = 0;
-
- sdh_cmd |= cmd;
+ int ret;
+ u16 sdh_cmd;
+ sdh_cmd = cmd | CMD_E;
if (flags & MMC_RSP_PRESENT)
sdh_cmd |= CMD_RSP;
-
if (flags & MMC_RSP_136)
sdh_cmd |= CMD_L_RSP;
bfin_write_SDH_ARGUMENT(arg);
- bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
+ bfin_write_SDH_COMMAND(sdh_cmd);
/* wait for a while */
+ timeout = 0;
do {
+ if (++timeout > 1000000) {
+ status = CMD_TIME_OUT;
+ break;
+ }
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
}
if (status & CMD_TIME_OUT)
- ret |= TIMEOUT;
+ ret = TIMEOUT;
else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
- ret |= COMM_ERR;
+ ret = COMM_ERR;
+ else
+ ret = 0;
bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
+
return ret;
}
int ret = 0;
u8 card_absent;
- /* Enable cache snooping */
- if (cfg && !cfg->no_snoop)
- esdhc_write32(®s->scr, 0x00000040);
-
/* Reset the entire host controller */
esdhc_write32(®s->sysctl, SYSCTL_RSTA);
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
+ /* Enable cache snooping */
+ if (cfg && !cfg->no_snoop)
+ esdhc_write32(®s->scr, 0x00000040);
+
esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */
- set_sysctl(mmc, 400000);
+ mmc_set_clock(mmc, 400000);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
{
struct fsl_esdhc *regs;
struct mmc *mmc;
- u32 caps;
+ u32 caps, voltage_caps;
if (!cfg)
return -1;
mmc->set_ios = esdhc_set_ios;
mmc->init = esdhc_init;
+ voltage_caps = 0;
caps = regs->hostcapblt;
-
if (caps & ESDHC_HOSTCAPBLT_VS18)
- mmc->voltages |= MMC_VDD_165_195;
+ voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
- mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & ESDHC_HOSTCAPBLT_VS33)
- mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+ voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+#ifdef CONFIG_SYS_SD_VOLTAGE
+ mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
+#else
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+#endif
+ if ((mmc->voltages & voltage_caps) == 0) {
+ printf("voltage not supported by controller\n");
+ return -1;
+ }
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
- mmc->f_max = MIN(gd->sdhc_clk, 50000000);
+ mmc->f_max = MIN(gd->sdhc_clk, 52000000);
mmc_register(mmc);
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
+ writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
/* Initial Time-outs */
writel(0x5f, &mci->dtor);
{
struct mmc_cmd cmd;
struct mmc_data data;
- int blklen, err;
-
- blklen = mmc->write_bl_len;
if ((start + blkcnt) > mmc->block_dev.lba) {
- printf("MMC: block number 0x%lx exceeds max(0x%lx)",
+ printf("MMC: block number 0x%lx exceeds max(0x%lx)\n",
start + blkcnt, mmc->block_dev.lba);
return 0;
}
if (mmc->high_capacity)
cmd.cmdarg = start;
else
- cmd.cmdarg = start * blklen;
+ cmd.cmdarg = start * mmc->write_bl_len;
cmd.resp_type = MMC_RSP_R1;
cmd.flags = 0;
data.src = src;
data.blocks = blkcnt;
- data.blocksize = blklen;
+ data.blocksize = mmc->write_bl_len;
data.flags = MMC_DATA_WRITE;
- err = mmc_send_cmd(mmc, &cmd, &data);
-
- if (err) {
- printf("mmc write failed\n\r");
- return err;
+ if (mmc_send_cmd(mmc, &cmd, &data)) {
+ printf("mmc write failed\n");
+ return 0;
}
#ifndef CONFIG_MMC_ASYNC_WRITE
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
cmd.flags = 0;
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (err) {
- printf("mmc fail to send stop cmd\n\r");
- return err;
+ if (mmc_send_cmd(mmc, &cmd, NULL)) {
+ printf("mmc fail to send stop cmd\n");
+ return 0;
}
}
#endif
static ulong
mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
{
- int err;
- struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t cur, blocks_todo = blkcnt;
+ struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
- return -1;
+ return 0;
- err = mmc_set_blocklen(mmc, mmc->write_bl_len);
- if (err) {
- printf("set write bl len failed\n\r");
- return err;
- }
+ if (mmc_set_blocklen(mmc, mmc->write_bl_len))
+ return 0;
do {
/*
*/
cur = (blocks_todo > 65535) ? 65535 : blocks_todo;
if(mmc_write_blocks(mmc, start, cur, src) != cur)
- return -1;
+ return 0;
blocks_todo -= cur;
start += cur;
src += cur * mmc->write_bl_len;
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
- if (!err & (ext_csd[EXT_CSD_REV] >= 2)) {
+ if (!err & (ext_csd[192] >= 2)) {
mmc->capacity = ext_csd[212] << 0 | ext_csd[213] << 8 |
ext_csd[214] << 16 | ext_csd[215] << 24;
mmc->capacity *= 512;
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Sukumar Ghorai <s-ghorai@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mmc.h>
+#include <part.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+
+/* If we fail after 1 second wait, something is really bad */
+#define MAX_RETRY_MS 1000
+
+static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size);
+static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz);
+static struct mmc hsmmc_dev[2];
+unsigned char mmc_board_init(hsmmc_t *mmc_base)
+{
+#if defined(CONFIG_TWL4030_POWER)
+ twl4030_power_mmc_init();
+#endif
+
+#if defined(CONFIG_OMAP34XX)
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+ writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
+ PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
+ &t2_base->pbias_lite);
+
+ writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
+ &t2_base->devconf0);
+
+ writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+ &t2_base->devconf1);
+
+ writel(readl(&prcm_base->fclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->fclken1_core);
+
+ writel(readl(&prcm_base->iclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->iclken1_core);
+#endif
+
+/* TODO add appropriate OMAP4 init - none currently necessary */
+
+ return 0;
+}
+
+void mmc_init_stream(hsmmc_t *mmc_base)
+{
+ ulong start;
+
+ writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
+
+ writel(MMC_CMD0, &mmc_base->cmd);
+ start = get_timer(0);
+ while (!(readl(&mmc_base->stat) & CC_MASK)) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for cc!\n", __func__);
+ return;
+ }
+ }
+ writel(CC_MASK, &mmc_base->stat)
+ ;
+ writel(MMC_CMD0, &mmc_base->cmd)
+ ;
+ start = get_timer(0);
+ while (!(readl(&mmc_base->stat) & CC_MASK)) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for cc2!\n", __func__);
+ return;
+ }
+ }
+ writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
+}
+
+
+static int mmc_init_setup(struct mmc *mmc)
+{
+ hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ unsigned int reg_val;
+ unsigned int dsor;
+ ulong start;
+
+ mmc_board_init(mmc_base);
+
+ writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
+ &mmc_base->sysconfig);
+ start = get_timer(0);
+ while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for cc2!\n", __func__);
+ return TIMEOUT;
+ }
+ }
+ writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
+ start = get_timer(0);
+ while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for softresetall!\n",
+ __func__);
+ return TIMEOUT;
+ }
+ }
+ writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
+ writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
+ &mmc_base->capa);
+
+ reg_val = readl(&mmc_base->con) & RESERVED_MASK;
+
+ writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
+ MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
+ HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
+
+ dsor = 240;
+ mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
+ (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+ mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
+ (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
+ start = get_timer(0);
+ while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for ics!\n", __func__);
+ return TIMEOUT;
+ }
+ }
+ writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
+
+ writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
+
+ writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
+ IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
+ &mmc_base->ie);
+
+ mmc_init_stream(mmc_base);
+
+ return 0;
+}
+
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ unsigned int flags, mmc_stat;
+ ulong start;
+
+ start = get_timer(0);
+ while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for cmddis!\n", __func__);
+ return TIMEOUT;
+ }
+ }
+ writel(0xFFFFFFFF, &mmc_base->stat);
+ start = get_timer(0);
+ while (readl(&mmc_base->stat)) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for stat!\n", __func__);
+ return TIMEOUT;
+ }
+ }
+ /*
+ * CMDREG
+ * CMDIDX[13:8] : Command index
+ * DATAPRNT[5] : Data Present Select
+ * ENCMDIDX[4] : Command Index Check Enable
+ * ENCMDCRC[3] : Command CRC Check Enable
+ * RSPTYP[1:0]
+ * 00 = No Response
+ * 01 = Length 136
+ * 10 = Length 48
+ * 11 = Length 48 Check busy after response
+ */
+ /* Delay added before checking the status of frq change
+ * retry not supported by mmc.c(core file)
+ */
+ if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
+ udelay(50000); /* wait 50 ms */
+
+ if (!(cmd->resp_type & MMC_RSP_PRESENT))
+ flags = 0;
+ else if (cmd->resp_type & MMC_RSP_136)
+ flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ flags = RSP_TYPE_LGHT48B;
+ else
+ flags = RSP_TYPE_LGHT48;
+
+ /* enable default flags */
+ flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
+ MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= CCCE_CHECK;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ flags |= CICE_CHECK;
+
+ if (data) {
+ if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
+ flags |= (MSBS_MULTIBLK | BCE_ENABLE);
+ data->blocksize = 512;
+ writel(data->blocksize | (data->blocks << 16),
+ &mmc_base->blk);
+ } else
+ writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
+
+ if (data->flags & MMC_DATA_READ)
+ flags |= (DP_DATA | DDIR_READ);
+ else
+ flags |= (DP_DATA | DDIR_WRITE);
+ }
+
+ writel(cmd->cmdarg, &mmc_base->arg);
+ writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
+
+ start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s : timeout: No status update\n", __func__);
+ return TIMEOUT;
+ }
+ } while (!mmc_stat);
+
+ if ((mmc_stat & IE_CTO) != 0)
+ return TIMEOUT;
+ else if ((mmc_stat & ERRI_MASK) != 0)
+ return -1;
+
+ if (mmc_stat & CC_MASK) {
+ writel(CC_MASK, &mmc_base->stat);
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ /* response type 2 */
+ cmd->response[3] = readl(&mmc_base->rsp10);
+ cmd->response[2] = readl(&mmc_base->rsp32);
+ cmd->response[1] = readl(&mmc_base->rsp54);
+ cmd->response[0] = readl(&mmc_base->rsp76);
+ } else
+ /* response types 1, 1b, 3, 4, 5, 6 */
+ cmd->response[0] = readl(&mmc_base->rsp10);
+ }
+ }
+
+ if (data && (data->flags & MMC_DATA_READ)) {
+ mmc_read_data(mmc_base, data->dest,
+ data->blocksize * data->blocks);
+ } else if (data && (data->flags & MMC_DATA_WRITE)) {
+ mmc_write_data(mmc_base, data->src,
+ data->blocksize * data->blocks);
+ }
+ return 0;
+}
+
+static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size)
+{
+ unsigned int *output_buf = (unsigned int *)buf;
+ unsigned int mmc_stat;
+ unsigned int count;
+
+ /*
+ * Start Polled Read
+ */
+ count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
+ count /= 4;
+
+ while (size) {
+ ulong start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for status!\n",
+ __func__);
+ return TIMEOUT;
+ }
+ } while (mmc_stat == 0);
+
+ if ((mmc_stat & ERRI_MASK) != 0)
+ return 1;
+
+ if (mmc_stat & BRR_MASK) {
+ unsigned int k;
+
+ writel(readl(&mmc_base->stat) | BRR_MASK,
+ &mmc_base->stat);
+ for (k = 0; k < count; k++) {
+ *output_buf = readl(&mmc_base->data);
+ output_buf++;
+ }
+ size -= (count*4);
+ }
+
+ if (mmc_stat & BWR_MASK)
+ writel(readl(&mmc_base->stat) | BWR_MASK,
+ &mmc_base->stat);
+
+ if (mmc_stat & TC_MASK) {
+ writel(readl(&mmc_base->stat) | TC_MASK,
+ &mmc_base->stat);
+ break;
+ }
+ }
+ return 0;
+}
+
+static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size)
+{
+ unsigned int *input_buf = (unsigned int *)buf;
+ unsigned int mmc_stat;
+ unsigned int count;
+
+ /*
+ * Start Polled Read
+ */
+ count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
+ count /= 4;
+
+ while (size) {
+ ulong start = get_timer(0);
+ do {
+ mmc_stat = readl(&mmc_base->stat);
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for status!\n",
+ __func__);
+ return TIMEOUT;
+ }
+ } while (mmc_stat == 0);
+
+ if ((mmc_stat & ERRI_MASK) != 0)
+ return 1;
+
+ if (mmc_stat & BWR_MASK) {
+ unsigned int k;
+
+ writel(readl(&mmc_base->stat) | BWR_MASK,
+ &mmc_base->stat);
+ for (k = 0; k < count; k++) {
+ writel(*input_buf, &mmc_base->data);
+ input_buf++;
+ }
+ size -= (count*4);
+ }
+
+ if (mmc_stat & BRR_MASK)
+ writel(readl(&mmc_base->stat) | BRR_MASK,
+ &mmc_base->stat);
+
+ if (mmc_stat & TC_MASK) {
+ writel(readl(&mmc_base->stat) | TC_MASK,
+ &mmc_base->stat);
+ break;
+ }
+ }
+ return 0;
+}
+
+static void mmc_set_ios(struct mmc *mmc)
+{
+ hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ unsigned int dsor = 0;
+ ulong start;
+
+ /* configue bus width */
+ switch (mmc->bus_width) {
+ case 8:
+ writel(readl(&mmc_base->con) | DTW_8_BITMODE,
+ &mmc_base->con);
+ break;
+
+ case 4:
+ writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
+ &mmc_base->con);
+ writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
+ &mmc_base->hctl);
+ break;
+
+ case 1:
+ default:
+ writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
+ &mmc_base->con);
+ writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
+ &mmc_base->hctl);
+ break;
+ }
+
+ /* configure clock with 96Mhz system clock.
+ */
+ if (mmc->clock != 0) {
+ dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
+ if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
+ dsor++;
+ }
+
+ mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
+ (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+
+ mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
+ (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
+
+ start = get_timer(0);
+ while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for ics!\n", __func__);
+ return;
+ }
+ }
+ writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
+}
+
+int omap_mmc_init(int dev_index)
+{
+ struct mmc *mmc;
+
+ mmc = &hsmmc_dev[dev_index];
+
+ sprintf(mmc->name, "OMAP SD/MMC");
+ mmc->send_cmd = mmc_send_cmd;
+ mmc->set_ios = mmc_set_ios;
+ mmc->init = mmc_init_setup;
+
+ switch (dev_index) {
+ case 0:
+ mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ break;
+ case 1:
+ mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
+ break;
+ case 2:
+ mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
+ break;
+ default:
+ mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ return 1;
+ }
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ mmc->f_min = 400000;
+ mmc->f_max = 52000000;
+
+ mmc_register(mmc);
+
+ return 0;
+}
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
+#include <asm/io.h>
#include "pxa_mmc.h"
debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
cmdat | wide);
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
- while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ;
- MMC_CMD = cmd;
- MMC_ARGH = argh;
- MMC_ARGL = argl;
- MMC_CMDAT = cmdat | wide;
- MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
- MMC_STRPCL = MMC_STRPCL_START_CLK;
- while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ;
-
- status = MMC_STAT;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
+ ;
+ writel(cmd, MMC_CMD);
+ writel(argh, MMC_ARGH);
+ writel(argl, MMC_ARGL);
+ writel(cmdat | wide, MMC_CMDAT);
+ writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
+ writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
+ ;
+
+ status = readl(MMC_STAT);
debug("MMC status 0x%08x\n", status);
if (status & MMC_STAT_TIME_OUT_RESPONSE) {
return 0;
* Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
- a = (MMC_RES & 0xffff);
+ a = (readl(MMC_RES) & 0xffff);
for (i = 0; i < 4; i++) {
- b = (MMC_RES & 0xffff);
- c = (MMC_RES & 0xffff);
+ b = (readl(MMC_RES) & 0xffff);
+ c = (readl(MMC_RES) & 0xffff);
resp[i] = (a << 24) | (b << 8) | (c >> 8);
a = c;
debug("MMC resp[%d] = %#08x\n", i, resp[i]);
/* send read command */
argh = src >> 16;
argl = src & 0xffff;
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_RDTO = 0xffff;
- MMC_NOB = 1;
- MMC_BLKLEN = len;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(0xffff, MMC_RDTO);
+ writel(1, MMC_NOB);
+ writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
- MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
+ writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
while (len) {
- if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+ if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
int i;
for (i = min(len, 32); i; i--) {
- *dst++ = *((volatile uchar *)&MMC_RXFIFO);
+ *dst++ = readb(MMC_RXFIFO);
len--;
}
#else
- *dst++ = MMC_RXFIFO;
+ *dst++ = readb(MMC_RXFIFO);
len--;
#endif
}
- status = MMC_STAT;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
- MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
- while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
- status = MMC_STAT;
+ writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+ ;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
/* send write command */
argh = dst >> 16;
argl = dst & 0xffff;
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_NOB = 1;
- MMC_BLKLEN = len;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(1, MMC_NOB);
+ writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
- MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
+ writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
while (len) {
- if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
+ if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
int i, bytes = min(32, len);
for (i = 0; i < bytes; i++) {
- MMC_TXFIFO = *src++;
+ writel(*src++, MMC_TXFIFO);
}
if (bytes < 32) {
- MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
+ writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
}
len -= bytes;
}
- status = MMC_STAT;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
- MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
- while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
- MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
- while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ;
- status = MMC_STAT;
+ writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+ ;
+ writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
+ ;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
set_GPIO_mode(GPIO8_MMCCS0_MD);
#endif
#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */
- CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1;
+ writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
#else /* pxa2xx */
- CKEN |= CKEN12_MMC; /* enable MMC unit clock */
+ writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */
#endif
- MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
- MMC_RESTO = MMC_RES_TO_MAX;
- MMC_SPI = MMC_SPI_DISABLE;
+ writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
+ writel(MMC_RES_TO_MAX, MMC_RESTO);
+ writel(MMC_SPI_DISABLE, MMC_SPI);
/* reset */
mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
mmc_decode_cid(cid_resp);
}
- MMC_CLKRT = 0; /* 20 MHz */
+ writel(0, MMC_CLKRT); /* 20 MHz */
resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
clk = (div << 8) | (1 << 0);
writew(clk, &host->reg->clkcon);
- if (set_mmc_clk)
- set_mmc_clk(host->dev_index, div);
+ set_mmc_clk(host->dev_index, div);
/* Wait max 10 ms */
timeout = 10;
* WIDE8[5]
* 0 = Depend on WIDE4
* 1 = 8-bit mode
- *
* WIDE4[1]
* 1 = 4-bit mode
* 0 = 1-bit mode
include $(TOPDIR)/config.mk
-LIB := $(obj)libmtd.a
+LIB := $(obj)libmtd.o
COBJS-$(CONFIG_MTD_DEVICE) += mtdcore.o
COBJS-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#endif
+/*
+ * 0xffff is an undefined value for the configuration register. When
+ * this value is returned, the configuration register shall not be
+ * written at all (default mode).
+ */
+static u16 cfi_flash_config_reg(int i)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
+ return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
+#else
+ return 0xffff;
+#endif
+}
+
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
#endif
phys_addr_t cfi_flash_bank_addr(int i)
__attribute__((weak, alias("__cfi_flash_bank_addr")));
+static unsigned long __cfi_flash_bank_size(int i)
+{
+#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
+ return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#else
+ return 0;
+#endif
+}
+unsigned long cfi_flash_bank_size(int i)
+ __attribute__((weak, alias("__cfi_flash_bank_size")));
+
static void __flash_write8(u8 value, void *addr)
{
__raw_writeb(value, addr);
{
int k;
int size;
- volatile unsigned long *flash;
+ u32 *flash;
/*
* Check if whole sector is erased
*/
size = flash_sector_size(info, i);
- flash = (volatile unsigned long *) info->start[i];
+ flash = (u32 *)info->start[i];
/* divide by 4 for longword access */
size = size >> 2;
for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff)
+ if (flash_read32(flash++) != 0xffffffff)
return 0; /* not erased */
}
#endif
};
+ /*
+ * Flash needs to be in status register read mode for
+ * flash_full_status_check() to work correctly
+ */
+ flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
if ((retcode =
flash_full_status_check (info, sector, info->erase_blk_tout,
prot ? "protect" : "unprotect")) == 0) {
int erase_region_size;
int erase_region_count;
struct cfi_qry qry;
+ unsigned long max_size;
memset(&qry, 0, sizeof(qry));
debug ("size_ratio %d port %d bits chip %d bits\n",
size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+ info->size = 1 << qry.dev_size;
+ /* multiply the size by the number of chips */
+ info->size *= size_ratio;
+ max_size = cfi_flash_bank_size(banknum);
+ if (max_size && (info->size > max_size)) {
+ debug("[truncated from %ldMiB]", info->size >> 20);
+ info->size = max_size;
+ }
debug ("found %d erase regions\n", num_erase_regions);
sect_cnt = 0;
sector = base;
debug ("erase_region_count = %d erase_region_size = %d\n",
erase_region_count, erase_region_size);
for (j = 0; j < erase_region_count; j++) {
+ if (sector - base >= info->size)
+ break;
if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
printf("ERROR: too many flash sectors\n");
break;
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
+ /*
+ * Set flash to read-id mode. Otherwise
+ * reading protected status is not
+ * guaranteed.
+ */
+ flash_write_cmd(info, sect_cnt, 0,
+ FLASH_CMD_READ_ID);
info->protect[sect_cnt] =
flash_isset (info, sect_cnt,
FLASH_OFFSET_PROTECT,
}
info->sector_count = sect_cnt;
- info->size = 1 << qry.dev_size;
- /* multiply the size by the number of chips */
- info->size *= size_ratio;
info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
tmp = 1 << qry.block_erase_timeout_typ;
info->erase_blk_tout = tmp *
flash_verbose = v;
}
+static void cfi_flash_set_config_reg(u32 base, u16 val)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
+ /*
+ * Only set this config register if really defined
+ * to a valid value (0xffff is invalid)
+ */
+ if (val == 0xffff)
+ return;
+
+ /*
+ * Set configuration register. Data is "encrypted" in the 16 lower
+ * address bits.
+ */
+ flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
+ flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
+
+ /*
+ * Finally issue reset-command to bring device back to
+ * read-array mode
+ */
+ flash_write16(FLASH_CMD_RESET, (void *)base);
+#endif
+}
+
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
+ /* Optionally write flash configuration register */
+ cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
+ cfi_flash_config_reg(i));
+
if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
flash_get_size(cfi_flash_bank_addr(i), i);
size += flash_info[i].size;
printf ("## Unknown FLASH on Bank %d "
"- Size = 0x%08lx = %ld MB\n",
i+1, flash_info[i].size,
- flash_info[i].size << 20);
+ flash_info[i].size >> 20);
#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
c = --mtd->usecount;
BUG_ON(c < 0);
}
+
+#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
+/**
+ * mtd_get_len_incl_bad
+ *
+ * Check if length including bad blocks fits into device.
+ *
+ * @param mtd an MTD device
+ * @param offset offset in flash
+ * @param length image length
+ * @return image length including bad blocks in *len_incl_bad and whether or not
+ * the length returned was truncated in *truncated
+ */
+void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+ const uint64_t length, uint64_t *len_incl_bad,
+ int *truncated)
+{
+ *truncated = 0;
+ *len_incl_bad = 0;
+
+ if (!mtd->block_isbad) {
+ *len_incl_bad = length;
+ return;
+ }
+
+ uint64_t len_excl_bad = 0;
+ uint64_t block_len;
+
+ while (len_excl_bad < length) {
+ if (offset >= mtd->size) {
+ *truncated = 1;
+ return;
+ }
+
+ block_len = mtd->erasesize - (offset & (mtd->erasesize - 1));
+
+ if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
+ len_excl_bad += block_len;
+
+ *len_incl_bad += block_len;
+ offset += block_len;
+ }
+}
+#endif /* defined(CONFIG_CMD_MTDPARTS_SPREAD) */
part->master->sync(part->master);
}
-static int part_suspend(struct mtd_info *mtd)
-{
- struct mtd_part *part = PART(mtd);
- return part->master->suspend(part->master);
-}
-
-static void part_resume(struct mtd_info *mtd)
-{
- struct mtd_part *part = PART(mtd);
- part->master->resume(part->master);
-}
-
static int part_block_isbad(struct mtd_info *mtd, loff_t ofs)
{
struct mtd_part *part = PART(mtd);
slave->mtd.get_fact_prot_info = part_get_fact_prot_info;
if (master->sync)
slave->mtd.sync = part_sync;
- if (!partno && master->suspend && master->resume) {
- slave->mtd.suspend = part_suspend;
- slave->mtd.resume = part_resume;
- }
if (master->lock)
slave->mtd.lock = part_lock;
if (master->unlock)
include $(TOPDIR)/config.mk
-LIB := $(obj)libnand.a
+LIB := $(obj)libnand.o
ifdef CONFIG_CMD_NAND
COBJS-y += nand.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
* register to 1.
*/
- __raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
+ __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
+ &davinci_emif_regs->nandfcr);
/*
* Wait for the corr_state field (bits 8 to 11) in the
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
+ (void)in_be32(upm->mxmr);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, mar);
+ (void)in_be32(upm->mar);
switch (width) {
case 8:
out_8(io_addr, 0x0);
if (nand_scan(mtd, maxchips) == 0) {
if (!mtd->name)
mtd->name = (char *)default_nand_name;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
else
mtd->name += gd->reloc_off;
#endif
*
*/
-/* XXX U-BOOT XXX */
-#if 0
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/compatmac.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/leds.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_MTD_PARTITIONS
-#include <linux/mtd/partitions.h>
-#endif
-
-#endif
-
#include <common.h>
#define ENOTSUPP 524 /* Operation is not supported */
#include <asm/io.h>
#include <asm/errno.h>
-#ifdef CONFIG_JFFS2_NAND
-#include <jffs2/jffs2.h>
-#endif
-
/*
* CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
* a flash. NAND flash is initialized prior to interrupts so standard timers
static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
-/*
- * For devices which display every fart in the system on a separate LED. Is
- * compiled away when LED support is disabled.
- */
-/* XXX U-BOOT XXX */
-#if 0
-DEFINE_LED_TRIGGER(nand_led_trigger);
-#endif
-
/**
* nand_release_device - [GENERIC] release chip
* @mtd: MTD device structure
*
* Deselect, release chip lock and wake up anyone waiting on the device
*/
-/* XXX U-BOOT XXX */
-#if 0
-static void nand_release_device(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- /* De-select the NAND device */
- chip->select_chip(mtd, -1);
-
- /* Release the controller and the chip */
- spin_lock(&chip->controller->lock);
- chip->controller->active = NULL;
- chip->state = FL_READY;
- wake_up(&chip->controller->wq);
- spin_unlock(&chip->controller->lock);
-}
-#else
static void nand_release_device (struct mtd_info *mtd)
{
struct nand_chip *this = mtd->priv;
this->select_chip(mtd, -1); /* De-select the NAND device */
}
-#endif
/**
* nand_read_byte - [DEFAULT] read one byte from the chip
* Wait for the ready pin, after a command
* The timeout is catched later.
*/
-/* XXX U-BOOT XXX */
-#if 0
-void nand_wait_ready(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
- unsigned long timeo = jiffies + 2;
-
- led_trigger_event(nand_led_trigger, LED_FULL);
- /* wait until command is processed or timeout occures */
- do {
- if (chip->dev_ready(mtd))
- break;
- touch_softlockup_watchdog();
- } while (time_before(jiffies, timeo));
- led_trigger_event(nand_led_trigger, LED_OFF);
-}
-EXPORT_SYMBOL_GPL(nand_wait_ready);
-#else
void nand_wait_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start;
- reset_timer();
+ time_start = get_timer(0);
/* wait until command is processed or timeout occures */
- while (get_timer(0) < timeo) {
+ while (get_timer(time_start) < timeo) {
if (chip->dev_ready)
if (chip->dev_ready(mtd))
break;
}
}
-#endif
/**
* nand_command - [DEFAULT] Send command to NAND device
*
* Get the device and lock it for exclusive access
*/
-/* XXX U-BOOT XXX */
-#if 0
-static int
-nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
-{
- spinlock_t *lock = &chip->controller->lock;
- wait_queue_head_t *wq = &chip->controller->wq;
- DECLARE_WAITQUEUE(wait, current);
- retry:
- spin_lock(lock);
-
- /* Hardware controller shared among independend devices */
- /* Hardware controller shared among independend devices */
- if (!chip->controller->active)
- chip->controller->active = chip;
-
- if (chip->controller->active == chip && chip->state == FL_READY) {
- chip->state = new_state;
- spin_unlock(lock);
- return 0;
- }
- if (new_state == FL_PM_SUSPENDED) {
- spin_unlock(lock);
- return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
- }
- set_current_state(TASK_UNINTERRUPTIBLE);
- add_wait_queue(wq, &wait);
- spin_unlock(lock);
- schedule();
- remove_wait_queue(wq, &wait);
- goto retry;
-}
-#else
static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
{
this->state = new_state;
return 0;
}
-#endif
/**
* nand_wait - [DEFAULT] wait until the command is done
* Erase can take up to 400ms and program up to 20ms according to
* general NAND and SmartMedia specs
*/
-/* XXX U-BOOT XXX */
-#if 0
-static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
-{
-
- unsigned long timeo = jiffies;
- int status, state = chip->state;
-
- if (state == FL_ERASING)
- timeo += (HZ * 400) / 1000;
- else
- timeo += (HZ * 20) / 1000;
-
- led_trigger_event(nand_led_trigger, LED_FULL);
-
- /* Apply this short delay always to ensure that we do wait tWB in
- * any case on any machine. */
- ndelay(100);
-
- if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
- chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
- else
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-
- while (time_before(jiffies, timeo)) {
- if (chip->dev_ready) {
- if (chip->dev_ready(mtd))
- break;
- } else {
- if (chip->read_byte(mtd) & NAND_STATUS_READY)
- break;
- }
- cond_resched();
- }
- led_trigger_event(nand_led_trigger, LED_OFF);
-
- status = (int)chip->read_byte(mtd);
- return status;
-}
-#else
static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
{
unsigned long timeo;
int state = this->state;
+ u32 time_start;
if (state == FL_ERASING)
timeo = (CONFIG_SYS_HZ * 400) / 1000;
else
this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- reset_timer();
+ time_start = get_timer(0);
while (1) {
- if (get_timer(0) > timeo) {
+ if (get_timer(time_start) > timeo) {
printf("Timeout!");
return 0x01;
}
}
}
#ifdef PPCHAMELON_NAND_TIMER_HACK
- reset_timer();
- while (get_timer(0) < 10);
+ time_start = get_timer(0);
+ while (get_timer(time_start) < 10)
+ ;
#endif /* PPCHAMELON_NAND_TIMER_HACK */
return this->read_byte(mtd);
}
-#endif
/**
* nand_read_page_raw - [Intern] read raw page data without ecc
if (!writelen)
return 0;
- /* reject writes, which are not page aligned */
- if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
- printk(KERN_NOTICE "nand_write: "
- "Attempt to write not page aligned data\n");
- return -EINVAL;
- }
-
column = to & (mtd->writesize - 1);
subpage = column || (writelen & (mtd->writesize - 1));
return chip->block_markbad(mtd, ofs);
}
-/**
- * nand_suspend - [MTD Interface] Suspend the NAND flash
- * @mtd: MTD device structure
- */
-static int nand_suspend(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
-}
-
-/**
- * nand_resume - [MTD Interface] Resume the NAND flash
- * @mtd: MTD device structure
- */
-static void nand_resume(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- if (chip->state == FL_PM_SUSPENDED)
- nand_release_device(mtd);
- else
- printk(KERN_ERR "nand_resume() called for a chip which is not "
- "in suspended state\n");
-}
-
/*
* Set default functions
*/
chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
-
- if (!chip->controller) {
+ if (!chip->controller)
chip->controller = &chip->hwcontrol;
-
- /* XXX U-BOOT XXX */
-#if 0
- spin_lock_init(&chip->controller->lock);
- init_waitqueue_head(&chip->controller->wq);
-#endif
- }
-
}
/*
* Get the flash and manufacturer id and lookup if the type is supported
*/
-static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
struct nand_chip *chip,
int busw, int *maf_id)
{
- struct nand_flash_dev *type = NULL;
+ const struct nand_flash_dev *type = NULL;
int i, dev_id, maf_idx;
int tmp_id, tmp_manf;
{
int i, busw, nand_maf_id;
struct nand_chip *chip = mtd->priv;
- struct nand_flash_dev *type;
+ const struct nand_flash_dev *type;
/* Get buswidth to select the correct functions */
busw = chip->options & NAND_BUSWIDTH_16;
mtd->sync = nand_sync;
mtd->lock = NULL;
mtd->unlock = NULL;
- mtd->suspend = nand_suspend;
- mtd->resume = nand_resume;
mtd->block_isbad = nand_block_isbad;
mtd->block_markbad = nand_block_markbad;
return 0;
}
-/* module_text_address() isn't exported, and it's mostly a pointless
- test if this is a module _anyway_ -- they'd have to try _really_ hard
- to call us from in-kernel code if the core NAND support is modular. */
-#ifdef MODULE
-#define caller_is_module() (1)
-#else
-#define caller_is_module() \
- module_text_address((unsigned long)__builtin_return_address(0))
-#endif
-
/**
* nand_scan - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
{
int ret;
- /* Many callers got this wrong, so check for it for a while... */
- /* XXX U-BOOT XXX */
-#if 0
- if (!mtd->owner && caller_is_module()) {
- printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
- BUG();
- }
-#endif
-
ret = nand_scan_ident(mtd, maxchips);
if (!ret)
ret = nand_scan_tail(mtd);
/* Deregister partitions */
del_mtd_partitions(mtd);
#endif
- /* Deregister the device */
- /* XXX U-BOOT XXX */
-#if 0
- del_mtd_device(mtd);
-#endif
/* Free bad block table memory */
kfree(chip->bbt);
if (!(chip->options & NAND_OWN_BUFFERS))
kfree(chip->buffers);
}
-
-/* XXX U-BOOT XXX */
-#if 0
-EXPORT_SYMBOL_GPL(nand_scan);
-EXPORT_SYMBOL_GPL(nand_scan_ident);
-EXPORT_SYMBOL_GPL(nand_scan_tail);
-EXPORT_SYMBOL_GPL(nand_release);
-
-static int __init nand_base_init(void)
-{
- led_trigger_register_simple("nand-disk", &nand_led_trigger);
- return 0;
-}
-
-static void __exit nand_base_exit(void)
-{
- led_trigger_unregister_simple(nand_led_trigger);
-}
-
-module_init(nand_base_init);
-module_exit(nand_base_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
-MODULE_DESCRIPTION("Generic NAND flash driver code");
-#endif
#include <asm/errno.h>
-/* XXX U-BOOT XXX */
-#if 0
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/compatmac.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/vmalloc.h>
-#endif
-
/**
* check_pattern - [GENERIC] check if a pattern is in the buffer
* @buf: the buffer to search
}
return 1;
}
-
-/* XXX U-BOOT XXX */
-#if 0
-EXPORT_SYMBOL(nand_scan_bbt);
-EXPORT_SYMBOL(nand_default_bbt);
-#endif
#include <common.h>
-/* XXX U-BOOT XXX */
-#if 0
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mtd/nand_ecc.h>
-#endif
-
#include <asm/errno.h>
#include <linux/mtd/mtd.h>
return 0;
}
-/* XXX U-BOOT XXX */
-#if 0
-EXPORT_SYMBOL(nand_calculate_ecc);
-#endif
#endif /* CONFIG_NAND_SPL */
static inline int countbits(uint32_t byte)
return -EBADMSG;
}
-
-/* XXX U-BOOT XXX */
-#if 0
-EXPORT_SYMBOL(nand_correct_data);
-#endif
+ 256 256 Byte page size
* 512 512 Byte page size
*/
-struct nand_flash_dev nand_flash_ids[] = {
+const struct nand_flash_dev nand_flash_ids[] = {
#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
/*
* Manufacturer ID list
*/
-struct nand_manufacturers nand_manuf_ids[] = {
+const struct nand_manufacturers nand_manuf_ids[] = {
{NAND_MFR_TOSHIBA, "Toshiba"},
{NAND_MFR_SAMSUNG, "Samsung"},
{NAND_MFR_FUJITSU, "Fujitsu"},
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
+ * Copyright 2010 Freescale Semiconductor
+ * The portions of this file whose copyright is held by Freescale and which
+ * are not considered a derived work of GPL v2-only code may be distributed
+ * and/or modified under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
*/
#include <common.h>
{
struct jffs2_unknown_node cleanmarker;
erase_info_t erase;
- ulong erase_length;
+ unsigned long erase_length, erased_length; /* in blocks */
int bbtest = 1;
int result;
int percent_complete = -1;
struct mtd_oob_ops oob_opts;
struct nand_chip *chip = meminfo->priv;
+ if ((opts->offset & (meminfo->writesize - 1)) != 0) {
+ printf("Attempt to erase non page aligned data\n");
+ return -1;
+ }
+
memset(&erase, 0, sizeof(erase));
memset(&oob_opts, 0, sizeof(oob_opts));
erase.mtd = meminfo;
erase.len = meminfo->erasesize;
erase.addr = opts->offset;
- erase_length = opts->length;
+ erase_length = lldiv(opts->length + meminfo->erasesize - 1,
+ meminfo->erasesize);
cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
priv_nand->bbt = NULL;
}
- if (erase_length < meminfo->erasesize) {
- printf("Warning: Erase size 0x%08lx smaller than one " \
- "erase block 0x%08x\n",erase_length, meminfo->erasesize);
- printf(" Erasing 0x%08x instead\n", meminfo->erasesize);
- erase_length = meminfo->erasesize;
- }
-
- for (;
- erase.addr < opts->offset + erase_length;
+ for (erased_length = 0;
+ erased_length < erase_length;
erase.addr += meminfo->erasesize) {
WATCHDOG_RESET ();
"0x%08llx "
" \n",
erase.addr);
+
+ if (!opts->spread)
+ erased_length++;
+
continue;
} else if (ret < 0) {
}
}
+ erased_length++;
+
result = meminfo->erase(meminfo, &erase);
if (result != 0) {
printf("\n%s: MTD Erase failure: %d\n",
}
if (!opts->quiet) {
- unsigned long long n =(unsigned long long)
- (erase.addr + meminfo->erasesize - opts->offset)
- * 100;
+ unsigned long long n = erased_length * 100ULL;
int percent;
do_div(n, erase_length);
return 0;
}
-/* XXX U-BOOT XXX */
-#if 0
-
-#define MAX_PAGE_SIZE 2048
-#define MAX_OOB_SIZE 64
-
-/*
- * buffer array used for writing data
- */
-static unsigned char data_buf[MAX_PAGE_SIZE];
-static unsigned char oob_buf[MAX_OOB_SIZE];
-
-/* OOB layouts to pass into the kernel as default */
-static struct nand_ecclayout none_ecclayout = {
- .useecc = MTD_NANDECC_OFF,
-};
-
-static struct nand_ecclayout jffs2_ecclayout = {
- .useecc = MTD_NANDECC_PLACE,
- .eccbytes = 6,
- .eccpos = { 0, 1, 2, 3, 6, 7 }
-};
-
-static struct nand_ecclayout yaffs_ecclayout = {
- .useecc = MTD_NANDECC_PLACE,
- .eccbytes = 6,
- .eccpos = { 8, 9, 10, 13, 14, 15}
-};
-
-static struct nand_ecclayout autoplace_ecclayout = {
- .useecc = MTD_NANDECC_AUTOPLACE
-};
-#endif
-
-/* XXX U-BOOT XXX */
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
/******************************************************************************
#endif
/**
- * get_len_incl_bad
+ * check_skip_len
*
- * Check if length including bad blocks fits into device.
+ * Check if there are any bad blocks, and whether length including bad
+ * blocks fits into device
*
* @param nand NAND device
* @param offset offset in flash
* @param length image length
- * @return image length including bad blocks
+ * @return 0 if the image fits and there are no bad blocks
+ * 1 if the image fits, but there are bad blocks
+ * -1 if the image does not fit
*/
-static size_t get_len_incl_bad (nand_info_t *nand, loff_t offset,
- const size_t length)
+static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length)
{
- size_t len_incl_bad = 0;
size_t len_excl_bad = 0;
- size_t block_len;
+ int ret = 0;
while (len_excl_bad < length) {
- block_len = nand->erasesize - (offset & (nand->erasesize - 1));
+ size_t block_len, block_off;
+ loff_t block_start;
- if (!nand_block_isbad (nand, offset & ~(nand->erasesize - 1)))
- len_excl_bad += block_len;
+ if (offset >= nand->size)
+ return -1;
- len_incl_bad += block_len;
- offset += block_len;
+ block_start = offset & ~(loff_t)(nand->erasesize - 1);
+ block_off = offset & (nand->erasesize - 1);
+ block_len = nand->erasesize - block_off;
- if (offset >= nand->size)
- break;
+ if (!nand_block_isbad(nand, block_start))
+ len_excl_bad += block_len;
+ else
+ ret = 1;
+
+ offset += block_len;
}
- return len_incl_bad;
+ return ret;
}
/**
{
int rval;
size_t left_to_write = *length;
- size_t len_incl_bad;
u_char *p_buffer = buffer;
+ int need_skip;
- /* Reject writes, which are not page aligned */
- if ((offset & (nand->writesize - 1)) != 0 ||
- (*length & (nand->writesize - 1)) != 0) {
+ /*
+ * nand_write() handles unaligned, partial page writes.
+ *
+ * We allow length to be unaligned, for convenience in
+ * using the $filesize variable.
+ *
+ * However, starting at an unaligned offset makes the
+ * semantics of bad block skipping ambiguous (really,
+ * you should only start a block skipping access at a
+ * partition boundary). So don't try to handle that.
+ */
+ if ((offset & (nand->writesize - 1)) != 0) {
printf ("Attempt to write non page aligned data\n");
+ *length = 0;
return -EINVAL;
}
- len_incl_bad = get_len_incl_bad (nand, offset, *length);
-
- if ((offset + len_incl_bad) > nand->size) {
+ need_skip = check_skip_len(nand, offset, *length);
+ if (need_skip < 0) {
printf ("Attempt to write outside the flash area\n");
+ *length = 0;
return -EINVAL;
}
- if (len_incl_bad == *length) {
+ if (!need_skip) {
rval = nand_write (nand, offset, length, buffer);
- if (rval != 0)
- printf ("NAND write to offset %llx failed %d\n",
- offset, rval);
+ if (rval == 0)
+ return 0;
+ *length = 0;
+ printf ("NAND write to offset %llx failed %d\n",
+ offset, rval);
return rval;
}
{
int rval;
size_t left_to_read = *length;
- size_t len_incl_bad;
u_char *p_buffer = buffer;
+ int need_skip;
- len_incl_bad = get_len_incl_bad (nand, offset, *length);
+ if ((offset & (nand->writesize - 1)) != 0) {
+ printf ("Attempt to read non page aligned data\n");
+ *length = 0;
+ return -EINVAL;
+ }
- if ((offset + len_incl_bad) > nand->size) {
+ need_skip = check_skip_len(nand, offset, *length);
+ if (need_skip < 0) {
printf ("Attempt to read outside the flash area\n");
+ *length = 0;
return -EINVAL;
}
- if (len_incl_bad == *length) {
+ if (!need_skip) {
rval = nand_read (nand, offset, length, buffer);
if (!rval || rval == -EUCLEAN)
return 0;
+
+ *length = 0;
printf ("NAND read from offset %llx failed %d\n",
offset, rval);
return rval;
#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;
nand->verify_buf = ndfc_verify_buf;
+
+ chip++;
#else
/*
* Setup EBC (CS0 only right now)
mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
#endif
- chip++;
-
return 0;
}
chip->IO_ADDR_W = (void *)IO_ADDR_W;
if (ctrl & NAND_NCE)
- writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
- &nand->NFCONF);
+ writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
+ &nand->nfconf);
else
- writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
- &nand->NFCONF);
+ writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
+ &nand->nfconf);
}
if (cmd != NAND_CMD_NONE)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
debugX(1, "dev_ready\n");
- return readl(&nand->NFSTAT) & 0x01;
+ return readl(&nand->nfstat) & 0x01;
}
#ifdef CONFIG_S3C2410_NAND_HWECC
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
- writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+ writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
}
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
struct s3c2410_nand *nand = s3c2410_get_base_nand();
- ecc_code[0] = readb(&nand->NFECC);
- ecc_code[1] = readb(&nand->NFECC + 1);
- ecc_code[2] = readb(&nand->NFECC + 2);
+ ecc_code[0] = readb(&nand->nfecc);
+ ecc_code[1] = readb(&nand->nfecc + 1);
+ ecc_code[2] = readb(&nand->nfecc + 2);
debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
debugX(1, "board_nand_init()\n");
- writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
/* initialize hardware */
- twrph0 = 3;
- twrph1 = 0;
- tacls = 0;
+#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
+ tacls = CONFIG_S3C24XX_TACLS;
+ twrph0 = CONFIG_S3C24XX_TWRPH0;
+ twrph1 = CONFIG_S3C24XX_TWRPH1;
+#else
+ tacls = 4;
+ twrph0 = 8;
+ twrph1 = 8;
+#endif
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
- writel(cfg, &nand_reg->NFCONF);
+ writel(cfg, &nand_reg->nfconf);
/* initialize nand_chip data structure */
- nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+ nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
+ nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
nand->select_chip = NULL;
include $(TOPDIR)/config.mk
-LIB := $(obj)libonenand.a
+LIB := $(obj)libonenand.o
COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
COBJS-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
}
static const struct onenand_manufacturers onenand_manuf_ids[] = {
+ {ONENAND_MFR_NUMONYX, "Numonyx"},
{ONENAND_MFR_SAMSUNG, "Samsung"},
};
include $(TOPDIR)/config.mk
-LIB := $(obj)libspi_flash.a
+LIB := $(obj)libspi_flash.o
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
+COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
+COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
COBJS := $(COBJS-y)
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010, ucRobotics Inc.
+ * Author: Chong Huang <chuang@ucrobotics.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+/* EN25Q128-specific commands */
+#define CMD_EN25Q128_WREN 0x06 /* Write Enable */
+#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */
+#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */
+#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */
+#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */
+#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_EN25Q128_PP 0x02 /* Page Program */
+#define CMD_EN25Q128_SE 0x20 /* Sector Erase */
+#define CMD_EN25Q128_BE 0xd8 /* Block Erase */
+#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */
+#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
+
+#define EON_ID_EN25Q128 0x18
+
+#define EON_SR_WIP (1 << 0) /* Write-in-Progress */
+
+struct eon_spi_flash_params {
+ u8 idcode1;
+ u16 page_size;
+ u16 pages_per_sector;
+ u16 sectors_per_block;
+ u16 nr_sectors;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct eon_spi_flash {
+ struct spi_flash flash;
+ const struct eon_spi_flash_params *params;
+};
+
+static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct eon_spi_flash, flash);
+}
+
+static const struct eon_spi_flash_params eon_spi_flash_table[] = {
+ {
+ .idcode1 = EON_ID_EN25Q128,
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_sectors = 4096,
+ .name = "EN25Q128",
+ },
+};
+
+static int eon_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timebase;
+ int ret;
+ u8 cmd = CMD_EN25Q128_RDSR;
+ u8 status;
+
+ ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+ if (ret) {
+ debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+ return ret;
+ }
+
+ timebase = get_timer(0);
+ do {
+ ret = spi_xfer(spi, 8, NULL, &status, 0);
+ if (ret)
+ return -1;
+
+ if ((status & EON_SR_WIP) == 0)
+ break;
+
+ } while (get_timer(timebase) < timeout);
+
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+ if ((status & EON_SR_WIP) == 0)
+ return 0;
+
+ /* Timed out */
+ return -1;
+}
+
+static int eon_read_fast(struct spi_flash *flash,
+ u32 offset, size_t len, void *buf)
+{
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long page_size;
+ u8 cmd[5];
+
+ page_size = eon->params->page_size;
+ page_addr = offset / page_size;
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = offset % page_size;
+ cmd[4] = 0x00;
+
+ return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
+static int eon_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long page_addr;
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = eon->params->page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[0] = CMD_EN25Q128_PP;
+ cmd[1] = page_addr >> 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ debug
+ ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: EON Page Program failed\n");
+ break;
+ }
+
+ ret = eon_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: EON page programming timed out\n");
+ break;
+ }
+
+ page_addr++;
+ byte_addr = 0;
+ }
+
+ debug("SF: EON: Successfully programmed %u bytes @ 0x%x\n",
+ len, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+int eon_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ /* block erase */
+ struct eon_spi_flash *eon = to_eon_spi_flash(flash);
+ unsigned long block_size;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+
+ block_size = eon->params->page_size * eon->params->pages_per_sector
+ * eon->params->sectors_per_block;
+
+ if (offset % block_size || len % block_size) {
+ debug("SF: Erase offset/length not multiple of block size\n");
+ return -1;
+ }
+
+ len /= block_size;
+ cmd[0] = CMD_EN25Q128_BE;
+ cmd[2] = 0x00;
+ cmd[3] = 0x00;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = 0;
+ for (actual = 0; actual < len; actual++) {
+ cmd[1] = (offset / block_size) + actual;
+ ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ break;
+ }
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+ if (ret < 0) {
+ debug("SF: EON page erase failed\n");
+ break;
+ }
+
+ ret = eon_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+ if (ret < 0) {
+ debug("SF: EON page erase timed out\n");
+ break;
+ }
+ }
+
+ debug("SF: EON: Successfully erased %u bytes @ 0x%x\n",
+ len * block_size, offset);
+
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode)
+{
+ const struct eon_spi_flash_params *params;
+ struct eon_spi_flash *eon;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) {
+ params = &eon_spi_flash_table[i];
+ if (params->idcode1 == idcode[2])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(eon_spi_flash_table)) {
+ debug("SF: Unsupported EON ID %02x\n", idcode[1]);
+ return NULL;
+ }
+
+ eon = malloc(sizeof(*eon));
+ if (!eon) {
+ debug("SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ eon->params = params;
+ eon->flash.spi = spi;
+ eon->flash.name = params->name;
+
+ eon->flash.write = eon_write;
+ eon->flash.erase = eon_erase;
+ eon->flash.read = eon_read_fast;
+ eon->flash.size = params->page_size * params->pages_per_sector
+ * params->nr_sectors;
+
+ debug("SF: Detected %s with page size %u, total %u bytes\n",
+ params->name, params->page_size, eon->flash.size);
+
+ return &eon->flash;
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs
+ * with an interface identical to SPI flash devices.
+ * However since they behave like RAM there are no delays or
+ * busy polls required. They can sustain read or write at the
+ * allowed SPI bus speed, which can be 40 MHz for some devices.
+ *
+ * Unfortunately some RAMTRON devices do not have a means of
+ * identifying them. They will leave the SO line undriven when
+ * the READ-ID command is issued. It is therefore mandatory
+ * that the MISO line has a proper pull-up, so that READ-ID
+ * will return a row of 0xff. This 0xff pseudo-id will cause
+ * probes by all vendor specific functions that are designed
+ * to handle it. If the MISO line is not pulled up, READ-ID
+ * could return any random noise, even mimicking another
+ * device.
+ *
+ * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
+ * to define which device will be assumed after a simple status
+ * register verify. This method is prone to false positive
+ * detection and should therefore be the last to be tried.
+ * Enter it in the last position in the table in spi_flash.c!
+ *
+ * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates
+ * compilation of the special handler and defines the device
+ * to assume.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* RAMTRON commands common to all devices */
+#define CMD_RAMTRON_WREN 0x06 /* Write Enable */
+#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */
+#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */
+#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */
+#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */
+#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */
+/* not all have those: */
+#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */
+#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */
+#define CMD_RAMTRON_RDID 0x9f /* Read ID */
+#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */
+
+/*
+ * Properties of supported FRAMs
+ * Note: speed is currently not used because we have no method to deliver that
+ * value to the upper layers
+ */
+struct ramtron_spi_fram_params {
+ u32 size; /* size in bytes */
+ u8 addr_len; /* number of address bytes */
+ u8 merge_cmd; /* some address bits are in the command byte */
+ u8 id1; /* device ID 1 (family, density) */
+ u8 id2; /* device ID 2 (sub, rev, rsvd) */
+ u32 speed; /* max. SPI clock in Hz */
+ const char *name; /* name for display and/or matching */
+};
+
+struct ramtron_spi_fram {
+ struct spi_flash flash;
+ const struct ramtron_spi_fram_params *params;
+};
+
+static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
+ *flash)
+{
+ return container_of(flash, struct ramtron_spi_fram, flash);
+}
+
+/*
+ * table describing supported FRAM chips:
+ * chips without RDID command must have the values 0xff for id1 and id2
+ */
+static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = {
+ {
+ .size = 32*1024,
+ .addr_len = 2,
+ .merge_cmd = 0,
+ .id1 = 0x22,
+ .id2 = 0x00,
+ .speed = 40000000,
+ .name = "FM25V02",
+ },
+ {
+ .size = 32*1024,
+ .addr_len = 2,
+ .merge_cmd = 0,
+ .id1 = 0x22,
+ .id2 = 0x01,
+ .speed = 40000000,
+ .name = "FM25VN02",
+ },
+ {
+ .size = 64*1024,
+ .addr_len = 2,
+ .merge_cmd = 0,
+ .id1 = 0x23,
+ .id2 = 0x00,
+ .speed = 40000000,
+ .name = "FM25V05",
+ },
+ {
+ .size = 64*1024,
+ .addr_len = 2,
+ .merge_cmd = 0,
+ .id1 = 0x23,
+ .id2 = 0x01,
+ .speed = 40000000,
+ .name = "FM25VN05",
+ },
+ {
+ .size = 128*1024,
+ .addr_len = 3,
+ .merge_cmd = 0,
+ .id1 = 0x24,
+ .id2 = 0x00,
+ .speed = 40000000,
+ .name = "FM25V10",
+ },
+ {
+ .size = 128*1024,
+ .addr_len = 3,
+ .merge_cmd = 0,
+ .id1 = 0x24,
+ .id2 = 0x01,
+ .speed = 40000000,
+ .name = "FM25VN10",
+ },
+#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
+ {
+ .size = 256*1024,
+ .addr_len = 3,
+ .merge_cmd = 0,
+ .id1 = 0xff,
+ .id2 = 0xff,
+ .speed = 40000000,
+ .name = "FM25H20",
+ },
+#endif
+};
+
+static int ramtron_common(struct spi_flash *flash,
+ u32 offset, size_t len, void *buf, u8 command)
+{
+ struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
+ u8 cmd[4];
+ int cmd_len;
+ int ret;
+
+ if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
+ cmd[0] = command;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset;
+ cmd_len = 4;
+ } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
+ cmd[0] = command;
+ cmd[1] = offset >> 8;
+ cmd[2] = offset;
+ cmd_len = 3;
+ } else {
+ printf("SF: unsupported addr_len or merge_cmd\n");
+ return -1;
+ }
+
+ /* claim the bus */
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ if (command == CMD_RAMTRON_WRITE) {
+ /* send WREN */
+ ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0);
+ if (ret < 0) {
+ debug("SF: Enabling Write failed\n");
+ goto releasebus;
+ }
+ }
+
+ /* do the transaction */
+ if (command == CMD_RAMTRON_WRITE)
+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
+ else
+ ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
+ if (ret < 0)
+ debug("SF: Transaction failed\n");
+
+releasebus:
+ /* release the bus */
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int ramtron_read(struct spi_flash *flash,
+ u32 offset, size_t len, void *buf)
+{
+ return ramtron_common(flash, offset, len, buf,
+ CMD_RAMTRON_READ);
+}
+
+static int ramtron_write(struct spi_flash *flash,
+ u32 offset, size_t len, const void *buf)
+{
+ return ramtron_common(flash, offset, len, (void *)buf,
+ CMD_RAMTRON_WRITE);
+}
+
+int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ debug("SF: Erase of RAMTRON FRAMs is pointless\n");
+ return -1;
+}
+
+/*
+ * nore: we are called here with idcode pointing to the first non-0x7f byte
+ * already!
+ */
+struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
+{
+ const struct ramtron_spi_fram_params *params;
+ struct ramtron_spi_fram *sn;
+ unsigned int i;
+#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
+ int ret;
+ u8 sr;
+#endif
+
+ /* NOTE: the bus has been claimed before this function is called! */
+ switch (idcode[0]) {
+ case 0xc2:
+ /* JEDEC conformant RAMTRON id */
+ for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
+ params = &ramtron_spi_fram_table[i];
+ if (idcode[1] == params->id1 && idcode[2] == params->id2)
+ goto found;
+ }
+ break;
+#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
+ case 0xff:
+ /*
+ * probably open MISO line, pulled up.
+ * We COULD have a non JEDEC conformant FRAM here,
+ * read the status register to verify
+ */
+ ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1);
+ if (ret)
+ return NULL;
+
+ /* Bits 5,4,0 are fixed 0 for all devices */
+ if ((sr & 0x31) != 0x00)
+ return NULL;
+ /* now find the device */
+ for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
+ params = &ramtron_spi_fram_table[i];
+ if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
+ goto found;
+ }
+ debug("SF: Unsupported non-JEDEC RAMTRON device "
+ CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n");
+ break;
+#endif
+ default:
+ break;
+ }
+
+ /* arriving here means no method has found a device we can handle */
+ debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
+ idcode[0], idcode[1], idcode[2]);
+ return NULL;
+
+found:
+ sn = malloc(sizeof(*sn));
+ if (!sn) {
+ debug("SF: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ sn->params = params;
+ sn->flash.spi = spi;
+ sn->flash.name = params->name;
+
+ sn->flash.write = ramtron_write;
+ sn->flash.read = ramtron_read;
+ sn->flash.erase = ramtron_erase;
+ sn->flash.size = params->size;
+
+ printf("SF: Detected %s with size ", params->name);
+ print_size(sn->flash.size, "\n");
+
+ return &sn->flash;
+}
#define SPSN_ID_S25FL128P 0x2018
#define SPSN_EXT_ID_S25FL128P_256KB 0x0300
#define SPSN_EXT_ID_S25FL128P_64KB 0x0301
+#define SPSN_EXT_ID_S25FL032P 0x4d00
#define SPANSION_SR_WIP (1 << 0) /* Write-in-Progress */
.nr_sectors = 64,
.name = "S25FL128P_256K",
},
+ {
+ .idcode1 = SPSN_ID_S25FL032A,
+ .idcode2 = SPSN_EXT_ID_S25FL032P,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "S25FL032P",
+ },
};
static int spansion_wait_ready(struct spi_flash *flash, unsigned long timeout)
return -1;
}
- len /= sector_size;
cmd[0] = CMD_S25FLXX_SE;
cmd[2] = 0x00;
cmd[3] = 0x00;
}
ret = 0;
- for (actual = 0; actual < len; actual++) {
- cmd[1] = (offset / sector_size) + actual;
+ for (actual = 0; actual < len; actual += sector_size) {
+ cmd[1] = (offset + actual) >> 16;
ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
if (ret < 0) {
}
debug("SF: SPANSION: Successfully erased %u bytes @ 0x%x\n",
- len * sector_size, offset);
+ len, offset);
spi_release_bus(flash->spi);
return ret;
* SPI flash interface
*
* Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ *
* Licensed under the GPL-2 or later.
*/
return ret;
}
+/*
+ * The following table holds all device probe functions
+ *
+ * shift: number of continuation bytes before the ID
+ * idcode: the expected IDCODE or 0xff for non JEDEC devices
+ * probe: the function to call
+ *
+ * Non JEDEC devices should be ordered in the table such that
+ * the probe functions with best detection algorithms come first.
+ *
+ * Several matching entries are permitted, they will be tried
+ * in sequence until a probe function returns non NULL.
+ *
+ * IDCODE_CONT_LEN may be redefined if a device needs to declare a
+ * larger "shift" value. IDCODE_PART_LEN generally shouldn't be
+ * changed. This is the max number of bytes probe functions may
+ * examine when looking up part-specific identification info.
+ *
+ * Probe functions will be given the idcode buffer starting at their
+ * manu id byte (the "idcode" in the table below). In other words,
+ * all of the continuation bytes will be skipped (the "shift" below).
+ */
+#define IDCODE_CONT_LEN 0
+#define IDCODE_PART_LEN 5
+static const struct {
+ const u8 shift;
+ const u8 idcode;
+ struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
+} flashes[] = {
+ /* Keep it sorted by define name */
+#ifdef CONFIG_SPI_FLASH_ATMEL
+ { 0, 0x1f, spi_flash_probe_atmel, },
+#endif
+#ifdef CONFIG_SPI_FLASH_EON
+ { 0, 0x1c, spi_flash_probe_eon, },
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+ { 0, 0xc2, spi_flash_probe_macronix, },
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION
+ { 0, 0x01, spi_flash_probe_spansion, },
+#endif
+#ifdef CONFIG_SPI_FLASH_SST
+ { 0, 0xbf, spi_flash_probe_sst, },
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ { 0, 0x20, spi_flash_probe_stmicro, },
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND
+ { 0, 0xef, spi_flash_probe_winbond, },
+#endif
+#ifdef CONFIG_SPI_FRAM_RAMTRON
+ { 6, 0xc2, spi_fram_probe_ramtron, },
+# undef IDCODE_CONT_LEN
+# define IDCODE_CONT_LEN 6
+#endif
+ /* Keep it sorted by best detection */
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ { 0, 0xff, spi_flash_probe_stmicro, },
+#endif
+#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
+ { 0, 0xff, spi_fram_probe_ramtron, },
+#endif
+};
+#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
- struct spi_flash *flash;
- int ret;
- u8 idcode[5];
+ struct spi_flash *flash = NULL;
+ int ret, i, shift;
+ u8 idcode[IDCODE_LEN], *idp;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
}
/* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, &idcode, sizeof(idcode));
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
if (ret)
goto err_read_id;
- debug("SF: Got idcode %02x %02x %02x %02x %02x\n", idcode[0],
- idcode[1], idcode[2], idcode[3], idcode[4]);
-
- switch (idcode[0]) {
-#ifdef CONFIG_SPI_FLASH_SPANSION
- case 0x01:
- flash = spi_flash_probe_spansion(spi, idcode);
- break;
-#endif
-#ifdef CONFIG_SPI_FLASH_ATMEL
- case 0x1F:
- flash = spi_flash_probe_atmel(spi, idcode);
- break;
+#ifdef DEBUG
+ printf("SF: Got idcodes\n");
+ print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX
- case 0xc2:
- flash = spi_flash_probe_macronix(spi, idcode);
- break;
-#endif
-#ifdef CONFIG_SPI_FLASH_WINBOND
- case 0xef:
- flash = spi_flash_probe_winbond(spi, idcode);
- break;
-#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
- case 0x20:
- case 0xff: /* Let the stmicro func handle non-JEDEC ids */
- flash = spi_flash_probe_stmicro(spi, idcode);
- break;
-#endif
-#ifdef CONFIG_SPI_FLASH_SST
- case 0xBF:
- flash = spi_flash_probe_sst(spi, idcode);
- break;
-#endif
- default:
- printf("SF: Unsupported manufacturer %02X\n", idcode[0]);
- flash = NULL;
- break;
- }
- if (!flash)
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+ shift < IDCODE_CONT_LEN && *idp == 0x7f;
+ ++shift, ++idp)
+ continue;
+
+ /* search the table for matches in shift and id */
+ for (i = 0; i < ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ if (!flash) {
+ printf("SF: Unsupported manufacturer %02x\n", *idp);
goto err_manufacturer_probe;
+ }
spi_release_bus(spi);
/* Manufacturer-specific probe functions */
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
#define CMD_W25_DP 0xb9 /* Deep Power-down */
#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
-#define WINBOND_ID_W25X16 0x3015
-#define WINBOND_ID_W25X32 0x3016
-#define WINBOND_ID_W25X64 0x3017
-
#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */
struct winbond_spi_flash_params {
uint8_t l2_page_size;
uint16_t pages_per_sector;
uint16_t sectors_per_block;
- uint8_t nr_blocks;
+ uint16_t nr_blocks;
const char *name;
};
static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
{
- .id = WINBOND_ID_W25X16,
+ .id = 0x3015,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.name = "W25X16",
},
{
- .id = WINBOND_ID_W25X32,
+ .id = 0x3016,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.name = "W25X32",
},
{
- .id = WINBOND_ID_W25X64,
+ .id = 0x3017,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
.nr_blocks = 128,
.name = "W25X64",
},
+ {
+ .id = 0x4015,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "W25Q16",
+ },
+ {
+ .id = 0x4016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "W25Q32",
+ },
+ {
+ .id = 0x4017,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25Q64",
+ },
+ {
+ .id = 0x4018,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "W25Q128",
+ },
};
static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
include $(TOPDIR)/config.mk
-LIB := $(obj)libubi.a
+LIB := $(obj)libubi.o
ifdef CONFIG_CMD_UBI
COBJS-y += build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o scan.o crc32.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libnet.a
+LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
-COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_BCM570x) += bcm570x.o
+COBJS-$(CONFIG_BCM570x) += bcm570x_autoneg.o
+COBJS-$(CONFIG_BCM570x) += 5701rls.o
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-$(CONFIG_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_ENC28J60_LPC2292) += enc28j60_lpc2292.o
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
COBJS-$(CONFIG_ETHOC) += ethoc.o
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS-$(CONFIG_SMC91111) += smc91111.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
-COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_TIGON3) += tigon3.o
+COBJS-$(CONFIG_TIGON3) += bcm570x_autoneg.o
+COBJS-$(CONFIG_TIGON3) += 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
-COBJS := $(COBJS-y)
+COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short *value)
{
+ unsigned long netstat;
at91emac_EnableMDIO(at91mac);
writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr),
&at91mac->man);
- udelay(10000);
+
+ do {
+ netstat = readl(&at91mac->sr);
+ DEBUG_AT91PHY("poll SR %08lx\n", netstat);
+ } while (!(netstat & AT91_EMAC_SR_IDLE));
+
*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
at91emac_DisableMDIO(at91mac);
int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short value)
{
+ unsigned long netstat;
DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)
at91emac_EnableMDIO(at91mac);
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
&at91mac->man);
- udelay(10000);
+
+ do {
+ netstat = readl(&at91mac->sr);
+ DEBUG_AT91PHY("poll SR %08lx\n", netstat);
+ } while (!(netstat & AT91_EMAC_SR_IDLE));
at91emac_DisableMDIO(at91mac);
+
return 0;
}
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
(BMCR_ANENABLE | BMCR_ANRESTART));
- for (i = 0; i < 100000 / 100; i++) {
+ for (i = 0; i < 30000; i++) {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
} else {
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
- return 1;
+ return -1;
}
return 0;
}
MII_PHYSID1, &phy_id);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
- return 1;
+ return -1;
}
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
if (at91emac_phy_reset(netdev))
- return 2;
+ return -2;
for (i = 0; i < 100000 / 100; i++) {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
}
if (!(status & BMSR_LSTATUS)) {
VERBOSEP("%s: link down\n", netdev->name);
- return 3;
+ return -3;
} else {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_ADVERTISE, &adv);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
- return 1;
+ return -1;
if (stat1 & BMSR_100FULL) {
/*set Emac for 100BaseTX and Full Duplex */
&emac->cfg);
return 0;
}
- return 1;
+ return 0;
}
static int at91emac_init(struct eth_device *netdev, bd_t *bd)
at91emac_UpdateLinkSpeed(emac);
return 0;
}
- return 1;
+ return -1;
}
static void at91emac_halt(struct eth_device *netdev)
iobase = AT91_EMAC_BASE;
emac = malloc(sizeof(*emac)+512);
if (emac == NULL)
- return 1;
+ return -1;
dev = malloc(sizeof(*dev));
if (dev == NULL) {
free(emac);
- return 1;
+ return -1;
}
/* alignment as per Errata (64 bytes) is insufficient! */
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
memset(emacfix, 0, sizeof(emac_device));
memset(dev, 0, sizeof(*dev));
-#ifndef CONFIG_RMII
- sprintf(dev->name, "AT91 EMAC");
-#else
- sprintf(dev->name, "AT91 EMAC RMII");
-#endif
+ sprintf(dev->name, "emac");
dev->iobase = iobase;
dev->priv = emacfix;
dev->init = at91emac_init;
goto out;
}
- if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+ if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
printf("Ethernet: tx DMA error\n");
goto out;
}
- for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+ for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
- *pDMA2_NEXT_DESC_PTR = txbuf[txIdx]->Dma;
- *pDMA2_CONFIG = txdmacfg.data;
- *pEMAC_OPMODE |= TE;
+ bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
+ bfin_write_DMA2_CONFIG(txdmacfg.data);
+ bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
NetRxPackets[rxIdx] =
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
NetReceive(NetRxPackets[rxIdx], length - 4);
- *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+ bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
size_t count;
/* Enable PHY output */
- *pVR_CTL |= CLKBUFOE;
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
/* Set all the pins to peripheral mode */
peripheral_request_list(pins, "bfin_mac");
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
/* Initialize the TX DMA channel registers */
- *pDMA2_X_COUNT = 0;
- *pDMA2_X_MODIFY = 4;
- *pDMA2_Y_COUNT = 0;
- *pDMA2_Y_MODIFY = 0;
+ bfin_write_DMA2_X_COUNT(0);
+ bfin_write_DMA2_X_MODIFY(4);
+ bfin_write_DMA2_Y_COUNT(0);
+ bfin_write_DMA2_Y_MODIFY(0);
/* Initialize the RX DMA channel registers */
- *pDMA1_X_COUNT = 0;
- *pDMA1_X_MODIFY = 4;
- *pDMA1_Y_COUNT = 0;
- *pDMA1_Y_MODIFY = 0;
+ bfin_write_DMA1_X_COUNT(0);
+ bfin_write_DMA1_X_MODIFY(4);
+ bfin_write_DMA1_Y_COUNT(0);
+ bfin_write_DMA1_Y_MODIFY(0);
return 0;
}
static int bfin_EMAC_setup_addr(struct eth_device *dev)
{
- *pEMAC_ADDRLO =
+ bfin_write_EMAC_ADDRLO(
dev->enetaddr[0] |
dev->enetaddr[1] << 8 |
dev->enetaddr[2] << 16 |
- dev->enetaddr[3] << 24;
- *pEMAC_ADDRHI =
+ dev->enetaddr[3] << 24
+ );
+ bfin_write_EMAC_ADDRHI(
dev->enetaddr[4] |
- dev->enetaddr[5] << 8;
+ dev->enetaddr[5] << 8
+ );
return 0;
}
}
/* Set RX DMA */
- *pDMA1_NEXT_DESC_PTR = rxbuf[0]->Dma;
- *pDMA1_CONFIG = rxbuf[0]->Dma[0].CONFIG_DATA;
+ bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
+ bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
/* Wait MII done */
bfin_miiphy_wait();
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
- *pEMAC_OPMODE = opmode;
+ bfin_write_EMAC_OPMODE(opmode);
return 0;
}
{
debug("Eth_halt: ......\n");
/* Turn off the EMAC */
- *pEMAC_OPMODE = 0x00000000;
+ bfin_write_EMAC_OPMODE(0);
/* Turn off the EMAC RX DMA */
- *pDMA1_CONFIG = 0x0000;
- *pDMA2_CONFIG = 0x0000;
-
+ bfin_write_DMA1_CONFIG(0);
+ bfin_write_DMA2_CONFIG(0);
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
uchar buf[64];
int i, value = 0;
int length;
+ uint addr;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
- buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
- buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
- buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
- buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
- buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
- buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+ addr = bfin_read_EMAC_ADDRLO();
+ buf[0] = buf[6] = addr;
+ buf[1] = buf[7] = addr >> 8;
+ buf[2] = buf[8] = addr >> 16;
+ buf[3] = buf[9] = addr >> 24;
+ addr = bfin_read_EMAC_ADDRHI();
+ buf[4] = buf[10] = addr;
+ buf[5] = buf[11] = addr >> 8;
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
davinci_eth_mdio_enable();
}
-static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-
-/*
- * This function must be called before emac_open() if you want to override
- * the default mac address.
- */
-void davinci_eth_set_mac_addr(const u_int8_t *addr)
-{
- int i;
-
- for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) {
- davinci_eth_mac_addr[i] = addr[i];
- }
-}
-
/* EMAC Addresses */
static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
phy_t phy;
+static int davinci_eth_set_mac_addr(struct eth_device *dev)
+{
+ unsigned long mac_hi;
+ unsigned long mac_lo;
+
+ /*
+ * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
+ * receive)
+ * Using channel 0 only - other channels are disabled
+ * */
+ writel(0, &adap_emac->MACINDEX);
+ mac_hi = (dev->enetaddr[3] << 24) |
+ (dev->enetaddr[2] << 16) |
+ (dev->enetaddr[1] << 8) |
+ (dev->enetaddr[0]);
+ mac_lo = (dev->enetaddr[5] << 8) |
+ (dev->enetaddr[4]);
+
+ writel(mac_hi, &adap_emac->MACADDRHI);
+#if defined(DAVINCI_EMAC_VERSION2)
+ writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
+ &adap_emac->MACADDRLO);
+#else
+ writel(mac_lo, &adap_emac->MACADDRLO);
+#endif
+
+ writel(0, &adap_emac->MACHASH1);
+ writel(0, &adap_emac->MACHASH2);
+
+ /* Set source MAC address - REQUIRED */
+ writel(mac_hi, &adap_emac->MACSRCADDRHI);
+ writel(mac_lo, &adap_emac->MACSRCADDRLO);
+
+
+ return 0;
+}
+
static void davinci_eth_mdio_enable(void)
{
u_int32_t clkdiv;
{
u_int16_t tmp;
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
+ (tmp & 0x04)) {
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ davinci_eth_phy_read(phy_addr, PHY_ANLPAR, &tmp);
+
+ /* Speed doesn't matter, there is no setting for it in EMAC. */
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_10FD)) {
+ /* set EMAC for Full Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
+ &adap_emac->MACCONTROL);
+ } else {
+ /*set EMAC for Half Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE,
+ &adap_emac->MACCONTROL);
+ }
+
+ if (tmp & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+ else
+ writel(readl(&adap_emac->MACCONTROL) &
+ ~EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+#endif
return(1);
+ }
return(0);
}
dv_reg_p addr;
u_int32_t clkdiv, cnt;
volatile emac_desc *rx_desc;
- unsigned long mac_hi;
- unsigned long mac_lo;
debug_emac("+ emac_open\n");
}
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
rx_desc = emac_rx_desc;
writel(1, &adap_emac->TXCONTROL);
writel(1, &adap_emac->RXCONTROL);
- /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
- /* Using channel 0 only - other channels are disabled */
- writel(0, &adap_emac->MACINDEX);
- mac_hi = (davinci_eth_mac_addr[3] << 24) |
- (davinci_eth_mac_addr[2] << 16) |
- (davinci_eth_mac_addr[1] << 8) |
- (davinci_eth_mac_addr[0]);
- mac_lo = (davinci_eth_mac_addr[5] << 8) |
- (davinci_eth_mac_addr[4]);
-
- writel(mac_hi, &adap_emac->MACADDRHI);
-#if defined(DAVINCI_EMAC_VERSION2)
- writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
- &adap_emac->MACADDRLO);
-#else
- writel(mac_lo, &adap_emac->MACADDRLO);
-#endif
-
- writel(0, &adap_emac->MACHASH1);
- writel(0, &adap_emac->MACHASH2);
-
- /* Set source MAC address - REQUIRED */
- writel(mac_hi, &adap_emac->MACSRCADDRHI);
- writel(mac_lo, &adap_emac->MACSRCADDRLO);
+ davinci_eth_set_mac_addr(dev);
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
addr = &adap_emac->TX0HDP;
writel(0, &adap_ewrap->EWCTL);
#endif
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
debug_emac("- emac_close\n");
}
dev->halt = davinci_eth_close;
dev->send = davinci_eth_send_packet;
dev->recv = davinci_eth_rcv_packet;
+ dev->write_hwaddr = davinci_eth_set_mac_addr;
eth_register(dev);
dev = (struct eth_device*) malloc(sizeof *dev);
+ if (!dev) {
+ printf("Can not allocalte memory of dc21x4x\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
+
#ifdef CONFIG_TULIP_FIX_DAVICOM
sprintf(dev->name, "Davicom#%d", card_number);
#else
static int
e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
{
+ void * nv_packet = (void *)packet;
struct e1000_hw *hw = nic->priv;
struct e1000_tx_desc *txp;
int i = 0;
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8;
- txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet));
+ txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;
E1000_WRITE_REG(hw, TDT, tx_tail);
}
nic = (struct eth_device *) malloc(sizeof (*nic));
+ if (!nic) {
+ printf("Error: e1000 - Can not alloc memory\n");
+ return 0;
+ }
+
hw = (struct e1000_hw *) malloc(sizeof (*hw));
+ if (!hw) {
+ free(nic);
+ printf("Error: e1000 - Can not alloc memory\n");
+ return 0;
+ }
+
+ memset(nic, 0, sizeof(*nic));
+ memset(hw, 0, sizeof(*hw));
+
hw->pdev = devno;
nic->priv = hw;
}
dev = (struct eth_device *) malloc (sizeof *dev);
+ if (!dev) {
+ printf("eepro100: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "i82559#%d", card_number);
dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ * Martin Krause, Martin.Krause@tqs.de
+ * reworked original enc28j60.c
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#include <config.h>
#include <common.h>
#include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-/*
- * Control Registers in Bank 0
- */
-
-#define CTL_REG_ERDPTL 0x00
-#define CTL_REG_ERDPTH 0x01
-#define CTL_REG_EWRPTL 0x02
-#define CTL_REG_EWRPTH 0x03
-#define CTL_REG_ETXSTL 0x04
-#define CTL_REG_ETXSTH 0x05
-#define CTL_REG_ETXNDL 0x06
-#define CTL_REG_ETXNDH 0x07
-#define CTL_REG_ERXSTL 0x08
-#define CTL_REG_ERXSTH 0x09
-#define CTL_REG_ERXNDL 0x0A
-#define CTL_REG_ERXNDH 0x0B
-#define CTL_REG_ERXRDPTL 0x0C
-#define CTL_REG_ERXRDPTH 0x0D
-#define CTL_REG_ERXWRPTL 0x0E
-#define CTL_REG_ERXWRPTH 0x0F
-#define CTL_REG_EDMASTL 0x10
-#define CTL_REG_EDMASTH 0x11
-#define CTL_REG_EDMANDL 0x12
-#define CTL_REG_EDMANDH 0x13
-#define CTL_REG_EDMADSTL 0x14
-#define CTL_REG_EDMADSTH 0x15
-#define CTL_REG_EDMACSL 0x16
-#define CTL_REG_EDMACSH 0x17
-/* these are common in all banks */
-#define CTL_REG_EIE 0x1B
-#define CTL_REG_EIR 0x1C
-#define CTL_REG_ESTAT 0x1D
-#define CTL_REG_ECON2 0x1E
-#define CTL_REG_ECON1 0x1F
-
-/*
- * Control Registers in Bank 1
- */
-
-#define CTL_REG_EHT0 0x00
-#define CTL_REG_EHT1 0x01
-#define CTL_REG_EHT2 0x02
-#define CTL_REG_EHT3 0x03
-#define CTL_REG_EHT4 0x04
-#define CTL_REG_EHT5 0x05
-#define CTL_REG_EHT6 0x06
-#define CTL_REG_EHT7 0x07
-#define CTL_REG_EPMM0 0x08
-#define CTL_REG_EPMM1 0x09
-#define CTL_REG_EPMM2 0x0A
-#define CTL_REG_EPMM3 0x0B
-#define CTL_REG_EPMM4 0x0C
-#define CTL_REG_EPMM5 0x0D
-#define CTL_REG_EPMM6 0x0E
-#define CTL_REG_EPMM7 0x0F
-#define CTL_REG_EPMCSL 0x10
-#define CTL_REG_EPMCSH 0x11
-#define CTL_REG_EPMOL 0x14
-#define CTL_REG_EPMOH 0x15
-#define CTL_REG_EWOLIE 0x16
-#define CTL_REG_EWOLIR 0x17
-#define CTL_REG_ERXFCON 0x18
-#define CTL_REG_EPKTCNT 0x19
-
-/*
- * Control Registers in Bank 2
- */
-
-#define CTL_REG_MACON1 0x00
-#define CTL_REG_MACON2 0x01
-#define CTL_REG_MACON3 0x02
-#define CTL_REG_MACON4 0x03
-#define CTL_REG_MABBIPG 0x04
-#define CTL_REG_MAIPGL 0x06
-#define CTL_REG_MAIPGH 0x07
-#define CTL_REG_MACLCON1 0x08
-#define CTL_REG_MACLCON2 0x09
-#define CTL_REG_MAMXFLL 0x0A
-#define CTL_REG_MAMXFLH 0x0B
-#define CTL_REG_MAPHSUP 0x0D
-#define CTL_REG_MICON 0x11
-#define CTL_REG_MICMD 0x12
-#define CTL_REG_MIREGADR 0x14
-#define CTL_REG_MIWRL 0x16
-#define CTL_REG_MIWRH 0x17
-#define CTL_REG_MIRDL 0x18
-#define CTL_REG_MIRDH 0x19
-
-/*
- * Control Registers in Bank 3
- */
-
-#define CTL_REG_MAADR1 0x00
-#define CTL_REG_MAADR0 0x01
-#define CTL_REG_MAADR3 0x02
-#define CTL_REG_MAADR2 0x03
-#define CTL_REG_MAADR5 0x04
-#define CTL_REG_MAADR4 0x05
-#define CTL_REG_EBSTSD 0x06
-#define CTL_REG_EBSTCON 0x07
-#define CTL_REG_EBSTCSL 0x08
-#define CTL_REG_EBSTCSH 0x09
-#define CTL_REG_MISTAT 0x0A
-#define CTL_REG_EREVID 0x12
-#define CTL_REG_ECOCON 0x15
-#define CTL_REG_EFLOCON 0x17
-#define CTL_REG_EPAUSL 0x18
-#define CTL_REG_EPAUSH 0x19
-
-
-/*
- * PHY Register
- */
-
-#define PHY_REG_PHID1 0x02
-#define PHY_REG_PHID2 0x03
-/* taken from the Linux driver */
-#define PHY_REG_PHCON1 0x00
-#define PHY_REG_PHCON2 0x10
-#define PHY_REG_PHLCON 0x14
-
-/*
- * Receive Filter Register (ERXFCON) bits
- */
-
-#define ENC_RFR_UCEN 0x80
-#define ENC_RFR_ANDOR 0x40
-#define ENC_RFR_CRCEN 0x20
-#define ENC_RFR_PMEN 0x10
-#define ENC_RFR_MPEN 0x08
-#define ENC_RFR_HTEN 0x04
-#define ENC_RFR_MCEN 0x02
-#define ENC_RFR_BCEN 0x01
+#include <spi.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include "enc28j60.h"
/*
- * ECON1 Register Bits
+ * IMPORTANT: spi_claim_bus() and spi_release_bus()
+ * are called at begin and end of each of the following functions:
+ * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
+ * enc_init(), enc_recv(), enc_send(), enc_halt()
+ * ALL other functions assume that the bus has already been claimed!
+ * Since NetReceive() might call enc_send() in return, the bus must be
+ * released, NetReceive() called and claimed again.
*/
-#define ENC_ECON1_TXRST 0x80
-#define ENC_ECON1_RXRST 0x40
-#define ENC_ECON1_DMAST 0x20
-#define ENC_ECON1_CSUMEN 0x10
-#define ENC_ECON1_TXRTS 0x08
-#define ENC_ECON1_RXEN 0x04
-#define ENC_ECON1_BSEL1 0x02
-#define ENC_ECON1_BSEL0 0x01
-
/*
- * ECON2 Register Bits
+ * Controller memory layout.
+ * We only allow 1 frame for transmission and reserve the rest
+ * for reception to handle as many broadcast packets as possible.
+ * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
+ * 0x0000 - 0x19ff 6656 bytes receive buffer
+ * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
+ * control(1)+frame(1518)+status(7)+reserve(10).
*/
-#define ENC_ECON2_AUTOINC 0x80
-#define ENC_ECON2_PKTDEC 0x40
-#define ENC_ECON2_PWRSV 0x20
-#define ENC_ECON2_VRPS 0x08
+#define ENC_RX_BUF_START 0x0000
+#define ENC_RX_BUF_END 0x19ff
+#define ENC_TX_BUF_START 0x1a00
+#define ENC_TX_BUF_END 0x1fff
+#define ENC_MAX_FRM_LEN 1518
+#define RX_RESET_COUNTER 1000
/*
- * EIR Register Bits
+ * For non data transfer functions, like phy read/write, set hwaddr, init
+ * we do not need a full, time consuming init including link ready wait.
+ * This enum helps to bring the chip through the minimum necessary inits.
*/
-#define ENC_EIR_PKTIF 0x40
-#define ENC_EIR_DMAIF 0x20
-#define ENC_EIR_LINKIF 0x10
-#define ENC_EIR_TXIF 0x08
-#define ENC_EIR_WOLIF 0x04
-#define ENC_EIR_TXERIF 0x02
-#define ENC_EIR_RXERIF 0x01
+enum enc_initstate {none=0, setupdone, linkready};
+typedef struct enc_device {
+ struct eth_device *dev; /* back pointer */
+ struct spi_slave *slave;
+ int rx_reset_counter;
+ u16 next_pointer;
+ u8 bank; /* current bank in enc28j60 */
+ enum enc_initstate initstate;
+} enc_dev_t;
/*
- * ESTAT Register Bits
+ * enc_bset: set bits in a common register
+ * enc_bclr: clear bits in a common register
+ *
+ * making the reg parameter u8 will give a compile time warning if the
+ * functions are called with a register not accessible in all Banks
*/
+static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+ u8 dout[2];
-#define ENC_ESTAT_INT 0x80
-#define ENC_ESTAT_LATECOL 0x10
-#define ENC_ESTAT_RXBUSY 0x04
-#define ENC_ESTAT_TXABRT 0x02
-#define ENC_ESTAT_CLKRDY 0x01
+ dout[0] = CMD_BFS(reg);
+ dout[1] = data;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+}
-/*
- * EIE Register Bits
- */
+static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+ u8 dout[2];
-#define ENC_EIE_INTIE 0x80
-#define ENC_EIE_PKTIE 0x40
-#define ENC_EIE_DMAIE 0x20
-#define ENC_EIE_LINKIE 0x10
-#define ENC_EIE_TXIE 0x08
-#define ENC_EIE_WOLIE 0x04
-#define ENC_EIE_TXERIE 0x02
-#define ENC_EIE_RXERIE 0x01
+ dout[0] = CMD_BFC(reg);
+ dout[1] = data;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+}
/*
- * MACON1 Register Bits
+ * high byte of the register contains bank number:
+ * 0: no bank switch necessary
+ * 1: switch to bank 0
+ * 2: switch to bank 1
+ * 3: switch to bank 2
+ * 4: switch to bank 3
*/
-#define ENC_MACON1_LOOPBK 0x10
-#define ENC_MACON1_TXPAUS 0x08
-#define ENC_MACON1_RXPAUS 0x04
-#define ENC_MACON1_PASSALL 0x02
-#define ENC_MACON1_MARXEN 0x01
-
+static void enc_set_bank(enc_dev_t *enc, const u16 reg)
+{
+ u8 newbank = reg >> 8;
+
+ if (newbank == 0 || newbank == enc->bank)
+ return;
+ switch (newbank) {
+ case 1:
+ enc_bclr(enc, CTL_REG_ECON1,
+ ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+ break;
+ case 2:
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ break;
+ case 3:
+ enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ break;
+ case 4:
+ enc_bset(enc, CTL_REG_ECON1,
+ ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+ break;
+ }
+ enc->bank = newbank;
+}
/*
- * MACON2 Register Bits
+ * local functions to access SPI
+ *
+ * reg: register inside ENC28J60
+ * data: 8/16 bits to write
+ * c: number of retries
+ *
+ * enc_r8: read 8 bits
+ * enc_r16: read 16 bits
+ * enc_w8: write 8 bits
+ * enc_w16: write 16 bits
+ * enc_w8_retry: write 8 bits, verify and retry
+ * enc_rbuf: read from ENC28J60 into buffer
+ * enc_wbuf: write from buffer into ENC28J60
*/
-#define ENC_MACON2_MARST 0x80
-#define ENC_MACON2_RNDRST 0x40
-#define ENC_MACON2_MARXRST 0x08
-#define ENC_MACON2_RFUNRST 0x04
-#define ENC_MACON2_MATXRST 0x02
-#define ENC_MACON2_TFUNRST 0x01
/*
- * MACON3 Register Bits
+ * MAC and MII registers need a 3 byte SPI transfer to read,
+ * all other registers need a 2 byte SPI transfer.
*/
-#define ENC_MACON3_PADCFG2 0x80
-#define ENC_MACON3_PADCFG1 0x40
-#define ENC_MACON3_PADCFG0 0x20
-#define ENC_MACON3_TXCRCEN 0x10
-#define ENC_MACON3_PHDRLEN 0x08
-#define ENC_MACON3_HFRMEN 0x04
-#define ENC_MACON3_FRMLNEN 0x02
-#define ENC_MACON3_FULDPX 0x01
+static int enc_reg2nbytes(const u16 reg)
+{
+ /* check if MAC or MII register */
+ return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
+ (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
+ (reg == CTL_REG_MISTAT)) ? 3 : 2;
+}
/*
- * MICMD Register Bits
+ * Read a byte register
*/
-#define ENC_MICMD_MIISCAN 0x02
-#define ENC_MICMD_MIIRD 0x01
+static u8 enc_r8(enc_dev_t *enc, const u16 reg)
+{
+ u8 dout[3];
+ u8 din[3];
+ int nbytes = enc_reg2nbytes(reg);
+
+ enc_set_bank(enc, reg);
+ dout[0] = CMD_RCR(reg);
+ spi_xfer(enc->slave, nbytes * 8, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ return din[nbytes-1];
+}
/*
- * MISTAT Register Bits
+ * Read a L/H register pair and return a word.
+ * Must be called with the L register's address.
*/
-#define ENC_MISTAT_NVALID 0x04
-#define ENC_MISTAT_SCAN 0x02
-#define ENC_MISTAT_BUSY 0x01
+static u16 enc_r16(enc_dev_t *enc, const u16 reg)
+{
+ u8 dout[3];
+ u8 din[3];
+ u16 result;
+ int nbytes = enc_reg2nbytes(reg);
+
+ enc_set_bank(enc, reg);
+ dout[0] = CMD_RCR(reg);
+ spi_xfer(enc->slave, nbytes * 8, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ result = din[nbytes-1];
+ dout[0]++; /* next register */
+ spi_xfer(enc->slave, nbytes * 8, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ result |= din[nbytes-1] << 8;
+ return result;
+}
/*
- * PHID1 and PHID2 values
+ * Write a byte register
*/
-#define ENC_PHID1_VALUE 0x0083
-#define ENC_PHID2_VALUE 0x1400
-#define ENC_PHID2_MASK 0xFC00
-
-
-#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
-#define ENC_RESET 0x00020000 /* pin P1.17 */
+static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
+{
+ u8 dout[2];
-#define FAILSAFE_VALUE 5000
+ enc_set_bank(enc, reg);
+ dout[0] = CMD_WCR(reg);
+ dout[1] = data;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+}
/*
- * Controller memory layout:
- *
- * 0x0000 - 0x17ff 6k bytes receive buffer
- * 0x1800 - 0x1fff 2k bytes transmit buffer
- */
-/* Use the lower memory for receiver buffer. See errata pt. 5 */
-#define ENC_RX_BUF_START 0x0000
-#define ENC_TX_BUF_START 0x1800
-/* taken from the Linux driver */
-#define ENC_RX_BUF_END 0x17ff
-#define ENC_TX_BUF_END 0x1fff
-
-/* maximum frame length */
-#define ENC_MAX_FRM_LEN 1518
-
-#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
-#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
-#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
-
-
-static unsigned char encReadReg (unsigned char regNo);
-static void encWriteReg (unsigned char regNo, unsigned char data);
-static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
-static void encReadBuff (unsigned short length, unsigned char *pBuff);
-static void encWriteBuff (unsigned short length, unsigned char *pBuff);
-static void encBitSet (unsigned char regNo, unsigned char data);
-static void encBitClr (unsigned char regNo, unsigned char data);
-static void encReset (void);
-static void encInit (unsigned char *pEthAddr);
-static unsigned short phyRead (unsigned char addr);
-static void phyWrite(unsigned char, unsigned short);
-static void encPoll (void);
-static void encRx (void);
-
-#define m_nic_read(reg) encReadReg(reg)
-#define m_nic_write(reg, data) encWriteReg(reg, data)
-#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
-#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
-#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
-
-/* bit field set */
-#define m_nic_bfs(reg, data) encBitSet(reg, data)
-
-/* bit field clear */
-#define m_nic_bfc(reg, data) encBitClr(reg, data)
-
-static unsigned char bank = 0; /* current bank in enc28j60 */
-static unsigned char next_pointer_lsb;
-static unsigned char next_pointer_msb;
-
-static unsigned char buffer[ENC_MAX_FRM_LEN];
-static int rxResetCounter = 0;
-
-#define RX_RESET_COUNTER 1000;
-
-/*-----------------------------------------------------------------------------
- * Always returns 0
+ * Write a L/H register pair.
+ * Must be called with the L register's address.
*/
-int eth_init (bd_t * bis)
+static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
{
- unsigned char estatVal;
- uchar enetaddr[6];
-
- /* configure GPIO */
- (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
- (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
-
- /* CS and RESET active low */
- PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
- PUT32 (IO1SET, ENC_RESET);
-
- spi_init ();
-
- /* taken from the Linux driver - dangerous stuff here! */
- /* Wait for CLKRDY to become set (i.e., check that we can communicate with
- the ENC) */
- do
- {
- estatVal = m_nic_read(CTL_REG_ESTAT);
- } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
-
- /* initialize controller */
- encReset ();
- eth_getenv_enetaddr("ethaddr", enetaddr);
- encInit (enetaddr);
-
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
-
- return 0;
+ u8 dout[2];
+
+ enc_set_bank(enc, reg);
+ dout[0] = CMD_WCR(reg);
+ dout[1] = data;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ dout[0]++; /* next register */
+ dout[1] = data >> 8;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
}
-int eth_send (volatile void *packet, int length)
+/*
+ * Write a byte register, verify and retry
+ */
+static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
{
- /* check frame length, etc. */
- /* TODO: */
-
- /* switch to bank 0 */
- m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
- /* set EWRPT */
- m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
- m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
-
- /* set ETXND */
- m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
- m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
-
- /* set ETXST */
- m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
- m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
-
- /* write packet */
- m_nic_write_data (length, (unsigned char *) packet);
+ u8 dout[2];
+ u8 readback;
+ int i;
- /* taken from the Linux driver */
- /* Verify that the internal transmit logic has not been altered by excessive
- collisions. See Errata B4 12 and 14.
- */
- if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
- m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
+ enc_set_bank(enc, reg);
+ for (i = 0; i < c; i++) {
+ dout[0] = CMD_WCR(reg);
+ dout[1] = data;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ readback = enc_r8(enc, reg);
+ if (readback == data)
+ break;
+ /* wait 1ms */
+ udelay(1000);
+ }
+ if (i == c) {
+ printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
}
- m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
-
- /* set ECON1.TXRTS */
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
-
- return 0;
}
-
-/*****************************************************************************
- * This function resets the receiver only. This function may be called from
- * interrupt-context.
+/*
+ * Read ENC RAM into buffer
*/
-static void encReceiverReset (void)
+static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
{
- unsigned char econ1;
-
- econ1 = m_nic_read (CTL_REG_ECON1);
- if ((econ1 & ENC_ECON1_RXRST) == 0) {
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
- rxResetCounter = RX_RESET_COUNTER;
- }
+ u8 dout[1];
+
+ dout[0] = CMD_RBM;
+ spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
+ spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
+#ifdef DEBUG
+ puts("Rx:\n");
+ print_buffer(0, buf, 1, length, 0);
+#endif
}
-/*****************************************************************************
- * receiver reset timer
+/*
+ * Write buffer into ENC RAM
*/
-static void encReceiverResetCallback (void)
+static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
{
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
+ u8 dout[2];
+ dout[0] = CMD_WBM;
+ dout[1] = control;
+ spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
+ spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
+#ifdef DEBUG
+ puts("Tx:\n");
+ print_buffer(0, buf, 1, length, 0);
+#endif
}
-/*-----------------------------------------------------------------------------
- * Check for received packets. Call NetReceive for each packet. The return
- * value is ignored by the caller.
+/*
+ * Try to claim the SPI bus.
+ * Print error message on failure.
*/
-int eth_rx (void)
+static int enc_claim_bus(enc_dev_t *enc)
{
- if (rxResetCounter > 0 && --rxResetCounter == 0) {
- encReceiverResetCallback ();
- }
-
- encPoll ();
-
- return 0;
+ int rc = spi_claim_bus(enc->slave);
+ if (rc)
+ printf("%s: failed to claim SPI bus\n", enc->dev->name);
+ return rc;
}
-void eth_halt (void)
+/*
+ * Release previously claimed SPI bus.
+ * This function is mainly for symmetry to enc_claim_bus().
+ * Let the toolchain decide to inline it...
+ */
+static void enc_release_bus(enc_dev_t *enc)
{
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
+ spi_release_bus(enc->slave);
}
-/*****************************************************************************/
-
-static void encPoll (void)
+/*
+ * Read PHY register
+ */
+static u16 phy_read(enc_dev_t *enc, const u8 addr)
{
- unsigned char eir_reg;
- volatile unsigned char estat_reg;
- unsigned char pkt_cnt;
+ uint64_t etime;
+ u8 status;
-#ifdef CONFIG_USE_IRQ
- /* clear global interrupt enable bit in enc28j60 */
- m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
- estat_reg = m_nic_read (CTL_REG_ESTAT);
-
- eir_reg = m_nic_read (CTL_REG_EIR);
-
- if (eir_reg & ENC_EIR_TXIF) {
- /* clear TXIF bit in EIR */
- m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
+ enc_w8(enc, CTL_REG_MIREGADR, addr);
+ enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
+ /* 1 second timeout - only happens on hardware problem */
+ etime = get_ticks() + get_tbclk();
+ /* poll MISTAT.BUSY bit until operation is complete */
+ do
+ {
+ status = enc_r8(enc, CTL_REG_MISTAT);
+ } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+ if (status & ENC_MISTAT_BUSY) {
+ printf("%s: timeout reading phy\n", enc->dev->name);
+ return 0;
}
+ enc_w8(enc, CTL_REG_MICMD, 0);
+ return enc_r16(enc, CTL_REG_MIRDL);
+}
- /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+/*
+ * Write PHY register
+ */
+static void phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
+{
+ uint64_t etime;
+ u8 status;
- /* move to bank 1 */
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ enc_w8(enc, CTL_REG_MIREGADR, addr);
+ enc_w16(enc, CTL_REG_MIWRL, data);
+ /* 1 second timeout - only happens on hardware problem */
+ etime = get_ticks() + get_tbclk();
+ /* poll MISTAT.BUSY bit until operation is complete */
+ do
+ {
+ status = enc_r8(enc, CTL_REG_MISTAT);
+ } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+ if (status & ENC_MISTAT_BUSY) {
+ printf("%s: timeout writing phy\n", enc->dev->name);
+ return;
+ }
+}
- /* read pktcnt */
- pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+/*
+ * Verify link status, wait if necessary
+ *
+ * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
+ * half/full duplex is a pure setup matter. For the time being, this driver
+ * will setup in half duplex mode only.
+ */
+static int enc_phy_link_wait(enc_dev_t *enc)
+{
+ u16 status;
+ int duplex;
+ uint64_t etime;
+
+#ifdef CONFIG_ENC_SILENTLINK
+ /* check if we have a link, then just return */
+ status = phy_read(enc, PHY_REG_PHSTAT1);
+ if (status & ENC_PHSTAT1_LLSTAT)
+ return 0;
+#endif
- if (pkt_cnt > 0) {
- if ((eir_reg & ENC_EIR_PKTIF) == 0) {
- /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
+ /* wait for link with 1 second timeout */
+ etime = get_ticks() + get_tbclk();
+ while (get_ticks() <= etime) {
+ status = phy_read(enc, PHY_REG_PHSTAT1);
+ if (status & ENC_PHSTAT1_LLSTAT) {
+ /* now we have a link */
+ status = phy_read(enc, PHY_REG_PHSTAT2);
+ duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
+ printf("%s: link up, 10Mbps %s-duplex\n",
+ enc->dev->name, duplex ? "full" : "half");
+ return 0;
}
- encRx ();
- /* clear PKTIF bit in EIR, this should not need to be done but it
- seems like we get problems if we do not */
- m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
+ udelay(1000);
}
- if (eir_reg & ENC_EIR_RXERIF) {
- printf ("encPoll: rx error\n");
- m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
- }
- if (eir_reg & ENC_EIR_TXERIF) {
- printf ("encPoll: tx error\n");
- m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
- }
-
-#ifdef CONFIG_USE_IRQ
- /* set global interrupt enable bit in enc28j60 */
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
+ /* timeout occured */
+ printf("%s: link down\n", enc->dev->name);
+ return 1;
}
-static void encRx (void)
+/*
+ * This function resets the receiver only.
+ */
+static void enc_reset_rx(enc_dev_t *enc)
{
- unsigned short pkt_len;
- unsigned short copy_len;
- unsigned short status;
- unsigned char eir_reg;
- unsigned char pkt_cnt = 0;
- unsigned short rxbuf_rdpt;
+ u8 econ1;
- /* switch to bank 0 */
- m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+ econ1 = enc_r8(enc, CTL_REG_ECON1);
+ if ((econ1 & ENC_ECON1_RXRST) == 0) {
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+ enc->rx_reset_counter = RX_RESET_COUNTER;
+ }
+}
- m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
- m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+/*
+ * Reset receiver and reenable it.
+ */
+static void enc_reset_rx_call(enc_dev_t *enc)
+{
+ enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+}
+/*
+ * Copy a packet from the receive ring and forward it to
+ * the protocol stack.
+ */
+static void enc_receive(enc_dev_t *enc)
+{
+ u8 *packet = (u8 *)NetRxPackets[0];
+ u16 pkt_len;
+ u16 copy_len;
+ u16 status;
+ u8 eir_reg;
+ u8 pkt_cnt = 0;
+ u16 rxbuf_rdpt;
+ u8 hbuf[6];
+
+ enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
do {
- m_nic_read_data (6, buffer);
- next_pointer_lsb = buffer[0];
- next_pointer_msb = buffer[1];
- pkt_len = buffer[2];
- pkt_len |= (unsigned short) buffer[3] << 8;
- status = buffer[4];
- status |= (unsigned short) buffer[5] << 8;
-
+ enc_rbuf(enc, 6, hbuf);
+ enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
+ pkt_len = hbuf[2] | (hbuf[3] << 8);
+ status = hbuf[4] | (hbuf[5] << 8);
+ debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
+ enc->next_pointer, pkt_len, status);
if (pkt_len <= ENC_MAX_FRM_LEN)
copy_len = pkt_len;
else
copy_len = 0;
-
if ((status & (1L << 7)) == 0) /* check Received Ok bit */
copy_len = 0;
-
- /* taken from the Linux driver */
/* check if next pointer is resonable */
- if ((((unsigned int)next_pointer_msb << 8) |
- (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
+ if (enc->next_pointer >= ENC_TX_BUF_START)
copy_len = 0;
-
if (copy_len > 0) {
- m_nic_read_data (copy_len, buffer);
+ enc_rbuf(enc, copy_len, packet);
}
-
/* advance read pointer to next pointer */
- m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
- m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
-
+ enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
/* decrease packet counter */
- m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
-
- /* taken from the Linux driver */
- /* Only odd values should be written to ERXRDPTL,
+ enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
+ /*
+ * Only odd values should be written to ERXRDPTL,
* see errata B4 pt.13
*/
- rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
- if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
- m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
- (m_nic_read(CTL_REG_ERXNDH) << 8 |
- m_nic_read(CTL_REG_ERXNDL)))) {
- m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
- m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
+ rxbuf_rdpt = enc->next_pointer - 1;
+ if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
+ (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
+ enc_w16(enc, CTL_REG_ERXRDPTL,
+ enc_r16(enc, CTL_REG_ERXNDL));
} else {
- m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
- m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
+ enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
}
-
- /* move to bank 1 */
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
-
/* read pktcnt */
- pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
-
- /* switch to bank 0 */
- m_nic_bfc (CTL_REG_ECON1,
- (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
+ pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
if (copy_len == 0) {
- eir_reg = m_nic_read (CTL_REG_EIR);
- encReceiverReset ();
- printf ("eth_rx: copy_len=0\n");
+ eir_reg = enc_r8(enc, CTL_REG_EIR);
+ enc_reset_rx(enc);
+ printf("%s: receive copy_len=0\n", enc->dev->name);
continue;
}
-
- NetReceive ((unsigned char *) buffer, pkt_len);
-
- eir_reg = m_nic_read (CTL_REG_EIR);
- } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
-}
-
-static void encWriteReg (unsigned char regNo, unsigned char data)
-{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x40 | regNo); /* write in regNo */
- spi_write (data);
-
- enc_disable ();
- enc_enable ();
-
- spi_write (0x1f); /* write reg 0x1f */
-
- enc_disable ();
- spi_unlock ();
+ /*
+ * Because NetReceive() might call enc_send(), we need to
+ * release the SPI bus, call NetReceive(), reclaim the bus
+ */
+ enc_release_bus(enc);
+ NetReceive(packet, pkt_len);
+ if (enc_claim_bus(enc))
+ return;
+ eir_reg = enc_r8(enc, CTL_REG_EIR);
+ } while (pkt_cnt);
+ /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
}
-static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
+/*
+ * Poll for completely received packets.
+ */
+static void enc_poll(enc_dev_t *enc)
{
- unsigned char readback;
- int i;
-
- spi_lock ();
+ u8 eir_reg;
+ u8 estat_reg;
+ u8 pkt_cnt;
- for (i = 0; i < c; i++) {
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x40 | regNo); /* write in regNo */
- spi_write (data);
-
- enc_disable ();
- enc_enable ();
-
- spi_write (0x1f); /* write reg 0x1f */
-
- enc_disable ();
-
- spi_unlock (); /* we must unlock spi first */
-
- readback = encReadReg (regNo);
-
- spi_lock ();
-
- if (readback == data)
- break;
+#ifdef CONFIG_USE_IRQ
+ /* clear global interrupt enable bit in enc28j60 */
+ enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+ estat_reg = enc_r8(enc, CTL_REG_ESTAT);
+ eir_reg = enc_r8(enc, CTL_REG_EIR);
+ if (eir_reg & ENC_EIR_TXIF) {
+ /* clear TXIF bit in EIR */
+ enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
}
- spi_unlock ();
-
- if (i == c) {
- printf ("enc28j60: write reg %d failed\n", regNo);
+ /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+ pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
+ if (pkt_cnt > 0) {
+ if ((eir_reg & ENC_EIR_PKTIF) == 0) {
+ debug("enc_poll: pkt cnt > 0, but pktif not set\n");
+ }
+ enc_receive(enc);
+ /*
+ * clear PKTIF bit in EIR, this should not need to be done
+ * but it seems like we get problems if we do not
+ */
+ enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
}
-}
-
-static unsigned char encReadReg (unsigned char regNo)
-{
- unsigned char rxByte;
-
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x1f); /* read reg 0x1f */
-
- bank = spi_read () & 0x3;
-
- enc_disable ();
- enc_enable ();
-
- spi_write (regNo);
- rxByte = spi_read ();
-
- /* check if MAC or MII register */
- if (((bank == 2) && (regNo <= 0x1a)) ||
- ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
- /* ignore first byte and read another byte */
- rxByte = spi_read ();
+ if (eir_reg & ENC_EIR_RXERIF) {
+ printf("%s: rx error\n", enc->dev->name);
+ enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
}
-
- enc_disable ();
- spi_unlock ();
-
- return rxByte;
-}
-
-static void encReadBuff (unsigned short length, unsigned char *pBuff)
-{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x20 | 0x1a); /* read buffer memory */
-
- while (length--) {
- if (pBuff != NULL)
- *pBuff++ = spi_read ();
- else
- spi_write (0);
+ if (eir_reg & ENC_EIR_TXERIF) {
+ printf("%s: tx error\n", enc->dev->name);
+ enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
}
-
- enc_disable ();
- spi_unlock ();
-}
-
-static void encWriteBuff (unsigned short length, unsigned char *pBuff)
-{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x60 | 0x1a); /* write buffer memory */
-
- spi_write (0x00); /* control byte */
-
- while (length--)
- spi_write (*pBuff++);
-
- enc_disable ();
- spi_unlock ();
-}
-
-static void encBitSet (unsigned char regNo, unsigned char data)
-{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0x80 | regNo); /* bit field set */
- spi_write (data);
-
- enc_disable ();
- spi_unlock ();
-}
-
-static void encBitClr (unsigned char regNo, unsigned char data)
-{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0xA0 | regNo); /* bit field clear */
- spi_write (data);
-
- enc_disable ();
- spi_unlock ();
+#ifdef CONFIG_USE_IRQ
+ /* set global interrupt enable bit in enc28j60 */
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
}
-static void encReset (void)
+/*
+ * Completely Reset the ENC
+ */
+static void enc_reset(enc_dev_t *enc)
{
- spi_lock ();
- enc_cfg_spi ();
- enc_enable ();
-
- spi_write (0xff); /* soft reset */
-
- enc_disable ();
- spi_unlock ();
+ u8 dout[1];
+ dout[0] = CMD_SRC;
+ spi_xfer(enc->slave, 8, dout, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
/* sleep 1 ms. See errata pt. 2 */
- udelay (1000);
+ udelay(1000);
}
-static void encInit (unsigned char *pEthAddr)
-{
- unsigned short phid1 = 0;
- unsigned short phid2 = 0;
-
- /* switch to bank 0 */
- m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
+/*
+ * Initialisation data for most of the ENC registers
+ */
+static const u16 enc_initdata[] = {
/*
* Setup the buffer space. The reset values are valid for the
* other pointers.
+ *
+ * We shall not write to ERXST, see errata pt. 5. Instead we
+ * have to make sure that ENC_RX_BUS_START is 0.
*/
- /* We shall not write to ERXST, see errata pt. 5. Instead we
- have to make sure that ENC_RX_BUS_START is 0. */
- m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
- m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
-
- /* taken from the Linux driver */
- m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
- m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
-
- m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
- m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
-
- next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
- next_pointer_msb = (ENC_RX_BUF_START >> 8);
-
- /* verify identification */
- phid1 = phyRead (PHY_REG_PHID1);
- phid2 = phyRead (PHY_REG_PHID2);
-
- if (phid1 != ENC_PHID1_VALUE
- || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
- printf ("ERROR: failed to identify controller\n");
- printf ("phid1 = %x, phid2 = %x\n",
- phid1, (phid2 & ENC_PHID2_MASK));
- printf ("should be phid1 = %x, phid2 = %x\n",
- ENC_PHID1_VALUE, ENC_PHID2_VALUE);
- }
-
+ CTL_REG_ERXSTL, ENC_RX_BUF_START,
+ CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
+ CTL_REG_ERXNDL, ENC_RX_BUF_END,
+ CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
+ CTL_REG_ERDPTL, ENC_RX_BUF_START,
+ CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
/*
- * --- MAC Initialization ---
+ * Set the filter to receive only good-CRC, unicast and broadcast
+ * frames.
+ * Note: some DHCP servers return their answers as broadcasts!
+ * So its unwise to remove broadcast from this. This driver
+ * might incur receiver overruns with packet loss on a broadcast
+ * flooded network.
*/
-
- /* Pull MAC out of Reset */
-
- /* switch to bank 2 */
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
/* enable MAC to receive frames */
- /* added some bits from the Linux driver */
- m_nic_write_retry (CTL_REG_MACON1
- ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
- ,10);
+ CTL_REG_MACON1,
+ ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
/* configure pad, tx-crc and duplex */
- /* added a bit from the Linux driver */
- m_nic_write_retry (CTL_REG_MACON3
- ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
- ,10);
+ CTL_REG_MACON3,
+ ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
+ ENC_MACON3_FRMLNEN,
- /* added 4 new lines from the Linux driver */
/* Allow infinite deferals if the medium is continously busy */
- m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
+ CTL_REG_MACON4, ENC_MACON4_DEFER,
/* Late collisions occur beyond 63 bytes */
- m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
+ CTL_REG_MACLCON2, 63,
- /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
- m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
+ /*
+ * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
+ * Recommended 0x12
+ */
+ CTL_REG_MAIPGL, 0x12,
/*
- * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
- * 0x0c for half-duplex. Nothing for full-duplex
- */
- m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
+ * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
+ * Recommended 0x0c for half-duplex. Nothing for full-duplex
+ */
+ CTL_REG_MAIPGH, 0x0C,
/* set maximum frame length */
- m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
- m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
+ CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
+ CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
/*
- * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
+ * Set MAC back-to-back inter-packet gap.
+ * Recommended 0x12 for half duplex
* and 0x15 for full duplex.
*/
- m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
+ CTL_REG_MABBIPG, 0x12,
- /* set MAC address */
+ /* end of table */
+ 0xffff
+};
- /* switch to bank 3 */
- m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
+/*
+ * Wait for the XTAL oscillator to become ready
+ */
+static int enc_clock_wait(enc_dev_t *enc)
+{
+ uint64_t etime;
- m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
- m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
- m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
- m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
- m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
- m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
+ /* one second timeout */
+ etime = get_ticks() + get_tbclk();
/*
- * PHY Initialization taken from the Linux driver
+ * Wait for CLKRDY to become set (i.e., check that we can
+ * communicate with the ENC)
*/
+ do
+ {
+ if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
+ return 0;
+ } while (get_ticks() <= etime);
+
+ printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
+ return -1;
+}
+
+/*
+ * Write the MAC address into the ENC
+ */
+static int enc_write_macaddr(enc_dev_t *enc)
+{
+ unsigned char *p = enc->dev->enetaddr;
+
+ enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
+ enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
+ enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
+ enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
+ enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
+ enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
+ return 0;
+}
+
+/*
+ * Setup most of the ENC registers
+ */
+static int enc_setup(enc_dev_t *enc)
+{
+ u16 phid1 = 0;
+ u16 phid2 = 0;
+ const u16 *tp;
+
+ /* reset enc struct values */
+ enc->next_pointer = ENC_RX_BUF_START;
+ enc->rx_reset_counter = RX_RESET_COUNTER;
+ enc->bank = 0xff; /* invalidate current bank in enc28j60 */
+
+ /* verify PHY identification */
+ phid1 = phy_read(enc, PHY_REG_PHID1);
+ phid2 = phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
+ if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
+ printf("%s: failed to identify PHY. Found %04x:%04x\n",
+ enc->dev->name, phid1, phid2);
+ return -1;
+ }
- /* Prevent automatic loopback of data beeing transmitted by setting
- ENC_PHCON2_HDLDIS */
- phyWrite(PHY_REG_PHCON2, (1<<8));
+ /* now program registers */
+ for (tp = enc_initdata; *tp != 0xffff; tp += 2)
+ enc_w8_retry(enc, tp[0], tp[1], 10);
+
+ /*
+ * Prevent automatic loopback of data beeing transmitted by setting
+ * ENC_PHCON2_HDLDIS
+ */
+ phy_write(enc, PHY_REG_PHCON2, (1<<8));
- /* LEDs configuration
+ /*
+ * LEDs configuration
* LEDA: LACFG = 0100 -> display link status
* LEDB: LBCFG = 0111 -> display TX & RX activity
* STRCH = 1 -> LED pulses
*/
- phyWrite(PHY_REG_PHLCON, 0x0472);
+ phy_write(enc, PHY_REG_PHLCON, 0x0472);
/* Reset PDPXMD-bit => half duplex */
- phyWrite(PHY_REG_PHCON1, 0);
-
- /*
- * Receive settings
- */
+ phy_write(enc, PHY_REG_PHCON1, 0);
#ifdef CONFIG_USE_IRQ
/* enable interrupts */
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
- m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
+ enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
#endif
+
+ return 0;
}
-/*****************************************************************************
- *
- * Description:
- * Read PHY registers.
- *
- * NOTE! This function will change to Bank 2.
- *
- * Params:
- * [in] addr address of the register to read
- *
- * Returns:
- * The value in the register
+/*
+ * Check if ENC has been initialized.
+ * If not, try to initialize it.
+ * Remember initialized state in struct.
*/
-static unsigned short phyRead (unsigned char addr)
+static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
{
- unsigned short ret = 0;
-
- /* move to bank 2 */
- m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ if (enc->initstate >= requiredstate)
+ return 0;
+
+ if (enc->initstate < setupdone) {
+ /* Initialize the ENC only */
+ enc_reset(enc);
+ /* if any of functions fails, skip the rest and return an error */
+ if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
+ return -1;
+ }
+ enc->initstate = setupdone;
+ }
+ /* if that's all we need, return here */
+ if (enc->initstate >= requiredstate)
+ return 0;
- /* write address to MIREGADR */
- m_nic_write (CTL_REG_MIREGADR, addr);
+ /* now wait for link ready condition */
+ if (enc_phy_link_wait(enc)) {
+ return -1;
+ }
+ enc->initstate = linkready;
+ return 0;
+}
- /* set MICMD.MIIRD */
- m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
+#if defined(CONFIG_CMD_MII)
+/*
+ * Read a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ enc_dev_t *enc;
+
+ if (!dev || phy_adr != 0)
+ return -1;
+
+ enc = dev->priv;
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, setupdone)) {
+ enc_release_bus(enc);
+ return -1;
+ }
+ *value = phy_read(enc, reg);
+ enc_release_bus(enc);
+ return 0;
+}
- /* taken from the Linux driver */
- /* move to bank 3 */
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * Write a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ enc_dev_t *enc;
+
+ if (!dev || phy_adr != 0)
+ return -1;
+
+ enc = dev->priv;
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, setupdone)) {
+ enc_release_bus(enc);
+ return -1;
+ }
+ phy_write(enc, reg, value);
+ enc_release_bus(enc);
+ return 0;
+}
+#endif
- /* poll MISTAT.BUSY bit until operation is complete */
- while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
- static int cnt = 0;
+/*
+ * Write hardware (MAC) address.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_write_hwaddr(struct eth_device *dev)
+{
+ enc_dev_t *enc = dev->priv;
- if (cnt++ >= 1000) {
- /* GJ - this seems extremely dangerous! */
- /* printf("#"); */
- cnt = 0;
- }
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, setupdone)) {
+ enc_release_bus(enc);
+ return -1;
}
+ enc_release_bus(enc);
+ return 0;
+}
- /* taken from the Linux driver */
- /* move to bank 2 */
- m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * Initialize ENC28J60 for use.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_init(struct eth_device *dev, bd_t *bis)
+{
+ enc_dev_t *enc = dev->priv;
- /* clear MICMD.MIIRD */
- m_nic_write (CTL_REG_MICMD, 0);
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, linkready)) {
+ enc_release_bus(enc);
+ return -1;
+ }
+ /* enable receive */
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+ enc_release_bus(enc);
+ return 0;
+}
- ret = (m_nic_read (CTL_REG_MIRDH) << 8);
- ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
+/*
+ * Check for received packets.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_recv(struct eth_device *dev)
+{
+ enc_dev_t *enc = dev->priv;
- return ret;
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, linkready)) {
+ enc_release_bus(enc);
+ return -1;
+ }
+ /* Check for dead receiver */
+ if (enc->rx_reset_counter > 0)
+ enc->rx_reset_counter--;
+ else
+ enc_reset_rx_call(enc);
+ enc_poll(enc);
+ enc_release_bus(enc);
+ return 0;
}
-/*****************************************************************************
- *
- * Taken from the Linux driver.
- * Description:
- * Write PHY registers.
- *
- * NOTE! This function will change to Bank 3.
+/*
+ * Send a packet.
*
- * Params:
- * [in] addr address of the register to write to
- * [in] data to be written
+ * This function entered into eth_device structure.
*
- * Returns:
- * None
+ * Should we wait here until we have a Link? Or shall we leave that to
+ * protocol retries?
*/
-static void phyWrite(unsigned char addr, unsigned short data)
+static int enc_send(
+ struct eth_device *dev,
+ volatile void *packet,
+ int length)
{
- /* move to bank 2 */
- m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ enc_dev_t *enc = dev->priv;
+
+ if (enc_claim_bus(enc))
+ return -1;
+ if (enc_initcheck(enc, linkready)) {
+ enc_release_bus(enc);
+ return -1;
+ }
+ /* setup transmit pointers */
+ enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
+ enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
+ enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
+ /* write packet to ENC */
+ enc_wbuf(enc, length, (u8 *) packet, 0x00);
+ /*
+ * Check that the internal transmit logic has not been altered
+ * by excessive collisions. Reset transmitter if so.
+ * See Errata B4 12 and 14.
+ */
+ if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+ enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+ }
+ enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
+ /* start transmitting */
+ enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
+ enc_release_bus(enc);
+ return 0;
+}
- /* write address to MIREGADR */
- m_nic_write(CTL_REG_MIREGADR, addr);
+/*
+ * Finish use of ENC.
+ *
+ * This function entered into eth_device structure.
+ */
+static void enc_halt(struct eth_device *dev)
+{
+ enc_dev_t *enc = dev->priv;
- m_nic_write(CTL_REG_MIWRL, data & 0xff);
- m_nic_write(CTL_REG_MIWRH, data >> 8);
+ if (enc_claim_bus(enc))
+ return;
+ /* Just disable receiver */
+ enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+ enc_release_bus(enc);
+}
- /* move to bank 3 */
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
- m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * This is the only exported function.
+ *
+ * It may be called several times with different bus:cs combinations.
+ */
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct eth_device *dev;
+ enc_dev_t *enc;
- /* poll MISTAT.BUSY bit until operation is complete */
- while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
- static int cnt = 0;
+ /* try to allocate, check and clear eth_device object */
+ dev = malloc(sizeof(*dev));
+ if (!dev) {
+ return -1;
+ }
+ memset(dev, 0, sizeof(*dev));
- if(cnt++ >= 1000) {
- cnt = 0;
- }
+ /* try to allocate, check and clear enc_dev_t object */
+ enc = malloc(sizeof(*enc));
+ if (!enc) {
+ free(dev);
+ return -1;
+ }
+ memset(enc, 0, sizeof(*enc));
+
+ /* try to setup the SPI slave */
+ enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
+ if (!enc->slave) {
+ printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
+ free(enc);
+ free(dev);
+ return -1;
}
+
+ enc->dev = dev;
+ /* now fill the eth_device object */
+ dev->priv = enc;
+ dev->init = enc_init;
+ dev->halt = enc_halt;
+ dev->send = enc_send;
+ dev->recv = enc_recv;
+ dev->write_hwaddr = enc_write_hwaddr;
+ sprintf(dev->name, "enc%i.%i", bus, cs);
+ eth_register(dev);
+#if defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
+#endif
+ return 0;
}
--- /dev/null
+/*
+ * (X) extracted from enc28j60.c
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _enc28j60_h
+#define _enc28j60_h
+
+/*
+ * SPI Commands
+ *
+ * Bits 7-5: Command
+ * Bits 4-0: Register
+ */
+#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
+#define CMD_RBM 0x3a /* Read Buffer Memory */
+#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
+#define CMD_WBM 0x7a /* Write Buffer Memory */
+#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
+#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
+#define CMD_SRC 0xff /* System Reset Command */
+
+/* NEW: encode (bank number+1) in upper byte */
+
+/* Common Control Registers accessible in all Banks */
+#define CTL_REG_EIE 0x01B
+#define CTL_REG_EIR 0x01C
+#define CTL_REG_ESTAT 0x01D
+#define CTL_REG_ECON2 0x01E
+#define CTL_REG_ECON1 0x01F
+
+/* Control Registers accessible in Bank 0 */
+#define CTL_REG_ERDPTL 0x100
+#define CTL_REG_ERDPTH 0x101
+#define CTL_REG_EWRPTL 0x102
+#define CTL_REG_EWRPTH 0x103
+#define CTL_REG_ETXSTL 0x104
+#define CTL_REG_ETXSTH 0x105
+#define CTL_REG_ETXNDL 0x106
+#define CTL_REG_ETXNDH 0x107
+#define CTL_REG_ERXSTL 0x108
+#define CTL_REG_ERXSTH 0x109
+#define CTL_REG_ERXNDL 0x10A
+#define CTL_REG_ERXNDH 0x10B
+#define CTL_REG_ERXRDPTL 0x10C
+#define CTL_REG_ERXRDPTH 0x10D
+#define CTL_REG_ERXWRPTL 0x10E
+#define CTL_REG_ERXWRPTH 0x10F
+#define CTL_REG_EDMASTL 0x110
+#define CTL_REG_EDMASTH 0x111
+#define CTL_REG_EDMANDL 0x112
+#define CTL_REG_EDMANDH 0x113
+#define CTL_REG_EDMADSTL 0x114
+#define CTL_REG_EDMADSTH 0x115
+#define CTL_REG_EDMACSL 0x116
+#define CTL_REG_EDMACSH 0x117
+
+/* Control Registers accessible in Bank 1 */
+#define CTL_REG_EHT0 0x200
+#define CTL_REG_EHT1 0x201
+#define CTL_REG_EHT2 0x202
+#define CTL_REG_EHT3 0x203
+#define CTL_REG_EHT4 0x204
+#define CTL_REG_EHT5 0x205
+#define CTL_REG_EHT6 0x206
+#define CTL_REG_EHT7 0x207
+#define CTL_REG_EPMM0 0x208
+#define CTL_REG_EPMM1 0x209
+#define CTL_REG_EPMM2 0x20A
+#define CTL_REG_EPMM3 0x20B
+#define CTL_REG_EPMM4 0x20C
+#define CTL_REG_EPMM5 0x20D
+#define CTL_REG_EPMM6 0x20E
+#define CTL_REG_EPMM7 0x20F
+#define CTL_REG_EPMCSL 0x210
+#define CTL_REG_EPMCSH 0x211
+#define CTL_REG_EPMOL 0x214
+#define CTL_REG_EPMOH 0x215
+#define CTL_REG_EWOLIE 0x216
+#define CTL_REG_EWOLIR 0x217
+#define CTL_REG_ERXFCON 0x218
+#define CTL_REG_EPKTCNT 0x219
+
+/* Control Registers accessible in Bank 2 */
+#define CTL_REG_MACON1 0x300
+#define CTL_REG_MACON2 0x301
+#define CTL_REG_MACON3 0x302
+#define CTL_REG_MACON4 0x303
+#define CTL_REG_MABBIPG 0x304
+#define CTL_REG_MAIPGL 0x306
+#define CTL_REG_MAIPGH 0x307
+#define CTL_REG_MACLCON1 0x308
+#define CTL_REG_MACLCON2 0x309
+#define CTL_REG_MAMXFLL 0x30A
+#define CTL_REG_MAMXFLH 0x30B
+#define CTL_REG_MAPHSUP 0x30D
+#define CTL_REG_MICON 0x311
+#define CTL_REG_MICMD 0x312
+#define CTL_REG_MIREGADR 0x314
+#define CTL_REG_MIWRL 0x316
+#define CTL_REG_MIWRH 0x317
+#define CTL_REG_MIRDL 0x318
+#define CTL_REG_MIRDH 0x319
+
+/* Control Registers accessible in Bank 3 */
+#define CTL_REG_MAADR1 0x400
+#define CTL_REG_MAADR0 0x401
+#define CTL_REG_MAADR3 0x402
+#define CTL_REG_MAADR2 0x403
+#define CTL_REG_MAADR5 0x404
+#define CTL_REG_MAADR4 0x405
+#define CTL_REG_EBSTSD 0x406
+#define CTL_REG_EBSTCON 0x407
+#define CTL_REG_EBSTCSL 0x408
+#define CTL_REG_EBSTCSH 0x409
+#define CTL_REG_MISTAT 0x40A
+#define CTL_REG_EREVID 0x412
+#define CTL_REG_ECOCON 0x415
+#define CTL_REG_EFLOCON 0x417
+#define CTL_REG_EPAUSL 0x418
+#define CTL_REG_EPAUSH 0x419
+
+/* PHY Register */
+#define PHY_REG_PHCON1 0x00
+#define PHY_REG_PHSTAT1 0x01
+#define PHY_REG_PHID1 0x02
+#define PHY_REG_PHID2 0x03
+#define PHY_REG_PHCON2 0x10
+#define PHY_REG_PHSTAT2 0x11
+#define PHY_REG_PHLCON 0x14
+
+/* Receive Filter Register (ERXFCON) bits */
+#define ENC_RFR_UCEN 0x80
+#define ENC_RFR_ANDOR 0x40
+#define ENC_RFR_CRCEN 0x20
+#define ENC_RFR_PMEN 0x10
+#define ENC_RFR_MPEN 0x08
+#define ENC_RFR_HTEN 0x04
+#define ENC_RFR_MCEN 0x02
+#define ENC_RFR_BCEN 0x01
+
+/* ECON1 Register Bits */
+#define ENC_ECON1_TXRST 0x80
+#define ENC_ECON1_RXRST 0x40
+#define ENC_ECON1_DMAST 0x20
+#define ENC_ECON1_CSUMEN 0x10
+#define ENC_ECON1_TXRTS 0x08
+#define ENC_ECON1_RXEN 0x04
+#define ENC_ECON1_BSEL1 0x02
+#define ENC_ECON1_BSEL0 0x01
+
+/* ECON2 Register Bits */
+#define ENC_ECON2_AUTOINC 0x80
+#define ENC_ECON2_PKTDEC 0x40
+#define ENC_ECON2_PWRSV 0x20
+#define ENC_ECON2_VRPS 0x08
+
+/* EIR Register Bits */
+#define ENC_EIR_PKTIF 0x40
+#define ENC_EIR_DMAIF 0x20
+#define ENC_EIR_LINKIF 0x10
+#define ENC_EIR_TXIF 0x08
+#define ENC_EIR_WOLIF 0x04
+#define ENC_EIR_TXERIF 0x02
+#define ENC_EIR_RXERIF 0x01
+
+/* ESTAT Register Bits */
+#define ENC_ESTAT_INT 0x80
+#define ENC_ESTAT_LATECOL 0x10
+#define ENC_ESTAT_RXBUSY 0x04
+#define ENC_ESTAT_TXABRT 0x02
+#define ENC_ESTAT_CLKRDY 0x01
+
+/* EIE Register Bits */
+#define ENC_EIE_INTIE 0x80
+#define ENC_EIE_PKTIE 0x40
+#define ENC_EIE_DMAIE 0x20
+#define ENC_EIE_LINKIE 0x10
+#define ENC_EIE_TXIE 0x08
+#define ENC_EIE_WOLIE 0x04
+#define ENC_EIE_TXERIE 0x02
+#define ENC_EIE_RXERIE 0x01
+
+/* MACON1 Register Bits */
+#define ENC_MACON1_LOOPBK 0x10
+#define ENC_MACON1_TXPAUS 0x08
+#define ENC_MACON1_RXPAUS 0x04
+#define ENC_MACON1_PASSALL 0x02
+#define ENC_MACON1_MARXEN 0x01
+
+/* MACON2 Register Bits */
+#define ENC_MACON2_MARST 0x80
+#define ENC_MACON2_RNDRST 0x40
+#define ENC_MACON2_MARXRST 0x08
+#define ENC_MACON2_RFUNRST 0x04
+#define ENC_MACON2_MATXRST 0x02
+#define ENC_MACON2_TFUNRST 0x01
+
+/* MACON3 Register Bits */
+#define ENC_MACON3_PADCFG2 0x80
+#define ENC_MACON3_PADCFG1 0x40
+#define ENC_MACON3_PADCFG0 0x20
+#define ENC_MACON3_TXCRCEN 0x10
+#define ENC_MACON3_PHDRLEN 0x08
+#define ENC_MACON3_HFRMEN 0x04
+#define ENC_MACON3_FRMLNEN 0x02
+#define ENC_MACON3_FULDPX 0x01
+
+/* MACON4 Register Bits */
+#define ENC_MACON4_DEFER 0x40
+
+/* MICMD Register Bits */
+#define ENC_MICMD_MIISCAN 0x02
+#define ENC_MICMD_MIIRD 0x01
+
+/* MISTAT Register Bits */
+#define ENC_MISTAT_NVALID 0x04
+#define ENC_MISTAT_SCAN 0x02
+#define ENC_MISTAT_BUSY 0x01
+
+/* PHID1 and PHID2 values */
+#define ENC_PHID1_VALUE 0x0083
+#define ENC_PHID2_VALUE 0x1400
+#define ENC_PHID2_MASK 0xFC00
+
+/* PHCON1 values */
+#define ENC_PHCON1_PDPXMD 0x0100
+
+/* PHSTAT1 values */
+#define ENC_PHSTAT1_LLSTAT 0x0004
+
+/* PHSTAT2 values */
+#define ENC_PHSTAT2_LSTAT 0x0400
+#define ENC_PHSTAT2_DPXSTAT 0x0200
+
+#endif
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#warning This driver is depreciated. Please update to new SPI framework enc28j60 driver
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spi.h>
+
+/*
+ * Control Registers in Bank 0
+ */
+
+#define CTL_REG_ERDPTL 0x00
+#define CTL_REG_ERDPTH 0x01
+#define CTL_REG_EWRPTL 0x02
+#define CTL_REG_EWRPTH 0x03
+#define CTL_REG_ETXSTL 0x04
+#define CTL_REG_ETXSTH 0x05
+#define CTL_REG_ETXNDL 0x06
+#define CTL_REG_ETXNDH 0x07
+#define CTL_REG_ERXSTL 0x08
+#define CTL_REG_ERXSTH 0x09
+#define CTL_REG_ERXNDL 0x0A
+#define CTL_REG_ERXNDH 0x0B
+#define CTL_REG_ERXRDPTL 0x0C
+#define CTL_REG_ERXRDPTH 0x0D
+#define CTL_REG_ERXWRPTL 0x0E
+#define CTL_REG_ERXWRPTH 0x0F
+#define CTL_REG_EDMASTL 0x10
+#define CTL_REG_EDMASTH 0x11
+#define CTL_REG_EDMANDL 0x12
+#define CTL_REG_EDMANDH 0x13
+#define CTL_REG_EDMADSTL 0x14
+#define CTL_REG_EDMADSTH 0x15
+#define CTL_REG_EDMACSL 0x16
+#define CTL_REG_EDMACSH 0x17
+/* these are common in all banks */
+#define CTL_REG_EIE 0x1B
+#define CTL_REG_EIR 0x1C
+#define CTL_REG_ESTAT 0x1D
+#define CTL_REG_ECON2 0x1E
+#define CTL_REG_ECON1 0x1F
+
+/*
+ * Control Registers in Bank 1
+ */
+
+#define CTL_REG_EHT0 0x00
+#define CTL_REG_EHT1 0x01
+#define CTL_REG_EHT2 0x02
+#define CTL_REG_EHT3 0x03
+#define CTL_REG_EHT4 0x04
+#define CTL_REG_EHT5 0x05
+#define CTL_REG_EHT6 0x06
+#define CTL_REG_EHT7 0x07
+#define CTL_REG_EPMM0 0x08
+#define CTL_REG_EPMM1 0x09
+#define CTL_REG_EPMM2 0x0A
+#define CTL_REG_EPMM3 0x0B
+#define CTL_REG_EPMM4 0x0C
+#define CTL_REG_EPMM5 0x0D
+#define CTL_REG_EPMM6 0x0E
+#define CTL_REG_EPMM7 0x0F
+#define CTL_REG_EPMCSL 0x10
+#define CTL_REG_EPMCSH 0x11
+#define CTL_REG_EPMOL 0x14
+#define CTL_REG_EPMOH 0x15
+#define CTL_REG_EWOLIE 0x16
+#define CTL_REG_EWOLIR 0x17
+#define CTL_REG_ERXFCON 0x18
+#define CTL_REG_EPKTCNT 0x19
+
+/*
+ * Control Registers in Bank 2
+ */
+
+#define CTL_REG_MACON1 0x00
+#define CTL_REG_MACON2 0x01
+#define CTL_REG_MACON3 0x02
+#define CTL_REG_MACON4 0x03
+#define CTL_REG_MABBIPG 0x04
+#define CTL_REG_MAIPGL 0x06
+#define CTL_REG_MAIPGH 0x07
+#define CTL_REG_MACLCON1 0x08
+#define CTL_REG_MACLCON2 0x09
+#define CTL_REG_MAMXFLL 0x0A
+#define CTL_REG_MAMXFLH 0x0B
+#define CTL_REG_MAPHSUP 0x0D
+#define CTL_REG_MICON 0x11
+#define CTL_REG_MICMD 0x12
+#define CTL_REG_MIREGADR 0x14
+#define CTL_REG_MIWRL 0x16
+#define CTL_REG_MIWRH 0x17
+#define CTL_REG_MIRDL 0x18
+#define CTL_REG_MIRDH 0x19
+
+/*
+ * Control Registers in Bank 3
+ */
+
+#define CTL_REG_MAADR1 0x00
+#define CTL_REG_MAADR0 0x01
+#define CTL_REG_MAADR3 0x02
+#define CTL_REG_MAADR2 0x03
+#define CTL_REG_MAADR5 0x04
+#define CTL_REG_MAADR4 0x05
+#define CTL_REG_EBSTSD 0x06
+#define CTL_REG_EBSTCON 0x07
+#define CTL_REG_EBSTCSL 0x08
+#define CTL_REG_EBSTCSH 0x09
+#define CTL_REG_MISTAT 0x0A
+#define CTL_REG_EREVID 0x12
+#define CTL_REG_ECOCON 0x15
+#define CTL_REG_EFLOCON 0x17
+#define CTL_REG_EPAUSL 0x18
+#define CTL_REG_EPAUSH 0x19
+
+
+/*
+ * PHY Register
+ */
+
+#define PHY_REG_PHID1 0x02
+#define PHY_REG_PHID2 0x03
+/* taken from the Linux driver */
+#define PHY_REG_PHCON1 0x00
+#define PHY_REG_PHCON2 0x10
+#define PHY_REG_PHLCON 0x14
+
+/*
+ * Receive Filter Register (ERXFCON) bits
+ */
+
+#define ENC_RFR_UCEN 0x80
+#define ENC_RFR_ANDOR 0x40
+#define ENC_RFR_CRCEN 0x20
+#define ENC_RFR_PMEN 0x10
+#define ENC_RFR_MPEN 0x08
+#define ENC_RFR_HTEN 0x04
+#define ENC_RFR_MCEN 0x02
+#define ENC_RFR_BCEN 0x01
+
+/*
+ * ECON1 Register Bits
+ */
+
+#define ENC_ECON1_TXRST 0x80
+#define ENC_ECON1_RXRST 0x40
+#define ENC_ECON1_DMAST 0x20
+#define ENC_ECON1_CSUMEN 0x10
+#define ENC_ECON1_TXRTS 0x08
+#define ENC_ECON1_RXEN 0x04
+#define ENC_ECON1_BSEL1 0x02
+#define ENC_ECON1_BSEL0 0x01
+
+/*
+ * ECON2 Register Bits
+ */
+#define ENC_ECON2_AUTOINC 0x80
+#define ENC_ECON2_PKTDEC 0x40
+#define ENC_ECON2_PWRSV 0x20
+#define ENC_ECON2_VRPS 0x08
+
+/*
+ * EIR Register Bits
+ */
+#define ENC_EIR_PKTIF 0x40
+#define ENC_EIR_DMAIF 0x20
+#define ENC_EIR_LINKIF 0x10
+#define ENC_EIR_TXIF 0x08
+#define ENC_EIR_WOLIF 0x04
+#define ENC_EIR_TXERIF 0x02
+#define ENC_EIR_RXERIF 0x01
+
+/*
+ * ESTAT Register Bits
+ */
+
+#define ENC_ESTAT_INT 0x80
+#define ENC_ESTAT_LATECOL 0x10
+#define ENC_ESTAT_RXBUSY 0x04
+#define ENC_ESTAT_TXABRT 0x02
+#define ENC_ESTAT_CLKRDY 0x01
+
+/*
+ * EIE Register Bits
+ */
+
+#define ENC_EIE_INTIE 0x80
+#define ENC_EIE_PKTIE 0x40
+#define ENC_EIE_DMAIE 0x20
+#define ENC_EIE_LINKIE 0x10
+#define ENC_EIE_TXIE 0x08
+#define ENC_EIE_WOLIE 0x04
+#define ENC_EIE_TXERIE 0x02
+#define ENC_EIE_RXERIE 0x01
+
+/*
+ * MACON1 Register Bits
+ */
+#define ENC_MACON1_LOOPBK 0x10
+#define ENC_MACON1_TXPAUS 0x08
+#define ENC_MACON1_RXPAUS 0x04
+#define ENC_MACON1_PASSALL 0x02
+#define ENC_MACON1_MARXEN 0x01
+
+
+/*
+ * MACON2 Register Bits
+ */
+#define ENC_MACON2_MARST 0x80
+#define ENC_MACON2_RNDRST 0x40
+#define ENC_MACON2_MARXRST 0x08
+#define ENC_MACON2_RFUNRST 0x04
+#define ENC_MACON2_MATXRST 0x02
+#define ENC_MACON2_TFUNRST 0x01
+
+/*
+ * MACON3 Register Bits
+ */
+#define ENC_MACON3_PADCFG2 0x80
+#define ENC_MACON3_PADCFG1 0x40
+#define ENC_MACON3_PADCFG0 0x20
+#define ENC_MACON3_TXCRCEN 0x10
+#define ENC_MACON3_PHDRLEN 0x08
+#define ENC_MACON3_HFRMEN 0x04
+#define ENC_MACON3_FRMLNEN 0x02
+#define ENC_MACON3_FULDPX 0x01
+
+/*
+ * MICMD Register Bits
+ */
+#define ENC_MICMD_MIISCAN 0x02
+#define ENC_MICMD_MIIRD 0x01
+
+/*
+ * MISTAT Register Bits
+ */
+#define ENC_MISTAT_NVALID 0x04
+#define ENC_MISTAT_SCAN 0x02
+#define ENC_MISTAT_BUSY 0x01
+
+/*
+ * PHID1 and PHID2 values
+ */
+#define ENC_PHID1_VALUE 0x0083
+#define ENC_PHID2_VALUE 0x1400
+#define ENC_PHID2_MASK 0xFC00
+
+
+#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
+#define ENC_RESET 0x00020000 /* pin P1.17 */
+
+#define FAILSAFE_VALUE 5000
+
+/*
+ * Controller memory layout:
+ *
+ * 0x0000 - 0x17ff 6k bytes receive buffer
+ * 0x1800 - 0x1fff 2k bytes transmit buffer
+ */
+/* Use the lower memory for receiver buffer. See errata pt. 5 */
+#define ENC_RX_BUF_START 0x0000
+#define ENC_TX_BUF_START 0x1800
+/* taken from the Linux driver */
+#define ENC_RX_BUF_END 0x17ff
+#define ENC_TX_BUF_END 0x1fff
+
+/* maximum frame length */
+#define ENC_MAX_FRM_LEN 1518
+
+#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
+#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
+#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
+
+
+static unsigned char encReadReg (unsigned char regNo);
+static void encWriteReg (unsigned char regNo, unsigned char data);
+static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
+static void encReadBuff (unsigned short length, unsigned char *pBuff);
+static void encWriteBuff (unsigned short length, unsigned char *pBuff);
+static void encBitSet (unsigned char regNo, unsigned char data);
+static void encBitClr (unsigned char regNo, unsigned char data);
+static void encReset (void);
+static void encInit (unsigned char *pEthAddr);
+static unsigned short phyRead (unsigned char addr);
+static void phyWrite(unsigned char, unsigned short);
+static void encPoll (void);
+static void encRx (void);
+
+#define m_nic_read(reg) encReadReg(reg)
+#define m_nic_write(reg, data) encWriteReg(reg, data)
+#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
+#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
+#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
+
+/* bit field set */
+#define m_nic_bfs(reg, data) encBitSet(reg, data)
+
+/* bit field clear */
+#define m_nic_bfc(reg, data) encBitClr(reg, data)
+
+static unsigned char bank = 0; /* current bank in enc28j60 */
+static unsigned char next_pointer_lsb;
+static unsigned char next_pointer_msb;
+
+static unsigned char buffer[ENC_MAX_FRM_LEN];
+static int rxResetCounter = 0;
+
+#define RX_RESET_COUNTER 1000;
+
+/*-----------------------------------------------------------------------------
+ * Always returns 0
+ */
+int eth_init (bd_t * bis)
+{
+ unsigned char estatVal;
+ uchar enetaddr[6];
+
+ /* configure GPIO */
+ (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
+ (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
+
+ /* CS and RESET active low */
+ PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
+ PUT32 (IO1SET, ENC_RESET);
+
+ spi_init ();
+
+ /* taken from the Linux driver - dangerous stuff here! */
+ /* Wait for CLKRDY to become set (i.e., check that we can communicate with
+ the ENC) */
+ do
+ {
+ estatVal = m_nic_read(CTL_REG_ESTAT);
+ } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
+
+ /* initialize controller */
+ encReset ();
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ encInit (enetaddr);
+
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
+
+ return 0;
+}
+
+int eth_send (volatile void *packet, int length)
+{
+ /* check frame length, etc. */
+ /* TODO: */
+
+ /* switch to bank 0 */
+ m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+ /* set EWRPT */
+ m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
+ m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
+
+ /* set ETXND */
+ m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
+ m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
+
+ /* set ETXST */
+ m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
+ m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
+
+ /* write packet */
+ m_nic_write_data (length, (unsigned char *) packet);
+
+ /* taken from the Linux driver */
+ /* Verify that the internal transmit logic has not been altered by excessive
+ collisions. See Errata B4 12 and 14.
+ */
+ if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
+ m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
+ }
+ m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
+
+ /* set ECON1.TXRTS */
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
+
+ return 0;
+}
+
+
+/*****************************************************************************
+ * This function resets the receiver only. This function may be called from
+ * interrupt-context.
+ */
+static void encReceiverReset (void)
+{
+ unsigned char econ1;
+
+ econ1 = m_nic_read (CTL_REG_ECON1);
+ if ((econ1 & ENC_ECON1_RXRST) == 0) {
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
+ rxResetCounter = RX_RESET_COUNTER;
+ }
+}
+
+/*****************************************************************************
+ * receiver reset timer
+ */
+static void encReceiverResetCallback (void)
+{
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
+}
+
+/*-----------------------------------------------------------------------------
+ * Check for received packets. Call NetReceive for each packet. The return
+ * value is ignored by the caller.
+ */
+int eth_rx (void)
+{
+ if (rxResetCounter > 0 && --rxResetCounter == 0) {
+ encReceiverResetCallback ();
+ }
+
+ encPoll ();
+
+ return 0;
+}
+
+void eth_halt (void)
+{
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
+}
+
+/*****************************************************************************/
+
+static void encPoll (void)
+{
+ unsigned char eir_reg;
+ volatile unsigned char estat_reg;
+ unsigned char pkt_cnt;
+
+#ifdef CONFIG_USE_IRQ
+ /* clear global interrupt enable bit in enc28j60 */
+ m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+ estat_reg = m_nic_read (CTL_REG_ESTAT);
+
+ eir_reg = m_nic_read (CTL_REG_EIR);
+
+ if (eir_reg & ENC_EIR_TXIF) {
+ /* clear TXIF bit in EIR */
+ m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
+ }
+
+ /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+
+ /* move to bank 1 */
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+
+ /* read pktcnt */
+ pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+
+ if (pkt_cnt > 0) {
+ if ((eir_reg & ENC_EIR_PKTIF) == 0) {
+ /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
+ }
+ encRx ();
+ /* clear PKTIF bit in EIR, this should not need to be done but it
+ seems like we get problems if we do not */
+ m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
+ }
+
+ if (eir_reg & ENC_EIR_RXERIF) {
+ printf ("encPoll: rx error\n");
+ m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
+ }
+ if (eir_reg & ENC_EIR_TXERIF) {
+ printf ("encPoll: tx error\n");
+ m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
+ }
+
+#ifdef CONFIG_USE_IRQ
+ /* set global interrupt enable bit in enc28j60 */
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+}
+
+static void encRx (void)
+{
+ unsigned short pkt_len;
+ unsigned short copy_len;
+ unsigned short status;
+ unsigned char eir_reg;
+ unsigned char pkt_cnt = 0;
+ unsigned short rxbuf_rdpt;
+
+ /* switch to bank 0 */
+ m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+ m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
+ m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+
+ do {
+ m_nic_read_data (6, buffer);
+ next_pointer_lsb = buffer[0];
+ next_pointer_msb = buffer[1];
+ pkt_len = buffer[2];
+ pkt_len |= (unsigned short) buffer[3] << 8;
+ status = buffer[4];
+ status |= (unsigned short) buffer[5] << 8;
+
+ if (pkt_len <= ENC_MAX_FRM_LEN)
+ copy_len = pkt_len;
+ else
+ copy_len = 0;
+
+ if ((status & (1L << 7)) == 0) /* check Received Ok bit */
+ copy_len = 0;
+
+ /* taken from the Linux driver */
+ /* check if next pointer is resonable */
+ if ((((unsigned int)next_pointer_msb << 8) |
+ (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
+ copy_len = 0;
+
+ if (copy_len > 0) {
+ m_nic_read_data (copy_len, buffer);
+ }
+
+ /* advance read pointer to next pointer */
+ m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
+ m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+
+ /* decrease packet counter */
+ m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
+
+ /* taken from the Linux driver */
+ /* Only odd values should be written to ERXRDPTL,
+ * see errata B4 pt.13
+ */
+ rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
+ if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
+ m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
+ (m_nic_read(CTL_REG_ERXNDH) << 8 |
+ m_nic_read(CTL_REG_ERXNDL)))) {
+ m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
+ m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
+ } else {
+ m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
+ m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
+ }
+
+ /* move to bank 1 */
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+
+ /* read pktcnt */
+ pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+
+ /* switch to bank 0 */
+ m_nic_bfc (CTL_REG_ECON1,
+ (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+ if (copy_len == 0) {
+ eir_reg = m_nic_read (CTL_REG_EIR);
+ encReceiverReset ();
+ printf ("eth_rx: copy_len=0\n");
+ continue;
+ }
+
+ NetReceive ((unsigned char *) buffer, pkt_len);
+
+ eir_reg = m_nic_read (CTL_REG_EIR);
+ } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
+}
+
+static void encWriteReg (unsigned char regNo, unsigned char data)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x40 | regNo); /* write in regNo */
+ spi_write (data);
+
+ enc_disable ();
+ enc_enable ();
+
+ spi_write (0x1f); /* write reg 0x1f */
+
+ enc_disable ();
+ spi_unlock ();
+}
+
+static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
+{
+ unsigned char readback;
+ int i;
+
+ spi_lock ();
+
+ for (i = 0; i < c; i++) {
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x40 | regNo); /* write in regNo */
+ spi_write (data);
+
+ enc_disable ();
+ enc_enable ();
+
+ spi_write (0x1f); /* write reg 0x1f */
+
+ enc_disable ();
+
+ spi_unlock (); /* we must unlock spi first */
+
+ readback = encReadReg (regNo);
+
+ spi_lock ();
+
+ if (readback == data)
+ break;
+ }
+ spi_unlock ();
+
+ if (i == c) {
+ printf ("enc28j60: write reg %d failed\n", regNo);
+ }
+}
+
+static unsigned char encReadReg (unsigned char regNo)
+{
+ unsigned char rxByte;
+
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x1f); /* read reg 0x1f */
+
+ bank = spi_read () & 0x3;
+
+ enc_disable ();
+ enc_enable ();
+
+ spi_write (regNo);
+ rxByte = spi_read ();
+
+ /* check if MAC or MII register */
+ if (((bank == 2) && (regNo <= 0x1a)) ||
+ ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
+ /* ignore first byte and read another byte */
+ rxByte = spi_read ();
+ }
+
+ enc_disable ();
+ spi_unlock ();
+
+ return rxByte;
+}
+
+static void encReadBuff (unsigned short length, unsigned char *pBuff)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x20 | 0x1a); /* read buffer memory */
+
+ while (length--) {
+ if (pBuff != NULL)
+ *pBuff++ = spi_read ();
+ else
+ spi_write (0);
+ }
+
+ enc_disable ();
+ spi_unlock ();
+}
+
+static void encWriteBuff (unsigned short length, unsigned char *pBuff)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x60 | 0x1a); /* write buffer memory */
+
+ spi_write (0x00); /* control byte */
+
+ while (length--)
+ spi_write (*pBuff++);
+
+ enc_disable ();
+ spi_unlock ();
+}
+
+static void encBitSet (unsigned char regNo, unsigned char data)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0x80 | regNo); /* bit field set */
+ spi_write (data);
+
+ enc_disable ();
+ spi_unlock ();
+}
+
+static void encBitClr (unsigned char regNo, unsigned char data)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0xA0 | regNo); /* bit field clear */
+ spi_write (data);
+
+ enc_disable ();
+ spi_unlock ();
+}
+
+static void encReset (void)
+{
+ spi_lock ();
+ enc_cfg_spi ();
+ enc_enable ();
+
+ spi_write (0xff); /* soft reset */
+
+ enc_disable ();
+ spi_unlock ();
+
+ /* sleep 1 ms. See errata pt. 2 */
+ udelay (1000);
+}
+
+static void encInit (unsigned char *pEthAddr)
+{
+ unsigned short phid1 = 0;
+ unsigned short phid2 = 0;
+
+ /* switch to bank 0 */
+ m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+ /*
+ * Setup the buffer space. The reset values are valid for the
+ * other pointers.
+ */
+ /* We shall not write to ERXST, see errata pt. 5. Instead we
+ have to make sure that ENC_RX_BUS_START is 0. */
+ m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
+ m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
+
+ /* taken from the Linux driver */
+ m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
+ m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
+
+ m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
+ m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
+
+ next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
+ next_pointer_msb = (ENC_RX_BUF_START >> 8);
+
+ /* verify identification */
+ phid1 = phyRead (PHY_REG_PHID1);
+ phid2 = phyRead (PHY_REG_PHID2);
+
+ if (phid1 != ENC_PHID1_VALUE
+ || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
+ printf ("ERROR: failed to identify controller\n");
+ printf ("phid1 = %x, phid2 = %x\n",
+ phid1, (phid2 & ENC_PHID2_MASK));
+ printf ("should be phid1 = %x, phid2 = %x\n",
+ ENC_PHID1_VALUE, ENC_PHID2_VALUE);
+ }
+
+ /*
+ * --- MAC Initialization ---
+ */
+
+ /* Pull MAC out of Reset */
+
+ /* switch to bank 2 */
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* enable MAC to receive frames */
+ /* added some bits from the Linux driver */
+ m_nic_write_retry (CTL_REG_MACON1
+ ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
+ ,10);
+
+ /* configure pad, tx-crc and duplex */
+ /* added a bit from the Linux driver */
+ m_nic_write_retry (CTL_REG_MACON3
+ ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
+ ,10);
+
+ /* added 4 new lines from the Linux driver */
+ /* Allow infinite deferals if the medium is continously busy */
+ m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
+
+ /* Late collisions occur beyond 63 bytes */
+ m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
+
+ /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
+ m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
+
+ /*
+ * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
+ * 0x0c for half-duplex. Nothing for full-duplex
+ */
+ m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
+
+ /* set maximum frame length */
+ m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
+ m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
+
+ /*
+ * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
+ * and 0x15 for full duplex.
+ */
+ m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
+
+ /* set MAC address */
+
+ /* switch to bank 3 */
+ m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
+
+ m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
+ m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
+ m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
+ m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
+ m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
+ m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
+
+ /*
+ * PHY Initialization taken from the Linux driver
+ */
+
+ /* Prevent automatic loopback of data beeing transmitted by setting
+ ENC_PHCON2_HDLDIS */
+ phyWrite(PHY_REG_PHCON2, (1<<8));
+
+ /* LEDs configuration
+ * LEDA: LACFG = 0100 -> display link status
+ * LEDB: LBCFG = 0111 -> display TX & RX activity
+ * STRCH = 1 -> LED pulses
+ */
+ phyWrite(PHY_REG_PHLCON, 0x0472);
+
+ /* Reset PDPXMD-bit => half duplex */
+ phyWrite(PHY_REG_PHCON1, 0);
+
+ /*
+ * Receive settings
+ */
+
+#ifdef CONFIG_USE_IRQ
+ /* enable interrupts */
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
+ m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+}
+
+/*****************************************************************************
+ *
+ * Description:
+ * Read PHY registers.
+ *
+ * NOTE! This function will change to Bank 2.
+ *
+ * Params:
+ * [in] addr address of the register to read
+ *
+ * Returns:
+ * The value in the register
+ */
+static unsigned short phyRead (unsigned char addr)
+{
+ unsigned short ret = 0;
+
+ /* move to bank 2 */
+ m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* write address to MIREGADR */
+ m_nic_write (CTL_REG_MIREGADR, addr);
+
+ /* set MICMD.MIIRD */
+ m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
+
+ /* taken from the Linux driver */
+ /* move to bank 3 */
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* poll MISTAT.BUSY bit until operation is complete */
+ while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
+ static int cnt = 0;
+
+ if (cnt++ >= 1000) {
+ /* GJ - this seems extremely dangerous! */
+ /* printf("#"); */
+ cnt = 0;
+ }
+ }
+
+ /* taken from the Linux driver */
+ /* move to bank 2 */
+ m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* clear MICMD.MIIRD */
+ m_nic_write (CTL_REG_MICMD, 0);
+
+ ret = (m_nic_read (CTL_REG_MIRDH) << 8);
+ ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
+
+ return ret;
+}
+
+/*****************************************************************************
+ *
+ * Taken from the Linux driver.
+ * Description:
+ * Write PHY registers.
+ *
+ * NOTE! This function will change to Bank 3.
+ *
+ * Params:
+ * [in] addr address of the register to write to
+ * [in] data to be written
+ *
+ * Returns:
+ * None
+ */
+static void phyWrite(unsigned char addr, unsigned short data)
+{
+ /* move to bank 2 */
+ m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* write address to MIREGADR */
+ m_nic_write(CTL_REG_MIREGADR, addr);
+
+ m_nic_write(CTL_REG_MIWRL, data & 0xff);
+ m_nic_write(CTL_REG_MIWRH, data >> 8);
+
+ /* move to bank 3 */
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+ m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+ /* poll MISTAT.BUSY bit until operation is complete */
+ while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
+ static int cnt = 0;
+
+ if(cnt++ >= 1000) {
+ cnt = 0;
+ }
+ }
+}
static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
{
-/*
- * The MX27 can store the mac address in internal eeprom
- * This mechanism is not supported now by MX51 or MX25
- */
-#if defined(CONFIG_MX51) || defined(CONFIG_MX25)
- return -1;
-#else
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- int i;
-
- for (i = 0; i < 6; i++)
- mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
-
+ imx_get_mac_from_fuse(mac);
return !is_valid_ether_addr(mac);
-#endif
}
static int fec_set_hwaddr(struct eth_device *dev)
uint32_t base;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ /* Initialize MAC address */
+ fec_set_hwaddr(dev);
+
/*
* reserve memory for both buffer descriptor chains at once
* Datasheet forces the startaddress of each chain is 16 byte
puts("fec_mxc: not enough malloc memory\n");
return -ENOMEM;
}
+ memset(edev, 0, sizeof(*edev));
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
eth_register(edev);
if (fec_get_hwaddr(edev, ethaddr) == 0) {
- printf("got MAC address from EEPROM: %pM\n", ethaddr);
+ printf("got MAC address from fuse: %pM\n", ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}
* MA 02111-1307 USA
*/
+/* #define DEBUG */
+
#include <common.h>
#include <command.h>
#include <net.h>
#include <ambapp.h>
#include <asm/leon.h>
-/* #define DEBUG */
-
#include "greth.h"
/* Default to 3s timeout on autonegotiation */
#define GRETH_PHY_TIMEOUT_MS 3000
#endif
+/* Default to PHY adrress 0 not not specified */
+#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
+#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
+#else
+#define GRETH_PHY_ADR_DEFAULT 0
+#endif
+
/* ByPass Cache when reading regs */
#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
/* Write-through cache ==> no bypassing needed on writes */
-#define GRETH_REGSAVE(addr,data) (*(unsigned int *)(addr) = (data))
+#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
} greth_priv;
/* Read MII register 'addr' from core 'regs' */
-static int read_mii(int addr, volatile greth_regs * regs)
+static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
{
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
- GRETH_REGSAVE(®s->mdio, (0 << 11) | ((addr & 0x1F) << 6) | 2);
+ GRETH_REGSAVE(®s->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
}
}
-static void write_mii(int addr, int data, volatile greth_regs * regs)
+static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
{
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
GRETH_REGSAVE(®s->mdio,
- ((data & 0xFFFF) << 16) | (0 << 11) | ((addr & 0x1F) << 6)
- | 1);
+ ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
+ ((regaddr & 0x1F) << 6) | 1);
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
greth_priv *greth = dev->priv;
greth_regs *regs = greth->regs;
-#ifdef DEBUG
- printf("greth_init\n");
-#endif
- GRETH_REGSAVE(®s->control, 0);
+ debug("greth_init\n");
+
+ /* Reset core */
+ GRETH_REGSAVE(®s->control, (GRETH_RESET | (greth->gb << 8) |
+ (greth->sp << 7) | (greth->fd << 4)));
+
+ /* Wait for Reset to complete */
+ while ( GRETH_REGLOAD(®s->control) & GRETH_RESET) ;
+
+ GRETH_REGSAVE(®s->control,
+ ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
if (!greth->rxbd_base) {
greth->rxbd_base = (greth_bd *)
memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
greth->txbd_base = (greth_bd *)
- memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
+ memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
/* allocate buffers to all descriptors */
greth->rxbuf_base =
for (i = 0; i < GRETH_TXBD_CNT; i++) {
greth->txbd_base[i].addr = 0;
/* enable desciptor & set wrap bit if last descriptor */
- if (i >= (GRETH_RXBD_CNT - 1)) {
+ if (i >= (GRETH_TXBD_CNT - 1)) {
greth->txbd_base[i].stat = GRETH_BD_WR;
} else {
greth->txbd_base[i].stat = 0;
/* Enable Transmitter, GRETH will now scan descriptors for packets
* to transmitt */
-#ifdef DEBUG
- printf("greth_init: enabling receiver\n");
-#endif
+ debug("greth_init: enabling receiver\n");
GRETH_REGORIN(®s->control, GRETH_RXEN);
return 0;
greth_regs *regs = dev->regs;
int tmp, tmp1, tmp2, i;
unsigned int start, timeout;
+ int phyaddr = GRETH_PHY_ADR_DEFAULT;
+
+#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
+ /* If BSP doesn't provide a hardcoded PHY address the driver will
+ * try to autodetect PHY address by stopping the search on the first
+ * PHY address which has REG0 implemented.
+ */
+ for (i=0; i<32; i++) {
+ tmp = read_mii(i, 0, regs);
+ if ( (tmp != 0) && (tmp != 0xffff) ) {
+ phyaddr = i;
+ break;
+ }
+ }
+#endif
+
+ /* Save PHY Address */
+ dev->phyaddr = phyaddr;
+
+ debug("GRETH PHY ADDRESS: %d\n", phyaddr);
/* X msecs to ticks */
timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
/* get phy control register default values */
- while ((tmp = read_mii(0, regs)) & 0x8000) {
- if (get_timer(start) > timeout)
+ while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
+ if (get_timer(start) > timeout) {
+ debug("greth_init_phy: PHY read 1 failed\n");
return 1; /* Fail */
+ }
}
/* reset PHY and wait for completion */
- write_mii(0, 0x8000 | tmp, regs);
+ write_mii(phyaddr, 0, 0x8000 | tmp, regs);
- while (((tmp = read_mii(0, regs))) & 0x8000) {
- if (get_timer(start) > timeout)
+ while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
+ if (get_timer(start) > timeout) {
+ debug("greth_init_phy: PHY read 2 failed\n");
return 1; /* Fail */
+ }
}
/* Check if PHY is autoneg capable and then determine operating
dev->sp = 0;
dev->auto_neg = 0;
if (!((tmp >> 12) & 1)) {
- write_mii(0, 0, regs);
+ write_mii(phyaddr, 0, 0, regs);
} else {
/* wait for auto negotiation to complete and then check operating mode */
dev->auto_neg = 1;
i = 0;
- while (!(((tmp = read_mii(1, regs)) >> 5) & 1)) {
+ while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
if (get_timer(start) > timeout) {
printf("Auto negotiation timed out. "
"Selecting default config\n");
- tmp = read_mii(0, regs);
+ tmp = read_mii(phyaddr, 0, regs);
dev->gb = ((tmp >> 6) & 1)
&& !((tmp >> 13) & 1);
dev->sp = !((tmp >> 6) & 1)
}
}
if ((tmp >> 8) & 1) {
- tmp1 = read_mii(9, regs);
- tmp2 = read_mii(10, regs);
+ tmp1 = read_mii(phyaddr, 9, regs);
+ tmp2 = read_mii(phyaddr, 10, regs);
if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
(tmp2 & GRETH_MII_EXTPRT_1000FD)) {
dev->gb = 1;
}
}
if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
- tmp1 = read_mii(4, regs);
- tmp2 = read_mii(5, regs);
+ tmp1 = read_mii(phyaddr, 4, regs);
+ tmp2 = read_mii(phyaddr, 5, regs);
if ((tmp1 & GRETH_MII_100TXFD) &&
(tmp2 & GRETH_MII_100TXFD)) {
dev->sp = 1;
if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
dev->gb = 0;
dev->fd = 0;
- write_mii(0, dev->sp << 13, regs);
+ write_mii(phyaddr, 0, dev->sp << 13, regs);
}
}
}
auto_neg_done:
-#ifdef DEBUG
- printf("%s GRETH Ethermac at [0x%x] irq %d. Running \
+ debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
%d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
-#endif
/* Read out PHY info if extended registers are available */
if (tmp & 1) {
- tmp1 = read_mii(2, regs);
- tmp2 = read_mii(3, regs);
+ tmp1 = read_mii(phyaddr, 2, regs);
+ tmp2 = read_mii(phyaddr, 3, regs);
tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
tmp = tmp2 & 0xF;
tmp2 = (tmp2 >> 4) & 0x3F;
-#ifdef DEBUG
- printf("PHY: Vendor %x Device %x Revision %d\n", tmp1,
+ debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
tmp2, tmp);
-#endif
} else {
printf("PHY info not available\n");
}
greth_priv *greth;
greth_regs *regs;
int i;
-#ifdef DEBUG
- printf("greth_halt\n");
-#endif
+
+ debug("greth_halt\n");
+
if (!dev || !dev->priv)
return;
greth_bd *txbd;
void *txbuf;
unsigned int status;
-#ifdef DEBUG
- printf("greth_send\n");
-#endif
+
+ debug("greth_send\n");
+
/* send data, wait for data to be sent, then return */
if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
&& !greth->gbit_mac) {
*/
if (!greth->txbuf) {
greth->txbuf = malloc(GRETH_RXBUF_SIZE);
-#ifdef DEBUG
- printf("GRETH: allocated aligned tx-buf\n");
-#endif
}
txbuf = greth->txbuf;
unsigned char *d;
int enable = 0;
int i;
-#ifdef DEBUG
-/* printf("greth_recv\n"); */
-#endif
+
/* Receive One packet only, but clear as many error packets as there are
* available.
*/
if (status & GRETH_BD_EN) {
goto done;
}
-#ifdef DEBUG
- printf("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
+
+ debug("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
(unsigned int)rxbd, status, status & GRETH_BD_LEN);
-#endif
/* Check status for errors.
*/
for (i = 0; i < GRETH_RXBD_CNT; i++) {
printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
GRETH_REGLOAD(&greth->rxbd_base[i].stat),
- GRETH_REGLOAD(&greth->rxbd_base[i].
- addr));
+ GRETH_REGLOAD(&greth->rxbd_base[i].addr));
}
} else {
/* Process the incoming packet. */
len = status & GRETH_BD_LEN;
d = (char *)rxbd->addr;
-#ifdef DEBUG
- printf
+
+ debug
("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
d[7]);
-#endif
+
/* flush all data cache to make sure we're not reading old packet data */
sparc_dcache_flush_all();
(unsigned int)greth->rxbd_max) ? greth->
rxbd_base : (greth->rxbd_curr + 1);
- };
+ }
if (enable) {
GRETH_REGORIN(®s->control, GRETH_RXEN);
greth->regs->esa_msb = (mac[0] << 8) | mac[1];
greth->regs->esa_lsb =
(mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
-#ifdef DEBUG
- printf("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+
+ debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-#endif
}
int greth_initialize(bd_t * bis)
int i;
char *addr_str, *end;
unsigned char addr[6];
-#ifdef DEBUG
- printf("Scanning for GRETH\n");
-#endif
+
+ debug("Scanning for GRETH\n");
+
/* Find Device & IRQ via AMBA Plug&Play information */
if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
return -1; /* GRETH not found */
greth->regs = (greth_regs *) apbdev.address;
greth->irq = apbdev.irq;
-#ifdef DEBUG
- printf("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
-#endif
+ debug("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
dev->priv = (void *)greth;
dev->iobase = (unsigned int)greth->regs;
dev->init = greth_init;
/* Make descriptor string */
if (greth->gbit_mac) {
- sprintf(dev->name, "GRETH 10/100/GB");
+ sprintf(dev->name, "GRETH_10/100/GB");
} else {
- sprintf(dev->name, "GRETH 10/100");
+ sprintf(dev->name, "GRETH_10/100");
}
/* initiate PHY, select speed/duplex depending on connected PHY */
if (greth_init_phy(greth, bis)) {
/* Failed to init PHY (timedout) */
+ debug("GRETH[0x%08x]: Failed to init PHY\n", greth->regs);
return -1;
}
/* set and remember MAC address */
greth_set_hwaddr(greth, addr);
+ debug("GRETH[0x%08x]: Initialized successfully\n", greth->regs);
return 0;
}
mpc5xxx_fec_init_phy(dev, bis);
/*
+ * Call board-specific PHY fixups (if any)
+ */
+#ifdef CONFIG_RESET_PHY_R
+ reset_phy();
+#endif
+
+ /*
* Initialize RxBD/TxBD rings
*/
mpc5xxx_fec_rbd_init(fec);
}
dev = (struct eth_device *) malloc(sizeof *dev);
+ if (!dev) {
+ printf("natsemi: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "dp83815#%d", card_number);
dev->iobase = bus_to_phys(iobase);
}
dev = (struct eth_device *) malloc(sizeof *dev);
+ if (!dev) {
+ printf("ns8382x: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "dp8382x#%d", card_number);
dev->iobase = bus_to_phys(iobase);
* Allocate and pre-fill the device structure.
*/
dev = (struct eth_device *) malloc (sizeof *dev);
+ if (!dev) {
+ printf("pcnet: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
dev->priv = (void *) devbusfn;
sprintf (dev->name, "pcnet#%d", dev_nr);
include $(TOPDIR)/config.mk
-LIB := $(obj)libphy.a
+LIB := $(obj)libphy.o
COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
int i;
for (i = 0; i < bb_miiphy_buses_num; i++) {
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* Relocate the hook pointers*/
BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
+ if (!dev) {
+ printf("Can not allocate memory of rtl8139\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8139#%d", card_number);
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
+ if (!dev) {
+ printf("Can not allocate memory of rtl8169\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
return length;
}
+static int smc_write_hwaddr(struct eth_device *dev)
+{
+ int i;
+
+ swap_to(ETHERNET);
+ SMC_SELECT_BANK (dev, 1);
+#ifdef USE_32_BIT
+ for (i = 0; i < 6; i += 2) {
+ word address;
+
+ address = dev->enetaddr[i + 1] << 8;
+ address |= dev->enetaddr[i];
+ SMC_outw(dev, address, (ADDR0_REG + i));
+ }
+#else
+ for (i = 0; i < 6; i++)
+ SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
+#endif
+ swap_to(FLASH);
+ return 0;
+}
+
/*
* Open and Initialize the board
*
*/
static int smc_init(struct eth_device *dev, bd_t *bd)
{
- int i;
-
swap_to(ETHERNET);
PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
/* SMC_SELECT_BANK(dev, 0); */
/* SMC_outw(dev, 0, RPC_REG); */
- SMC_SELECT_BANK (dev, 1);
-
-#ifdef USE_32_BIT
- for (i = 0; i < 6; i += 2) {
- word address;
-
- address = dev->enetaddr[i + 1] << 8;
- address |= dev->enetaddr[i];
- SMC_outw(dev, address, (ADDR0_REG + i));
- }
-#else
- for (i = 0; i < 6; i++)
- SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
-#endif
printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
return 0;
}
+ memset(dev, 0, sizeof(*dev));
priv->dev_num = dev_num;
dev->priv = priv;
dev->iobase = base_addr;
dev->halt = smc_halt;
dev->send = smc_send;
dev->recv = smc_rcv;
+ dev->write_hwaddr = smc_write_hwaddr;
sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
eth_register(dev);
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
#ifndef CONFIG_TSEC_TBICR_SETTINGS
-#define TBICR_SETTINGS ( \
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
-#else
-#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
#endif /* CONFIG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
- TBICR_SETTINGS);
+ CONFIG_TSEC_TBICR_SETTINGS);
}
/* Discover which PHY is attached to the device, and configure it
for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
-
+ if (!dev) {
+ printf("tsi108: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "TSI108_eth%d", index);
dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007, 2010 Freescale Semiconductor, Inc.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
*
iobase &= ~0xf;
dev = (struct eth_device *)malloc(sizeof *dev);
+ if (!dev) {
+ printf("uli526x: Can not allocate memory\n");
+ break;
+ }
+ memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "uli526x#%d", card_number);
db = (struct uli526x_board_info *)
malloc(sizeof(struct uli526x_board_info));
i));
/* Set Node address */
- if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
+ if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
+ ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
/* SROM absent, so write MAC address to ID Table */
set_mac_addr(dev);
else { /*Exist SROM*/
#include <common.h>
#include <net.h>
#include <config.h>
+#include <malloc.h>
#include <asm/io.h>
#undef DEBUG
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
typedef struct {
- unsigned int baseaddress; /* Base address for device (IPIF) */
- unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
- unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
- unsigned char deviceid; /* Unique ID of device - for future */
+ u32 baseaddress; /* Base address for device (IPIF) */
+ u32 nexttxbuffertouse; /* Next TX buffer to write to */
+ u32 nextrxbuffertouse; /* Next RX buffer to read from */
+ uchar deviceid; /* Unique ID of device - for future */
} xemaclite;
static xemaclite emaclite;
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
-/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
-#ifdef CONFIG_ENV_IS_NOWHERE
-static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
-#else
-static u8 emacaddr[ENET_ADDR_LENGTH];
-#endif
-
-void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
+static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
{
- unsigned int i;
+ u32 i;
u32 alignbuffer;
u32 *to32ptr;
u32 *from32ptr;
}
}
-void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
+static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
{
- unsigned i;
+ u32 i;
u32 alignbuffer;
u32 *to32ptr = (u32 *) destptr;
u32 *from32ptr;
*to32ptr++ = alignbuffer;
}
-void eth_halt (void)
+static void emaclite_halt(struct eth_device *dev)
{
debug ("eth_halt\n");
}
-int eth_init (bd_t * bis)
+static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
- uchar enetaddr[6];
-
debug ("EmacLite Initialization Started\n");
memset (&emaclite, 0, sizeof (xemaclite));
- emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
+ emaclite.baseaddress = dev->iobase;
/*
* TX - TX_PING & TX_PONG initialization
/* Restart PING TX */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
/* Copy MAC address */
- xemaclite_alignedwrite (enetaddr,
+ xemaclite_alignedwrite (dev->enetaddr,
emaclite.baseaddress, ENET_ADDR_LENGTH);
/* Set the length */
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
/* The same operation with PONG TX */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
- xemaclite_alignedwrite (enetaddr, emaclite.baseaddress +
+ xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
return 0;
}
-int xemaclite_txbufferavailable (xemaclite * instanceptr)
+static int xemaclite_txbufferavailable (xemaclite *instanceptr)
{
u32 reg;
u32 txpingbusy;
return (!(txpingbusy && txpongbusy));
}
-int eth_send (volatile void *ptr, int len) {
-
- unsigned int reg;
- unsigned int baseaddress;
+static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
+{
+ u32 reg;
+ u32 baseaddress;
- unsigned maxtry = 1000;
+ u32 maxtry = 1000;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
return 0;
}
-int eth_rx (void)
+static int emaclite_recv(struct eth_device *dev)
{
- unsigned int length;
- unsigned int reg;
- unsigned int baseaddress;
+ u32 length;
+ u32 reg;
+ u32 baseaddress;
baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
#endif
}
/* Get the length of the frame that arrived */
- switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
+ switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
0xFFFF0000 ) >> 16) {
case 0x806:
length = 42 + 20; /* FIXME size of ARP */
break;
case 0x800:
length = 14 + 14 +
- (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
+ (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) &
0xFFFF0000) >> 16); /* FIXME size of IP packet */
debug ("IP Packet\n");
break;
return 1;
}
+
+int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
+{
+ struct eth_device *dev;
+
+ dev = malloc(sizeof(*dev));
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "Xilinx_Emaclite");
+
+ dev->iobase = base_addr;
+ dev->priv = 0;
+ dev->init = emaclite_init;
+ dev->halt = emaclite_halt;
+ dev->send = emaclite_send;
+ dev->recv = emaclite_recv;
+
+ eth_register(dev);
+
+ return 0;
+}
include $(TOPDIR)/config.mk
-LIB := $(obj)libpci.a
+LIB := $(obj)libpci.o
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
+ /* Reset hose to make sure its in a clean state */
+ memset(hose, 0, sizeof(struct pci_controller));
+
pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
return fsl_is_pci_agent(hose);
* 1 == pci agent or pcie end-point
*/
if (!temp8) {
- printf(" Scanning PCI bus %02x\n",
+ debug(" Scanning PCI bus %02x\n",
hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
} else {
- debug(" Not scanning PCI bus %02x. PI=%x\n",
+ debug(" Not scanning PCI bus %02x. PI=%x\n",
hose->current_busno, temp8);
hose->last_busno = hose->current_busno;
}
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
+ pci_dev_t dev = PCI_BDF(busno,0,0);
+ u8 pcie_cap;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
hose->last_busno = hose->first_busno;
}
- printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
- hose->first_busno, hose->last_busno);
+ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+ printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
+ "E" : "", pci_info->pci_num,
+ hose->first_busno, hose->last_busno);
return(hose->last_busno + 1);
}
*
*/
-static struct pci_controller* hose_head = NULL;
+static struct pci_controller* hose_head;
void pci_register_hose(struct pci_controller* hose)
{
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern void pciauto_config_init(struct pci_controller *hose);
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
+const char * pci_class_str(u8 class)
+{
+ switch (class) {
+ case PCI_CLASS_NOT_DEFINED:
+ return "Build before PCI Rev2.0";
+ break;
+ case PCI_BASE_CLASS_STORAGE:
+ return "Mass storage controller";
+ break;
+ case PCI_BASE_CLASS_NETWORK:
+ return "Network controller";
+ break;
+ case PCI_BASE_CLASS_DISPLAY:
+ return "Display controller";
+ break;
+ case PCI_BASE_CLASS_MULTIMEDIA:
+ return "Multimedia device";
+ break;
+ case PCI_BASE_CLASS_MEMORY:
+ return "Memory controller";
+ break;
+ case PCI_BASE_CLASS_BRIDGE:
+ return "Bridge device";
+ break;
+ case PCI_BASE_CLASS_COMMUNICATION:
+ return "Simple comm. controller";
+ break;
+ case PCI_BASE_CLASS_SYSTEM:
+ return "Base system peripheral";
+ break;
+ case PCI_BASE_CLASS_INPUT:
+ return "Input device";
+ break;
+ case PCI_BASE_CLASS_DOCKING:
+ return "Docking station";
+ break;
+ case PCI_BASE_CLASS_PROCESSOR:
+ return "Processor";
+ break;
+ case PCI_BASE_CLASS_SERIAL:
+ return "Serial bus controller";
+ break;
+ case PCI_BASE_CLASS_INTELLIGENT:
+ return "Intelligent controller";
+ break;
+ case PCI_BASE_CLASS_SATELLITE:
+ return "Satellite controller";
+ break;
+ case PCI_BASE_CLASS_CRYPT:
+ return "Cryptographic device";
+ break;
+ case PCI_BASE_CLASS_SIGNAL_PROCESSING:
+ return "DSP";
+ break;
+ case PCI_CLASS_OTHERS:
+ return "Does not fit any class";
+ break;
+ default:
+ return "???";
+ break;
+ };
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
+
int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
unsigned char header_type;
struct pci_config_table *cfg;
pci_dev_t dev;
+#ifdef CONFIG_PCI_SCAN_SHOW
+ static int indent = 0;
+#endif
sub_bus = bus;
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
- if (vendor != 0xffff && vendor != 0x0000) {
+ if (vendor == 0xffff || vendor == 0x0000)
+ continue;
+
+ if (!PCI_FUNC(dev))
+ found_multi = header_type & 0x80;
+
+ debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
+ pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
+ pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ indent++;
- debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
+ /* Print leading space, including bus indentation */
+ printf("%*c", indent + 1, ' ');
- pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+ if (pci_print_dev(hose, dev)) {
+ printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
+ PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
+ vendor, device, pci_class_str(class >> 8));
+ }
+#endif
- cfg = pci_find_config(hose, class, vendor, device,
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
- if (cfg) {
- cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus, hose->current_busno);
+ cfg = pci_find_config(hose, class, vendor, device,
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
+ if (cfg) {
+ cfg->config_device(hose, dev, cfg);
+ sub_bus = max(sub_bus, hose->current_busno);
#ifdef CONFIG_PCI_PNP
- } else {
- int n = pciauto_config_device(hose, dev);
+ } else {
+ int n = pciauto_config_device(hose, dev);
- sub_bus = max(sub_bus, n);
+ sub_bus = max(sub_bus, n);
#endif
- }
- if (hose->fixup_irq)
- hose->fixup_irq(hose, dev);
+ }
#ifdef CONFIG_PCI_SCAN_SHOW
- if (pci_print_dev(hose, dev)) {
- unsigned char int_line;
-
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- &int_line);
- printf(" %02x %02x %04x %04x %04x %02x\n",
- PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
- int_line);
- }
+ indent--;
#endif
- }
+
+ if (hose->fixup_irq)
+ hose->fixup_irq(hose, dev);
}
return sub_bus;
}
#endif /* CONFIG_PCI_BOOTDELAY */
+ hose_head = NULL;
+
/* now call board specific pci_init()... */
pci_init_board();
}
".section __ex_table,\"a\"\n"
" .align 2\n"
" .long 1b,3b\n"
- ".text":"=r"(retval):"r"(addr));
+ ".section .text.__get_pci_config_dword"
+ : "=r"(retval) : "r"(addr));
return (retval);
}
include $(TOPDIR)/config.mk
-LIB := $(obj)libpcmcia.a
+LIB := $(obj)libpcmcia.o
COBJS-$(CONFIG_I82365) += i82365.o
COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libpower.a
+LIB := $(obj)libpower.o
COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o
COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
return i2c_read(chip_no, reg, 1, val, 1);
}
+static int twl6030_gpadc_read_channel(u8 channel_no)
+{
+ u8 lsb = 0;
+ u8 msb = 0;
+ int ret = 0;
+
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb,
+ GPCH0_LSB + channel_no * 2);
+ if (ret)
+ return ret;
+
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb,
+ GPCH0_MSB + channel_no * 2);
+ if (ret)
+ return ret;
+
+ return (msb << 8) | lsb;
+}
+
+static int twl6030_gpadc_sw2_trigger(void)
+{
+ u8 val;
+ int ret = 0;
+
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2);
+ if (ret)
+ return ret;
+
+ /* Waiting until the SW1 conversion ends*/
+ val = CTRL_P2_BUSY;
+
+ while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
+ ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2);
+ if (ret)
+ return ret;
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+void twl6030_stop_usb_charging(void)
+{
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1);
+
+ return;
+}
+
void twl6030_start_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
CHARGERUSB_INT_MASK);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
CHARGERUSB_VOREG);
- twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_100,
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400,
CHARGERUSB_CTRL2);
+ twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1);
/* Enable USB charging */
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
CONTROLLER_CTRL1);
return;
}
+int twl6030_get_battery_current(void)
+{
+ int battery_current = 0;
+ u8 msb = 0;
+ u8 lsb = 0;
+
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11);
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10);
+ battery_current = ((msb << 8) | lsb);
+
+ /* convert 10 bit signed number to 16 bit signed number */
+ if (battery_current >= 0x2000)
+ battery_current = (battery_current - 0x4000);
+
+ battery_current = battery_current * 3000 / 4096;
+ printf("Battery Current: %d mA\n", battery_current);
+
+ return battery_current;
+}
+
+int twl6030_get_battery_voltage(void)
+{
+ int battery_volt = 0;
+ int ret = 0;
+
+ /* Start GPADC SW conversion */
+ ret = twl6030_gpadc_sw2_trigger();
+ if (ret) {
+ printf("Failed to convert battery voltage\n");
+ return ret;
+ }
+
+ /* measure Vbat voltage */
+ battery_volt = twl6030_gpadc_read_channel(7);
+ if (battery_volt < 0) {
+ printf("Failed to read battery voltage\n");
+ return ret;
+ }
+ battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
+ printf("Battery Voltage: %d mV\n", battery_volt);
+
+ return battery_volt;
+}
+
void twl6030_init_battery_charging(void)
{
- twl6030_start_usb_charging();
+ u8 stat1 = 0;
+ int battery_volt = 0;
+ int ret = 0;
+
+ /* Enable VBAT measurement */
+ twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1);
+
+ /* Enable GPADC module */
+ ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1);
+ if (ret) {
+ printf("Failed to enable GPADC\n");
+ return;
+ }
+
+ battery_volt = twl6030_get_battery_voltage();
+ if (battery_volt < 0)
+ return;
+
+ if (battery_volt < 3000)
+ printf("Main battery voltage too low!\n");
+
+ /* Check for the presence of USB charger */
+ twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1);
+
+ /* check for battery presence indirectly via Fuel gauge */
+ if ((stat1 & VBUS_DET) && (battery_volt < 3300))
+ twl6030_start_usb_charging();
+
return;
}
include $(TOPDIR)/config.mk
-LIB := $(obj)qe.a
+LIB := $(obj)libqe.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(and $(CONFIG_QE),$(CONFIG_OF_LIBFDT)) += fdt.o
COBJS-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
COBJS := $(COBJS-y)
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
void ft_qe_setup(void *blob)
{
-#ifdef CONFIG_QE
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
"clock-frequency", gd->qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
-#endif
}
/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
}
static int uec_set_mac_if_mode(uec_private_t *uec,
- enet_interface_type_e if_mode, int speed)
+ enum fsl_phy_enet_if if_mode, int speed)
{
- enet_interface_type_e enet_if_mode;
+ enum fsl_phy_enet_if enet_if_mode;
uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev,
- enet_interface_type_e mode, int speed);
+ enum fsl_phy_enet_if mode, int speed);
uec_regs = uec->uec_regs;
if (mii_info->link) {
}
if (mii_info->speed != uec->oldspeed) {
- enet_interface_type_e mode = \
+ enum fsl_phy_enet_if mode = \
uec->uec_info->enet_interface_type;
if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
switch (mii_info->speed) {
i = 50;
do {
err = curphy->read_status(uec->mii_info);
+ if (!(((i-- > 0) && !uec->mii_info->link) || err))
+ break;
udelay(100000);
- } while (((i-- > 0) && !uec->mii_info->link) || err);
+ } while (1);
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
#include "qe.h"
#include "uccf.h"
+#include <asm/fsl_enet.h>
#define MAX_TX_THREADS 8
#define MAX_RX_THREADS 8
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
} uec_num_of_threads_e;
-/* UEC ethernet interface type
-*/
-typedef enum enet_interface_type {
- MII,
- RMII,
- RGMII,
- GMII,
- RGMII_ID,
- RGMII_RXID,
- RGMII_TXID,
- TBI,
- RTBI,
- SGMII
-} enet_interface_type_e;
-
/* UEC initialization info struct
*/
#define STD_UEC_INFO(num) \
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;
- enet_interface_type_e enet_interface_type;
+ enum fsl_phy_enet_if enet_interface_type;
int speed;
} uec_info_t;
/*
- * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ * Copyright (C) 2005,2010 Freescale Semiconductor, Inc.
*
* Author: Shlomi Gridish
*
static int genmii_config_aneg (struct uec_mii_info *mii_info)
{
if (mii_info->autoneg) {
+ /* Speed up the common case, if link is already up, speed and
+ duplex match, skip auto neg as it already matches */
+ if (!genmii_read_status(mii_info) && mii_info->link)
+ if (mii_info->duplex == DUPLEX_FULL &&
+ mii_info->speed == SPEED_100)
+ if (mii_info->advertising &
+ ADVERTISED_100baseT_Full)
+ return 0;
+
config_genmii_advert (mii_info);
genmii_restart_aneg (mii_info);
} else
status = phy_read(mii_info, PHY_BMSR);
}
mii_info->link = 1;
- udelay(500000); /* another 500 ms (results in faster booting) */
} else {
if (status & PHY_BMSR_LS)
mii_info->link = 1;
{
struct eth_device *edev = mii_info->dev;
uec_private_t *uec = edev->priv;
- enum enet_interface_type iface = uec->uec_info->enet_interface_type;
+ enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type;
int speed = uec->uec_info->speed;
if ((speed == 1000) &&
}
void marvell_phy_interface_mode (struct eth_device *dev,
- enet_interface_type_e type,
+ enum fsl_phy_enet_if type,
int speed
)
{
}
void change_phy_interface_mode (struct eth_device *dev,
- enet_interface_type_e type, int speed)
+ enum fsl_phy_enet_if type, int speed)
{
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode (dev, type, speed);
#CFLAGS += -DDEBUG
-LIB = $(obj)librtc.a
+LIB = $(obj)librtc.o
COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
+COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
unsigned int alarm_hour; /* 0x18 */
unsigned int record; /* 0x1c */
unsigned int cr; /* 0x20 */
+ unsigned int wsec; /* 0x24 */
+ unsigned int wmin; /* 0x28 */
+ unsigned int whour; /* 0x2c */
+ unsigned int wday; /* 0x30 */
+ unsigned int intr; /* 0x34 */
+ unsigned int div; /* 0x38 */
+ unsigned int rev; /* 0x3c */
};
/*
debug("%s(): record register: %x\n",
__func__, readl(&rtc->record));
+#ifdef CONFIG_FTRTC010_PCLK
+ now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT;
+#else /* CONFIG_FTRTC010_EXTCLK */
now = ftrtc010_time() + readl(&rtc->record);
+#endif
to_tm(now, tmp);
--- /dev/null
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file provides Date & Time support (no alarms) for PT7C4338 chip.
+ *
+ * This file is based on drivers/rtc/ds1337.c
+ *
+ * PT7C4338 chip is manufactured by Pericom Technology Inc.
+ * It is a serial real-time clock which provides
+ * 1)Low-power clock/calendar.
+ * 2)Programmable square-wave output.
+ * It has 56 bytes of nonvolatile RAM.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+/* RTC register addresses */
+#define RTC_SEC_REG_ADDR 0x0
+#define RTC_MIN_REG_ADDR 0x1
+#define RTC_HR_REG_ADDR 0x2
+#define RTC_DAY_REG_ADDR 0x3
+#define RTC_DATE_REG_ADDR 0x4
+#define RTC_MON_REG_ADDR 0x5
+#define RTC_YR_REG_ADDR 0x6
+#define RTC_CTL_STAT_REG_ADDR 0x7
+
+/* RTC second register address bit */
+#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+
+/* RTC control and status register bits */
+#define RTC_CTL_STAT_BIT_RS0 0x1 /* Rate select 0 */
+#define RTC_CTL_STAT_BIT_RS1 0x2 /* Rate select 1 */
+#define RTC_CTL_STAT_BIT_SQWE 0x10 /* Square Wave Enable */
+#define RTC_CTL_STAT_BIT_OSF 0x20 /* Oscillator Stop Flag */
+#define RTC_CTL_STAT_BIT_OUT 0x80 /* Output Level Control */
+
+/* RTC reset value */
+#define RTC_PT7C4338_RESET_VAL \
+ (RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
+
+/****** Helper functions ****************************************/
+static u8 rtc_read(u8 reg)
+{
+ return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
+}
+
+static void rtc_write(u8 reg, u8 val)
+{
+ i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+}
+/****************************************************************/
+
+/* Get the current time from the RTC */
+int rtc_get(struct rtc_time *tmp)
+{
+ int ret = 0;
+ u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
+
+ ctl_stat = rtc_read(RTC_CTL_STAT_REG_ADDR);
+ sec = rtc_read(RTC_SEC_REG_ADDR);
+ min = rtc_read(RTC_MIN_REG_ADDR);
+ hour = rtc_read(RTC_HR_REG_ADDR);
+ wday = rtc_read(RTC_DAY_REG_ADDR);
+ mday = rtc_read(RTC_DATE_REG_ADDR);
+ mon = rtc_read(RTC_MON_REG_ADDR);
+ year = rtc_read(RTC_YR_REG_ADDR);
+ debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x control_status: %02x\n",
+ year, mon, mday, wday, hour, min, sec, ctl_stat);
+
+ if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ rtc_write(RTC_CTL_STAT_REG_ADDR,
+ rtc_read(RTC_CTL_STAT_REG_ADDR)\
+ & ~RTC_CTL_STAT_BIT_OSF);
+ ret = -1;
+ }
+
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
+ tmp->tm_mday = bcd2bin(mday & 0x3F);
+ tmp->tm_mon = bcd2bin(mon & 0x1F);
+ tmp->tm_year = bcd2bin(year) + 2000;
+ tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ return ret;
+}
+
+/* Set the RTC */
+int rtc_set(struct rtc_time *tmp)
+{
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+ rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
+ rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
+ rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+ rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+ rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+ rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+
+ return 0;
+}
+
+/* Reset the RTC */
+void rtc_reset(void)
+{
+ rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
+ rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
+}
switch (a) {
case RTC_ENABLE:
- writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON);
+ writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
break;
case RTC_DISABLE:
- writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON);
+ writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
break;
}
}
/* read RTC registers */
do {
- sec = readb(&rtc->BCDSEC);
- min = readb(&rtc->BCDMIN);
- hour = readb(&rtc->BCDHOUR);
- mday = readb(&rtc->BCDDATE);
- wday = readb(&rtc->BCDDAY);
- mon = readb(&rtc->BCDMON);
- year = readb(&rtc->BCDYEAR);
- } while (sec != readb(&rtc->BCDSEC));
+ sec = readb(&rtc->bcdsec);
+ min = readb(&rtc->bcdmin);
+ hour = readb(&rtc->bcdhour);
+ mday = readb(&rtc->bcddate);
+ wday = readb(&rtc->bcdday);
+ mon = readb(&rtc->bcdmon);
+ year = readb(&rtc->bcdyear);
+ } while (sec != readb(&rtc->bcdsec));
/* read ALARM registers */
- a_sec = readb(&rtc->ALMSEC);
- a_min = readb(&rtc->ALMMIN);
- a_hour = readb(&rtc->ALMHOUR);
- a_date = readb(&rtc->ALMDATE);
- a_mon = readb(&rtc->ALMMON);
- a_year = readb(&rtc->ALMYEAR);
- a_armed = readb(&rtc->RTCALM);
+ a_sec = readb(&rtc->almsec);
+ a_min = readb(&rtc->almmin);
+ a_hour = readb(&rtc->almhour);
+ a_date = readb(&rtc->almdate);
+ a_mon = readb(&rtc->almmon);
+ a_year = readb(&rtc->almyear);
+ a_armed = readb(&rtc->rtcalm);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
SetRTC_Access(RTC_ENABLE);
/* write RTC registers */
- writeb(sec, &rtc->BCDSEC);
- writeb(min, &rtc->BCDMIN);
- writeb(hour, &rtc->BCDHOUR);
- writeb(mday, &rtc->BCDDATE);
- writeb(wday, &rtc->BCDDAY);
- writeb(mon, &rtc->BCDMON);
- writeb(year, &rtc->BCDYEAR);
+ writeb(sec, &rtc->bcdsec);
+ writeb(min, &rtc->bcdmin);
+ writeb(hour, &rtc->bcdhour);
+ writeb(mday, &rtc->bcddate);
+ writeb(wday, &rtc->bcdday);
+ writeb(mon, &rtc->bcdmon);
+ writeb(year, &rtc->bcdyear);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
- writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON);
- writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON);
+ writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
+ writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}
#endif
include $(TOPDIR)/config.mk
-LIB := $(obj)libserial.a
+LIB := $(obj)libserial.o
COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
+ * Modified to support C structur SoC access by
+ * Andreas Bießmann <biessmann@corscience.de>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
-#ifndef CONFIG_AT91_LEGACY
-#define CONFIG_AT91_LEGACY
-#warning Please update to use C structur SoC access !
-#endif
#include <watchdog.h>
#include <asm/io.h>
void serial_setbrg(void)
{
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
unsigned long divisor;
unsigned long usart_hz;
*/
usart_hz = get_usart_clk_rate(USART_ID);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
- usart3_writel(BRGR, USART3_BF(CD, divisor));
+ writel(USART3_BF(CD, divisor), &usart->brgr);
}
int serial_init(void)
{
- usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
+ writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN));
- usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
- | USART3_BF(NBSTOP, USART3_NBSTOP_1)));
+ | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
+ &usart->mr);
return 0;
}
void serial_putc(char c)
{
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
if (c == '\n')
serial_putc('\r');
- while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ;
- usart3_writel(THR, c);
+ while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
+ writel(c, &usart->thr);
}
void serial_puts(const char *s)
int serial_getc(void)
{
- while (!(usart3_readl(CSR) & USART3_BIT(RXRDY)))
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
+ while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
WATCHDOG_RESET();
- return usart3_readl(RHR);
+ return readl(&usart->rhr);
}
int serial_tstc(void)
{
- return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0;
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
*
* Copyright (C) 2005-2006 Atmel Corporation
*
+ * Modified to support C structure SoC access by
+ * Andreas Bießmann <biessmann@corscience.de>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
#ifndef __DRIVERS_ATMEL_USART_H__
#define __DRIVERS_ATMEL_USART_H__
-/* USART3 register offsets */
-#define USART3_CR 0x0000
-#define USART3_MR 0x0004
-#define USART3_IER 0x0008
-#define USART3_IDR 0x000c
-#define USART3_IMR 0x0010
-#define USART3_CSR 0x0014
-#define USART3_RHR 0x0018
-#define USART3_THR 0x001c
-#define USART3_BRGR 0x0020
-#define USART3_RTOR 0x0024
-#define USART3_TTGR 0x0028
-#define USART3_FIDI 0x0040
-#define USART3_NER 0x0044
-#define USART3_XXR 0x0048
-#define USART3_IFR 0x004c
-#define USART3_RPR 0x0100
-#define USART3_RCR 0x0104
-#define USART3_TPR 0x0108
-#define USART3_TCR 0x010c
-#define USART3_RNPR 0x0110
-#define USART3_RNCR 0x0114
-#define USART3_TNPR 0x0118
-#define USART3_TNCR 0x011c
-#define USART3_PTCR 0x0120
-#define USART3_PTSR 0x0124
+/* USART3 register footprint */
+typedef struct atmel_usart3 {
+ u32 cr;
+ u32 mr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 csr;
+ u32 rhr;
+ u32 thr;
+ u32 brgr;
+ u32 rtor;
+ u32 ttgr;
+ u32 reserved0[5];
+ u32 fidi;
+ u32 ner;
+ u32 reserved1;
+ u32 ifr;
+ u32 man;
+ u32 reserved2[54]; /* version and PDC not needed */
+} atmel_usart3_t;
/* Bitfields in CR */
#define USART3_RSTRX_OFFSET 2
<< USART3_##name##_OFFSET)) \
| USART3_BF(name,value))
-/* Register access macros */
-#define usart3_readl(reg) \
- readl((void *)USART_BASE + USART3_##reg)
-#define usart3_writel(reg,value) \
- writel((value), (void *)USART_BASE + USART3_##reg)
-
#endif /* __DRIVERS_ATMEL_USART_H__ */
#define serial_in(y) readb(y)
#endif
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER 0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
void NS16550_init (NS16550_t com_port, int baud_divisor)
{
- serial_out(0x00, &com_port->ier);
+ serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
- serial_out(0x00, &com_port->ier);
+ serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
serial_out(0, &com_port->dll);
serial_out(0, &com_port->dlm);
{
while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0);
serial_out(c, &com_port->thr);
+
+ /*
+ * Call watchdog_reset() upon newline. This is done here in putc
+ * since the environment code uses a single puts() to print the complete
+ * environment upon "printenv". So we can't put this watchdog call
+ * in puts().
+ */
+ if (c == '\n')
+ WATCHDOG_RESET();
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
#include <asm/arch/s3c6400.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SERIAL1
#define UART_NR S3C64XX_UART0
void serial_setbrg(void)
{
- DECLARE_GLOBAL_DATA_PTR;
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
u32 pclk = get_PCLK();
u32 baudrate = gd->baudrate;
#endif
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/kirkwood.h>
-#endif
-#ifdef CONFIG_ORION5X
+#elif defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
+#elif defined(CONFIG_ARMADA100)
+#include <asm/arch/armada100.h>
#endif
#if defined (CONFIG_SERIAL_MULTI)
*/
#include <common.h>
+#include <watchdog.h>
#ifdef CONFIG_MX31
#include <asm/arch/mx31.h>
#else
int serial_getc (void)
{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
}
__REG(UART_PHYS + UTXD) = c;
/* wait for transmitter to be ready */
- while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+ WATCHDOG_RESET();
/* If \n, also do \r */
if (c == '\n')
#include <common.h>
#include <watchdog.h>
-
+#include <asm/io.h>
#include "serial_pl01x.h"
-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned int *)(addr))
-
/*
* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
* Versatile PB has four UARTs.
*/
#define CONSOLE_PORT CONFIG_CONS_INDEX
-#define baudRate CONFIG_BAUDRATE
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
static void pl01x_putc (int portnum, char c);
static int pl01x_getc (int portnum);
static int pl01x_tstc (int portnum);
+unsigned int baudrate = CONFIG_BAUDRATE;
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_regs *pl01x_get_regs(int portnum)
+{
+ return (struct pl01x_regs *) port[portnum];
+}
#ifdef CONFIG_PL010_SERIAL
int serial_init (void)
{
+ struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int divisor;
- /*
- ** First, disable everything.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
+ /* First, disable everything */
+ writel(0, ®s->pl010_cr);
- /*
- ** Set baud rate
- **
- */
- switch (baudRate) {
+ /* Set baud rate */
+ switch (baudrate) {
case 9600:
divisor = UART_PL010_BAUD_9600;
break;
divisor = UART_PL010_BAUD_38400;
}
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
- ((divisor & 0xf00) >> 8));
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
+ writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
+ writel(divisor & 0xff, ®s->pl010_lcrl);
- /*
- ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
- (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
+ /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
+ writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
- /*
- ** Finally, enable the UART
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
+ /* Finally, enable the UART */
+ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
return 0;
}
int serial_init (void)
{
+ struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int temp;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
- /*
- ** First, disable everything.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
+ /* First, disable everything */
+ writel(0, ®s->pl011_cr);
/*
- ** Set baud rate
- **
- ** IBRD = UART_CLK / (16 * BAUD_RATE)
- ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
+ * Set baud rate
+ *
+ * IBRD = UART_CLK / (16 * BAUD_RATE)
+ * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
*/
- temp = 16 * baudRate;
+ temp = 16 * baudrate;
divider = CONFIG_PL011_CLOCK / temp;
remainder = CONFIG_PL011_CLOCK % temp;
- temp = (8 * remainder) / baudRate;
+ temp = (8 * remainder) / baudrate;
fraction = (temp >> 1) + (temp & 1);
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
+ writel(divider, ®s->pl011_ibrd);
+ writel(fraction, ®s->pl011_fbrd);
- /*
- ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
- (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
+ /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
+ writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
+ ®s->pl011_lcrh);
- /*
- ** Finally, enable the UART
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
- (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
- UART_PL011_CR_RXE));
+ /* Finally, enable the UART */
+ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
+ ®s->pl011_cr);
return 0;
}
void serial_setbrg (void)
{
+ baudrate = gd->baudrate;
+ serial_init();
}
static void pl01x_putc (int portnum, char c)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
/* Wait until there is space in the FIFO */
- while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
+ while (readl(®s->fr) & UART_PL01x_FR_TXFF)
WATCHDOG_RESET();
/* Send the character */
- IO_WRITE (port[portnum] + UART_PL01x_DR, c);
+ writel(c, ®s->dr);
}
static int pl01x_getc (int portnum)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
unsigned int data;
/* Wait until there is data in the FIFO */
- while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
+ while (readl(®s->fr) & UART_PL01x_FR_RXFE)
WATCHDOG_RESET();
- data = IO_READ (port[portnum] + UART_PL01x_DR);
+ data = readl(®s->dr);
/* Check for an error flag */
if (data & 0xFFFFFF00) {
/* Clear the error */
- IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+ writel(0xFFFFFFFF, ®s->ecr);
return -1;
}
static int pl01x_tstc (int portnum)
{
+ struct pl01x_regs *regs = pl01x_get_regs(portnum);
+
WATCHDOG_RESET();
- return !(IO_READ (port[portnum] + UART_PL01x_FR) &
- UART_PL01x_FR_RXFE);
+ return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
* Definitions common to both PL010 & PL011
*
*/
-#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */
-#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */
-#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */
-#define UART_PL01x_FR 0x18 /* Flag register (Read only). */
+
+#ifndef __ASSEMBLY__
+/*
+ * We can use a combined structure for PL010 and PL011, because they overlap
+ * only in common registers.
+ */
+struct pl01x_regs {
+ u32 dr; /* 0x00 Data register */
+ u32 ecr; /* 0x04 Error clear register (Write) */
+ u32 pl010_lcrh; /* 0x08 Line control register, high byte */
+ u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
+ u32 pl010_lcrl; /* 0x10 Line control register, low byte */
+ u32 pl010_cr; /* 0x14 Control register */
+ u32 fr; /* 0x18 Flag register (Read only) */
+ u32 reserved;
+ u32 ilpr; /* 0x20 IrDA low-power counter register */
+ u32 pl011_ibrd; /* 0x24 Integer baud rate register */
+ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
+ u32 pl011_lcrh; /* 0x2C Line control register */
+ u32 pl011_cr; /* 0x30 Control register */
+};
+#endif
#define UART_PL01x_RSR_OE 0x08
#define UART_PL01x_RSR_BE 0x04
* PL010 definitions
*
*/
-#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */
-#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */
-#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */
-#define UART_PL010_CR 0x14 /* Control register. */
-#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */
-#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */
-#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */
-
#define UART_PL010_CR_LPE (1 << 7)
#define UART_PL010_CR_RTIE (1 << 6)
#define UART_PL010_CR_TIE (1 << 5)
* PL011 definitions
*
*/
-#define UART_PL011_IBRD 0x24
-#define UART_PL011_FBRD 0x28
-#define UART_PL011_LCRH 0x2C
-#define UART_PL011_CR 0x30
-#define UART_PL011_IMSC 0x38
-#define UART_PL011_PERIPH_ID0 0xFE0
-
#define UART_PL011_LCRH_SPS (1 << 7)
#define UART_PL011_LCRH_WLEN_8 (3 << 5)
#define UART_PL011_LCRH_WLEN_7 (2 << 5)
#include <watchdog.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
switch (uart_index) {
case FFUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_22_FFUART;
+ writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
#else
- CKEN |= CKEN6_FFUART;
+ writel(readl(CKEN) | CKEN6_FFUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- FFIER = 0; /* Disable for now */
- FFFCR = 0; /* No fifos enabled */
+ writel(0, FFIER); /* Disable for now */
+ writel(0, FFFCR); /* No fifos enabled */
/* set baud rate */
- FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
- FFDLL = quot & 0xff;
- FFDLH = quot >> 8;
- FFLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
+ writel(quot & 0xff, FFDLL);
+ writel(quot >> 8, FFDLH);
+ writel(LCR_WLS0 | LCR_WLS1, FFLCR);
- FFIER = IER_UUE; /* Enable FFUART */
+ writel(IER_UUE, FFIER); /* Enable FFUART */
break;
case BTUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_21_BTUART;
+ writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
#else
- CKEN |= CKEN7_BTUART;
+ writel(readl(CKEN) | CKEN7_BTUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- BTIER = 0;
- BTFCR = 0;
+ writel(0, BTIER);
+ writel(0, BTFCR);
/* set baud rate */
- BTLCR = LCR_DLAB;
- BTDLL = quot & 0xff;
- BTDLH = quot >> 8;
- BTLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_DLAB, BTLCR);
+ writel(quot & 0xff, BTDLL);
+ writel(quot >> 8, BTDLH);
+ writel(LCR_WLS0 | LCR_WLS1, BTLCR);
- BTIER = IER_UUE; /* Enable BFUART */
+ writel(IER_UUE, BTIER); /* Enable BFUART */
break;
case STUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_23_STUART;
+ writel(readl(CKENA) | CKENA_23_STUART, CKENA);
#else
- CKEN |= CKEN5_STUART;
+ writel(readl(CKEN) | CKEN5_STUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- STIER = 0;
- STFCR = 0;
+ writel(0, STIER);
+ writel(0, STFCR);
/* set baud rate */
- STLCR = LCR_DLAB;
- STDLL = quot & 0xff;
- STDLH = quot >> 8;
- STLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_DLAB, STLCR);
+ writel(quot & 0xff, STDLL);
+ writel(quot >> 8, STDLH);
+ writel(LCR_WLS0 | LCR_WLS1, STLCR);
- STIER = IER_UUE; /* Enable STUART */
+ writel(IER_UUE, STIER); /* Enable STUART */
break;
default:
switch (uart_index) {
case FFUART_INDEX:
/* wait for room in the tx FIFO on FFUART */
- while ((FFLSR & LSR_TEMT) == 0)
+ while ((readl(FFLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- FFTHR = c;
+ writel(c, FFTHR);
break;
case BTUART_INDEX:
- while ((BTLSR & LSR_TEMT ) == 0 )
+ while ((readl(BTLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- BTTHR = c;
+ writel(c, BTTHR);
break;
case STUART_INDEX:
- while ((STLSR & LSR_TEMT ) == 0 )
+ while ((readl(STLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- STTHR = c;
+ writel(c, STTHR);
break;
}
{
switch (uart_index) {
case FFUART_INDEX:
- return FFLSR & LSR_DR;
+ return readl(FFLSR) & LSR_DR;
case BTUART_INDEX:
- return BTLSR & LSR_DR;
+ return readl(BTLSR) & LSR_DR;
case STUART_INDEX:
- return STLSR & LSR_DR;
+ return readl(STLSR) & LSR_DR;
}
return -1;
}
{
switch (uart_index) {
case FFUART_INDEX:
- while (!(FFLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) FFRBR & 0xff;
+ while (!(readl(FFLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(FFRBR) & 0xff;
case BTUART_INDEX:
- while (!(BTLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) BTRBR & 0xff;
+ while (!(readl(BTLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(BTRBR) & 0xff;
case STUART_INDEX:
- while (!(STLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) STRBR & 0xff;
+ while (!(readl(STLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(STRBR) & 0xff;
}
return -1;
}
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
- writel(reg, &uart->UBRDIV);
+ writel(reg, &uart->ubrdiv);
for (i = 0; i < 100; i++)
/* Delay */ ;
}
#endif
/* FIFO enable, Tx/Rx FIFO clear */
- writel(0x07, &uart->UFCON);
- writel(0x0, &uart->UMCON);
+ writel(0x07, &uart->ufcon);
+ writel(0x0, &uart->umcon);
/* Normal,No parity,1 stop,8 bit */
- writel(0x3, &uart->ULCON);
+ writel(0x3, &uart->ulcon);
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- writel(0x245, &uart->UCON);
+ writel(0x245, &uart->ucon);
#ifdef CONFIG_HWFLOW
- writel(0x1, &uart->UMCON); /* RTS up */
+ writel(0x1, &uart->umcon); /* rts up */
#endif
/* FIXME: This is sooooooooooooooooooo ugly */
#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
/* we need auto hw flow control on the gsm and gps port */
if (dev_index == 0 || dev_index == 1)
- writel(0x10, &uart->UMCON);
+ writel(0x10, &uart->umcon);
#endif
_serial_setbrg(dev_index);
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- while (!(readl(&uart->UTRSTAT) & 0x1))
+ while (!(readl(&uart->utrstat) & 0x1))
/* wait for character to arrive */ ;
- return readb(&uart->URXH) & 0xff;
+ return readb(&uart->urxh) & 0xff;
}
#if defined(CONFIG_SERIAL_MULTI)
return;
#endif
- while (!(readl(&uart->UTRSTAT) & 0x2))
+ while (!(readl(&uart->utrstat) & 0x2))
/* wait for room in the tx FIFO */ ;
#ifdef CONFIG_HWFLOW
- while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+ while (hwflow && !(readl(&uart->umstat) & 0x1))
/* Wait for CTS up */ ;
#endif
- writeb(c, &uart->UTXH);
+ writeb(c, &uart->utxh);
/* If \n, also do \r */
if (c == '\n')
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- return readl(&uart->UTRSTAT) & 0x1;
+ return readl(&uart->utrstat) & 0x1;
}
#if defined(CONFIG_SERIAL_MULTI)
#include <asm/arch/clk.h>
#include <serial.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
{
u32 offset = dev_index * sizeof(struct s5p_uart);
void serial_setbrg_dev(const int dev_index)
{
- DECLARE_GLOBAL_DATA_PTR;
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
u32 uclk = get_uart_clk(dev_index);
u32 baudrate = gd->baudrate;
#include <asm/io.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE SCIF0_BASE
#elif defined(CONFIG_CONS_SCIF1)
void serial_setbrg(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
}
include $(TOPDIR)/config.mk
-LIB := $(obj)libspi.a
+LIB := $(obj)libspi.o
COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
+COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SPI_GPIO) += spi_gpio.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/*
* Driver for Blackfin On-Chip SPI device
*
- * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <spi.h>
#include <asm/blackfin.h>
+#include <asm/dma.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/spi.h>
SSYNC();
}
+#ifdef __ADSPBF54x__
+# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
+#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
+ defined(__ADSPBF538__) || defined(__ADSPBF539__)
+# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
+#elif defined(__ADSPBF561__)
+# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
+ defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
+#else
+# error "Please provide SPI DMA channel defines"
+#endif
+static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
+
#ifndef CONFIG_BFIN_SPI_IDLE_VAL
# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
#endif
+#ifdef CONFIG_BFIN_SPI_NO_DMA
+# define SPI_DMA 0
+#else
+# define SPI_DMA 1
+#endif
+
+static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
+ uint bytes)
+{
+ int ret = -1;
+ u16 ndsize, spi_config, dma_config;
+ struct dmasg dmasg[2];
+ const u8 *buf;
+
+ if (tx) {
+ debug("%s: doing half duplex TX\n", __func__);
+ buf = tx;
+ spi_config = TDBR_DMA;
+ dma_config = 0;
+ } else {
+ debug("%s: doing half duplex RX\n", __func__);
+ buf = rx;
+ spi_config = RDBR_DMA;
+ dma_config = WNR;
+ }
+
+ dmasg[0].start_addr = (unsigned long)buf;
+ dmasg[0].x_modify = 1;
+ dma_config |= WDSIZE_8 | DMAEN;
+ if (bytes <= 65536) {
+ blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
+ ndsize = NDSIZE_5;
+ dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
+ dmasg[0].x_count = bytes;
+ } else {
+ blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
+ ndsize = NDSIZE_7;
+ dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
+ dmasg[0].x_count = 0; /* 2^16 */
+ dmasg[0].y_count = bytes >> 16; /* count / 2^16 */
+ dmasg[0].y_modify = 1;
+ dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
+ dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
+ dmasg[1].x_count = bytes & 0xFFFF; /* count % 2^16 */
+ dmasg[1].x_modify = 1;
+ }
+
+ dma->cfg = 0;
+ dma->irq_status = DMA_DONE | DMA_ERR;
+ dma->curr_desc_ptr = dmasg;
+ write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
+ write_SPI_STAT(bss, -1);
+ SSYNC();
+
+ write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
+ dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
+ write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
+ SSYNC();
+
+ /*
+ * We already invalidated the first 64k,
+ * now while we just wait invalidate the remaining part.
+ * Its not likely that the DMA is going to overtake
+ */
+ if (bytes > 65536)
+ blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
+
+ while (!(dma->irq_status & DMA_DONE))
+ if (ctrlc())
+ goto done;
+
+ dma->cfg = 0;
+
+ ret = 0;
+ done:
+ write_SPI_CTL(bss, bss->ctl);
+ return ret;
+}
+
+static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
+ uint bytes)
+{
+ /* todo: take advantage of hardware fifos */
+ while (bytes--) {
+ u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
+ debug("%s: tx:%x ", __func__, value);
+ write_SPI_TDBR(bss, value);
+ SSYNC();
+ while ((read_SPI_STAT(bss) & TXS))
+ if (ctrlc())
+ return -1;
+ while (!(read_SPI_STAT(bss) & SPIF))
+ if (ctrlc())
+ return -1;
+ while (!(read_SPI_STAT(bss) & RXS))
+ if (ctrlc())
+ return -1;
+ value = read_SPI_RDBR(bss);
+ if (rx)
+ *rx++ = value;
+ debug("rx:%x\n", value);
+ }
+
+ return 0;
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
- /* todo: take advantage of hardware fifos and setup RX dma */
- while (bytes--) {
- u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
- debug("%s: tx:%x ", __func__, value);
- write_SPI_TDBR(bss, value);
- SSYNC();
- while ((read_SPI_STAT(bss) & TXS))
- if (ctrlc()) {
- ret = -1;
- goto done;
- }
- while (!(read_SPI_STAT(bss) & SPIF))
- if (ctrlc()) {
- ret = -1;
- goto done;
- }
- while (!(read_SPI_STAT(bss) & RXS))
- if (ctrlc()) {
- ret = -1;
- goto done;
- }
- value = read_SPI_RDBR(bss);
- if (rx)
- *rx++ = value;
- debug("rx:%x\n", value);
- }
+ /* TX DMA doesn't work quite right */
+ if (SPI_DMA && bytes > 6 && (!tx /*|| !rx*/))
+ ret = spi_dma_xfer(bss, tx, rx, bytes);
+ else
+ ret = spi_pio_xfer(bss, tx, rx, bytes);
done:
if (flags & SPI_XFER_END)
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
+#include <mxc_gpio.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
#define MXC_CSPICTRL_MAXBITS 0x1f
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 4
static unsigned long spi_bases[] = {
0x43fa4000,
0x53f84000,
};
-#define OUT MX31_GPIO_DIRECTION_OUT
-#define mxc_gpio_direction mx31_gpio_direction
-#define mxc_gpio_set mx31_gpio_set
#elif defined(CONFIG_MX51)
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
CSPI2_BASE_ADDR,
CSPI3_BASE_ADDR,
};
-#define mxc_gpio_direction(gpio, dir) (0)
-#define mxc_gpio_set(gpio, value) {}
-#define OUT 1
#else
#error "Unsupported architecture"
#endif
+#define OUT MXC_GPIO_DIRECTION_OUT
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 cfg_reg;
#endif
int gpio;
+ int ss_pol;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
- mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+ mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
}
void spi_cs_deactivate(struct spi_slave *slave)
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
- !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+ !(mxcs->ss_pol));
}
#ifdef CONFIG_MX51
if (mode & SPI_CS_HIGH)
ss_pol = 1;
- if (!(mode & SPI_CPOL))
+ if (mode & SPI_CPOL)
sclkpol = 1;
if (mode & SPI_CPHA)
}
#endif
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
- unsigned long flags)
+int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
+ const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ int nbytes = (bitlen + 7) / 8;
+ u32 data, cnt, i;
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ debug("%s: bitlen %d dout 0x%x din 0x%x\n",
+ __func__, bitlen, (u32)dout, (u32)din);
mxcs->ctrl_reg = (mxcs->ctrl_reg &
~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
reg_write(mxcs->base + MXC_CSPISTAT,
MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- debug("Sending SPI 0x%x\n", data);
- reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ /*
+ * The SPI controller works only with words,
+ * check if less than a word is sent.
+ * Access to the FIFO is only 32 bit
+ */
+ if (bitlen % 32) {
+ data = 0;
+ cnt = (bitlen % 32) / 8;
+ if (dout) {
+ for (i = 0; i < cnt; i++) {
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ }
+ debug("Sending SPI 0x%x\n", data);
+
+ reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ nbytes -= cnt;
+ }
+
+ data = 0;
+
+ while (nbytes > 0) {
+ data = 0;
+ if (dout) {
+ /* Buffer is not 32-bit aligned */
+ if ((unsigned long)dout & 0x03) {
+ data = 0;
+ for (i = 0; i < 4; i++, data <<= 8) {
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ } else {
+ data = *(u32 *)dout;
+ data = cpu_to_be32(data);
+ }
+ dout += 4;
+ }
+ debug("Sending SPI 0x%x\n", data);
+ reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ nbytes -= 4;
+ }
/* FIFO is written, now starts the transfer setting the XCH bit */
reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
reg_write(mxcs->base + MXC_CSPISTAT,
MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- data = reg_read(mxcs->base + MXC_CSPIRXDATA);
- debug("SPI Rx: 0x%x\n", data);
+ nbytes = (bitlen + 7) / 8;
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ cnt = nbytes % 32;
+
+ if (bitlen % 32) {
+ data = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ cnt = (bitlen % 32) / 8;
+ debug("SPI Rx unaligned: 0x%x\n", data);
+ if (din) {
+ for (i = 0; i < cnt; i++, data >>= 8) {
+ *din++ = data & 0xFF;
+ }
+ }
+ nbytes -= cnt;
+ }
- return data;
+ while (nbytes > 0) {
+ u32 tmp;
+ tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ data = cpu_to_be32(tmp);
+ debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
+ cnt = min(nbytes, sizeof(data));
+ if (din) {
+ memcpy(din, &data, cnt);
+ din += cnt;
+ }
+ nbytes -= cnt;
+ }
+
+ return 0;
}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
- int n_blks = (bitlen + 31) / 32;
- u32 *out_l, *in_l;
- int i;
+ int n_bytes = (bitlen + 7) / 8;
+ int n_bits;
+ int ret;
+ u32 blk_size;
+ u8 *p_outbuf = (u8 *)dout;
+ u8 *p_inbuf = (u8 *)din;
- if ((int)dout & 3 || (int)din & 3) {
- printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
- return 1;
- }
+ if (!slave)
+ return -1;
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ while (n_bytes > 0) {
+
+ if (n_bytes < MAX_SPI_BYTES)
+ blk_size = n_bytes;
+ else
+ blk_size = MAX_SPI_BYTES;
+
+ n_bits = blk_size * 8;
- /* This driver is currently partly broken, alert the user */
- if (bitlen > 16 && (bitlen % 32)) {
- printf("Error: SPI transfer with bitlen=%d is broken.\n",
- bitlen);
- return 1;
+ ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
+
+ if (ret)
+ return ret;
+ if (dout)
+ p_outbuf += blk_size;
+ if (din)
+ p_inbuf += blk_size;
+ n_bytes -= blk_size;
}
- for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
- i < n_blks;
- i++, in_l++, out_l++, bitlen -= 32) {
- u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
-
- /* Check if we're only transfering 8 or 16 bits */
- if (!i) {
- if (bitlen < 9)
- *(u8 *)din = data;
- else if (bitlen < 17)
- *(u16 *)din = data;
- else
- *in_l = data;
- }
+ if (flags & SPI_XFER_END) {
+ spi_cs_deactivate(slave);
}
return 0;
return NULL;
mxcs = malloc(sizeof(struct mxc_spi_slave));
- if (!mxcs)
+ if (!mxcs) {
+ puts("mxc_spi: SPI Slave not allocated !\n");
return NULL;
+ }
ret = decode_cs(mxcs, cs);
if (ret < 0) {
mxcs->slave.bus = bus;
mxcs->slave.cs = cs;
mxcs->base = spi_bases[bus];
+ mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
#ifdef CONFIG_MX51
/* Can be used for i.MX31 too ? */
if (mode & SPI_CPHA)
ctrl_reg |= MXC_CSPICTRL_PHA;
- if (!(mode & SPI_CPOL))
+ if (mode & SPI_CPOL)
ctrl_reg |= MXC_CSPICTRL_POL;
if (mode & SPI_CS_HIGH)
ctrl_reg |= MXC_CSPICTRL_SSPOL;
--- /dev/null
+/*
+ * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
+ *
+ * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Parts taken from linux/drivers/spi/omap2_mcspi.c
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ *
+ * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include "omap3_spi.h"
+
+#define WORD_LEN 8
+#define SPI_WAIT_TIMEOUT 3000000;
+
+static void spi_reset(struct omap3_spi_slave *ds)
+{
+ unsigned int tmp;
+
+ writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
+ do {
+ tmp = readl(&ds->regs->sysstatus);
+ } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
+
+ writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
+ OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
+ OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
+ &ds->regs->sysconfig);
+
+ writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
+}
+
+void spi_init()
+{
+ /* do nothing */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct omap3_spi_slave *ds;
+
+ ds = malloc(sizeof(struct omap3_spi_slave));
+ if (!ds) {
+ printf("SPI error: malloc of SPI structure failed\n");
+ return NULL;
+ }
+
+ /*
+ * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+ * with different number of chip selects (CS, channels):
+ * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+ * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+ * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+ * McSPI4 has 1 CS (bus 3, cs 0)
+ */
+
+ switch (bus) {
+ case 0:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
+ break;
+ case 1:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
+ break;
+ case 2:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
+ break;
+ case 3:
+ ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
+ break;
+ default:
+ printf("SPI error: unsupported bus %i. \
+ Supported busses 0 - 3\n", bus);
+ return NULL;
+ }
+ ds->slave.bus = bus;
+
+ if (((bus == 0) && (cs > 3)) ||
+ ((bus == 1) && (cs > 1)) ||
+ ((bus == 2) && (cs > 1)) ||
+ ((bus == 3) && (cs > 0))) {
+ printf("SPI error: unsupported chip select %i \
+ on bus %i\n", cs, bus);
+ return NULL;
+ }
+ ds->slave.cs = cs;
+
+ if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
+ printf("SPI error: unsupported frequency %i Hz. \
+ Max frequency is 48 Mhz\n", max_hz);
+ return NULL;
+ }
+ ds->freq = max_hz;
+
+ if (mode > SPI_MODE_3) {
+ printf("SPI error: unsupported SPI mode %i\n", mode);
+ return NULL;
+ }
+ ds->mode = mode;
+
+ return &ds->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+
+ free(ds);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ unsigned int conf, div = 0;
+
+ /* McSPI global module configuration */
+
+ /*
+ * setup when switching from (reset default) slave mode
+ * to single-channel master mode
+ */
+ spi_reset(ds);
+ conf = readl(&ds->regs->modulctrl);
+ conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
+ conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
+ writel(conf, &ds->regs->modulctrl);
+
+ /* McSPI individual channel configuration */
+
+ /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
+ if (ds->freq) {
+ while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
+ > ds->freq)
+ div++;
+ } else
+ div = 0xC;
+
+ conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
+ * REVISIT: this controller could support SPI_3WIRE mode.
+ */
+ conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+ conf |= OMAP3_MCSPI_CHCONF_DPE0;
+
+ /* wordlength */
+ conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
+ conf |= (WORD_LEN - 1) << 7;
+
+ /* set chipselect polarity; manage with FORCE */
+ if (!(ds->mode & SPI_CS_HIGH))
+ conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
+
+ /* set clock divisor */
+ conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
+ conf |= div << 2;
+
+ /* set SPI mode 0..3 */
+ if (ds->mode & SPI_CPOL)
+ conf |= OMAP3_MCSPI_CHCONF_POL;
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_POL;
+ if (ds->mode & SPI_CPHA)
+ conf |= OMAP3_MCSPI_CHCONF_PHA;
+ else
+ conf &= ~OMAP3_MCSPI_CHCONF_PHA;
+
+ /* Transmit & receive mode */
+ conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+
+ writel(conf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+
+ /* Reset the SPI hardware */
+ spi_reset(ds);
+}
+
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+ unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ int i;
+ int timeout = SPI_WAIT_TIMEOUT;
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN)
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ for (i = 0; i < len; i++) {
+ /* wait till TX register is empty (TXS == 1) */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_TXS)) {
+ if (--timeout <= 0) {
+ printf("SPI TXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Write the data */
+ writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+ }
+
+ if (flags & SPI_XFER_END) {
+ /* wait to finish of transfer */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_EOT));
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+ return 0;
+}
+
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+ unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ int i;
+ int timeout = SPI_WAIT_TIMEOUT;
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN)
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+
+ chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+ chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].tx);
+
+ for (i = 0; i < len; i++) {
+ /* Wait till RX register contains data (RXS == 1) */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_RXS)) {
+ if (--timeout <= 0) {
+ printf("SPI RXS timed out, status=0x%08x\n",
+ readl(&ds->regs->channel[ds->slave.cs].chstat));
+ return -1;
+ }
+ }
+ /* Read the data */
+ rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+ }
+
+ if (flags & SPI_XFER_END) {
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct omap3_spi_slave *ds = to_omap3_spi(slave);
+ unsigned int len;
+ const u8 *txp = dout;
+ u8 *rxp = din;
+ int ret = -1;
+
+ if (bitlen % 8)
+ return -1;
+
+ len = bitlen / 8;
+
+ if (bitlen == 0) { /* only change CS */
+ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+ if (flags & SPI_XFER_BEGIN) {
+ writel(OMAP3_MCSPI_CHCTRL_EN,
+ &ds->regs->channel[ds->slave.cs].chctrl);
+ chconf |= OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf,
+ &ds->regs->channel[ds->slave.cs].chconf);
+ }
+ if (flags & SPI_XFER_END) {
+ chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
+ writel(chconf,
+ &ds->regs->channel[ds->slave.cs].chconf);
+ writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ }
+ ret = 0;
+ } else {
+ if (dout != NULL)
+ ret = omap3_spi_write(slave, len, txp, flags);
+
+ if (din != NULL)
+ ret = omap3_spi_read(slave, len, rxp, flags);
+ }
+ return ret;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
--- /dev/null
+/*
+ * Register definitions for the OMAP3 McSPI Controller
+ *
+ * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
+ *
+ * Parts taken from linux/drivers/spi/omap2_mcspi.c
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ *
+ * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP3_SPI_H_
+#define _OMAP3_SPI_H_
+
+#define OMAP3_MCSPI1_BASE 0x48098000
+#define OMAP3_MCSPI2_BASE 0x4809A000
+#define OMAP3_MCSPI3_BASE 0x480B8000
+#define OMAP3_MCSPI4_BASE 0x480BA000
+
+#define OMAP3_MCSPI_MAX_FREQ 48000000
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+ unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
+ unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
+ unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
+ unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
+ unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned int irqstatus; /* 0x18 */
+ unsigned int irqenable; /* 0x1C */
+ unsigned int wakeupenable; /* 0x20 */
+ unsigned int syst; /* 0x24 */
+ unsigned int modulctrl; /* 0x28 */
+ struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+ /* channel1: 0x40 - 0x50, bus 0 & 1 */
+ /* channel2: 0x54 - 0x64, bus 0 & 1 */
+ /* channel3: 0x68 - 0x78, bus 0 */
+};
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
+#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
+#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
+
+#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
+#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
+#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
+#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
+#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
+#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
+#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
+#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
+#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
+#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
+
+#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
+
+struct omap3_spi_slave {
+ struct spi_slave slave;
+ struct mcspi *regs;
+ unsigned int freq;
+ unsigned int mode;
+};
+
+static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct omap3_spi_slave, slave);
+}
+
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+ unsigned long flags);
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+ unsigned long flags);
+
+#endif /* _OMAP3_SPI_H_ */
include $(TOPDIR)/config.mk
-LIB := $(obj)libtws.a
+LIB := $(obj)libtws.o
COBJS-$(CONFIG_SOFT_TWS) += soft_tws.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libusb_gadget.a
+LIB := $(obj)libusb_gadget.o
# new USB gadget layer dependencies
ifdef CONFIG_USB_GADGET
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
cp->bmAttributes |= USB_CONFIG_ATT_ONE;
return len;
}
-
dprintf("%s\n", __func__);
dprintf("rx status %d, len %d\n", req->status, req->actual);
+<<<<<<< HEAD
packet_received=1;
if (!req)
return;
}
req->actual = length;
dev->rx_req=req;
+=======
+ packet_received = 1;
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
}
dev->tx_req = usb_ep_alloc_request (dev->in_ep, 0);
if (!dev->tx_req)
- goto fail;
+ goto fail1;
dev->rx_req = usb_ep_alloc_request (dev->out_ep, 0);
if (!dev->rx_req)
- goto fail;
+ goto fail2;
return 0;
+<<<<<<< HEAD
fail:
DEBUG (dev, "can't alloc requests\n");
+=======
+fail2:
+ usb_ep_free_request(dev->in_ep, dev->tx_req);
+fail1:
+ error("can't alloc requests");
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
return -1;
}
usb_gadget_handle_interrupts();
dev->network_started = 0;
- dev->tx_req = NULL;
- dev->rx_req = NULL;
packet_received = 0;
packet_sent = 1;
printf(".");
}
+<<<<<<< HEAD
if (rndis_active(dev)) {
printf("Waiting for RNDIS link...");
printf("\n");
}
rx_submit (dev, dev->rx_req, 0);
+=======
+ packet_received = 0;
+ rx_submit(dev, dev->rx_req, 0);
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
return 0;
fail:
return -1;
static int usb_eth_send(struct eth_device* netdev, volatile void* packet, int length)
{
int retval;
+<<<<<<< HEAD
struct usb_request *req = NULL;
+=======
+ struct eth_dev *dev = &l_ethdev;
+ struct usb_request *req = dev->tx_req;
+ unsigned long ts;
+ unsigned long timeout = USB_CONNECT_TIMEOUT;
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
struct eth_dev *dev = &l_ethdev;
rndis_packet_buffer *rndis_buf = NULL;
dprintf("^");
}
+<<<<<<< HEAD
req = dev->tx_req;
if (rndis_active(dev)) {
packet = (void*) rndis_buf->data;
length = rndis_buf->len;
}
+=======
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
req->buf = (void *)packet;
req->context = NULL;
req->complete = tx_complete;
usb_gadget_handle_interrupts();
+<<<<<<< HEAD
if (packet_received)
{
dprintf("%s: packet received \n",__func__);
dprintf("-");
}
else printf("dev->rx_req invalid\n");
+=======
+ rx_submit(dev, dev->rx_req, 0);
+ } else
+ error("dev->rx_req invalid");
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
}
dprintf("done\n");
return 0;
printf("%s failed\n", __func__ );
return status;
}
-
buf[1] = USB_DT_STRING;
return buf[0];
}
-
include $(TOPDIR)/config.mk
-LIB := $(obj)libusb_host.a
+LIB := $(obj)libusb_host.o
# ohci
COBJS-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
+ifdef CONFIG_MPC512X
+COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
+else
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
+endif
+COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
{
struct usb_ehci *ehci;
- ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
#include <usb.h>
#include <asm/io.h>
#include <malloc.h>
+#include <watchdog.h>
#include "ehci.h"
uint32_t result;
do {
result = ehci_readl(ptr);
+ udelay(5);
if (result == ~(uint32_t)0)
return -1;
result &= mask;
if (result == done)
return 0;
- udelay(1);
usec--;
} while (usec > 0);
return -1;
int ret = 0;
cmd = ehci_readl(&hcor->or_usbcmd);
- cmd |= CMD_RESET;
+ cmd = (cmd & ~CMD_RUN) | CMD_RESET;
ehci_writel(&hcor->or_usbcmd, cmd);
ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
if (ret < 0) {
idx = 0;
while (idx < 5) {
td->qt_buffer[idx] = cpu_to_hc32(addr);
+ td->qt_buffer_hi[idx] = 0;
next = (addr + 4096) & ~4095;
delta = next - addr;
if (delta >= sz)
token = hc32_to_cpu(vtd->qt_token);
if (!(token & 0x80))
break;
+ WATCHDOG_RESET();
} while (get_timer(ts) < CONFIG_SYS_HZ);
/* Disable async schedule. */
break;
default:
dev->status = USB_ST_CRC_ERR;
+ if ((token & 0x40) == 0x40)
+ dev->status |= USB_ST_STALLED;
break;
}
dev->act_len = length - ((token >> 16) & 0x7fff);
--- /dev/null
+/*
+ * (C) Copyright 2010, Damien Dusha, <d.dusha@gmail.com>
+ *
+ * (C) Copyright 2009, Value Team S.p.A.
+ * Francesco Rendine, <francesco.rendine@valueteam.com>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
+ *
+ * Author: Tor Krill tor@excito.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <usb/ehci-fsl.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+static void fsl_setup_phy(volatile struct ehci_hcor *);
+static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
+static int reset_usb_controller(volatile struct usb_ehci *ehci);
+static void usb_platform_dr_init(volatile struct usb_ehci *ehci);
+
+/*
+ * Initialize SOC FSL EHCI Controller
+ *
+ * This code is derived from EHCI FSL USB Linux driver for MPC5121
+ *
+ */
+int ehci_hcd_init(void)
+{
+ volatile struct usb_ehci *ehci;
+
+ /* Hook the memory mapped registers for EHCI-Controller */
+ ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+ hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
+ hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ /* configure interface for UTMI_WIDE */
+ usb_platform_dr_init(ehci);
+
+ /* Init Phy USB0 to UTMI+ */
+ fsl_setup_phy(hcor);
+
+ /* Set to host mode */
+ fsl_platform_set_host_mode(ehci);
+
+ /*
+ * Setting the burst size seems to be required to prevent the
+ * USB from hanging when communicating with certain USB Mass
+ * storage devices. This was determined by analysing the
+ * EHCI registers under Linux vs U-Boot and burstsize was the
+ * major non-interrupt related difference between the two
+ * implementations.
+ *
+ * Some USB sticks behave better than others. In particular,
+ * the following USB stick is especially problematic:
+ * 0930:6545 Toshiba Corp
+ *
+ * The burstsize is set here to match the Linux implementation.
+ */
+ out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) |
+ FSL_EHCI_RXPBURST(8));
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ volatile struct usb_ehci *ehci;
+ int exit_status = 0;
+
+ if (hcor) {
+ /* Unhook struct */
+ hccr = NULL;
+ hcor = NULL;
+
+ /* Reset the USB controller */
+ ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+ exit_status = reset_usb_controller(ehci);
+ }
+
+ return exit_status;
+}
+
+static int reset_usb_controller(volatile struct usb_ehci *ehci)
+{
+ unsigned int i;
+
+ /* Command a reset of the USB Controller */
+ out_be32(&(ehci->usbcmd), EHCI_FSL_USBCMD_RST);
+
+ /* Wait for the reset process to finish */
+ for (i = 65535 ; i > 0 ; i--) {
+ /*
+ * The host will set this bit to zero once the
+ * reset process is complete
+ */
+ if ((in_be32(&(ehci->usbcmd)) & EHCI_FSL_USBCMD_RST) == 0)
+ return 0;
+ }
+
+ /* Hub did not reset in time */
+ return -1;
+}
+
+static void fsl_setup_phy(volatile struct ehci_hcor *hcor)
+{
+ uint32_t portsc;
+
+ portsc = ehci_readl(&hcor->or_portsc[0]);
+ portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
+
+ /* Enable the phy mode to UTMI Wide */
+ portsc |= PORT_PTS_PTW;
+ portsc |= PORT_PTS_UTMI;
+
+ ehci_writel(&hcor->or_portsc[0], portsc);
+}
+
+static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci)
+{
+ uint32_t temp;
+
+ temp = in_le32(&ehci->usbmode);
+ temp |= CM_HOST | ES_BE;
+ out_le32(&ehci->usbmode, temp);
+}
+
+static void usb_platform_dr_init(volatile struct usb_ehci *ehci)
+{
+ /* Configure interface for UTMI_WIDE */
+ out_be32(&ehci->isiphyctrl, PHYCTRL_PHYE | PHYCTRL_PXE);
+ out_be32(&ehci->usbgenctrl, GC_PPP | GC_PFP );
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/mx31-regs.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#define USBCTRL_OTGBASE_OFFSET 0x600
+
+#define MX31_OTG_SIC_SHIFT 29
+#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
+#define MX31_OTG_PM_BIT (1 << 24)
+
+#define MX31_H2_SIC_SHIFT 21
+#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT (1 << 16)
+#define MX31_H2_DT_BIT (1 << 5)
+
+#define MX31_H1_SIC_SHIFT 13
+#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT (1 << 8)
+#define MX31_H1_DT_BIT (1 << 4)
+
+static int mxc_set_usbcontrol(int port, unsigned int flags)
+{
+ unsigned int v;
+#ifdef CONFIG_MX31
+ v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
+
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK)
+ << MX31_OTG_SIC_SHIFT;
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_OTG_PM_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
+ MX31_H1_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK)
+ << MX31_H1_SIC_SHIFT;
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H1_DT_BIT;
+
+ break;
+ case 2: /* H2 port */
+ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
+ MX31_H2_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK)
+ << MX31_H2_SIC_SHIFT;
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H2_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H2_DT_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(v, MX31_OTG_BASE_ADDR +
+ USBCTRL_OTGBASE_OFFSET);
+#endif
+ return 0;
+}
+
+int ehci_hcd_init(void)
+{
+ u32 tmp;
+ struct usb_ehci *ehci;
+ struct clock_control_regs *sc_regs =
+ (struct clock_control_regs *)CCM_BASE;
+
+ tmp = __raw_readl(&sc_regs->ccmr);
+ __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
+
+ udelay(80);
+
+ /* Take USB2 */
+ ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
+ (0x200 * CONFIG_MXC_USB_PORT));
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ setbits_le32(&ehci->control, USB_EN);
+
+ __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+
+ mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+
+ udelay(10000);
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
return 0;
}
hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- usb_dev_init();
return 0;
}
#define STD_ASS (1 << 15)
#define STS_HALT (1 << 12)
uint32_t or_usbintr;
+#define INTR_UE (1 << 0) /* USB interrupt enable */
+#define INTR_UEE (1 << 1) /* USB error interrupt enable */
+#define INTR_PCE (1 << 2) /* Port change detect enable */
+#define INTR_SEE (1 << 4) /* system error enable */
+#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
uint32_t or_frindex;
uint32_t or_ctrldssegment;
uint32_t or_periodiclistbase;
/* Queue Element Transfer Descriptor (qTD). */
struct qTD {
- uint32_t qt_next;
+ /* this part defined by EHCI spec */
+ uint32_t qt_next; /* see EHCI 3.5.1 */
#define QT_NEXT_TERMINATE 1
- uint32_t qt_altnext;
- uint32_t qt_token;
- uint32_t qt_buffer[5];
+ uint32_t qt_altnext; /* see EHCI 3.5.2 */
+ uint32_t qt_token; /* see EHCI 3.5.3 */
+ uint32_t qt_buffer[5]; /* see EHCI 3.5.4 */
+ uint32_t qt_buffer_hi[5]; /* Appendix B */
+ /* pad struct for 32 byte alignment */
+ uint32_t unused[3];
};
/* Queue Head (QH). */
if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
- timeout = 100;
+ timeout = 1000;
/* wait for it to complete */
for (;;) {
include $(TOPDIR)/config.mk
-LIB := $(obj)libusb_musb.a
+LIB := $(obj)libusb_musb.o
COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o
COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* epinfo - Pointer to EP configuration table
* cnt - Number of entries in the EP conf table.
*/
-void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt)
+void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
{
u16 csr;
u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
/* exported functions */
extern void musb_start(void);
-extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
+extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
#define USB_MSC_BBB_GET_MAX_LUN 0xFE
/* Endpoint configuration information */
-static struct musb_epinfo epinfo[3] = {
+static const struct musb_epinfo epinfo[3] = {
{MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
{MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
{MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
static u32 port_status;
/* Device descriptor */
-static u8 root_hub_dev_des[] = {
+static const u8 root_hub_dev_des[] = {
0x12, /* __u8 bLength; */
0x01, /* __u8 bDescriptorType; Device */
0x00, /* __u16 bcdUSB; v1.1 */
};
/* Configuration descriptor */
-static u8 root_hub_config_des[] = {
+static const u8 root_hub_config_des[] = {
0x09, /* __u8 bLength; */
0x02, /* __u8 bDescriptorType; Configuration */
0x19, /* __u16 wTotalLength; */
0xff /* __u8 ep_bInterval; 255 ms */
};
-static unsigned char root_hub_str_index0[] = {
+static const unsigned char root_hub_str_index0[] = {
0x04, /* __u8 bLength; */
0x03, /* __u8 bDescriptorType; String-descriptor */
0x09, /* __u8 lang ID */
0x04, /* __u8 lang ID */
};
-static unsigned char root_hub_str_index1[] = {
+static const unsigned char root_hub_str_index1[] = {
0x1c, /* __u8 bLength; */
0x03, /* __u8 bDescriptorType; String-descriptor */
'M', /* __u8 Unicode */
u16 csr;
if (dir_out) {
- if (!toggle)
- writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
- else {
- csr = readw(&musbr->txcsr);
+ csr = readw(&musbr->txcsr);
+ if (!toggle) {
+ if (csr & MUSB_TXCSR_MODE)
+ csr = MUSB_TXCSR_CLRDATATOG;
+ else
+ csr = 0;
+ writew(csr, &musbr->txcsr);
+ } else {
csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
writew(csr, &musbr->txcsr);
csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
writew(csr, &musbr->txcsr);
}
} else {
- if (!toggle)
- writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
- else {
+ if (!toggle) {
+ csr = readw(&musbr->txcsr);
+ if (csr & MUSB_TXCSR_MODE)
+ csr = MUSB_RXCSR_CLRDATATOG;
+ else
+ csr = 0;
+ writew(csr, &musbr->rxcsr);
+ } else {
csr = readw(&musbr->rxcsr);
csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
writew(csr, &musbr->rxcsr);
int len = 0;
int stat = 0;
u32 datab[4];
- u8 *data_buf = (u8 *) datab;
+ const u8 *data_buf = (u8 *) datab;
u16 bmRType_bReq;
u16 wValue;
u16 wIndex;
break;
- case RH_GET_DESCRIPTOR | RH_CLASS:
+ case RH_GET_DESCRIPTOR | RH_CLASS: {
+ u8 *_data_buf = (u8 *) datab;
debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
- data_buf[0] = 0x09; /* min length; */
- data_buf[1] = 0x29;
- data_buf[2] = 0x1; /* 1 port */
- data_buf[3] = 0x01; /* per-port power switching */
- data_buf[3] |= 0x10; /* no overcurrent reporting */
+ _data_buf[0] = 0x09; /* min length; */
+ _data_buf[1] = 0x29;
+ _data_buf[2] = 0x1; /* 1 port */
+ _data_buf[3] = 0x01; /* per-port power switching */
+ _data_buf[3] |= 0x10; /* no overcurrent reporting */
/* Corresponds to data_buf[4-7] */
- data_buf[4] = 0;
- data_buf[5] = 5;
- data_buf[6] = 0;
- data_buf[7] = 0x02;
- data_buf[8] = 0xff;
+ _data_buf[4] = 0;
+ _data_buf[5] = 5;
+ _data_buf[6] = 0;
+ _data_buf[7] = 0x02;
+ _data_buf[8] = 0xff;
len = min_t(unsigned int, leni,
min_t(unsigned int, data_buf[0], wLength));
break;
+ }
case RH_GET_CONFIGURATION:
debug("RH_GET_CONFIGURATION\n");
include $(TOPDIR)/config.mk
-LIB := $(obj)libusb_phy.a
+LIB := $(obj)libusb_phy.o
COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB := $(obj)libvideo.a
+LIB := $(obj)libvideo.o
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
+COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
/* Set contrast */
value = ATMEL_LCDC_PS_DIV8 |
- ATMEL_LCDC_POL_POSITIVE |
ATMEL_LCDC_ENA_PWMENABLE;
+ if (!panel_info.vl_cont_pol_low)
+ value |= ATMEL_LCDC_POL_POSITIVE;
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
#include <malloc.h>
#include <asm/io.h>
-#include "fsl_diu_fb.h"
+#include <fsl_diu_fb.h>
struct fb_videomode {
const char *name; /* optional */
buf->offset = 0;
return 0;
}
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <stdio_dev.h>
+#include <video_fb.h>
+/*
+ * The Graphic Device
+ */
+static GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+ struct fb_info *info;
+
+ if (platform_diu_init(&ctfb.winSizeX, &ctfb.winSizeY) < 0)
+ return NULL;
+
+ /* fill in Graphic device struct */
+ sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
+ ctfb.winSizeX, ctfb.winSizeY, 32, 64, 60);
+
+ ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info);
+ ctfb.plnSizeX = ctfb.winSizeX;
+ ctfb.plnSizeY = ctfb.winSizeY;
+
+ ctfb.gdfBytesPP = 4;
+ ctfb.gdfIndex = GDF_32BIT_X888RGB;
+
+ ctfb.isaBase = 0;
+ ctfb.pciBase = 0;
+ ctfb.memSize = info->screen_size;
+
+ /* Cursor Start Address */
+ ctfb.dprBase = 0;
+ ctfb.vprBase = 0;
+ ctfb.cprBase = 0;
+
+ return &ctfb;
+}
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IPU_H__
+#define __ASM_ARCH_IPU_H__
+
+#include <linux/types.h>
+
+#define IDMA_CHAN_INVALID 0xFF
+#define HIGH_RESOLUTION_WIDTH 1024
+
+struct clk {
+ const char *name;
+ int id;
+ /* Source clock this clk depends on */
+ struct clk *parent;
+ /* Secondary clock to enable/disable with this clock */
+ struct clk *secondary;
+ /* Current clock rate */
+ unsigned long rate;
+ /* Reference count of clock enable/disable */
+ __s8 usecount;
+ /* Register bit position for clock's enable/disable control. */
+ u8 enable_shift;
+ /* Register address for clock's enable/disable control. */
+ void *enable_reg;
+ u32 flags;
+ /*
+ * Function ptr to recalculate the clock's rate based on parent
+ * clock's rate
+ */
+ void (*recalc) (struct clk *);
+ /*
+ * Function ptr to set the clock to a new rate. The rate must match a
+ * supported rate returned from round_rate. Leave blank if clock is not
+ * programmable
+ */
+ int (*set_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to round the requested clock rate to the nearest
+ * supported rate that is less than or equal to the requested rate.
+ */
+ unsigned long (*round_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to enable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ int (*enable) (struct clk *);
+ /*
+ * Function ptr to disable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ void (*disable) (struct clk *);
+ /* Function ptr to set the parent clock of the clock. */
+ int (*set_parent) (struct clk *, struct clk *);
+};
+
+/*
+ * Enumeration of Synchronous (Memory-less) panel types
+ */
+typedef enum {
+ IPU_PANEL_SHARP_TFT,
+ IPU_PANEL_TFT,
+} ipu_panel_t;
+
+/* IPU Pixel format definitions */
+#define fourcc(a, b, c, d)\
+ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
+
+#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
+#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
+#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
+#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
+#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
+#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
+#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
+#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
+#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
+#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
+#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
+#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
+
+/* YUV Interleaved Formats */
+#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved */
+#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
+
+#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
+
+/*
+ * IPU Driver channels definitions.
+ * Note these are different from IDMA channels
+ */
+#define IPU_MAX_CH 32
+#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
+ ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
+#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
+#define IPU_CHAN_ID(ch) (ch >> 24)
+#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
+#define NO_DMA 0x3F
+#define ALT 1
+
+/*
+ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
+ * combination of an input (memory to IPU), output (IPU to memory), and/or
+ * secondary input IDMA channels and in some cases an Image Converter task.
+ * Some channels consist of only an input or output.
+ */
+typedef enum {
+ CHAN_NONE = -1,
+
+ MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
+ MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
+ MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
+ MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
+
+ MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
+ MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
+ MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
+ MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
+
+ DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+ DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+
+} ipu_channel_t;
+
+/*
+ * Enumeration of types of buffers for a logical channel.
+ */
+typedef enum {
+ IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
+ IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
+ IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
+ IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
+ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
+ IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
+} ipu_buffer_t;
+
+#define IPU_PANEL_SERIAL 1
+#define IPU_PANEL_PARALLEL 2
+
+struct ipu_channel {
+ u8 video_in_dma;
+ u8 alpha_in_dma;
+ u8 graph_in_dma;
+ u8 out_dma;
+};
+
+enum ipu_dmfc_type {
+ DMFC_NORMAL = 0,
+ DMFC_HIGH_RESOLUTION_DC,
+ DMFC_HIGH_RESOLUTION_DP,
+ DMFC_HIGH_RESOLUTION_ONLY_DP,
+};
+
+
+/*
+ * Union of initialization parameters for a logical channel.
+ */
+typedef union {
+ struct {
+ uint32_t di;
+ unsigned char interlaced;
+ } mem_dc_sync;
+ struct {
+ uint32_t temp;
+ } mem_sdc_fg;
+ struct {
+ uint32_t di;
+ unsigned char interlaced;
+ uint32_t in_pixel_fmt;
+ uint32_t out_pixel_fmt;
+ unsigned char alpha_chan_en;
+ } mem_dp_bg_sync;
+ struct {
+ uint32_t temp;
+ } mem_sdc_bg;
+ struct {
+ uint32_t di;
+ unsigned char interlaced;
+ uint32_t in_pixel_fmt;
+ uint32_t out_pixel_fmt;
+ unsigned char alpha_chan_en;
+ } mem_dp_fg_sync;
+} ipu_channel_params_t;
+
+/*
+ * Bitfield of Display Interface signal polarities.
+ */
+typedef struct {
+ unsigned datamask_en:1;
+ unsigned ext_clk:1;
+ unsigned interlaced:1;
+ unsigned odd_field_first:1;
+ unsigned clksel_en:1;
+ unsigned clkidle_en:1;
+ unsigned data_pol:1; /* true = inverted */
+ unsigned clk_pol:1; /* true = rising edge */
+ unsigned enable_pol:1;
+ unsigned Hsync_pol:1; /* true = active high */
+ unsigned Vsync_pol:1;
+} ipu_di_signal_cfg_t;
+
+typedef enum {
+ RGB,
+ YCbCr,
+ YUV
+} ipu_color_space_t;
+
+/* Common IPU API */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
+void ipu_uninit_channel(ipu_channel_t channel);
+
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+ uint32_t u_offset, uint32_t v_offset);
+
+int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum, dma_addr_t phyaddr);
+
+int32_t ipu_is_channel_busy(ipu_channel_t channel);
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum);
+int32_t ipu_enable_channel(ipu_channel_t channel);
+int32_t ipu_disable_channel(ipu_channel_t channel);
+
+int32_t ipu_init_sync_panel(int disp,
+ uint32_t pixel_clk,
+ uint16_t width, uint16_t height,
+ uint32_t pixel_fmt,
+ uint16_t h_start_width, uint16_t h_sync_width,
+ uint16_t h_end_width, uint16_t v_start_width,
+ uint16_t v_sync_width, uint16_t v_end_width,
+ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+
+int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
+ uint8_t alpha);
+int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
+ uint32_t colorKey);
+
+uint32_t bytes_per_pixel(uint32_t fmt);
+
+void clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+u32 clk_get_rate(struct clk *clk);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+int clk_get_usecount(struct clk *clk);
+struct clk *clk_get_parent(struct clk *clk);
+
+void ipu_dump_registers(void);
+int ipu_probe(void);
+
+void ipu_dmfc_init(int dmfc_type, int first);
+void ipu_init_dc_mappings(void);
+void ipu_dmfc_set_wait4eot(int dma_chan, int width);
+void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
+void ipu_dc_uninit(int dc_chan);
+void ipu_dp_dc_enable(ipu_channel_t channel);
+int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+ uint32_t out_pixel_fmt);
+void ipu_dp_uninit(ipu_channel_t channel);
+void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
+ipu_color_space_t format_to_colorspace(uint32_t fmt);
+
+#endif
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include "ipu.h"
+#include "ipu_regs.h"
+
+extern struct mxc_ccm_reg *mxc_ccm;
+extern u32 *ipu_cpmem_base;
+
+struct ipu_ch_param_word {
+ uint32_t data[5];
+ uint32_t res[3];
+};
+
+struct ipu_ch_param {
+ struct ipu_ch_param_word word[2];
+};
+
+#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
+
+#define _param_word(base, w) \
+ (((struct ipu_ch_param *)(base))->word[(w)].data)
+
+#define ipu_ch_param_set_field(base, w, bit, size, v) { \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ _param_word(base, w)[i] |= (v) << off; \
+ if (((bit) + (size) - 1) / 32 > i) { \
+ _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
+ } \
+}
+
+#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ u32 mask = (1UL << size) - 1; \
+ u32 temp = _param_word(base, w)[i]; \
+ temp &= ~(mask << off); \
+ _param_word(base, w)[i] = temp | (v) << off; \
+ if (((bit) + (size) - 1) / 32 > i) { \
+ temp = _param_word(base, w)[i + 1]; \
+ temp &= ~(mask >> (32 - off)); \
+ _param_word(base, w)[i + 1] = \
+ temp | ((v) >> (off ? (32 - off) : 0)); \
+ } \
+}
+
+#define ipu_ch_param_read_field(base, w, bit, size) ({ \
+ u32 temp2; \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ u32 mask = (1UL << size) - 1; \
+ u32 temp1 = _param_word(base, w)[i]; \
+ temp1 = mask & (temp1 >> off); \
+ if (((bit)+(size) - 1) / 32 > i) { \
+ temp2 = _param_word(base, w)[i + 1]; \
+ temp2 &= mask >> (off ? (32 - off) : 0); \
+ temp1 |= temp2 << (off ? (32 - off) : 0); \
+ } \
+ temp1; \
+})
+
+
+void clk_enable(struct clk *clk)
+{
+ if (clk) {
+ if (clk->usecount++ == 0) {
+ clk->enable(clk);
+ }
+ }
+}
+
+void clk_disable(struct clk *clk)
+{
+ if (clk) {
+ if (!(--clk->usecount)) {
+ if (clk->disable)
+ clk->disable(clk);
+ }
+ }
+}
+
+int clk_get_usecount(struct clk *clk)
+{
+ if (clk == NULL)
+ return 0;
+
+ return clk->usecount;
+}
+
+u32 clk_get_rate(struct clk *clk)
+{
+ if (!clk)
+ return 0;
+
+ return clk->rate;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ if (!clk)
+ return 0;
+
+ return clk->parent;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ if (clk && clk->set_rate)
+ clk->set_rate(clk, rate);
+ return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ if (clk == NULL || !clk->round_rate)
+ return 0;
+
+ return clk->round_rate(clk, rate);
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ clk->parent = parent;
+ if (clk->set_parent)
+ return clk->set_parent(clk, parent);
+ return 0;
+}
+
+static int clk_ipu_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ /* Handshake with IPU when certain clock rates are changed. */
+ reg = __raw_readl(&mxc_ccm->ccdr);
+ reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+ __raw_writel(reg, &mxc_ccm->ccdr);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ reg = __raw_readl(&mxc_ccm->clpcr);
+ reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+ __raw_writel(reg, &mxc_ccm->clpcr);
+
+ return 0;
+}
+
+static void clk_ipu_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+
+ /*
+ * No handshake with IPU whe dividers are changed
+ * as its not enabled.
+ */
+ reg = __raw_readl(&mxc_ccm->ccdr);
+ reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+ __raw_writel(reg, &mxc_ccm->ccdr);
+
+ /* No handshake with IPU when LPM is entered as its not enabled. */
+ reg = __raw_readl(&mxc_ccm->clpcr);
+ reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+ __raw_writel(reg, &mxc_ccm->clpcr);
+}
+
+
+static struct clk ipu_clk = {
+ .name = "ipu_clk",
+ .rate = 133000000,
+ .enable_reg = (u32 *)(MXC_CCM_BASE +
+ offsetof(struct mxc_ccm_reg, CCGR5)),
+ .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+ .enable = clk_ipu_enable,
+ .disable = clk_ipu_disable,
+ .usecount = 0,
+};
+
+/* Globals */
+struct clk *g_ipu_clk;
+unsigned char g_ipu_clk_enabled;
+struct clk *g_di_clk[2];
+struct clk *g_pixel_clk[2];
+unsigned char g_dc_di_assignment[10];
+uint32_t g_channel_init_mask;
+uint32_t g_channel_enable_mask;
+
+static int ipu_dc_use_count;
+static int ipu_dp_use_count;
+static int ipu_dmfc_use_count;
+static int ipu_di_use_count[2];
+
+u32 *ipu_cpmem_base;
+u32 *ipu_dc_tmpl_reg;
+
+/* Static functions */
+
+static inline void ipu_ch_param_set_high_priority(uint32_t ch)
+{
+ ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
+};
+
+static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+ return ((uint32_t) ch >> (6 * type)) & 0x3F;
+};
+
+/* Either DP BG or DP FG can be graphic window */
+static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
+{
+ return (dma_chan == 23 || dma_chan == 27);
+}
+
+static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
+{
+ return ((dma_chan >= 23) && (dma_chan <= 29));
+}
+
+
+static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
+ dma_addr_t phyaddr)
+{
+ ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
+ phyaddr / 8);
+};
+
+#define idma_is_valid(ch) (ch != NO_DMA)
+#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
+#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
+
+static void ipu_pixel_clk_recalc(struct clk *clk)
+{
+ u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+ if (div == 0)
+ clk->rate = 0;
+ else
+ clk->rate = (clk->parent->rate * 16) / div;
+}
+
+static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div, div1;
+ u32 tmp;
+ /*
+ * Calculate divider
+ * Fractional part is 4 bits,
+ * so simply multiply by 2^4 to get fractional part.
+ */
+ tmp = (clk->parent->rate * 16);
+ div = tmp / rate;
+
+ if (div < 0x10) /* Min DI disp clock divider is 1 */
+ div = 0x10;
+ if (div & ~0xFEF)
+ div &= 0xFF8;
+ else {
+ div1 = div & 0xFE0;
+ if ((tmp/div1 - tmp/div) < rate / 4)
+ div = div1;
+ else
+ div &= 0xFF8;
+ }
+ return (clk->parent->rate * 16) / div;
+}
+
+static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 div = (clk->parent->rate * 16) / rate;
+
+ __raw_writel(div, DI_BS_CLKGEN0(clk->id));
+
+ /* Setup pixel clock timing */
+ __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
+
+ clk->rate = (clk->parent->rate * 16) / div;
+ return 0;
+}
+
+static int ipu_pixel_clk_enable(struct clk *clk)
+{
+ u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+ disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
+ __raw_writel(disp_gen, IPU_DISP_GEN);
+
+ return 0;
+}
+
+static void ipu_pixel_clk_disable(struct clk *clk)
+{
+ u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+ disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
+ __raw_writel(disp_gen, IPU_DISP_GEN);
+
+}
+
+static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
+
+ if (parent == g_ipu_clk)
+ di_gen &= ~DI_GEN_DI_CLK_EXT;
+ else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+ di_gen |= DI_GEN_DI_CLK_EXT;
+ else
+ return -EINVAL;
+
+ __raw_writel(di_gen, DI_GENERAL(clk->id));
+ ipu_pixel_clk_recalc(clk);
+ return 0;
+}
+
+static struct clk pixel_clk[] = {
+ {
+ .name = "pixel_clk",
+ .id = 0,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
+ .usecount = 0,
+ },
+ {
+ .name = "pixel_clk",
+ .id = 1,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
+ .usecount = 0,
+ },
+};
+
+/*
+ * This function resets IPU
+ */
+void ipu_reset(void)
+{
+ u32 *reg;
+ u32 value;
+
+ reg = (u32 *)SRC_BASE_ADDR;
+ value = __raw_readl(reg);
+ value = value | SW_IPU_RST;
+ __raw_writel(value, reg);
+}
+
+/*
+ * This function is called by the driver framework to initialize the IPU
+ * hardware.
+ *
+ * @param dev The device structure for the IPU passed in by the
+ * driver framework.
+ *
+ * @return Returns 0 on success or negative error code on error
+ */
+int ipu_probe(void)
+{
+ unsigned long ipu_base;
+ u32 temp;
+
+ u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
+ u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
+
+ __raw_writel(0xF00, reg_hsc_mcd);
+
+ /* CSI mode reserved*/
+ temp = __raw_readl(reg_hsc_mxt_conf);
+ __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
+
+ temp = __raw_readl(reg_hsc_mxt_conf);
+ __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
+
+ ipu_base = IPU_CTRL_BASE_ADDR;
+ ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
+ ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
+
+ g_pixel_clk[0] = &pixel_clk[0];
+ g_pixel_clk[1] = &pixel_clk[1];
+
+ g_ipu_clk = &ipu_clk;
+ debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
+
+ ipu_reset();
+
+ clk_set_parent(g_pixel_clk[0], g_ipu_clk);
+ clk_set_parent(g_pixel_clk[1], g_ipu_clk);
+ clk_enable(g_ipu_clk);
+
+ g_di_clk[0] = NULL;
+ g_di_clk[1] = NULL;
+
+ __raw_writel(0x807FFFFF, IPU_MEM_RST);
+ while (__raw_readl(IPU_MEM_RST) & 0x80000000)
+ ;
+
+ ipu_init_dc_mappings();
+
+ __raw_writel(0, IPU_INT_CTRL(5));
+ __raw_writel(0, IPU_INT_CTRL(6));
+ __raw_writel(0, IPU_INT_CTRL(9));
+ __raw_writel(0, IPU_INT_CTRL(10));
+
+ /* DMFC Init */
+ ipu_dmfc_init(DMFC_NORMAL, 1);
+
+ /* Set sync refresh channels as high priority */
+ __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
+
+ /* Set MCU_T to divide MCU access window into 2 */
+ __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
+
+ clk_disable(g_ipu_clk);
+
+ return 0;
+}
+
+void ipu_dump_registers(void)
+{
+ debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
+ debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
+ debug("IDMAC_CHA_EN1 = \t0x%08X\n",
+ __raw_readl(IDMAC_CHA_EN(0)));
+ debug("IDMAC_CHA_EN2 = \t0x%08X\n",
+ __raw_readl(IDMAC_CHA_EN(32)));
+ debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
+ __raw_readl(IDMAC_CHA_PRI(0)));
+ debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
+ __raw_readl(IDMAC_CHA_PRI(32)));
+ debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+ __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
+ debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+ __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
+ debug("DMFC_WR_CHAN = \t0x%08X\n",
+ __raw_readl(DMFC_WR_CHAN));
+ debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
+ __raw_readl(DMFC_WR_CHAN_DEF));
+ debug("DMFC_DP_CHAN = \t0x%08X\n",
+ __raw_readl(DMFC_DP_CHAN));
+ debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
+ __raw_readl(DMFC_DP_CHAN_DEF));
+ debug("DMFC_IC_CTRL = \t0x%08X\n",
+ __raw_readl(DMFC_IC_CTRL));
+ debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+ __raw_readl(IPU_FS_PROC_FLOW1));
+ debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+ __raw_readl(IPU_FS_PROC_FLOW2));
+ debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+ __raw_readl(IPU_FS_PROC_FLOW3));
+ debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+ __raw_readl(IPU_FS_DISP_FLOW1));
+}
+
+/*
+ * This function is called to initialize a logical IPU channel.
+ *
+ * @param channel Input parameter for the logical channel ID to init.
+ *
+ * @param params Input parameter containing union of channel
+ * initialization parameters.
+ *
+ * @return Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
+{
+ int ret = 0;
+ uint32_t ipu_conf;
+
+ debug("init channel = %d\n", IPU_CHAN_ID(channel));
+
+ if (g_ipu_clk_enabled == 0) {
+ g_ipu_clk_enabled = 1;
+ clk_enable(g_ipu_clk);
+ }
+
+
+ if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+ printf("Warning: channel already initialized %d\n",
+ IPU_CHAN_ID(channel));
+ }
+
+ ipu_conf = __raw_readl(IPU_CONF);
+
+ switch (channel) {
+ case MEM_DC_SYNC:
+ if (params->mem_dc_sync.di > 1) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ g_dc_di_assignment[1] = params->mem_dc_sync.di;
+ ipu_dc_init(1, params->mem_dc_sync.di,
+ params->mem_dc_sync.interlaced);
+ ipu_di_use_count[params->mem_dc_sync.di]++;
+ ipu_dc_use_count++;
+ ipu_dmfc_use_count++;
+ break;
+ case MEM_BG_SYNC:
+ if (params->mem_dp_bg_sync.di > 1) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
+ ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
+ params->mem_dp_bg_sync.out_pixel_fmt);
+ ipu_dc_init(5, params->mem_dp_bg_sync.di,
+ params->mem_dp_bg_sync.interlaced);
+ ipu_di_use_count[params->mem_dp_bg_sync.di]++;
+ ipu_dc_use_count++;
+ ipu_dp_use_count++;
+ ipu_dmfc_use_count++;
+ break;
+ case MEM_FG_SYNC:
+ ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
+ params->mem_dp_fg_sync.out_pixel_fmt);
+
+ ipu_dc_use_count++;
+ ipu_dp_use_count++;
+ ipu_dmfc_use_count++;
+ break;
+ default:
+ printf("Missing channel initialization\n");
+ break;
+ }
+
+ /* Enable IPU sub module */
+ g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+ if (ipu_dc_use_count == 1)
+ ipu_conf |= IPU_CONF_DC_EN;
+ if (ipu_dp_use_count == 1)
+ ipu_conf |= IPU_CONF_DP_EN;
+ if (ipu_dmfc_use_count == 1)
+ ipu_conf |= IPU_CONF_DMFC_EN;
+ if (ipu_di_use_count[0] == 1) {
+ ipu_conf |= IPU_CONF_DI0_EN;
+ }
+ if (ipu_di_use_count[1] == 1) {
+ ipu_conf |= IPU_CONF_DI1_EN;
+ }
+
+ __raw_writel(ipu_conf, IPU_CONF);
+
+err:
+ return ret;
+}
+
+/*
+ * This function is called to uninitialize a logical IPU channel.
+ *
+ * @param channel Input parameter for the logical channel ID to uninit.
+ */
+void ipu_uninit_channel(ipu_channel_t channel)
+{
+ uint32_t reg;
+ uint32_t in_dma, out_dma = 0;
+ uint32_t ipu_conf;
+
+ if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+ debug("Channel already uninitialized %d\n",
+ IPU_CHAN_ID(channel));
+ return;
+ }
+
+ /*
+ * Make sure channel is disabled
+ * Get input and output dma channels
+ */
+ in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+ out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+ if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
+ idma_is_set(IDMAC_CHA_EN, out_dma)) {
+ printf(
+ "Channel %d is not disabled, disable first\n",
+ IPU_CHAN_ID(channel));
+ return;
+ }
+
+ ipu_conf = __raw_readl(IPU_CONF);
+
+ /* Reset the double buffer */
+ reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
+ __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
+ reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
+ __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
+
+ switch (channel) {
+ case MEM_DC_SYNC:
+ ipu_dc_uninit(1);
+ ipu_di_use_count[g_dc_di_assignment[1]]--;
+ ipu_dc_use_count--;
+ ipu_dmfc_use_count--;
+ break;
+ case MEM_BG_SYNC:
+ ipu_dp_uninit(channel);
+ ipu_dc_uninit(5);
+ ipu_di_use_count[g_dc_di_assignment[5]]--;
+ ipu_dc_use_count--;
+ ipu_dp_use_count--;
+ ipu_dmfc_use_count--;
+ break;
+ case MEM_FG_SYNC:
+ ipu_dp_uninit(channel);
+ ipu_dc_use_count--;
+ ipu_dp_use_count--;
+ ipu_dmfc_use_count--;
+ break;
+ default:
+ break;
+ }
+
+ g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+ if (ipu_dc_use_count == 0)
+ ipu_conf &= ~IPU_CONF_DC_EN;
+ if (ipu_dp_use_count == 0)
+ ipu_conf &= ~IPU_CONF_DP_EN;
+ if (ipu_dmfc_use_count == 0)
+ ipu_conf &= ~IPU_CONF_DMFC_EN;
+ if (ipu_di_use_count[0] == 0) {
+ ipu_conf &= ~IPU_CONF_DI0_EN;
+ }
+ if (ipu_di_use_count[1] == 0) {
+ ipu_conf &= ~IPU_CONF_DI1_EN;
+ }
+
+ __raw_writel(ipu_conf, IPU_CONF);
+
+ if (ipu_conf == 0) {
+ clk_disable(g_ipu_clk);
+ g_ipu_clk_enabled = 0;
+ }
+
+}
+
+static inline void ipu_ch_param_dump(int ch)
+{
+#ifdef DEBUG
+ struct ipu_ch_param *p = ipu_ch_param_addr(ch);
+ debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
+ p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
+ p->word[0].data[3], p->word[0].data[4]);
+ debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
+ p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
+ p->word[1].data[3], p->word[1].data[4]);
+ debug("PFS 0x%x, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
+ debug("BPP 0x%x, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
+ debug("NPB 0x%x\n",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
+
+ debug("FW %d, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
+ debug("FH %d, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
+ debug("Stride %d\n",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
+
+ debug("Width0 %d+1, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
+ debug("Width1 %d+1, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
+ debug("Width2 %d+1, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
+ debug("Width3 %d+1, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
+ debug("Offset0 %d, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
+ debug("Offset1 %d, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
+ debug("Offset2 %d, ",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
+ debug("Offset3 %d\n",
+ ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
+#endif
+}
+
+static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
+ int red_width, int red_offset,
+ int green_width, int green_offset,
+ int blue_width, int blue_offset,
+ int alpha_width, int alpha_offset)
+{
+ /* Setup red width and offset */
+ ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
+ ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
+ /* Setup green width and offset */
+ ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
+ ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
+ /* Setup blue width and offset */
+ ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
+ ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
+ /* Setup alpha width and offset */
+ ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
+ ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
+}
+
+static void ipu_ch_param_init(int ch,
+ uint32_t pixel_fmt, uint32_t width,
+ uint32_t height, uint32_t stride,
+ uint32_t u, uint32_t v,
+ uint32_t uv_stride, dma_addr_t addr0,
+ dma_addr_t addr1)
+{
+ uint32_t u_offset = 0;
+ uint32_t v_offset = 0;
+ struct ipu_ch_param params;
+
+ memset(¶ms, 0, sizeof(params));
+
+ ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1);
+
+ if ((ch == 8) || (ch == 9) || (ch == 10)) {
+ ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1);
+ ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1);
+ } else {
+ ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1);
+ ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1);
+ }
+
+ ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3);
+ ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3);
+
+ switch (pixel_fmt) {
+ case IPU_PIX_FMT_GENERIC:
+ /*Represents 8-bit Generic data */
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */
+
+ break;
+ case IPU_PIX_FMT_GENERIC_32:
+ /*Represents 32-bit Generic data */
+ break;
+ case IPU_PIX_FMT_RGB565:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+
+ ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16);
+ break;
+ case IPU_PIX_FMT_BGR24:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
+
+ ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
+ break;
+ case IPU_PIX_FMT_RGB24:
+ case IPU_PIX_FMT_YUV444:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
+
+ ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24);
+ break;
+ case IPU_PIX_FMT_BGRA32:
+ case IPU_PIX_FMT_BGR32:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+
+ ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0);
+ break;
+ case IPU_PIX_FMT_RGBA32:
+ case IPU_PIX_FMT_RGB32:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+
+ ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0);
+ break;
+ case IPU_PIX_FMT_ABGR32:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+
+ ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
+ break;
+ case IPU_PIX_FMT_UYVY:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+ break;
+ case IPU_PIX_FMT_YUYV:
+ ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ break;
+ case IPU_PIX_FMT_YUV420P2:
+ case IPU_PIX_FMT_YUV420P:
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */
+
+ if (uv_stride < stride / 2)
+ uv_stride = stride / 2;
+
+ u_offset = stride * height;
+ v_offset = u_offset + (uv_stride * height / 2);
+ /* burst size */
+ if ((ch == 8) || (ch == 9) || (ch == 10)) {
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 15);
+ uv_stride = uv_stride*2;
+ } else {
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 31);
+ }
+ break;
+ case IPU_PIX_FMT_YVU422P:
+ /* BPP & pixel format */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+
+ if (uv_stride < stride / 2)
+ uv_stride = stride / 2;
+
+ v_offset = (v == 0) ? stride * height : v;
+ u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
+ break;
+ case IPU_PIX_FMT_YUV422P:
+ /* BPP & pixel format */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+
+ if (uv_stride < stride / 2)
+ uv_stride = stride / 2;
+
+ u_offset = (u == 0) ? stride * height : u;
+ v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
+ break;
+ case IPU_PIX_FMT_NV12:
+ /* BPP & pixel format */
+ ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */
+ ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ uv_stride = stride;
+ u_offset = (u == 0) ? stride * height : u;
+ break;
+ default:
+ puts("mxc ipu: unimplemented pixel format\n");
+ break;
+ }
+
+
+ if (uv_stride)
+ ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1);
+
+ /* Get the uv offset from user when need cropping */
+ if (u || v) {
+ u_offset = u;
+ v_offset = v;
+ }
+
+ /* UBO and VBO are 22-bit */
+ if (u_offset/8 > 0x3fffff)
+ puts("The value of U offset exceeds IPU limitation\n");
+ if (v_offset/8 > 0x3fffff)
+ puts("The value of V offset exceeds IPU limitation\n");
+
+ ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8);
+ ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8);
+
+ debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
+ memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params));
+};
+
+/*
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param channel Input parameter for the logical channel ID.
+ *
+ * @param type Input parameter which buffer to initialize.
+ *
+ * @param pixel_fmt Input parameter for pixel format of buffer.
+ * Pixel format is a FOURCC ASCII code.
+ *
+ * @param width Input parameter for width of buffer in pixels.
+ *
+ * @param height Input parameter for height of buffer in pixels.
+ *
+ * @param stride Input parameter for stride length of buffer
+ * in pixels.
+ *
+ * @param phyaddr_0 Input parameter buffer 0 physical address.
+ *
+ * @param phyaddr_1 Input parameter buffer 1 physical address.
+ * Setting this to a value other than NULL enables
+ * double buffering mode.
+ *
+ * @param u private u offset for additional cropping,
+ * zero if not used.
+ *
+ * @param v private v offset for additional cropping,
+ * zero if not used.
+ *
+ * @return Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+ uint32_t u, uint32_t v)
+{
+ uint32_t reg;
+ uint32_t dma_chan;
+
+ dma_chan = channel_2_dma(channel, type);
+ if (!idma_is_valid(dma_chan))
+ return -EINVAL;
+
+ if (stride < width * bytes_per_pixel(pixel_fmt))
+ stride = width * bytes_per_pixel(pixel_fmt);
+
+ if (stride % 4) {
+ printf(
+ "Stride not 32-bit aligned, stride = %d\n", stride);
+ return -EINVAL;
+ }
+ /* Build parameter memory data for DMA channel */
+ ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
+ phyaddr_0, phyaddr_1);
+
+ if (ipu_is_dmfc_chan(dma_chan)) {
+ ipu_dmfc_set_wait4eot(dma_chan, width);
+ }
+
+ if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
+ ipu_ch_param_set_high_priority(dma_chan);
+
+ ipu_ch_param_dump(dma_chan);
+
+ reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
+ if (phyaddr_1)
+ reg |= idma_mask(dma_chan);
+ else
+ reg &= ~idma_mask(dma_chan);
+ __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+ /* Reset to buffer 0 */
+ __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
+
+ return 0;
+}
+
+/*
+ * This function enables a logical channel.
+ *
+ * @param channel Input parameter for the logical channel ID.
+ *
+ * @return This function returns 0 on success or negative error code on
+ * fail.
+ */
+int32_t ipu_enable_channel(ipu_channel_t channel)
+{
+ uint32_t reg;
+ uint32_t in_dma;
+ uint32_t out_dma;
+
+ if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
+ printf("Warning: channel already enabled %d\n",
+ IPU_CHAN_ID(channel));
+ }
+
+ /* Get input and output dma channels */
+ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+ if (idma_is_valid(in_dma)) {
+ reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+ __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+ }
+ if (idma_is_valid(out_dma)) {
+ reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+ __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+ }
+
+ if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
+ (channel == MEM_FG_SYNC))
+ ipu_dp_dc_enable(channel);
+
+ g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
+
+ return 0;
+}
+
+/*
+ * This function clear buffer ready for a logical channel.
+ *
+ * @param channel Input parameter for the logical channel ID.
+ *
+ * @param type Input parameter which buffer to clear.
+ *
+ * @param bufNum Input parameter for which buffer number clear
+ * ready state.
+ *
+ */
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum)
+{
+ uint32_t dma_ch = channel_2_dma(channel, type);
+
+ if (!idma_is_valid(dma_ch))
+ return;
+
+ __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
+ if (bufNum == 0) {
+ if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
+ __raw_writel(idma_mask(dma_ch),
+ IPU_CHA_BUF0_RDY(dma_ch));
+ }
+ } else {
+ if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
+ __raw_writel(idma_mask(dma_ch),
+ IPU_CHA_BUF1_RDY(dma_ch));
+ }
+ }
+ __raw_writel(0x0, IPU_GPR); /* write one to set */
+}
+
+/*
+ * This function disables a logical channel.
+ *
+ * @param channel Input parameter for the logical channel ID.
+ *
+ * @param wait_for_stop Flag to set whether to wait for channel end
+ * of frame or return immediately.
+ *
+ * @return This function returns 0 on success or negative error code on
+ * fail.
+ */
+int32_t ipu_disable_channel(ipu_channel_t channel)
+{
+ uint32_t reg;
+ uint32_t in_dma;
+ uint32_t out_dma;
+
+ if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+ debug("Channel already disabled %d\n",
+ IPU_CHAN_ID(channel));
+ return 0;
+ }
+
+ /* Get input and output dma channels */
+ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+ if ((idma_is_valid(in_dma) &&
+ !idma_is_set(IDMAC_CHA_EN, in_dma))
+ && (idma_is_valid(out_dma) &&
+ !idma_is_set(IDMAC_CHA_EN, out_dma)))
+ return -EINVAL;
+
+ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+ (channel == MEM_DC_SYNC)) {
+ ipu_dp_dc_disable(channel, 0);
+ }
+
+ /* Disable DMA channel(s) */
+ if (idma_is_valid(in_dma)) {
+ reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+ __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+ __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
+ }
+ if (idma_is_valid(out_dma)) {
+ reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+ __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+ __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
+ }
+
+ g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+ /* Set channel buffers NOT to be ready */
+ if (idma_is_valid(in_dma)) {
+ ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
+ ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
+ }
+ if (idma_is_valid(out_dma)) {
+ ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
+ ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
+ }
+
+ return 0;
+}
+
+uint32_t bytes_per_pixel(uint32_t fmt)
+{
+ switch (fmt) {
+ case IPU_PIX_FMT_GENERIC: /*generic data */
+ case IPU_PIX_FMT_RGB332:
+ case IPU_PIX_FMT_YUV420P:
+ case IPU_PIX_FMT_YUV422P:
+ return 1;
+ break;
+ case IPU_PIX_FMT_RGB565:
+ case IPU_PIX_FMT_YUYV:
+ case IPU_PIX_FMT_UYVY:
+ return 2;
+ break;
+ case IPU_PIX_FMT_BGR24:
+ case IPU_PIX_FMT_RGB24:
+ return 3;
+ break;
+ case IPU_PIX_FMT_GENERIC_32: /*generic data */
+ case IPU_PIX_FMT_BGR32:
+ case IPU_PIX_FMT_BGRA32:
+ case IPU_PIX_FMT_RGB32:
+ case IPU_PIX_FMT_RGBA32:
+ case IPU_PIX_FMT_ABGR32:
+ return 4;
+ break;
+ default:
+ return 1;
+ break;
+ }
+ return 0;
+}
+
+ipu_color_space_t format_to_colorspace(uint32_t fmt)
+{
+ switch (fmt) {
+ case IPU_PIX_FMT_RGB666:
+ case IPU_PIX_FMT_RGB565:
+ case IPU_PIX_FMT_BGR24:
+ case IPU_PIX_FMT_RGB24:
+ case IPU_PIX_FMT_BGR32:
+ case IPU_PIX_FMT_BGRA32:
+ case IPU_PIX_FMT_RGB32:
+ case IPU_PIX_FMT_RGBA32:
+ case IPU_PIX_FMT_ABGR32:
+ case IPU_PIX_FMT_LVDS666:
+ case IPU_PIX_FMT_LVDS888:
+ return RGB;
+ break;
+
+ default:
+ return YCbCr;
+ break;
+ }
+ return RGB;
+}
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include "ipu.h"
+#include "ipu_regs.h"
+
+enum csc_type_t {
+ RGB2YUV = 0,
+ YUV2RGB,
+ RGB2RGB,
+ YUV2YUV,
+ CSC_NONE,
+ CSC_NUM
+};
+
+struct dp_csc_param_t {
+ int mode;
+ void *coeff;
+};
+
+#define SYNC_WAVE 0
+
+/* DC display ID assignments */
+#define DC_DISP_ID_SYNC(di) (di)
+#define DC_DISP_ID_SERIAL 2
+#define DC_DISP_ID_ASYNC 3
+
+int dmfc_type_setup;
+static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
+int g_di1_tvout;
+
+extern struct clk *g_ipu_clk;
+extern struct clk *g_di_clk[2];
+extern struct clk *g_pixel_clk[2];
+
+extern unsigned char g_ipu_clk_enabled;
+extern unsigned char g_dc_di_assignment[];
+
+void ipu_dmfc_init(int dmfc_type, int first)
+{
+ u32 dmfc_wr_chan, dmfc_dp_chan;
+
+ if (first) {
+ if (dmfc_type_setup > dmfc_type)
+ dmfc_type = dmfc_type_setup;
+ else
+ dmfc_type_setup = dmfc_type;
+
+ /* disable DMFC-IC channel*/
+ __raw_writel(0x2, DMFC_IC_CTRL);
+ } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
+ printf("DMFC high resolution has set, will not change\n");
+ return;
+ } else
+ dmfc_type_setup = dmfc_type;
+
+ if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
+ /* 1 - segment 0~3;
+ * 5B - segement 4, 5;
+ * 5F - segement 6, 7;
+ * 1C, 2C and 6B, 6F unused;
+ */
+ debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
+ dmfc_wr_chan = 0x00000088;
+ dmfc_dp_chan = 0x00009694;
+ dmfc_size_28 = 256 * 4;
+ dmfc_size_29 = 0;
+ dmfc_size_24 = 0;
+ dmfc_size_27 = 128 * 4;
+ dmfc_size_23 = 128 * 4;
+ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
+ /* 1 - segment 0, 1;
+ * 5B - segement 2~5;
+ * 5F - segement 6,7;
+ * 1C, 2C and 6B, 6F unused;
+ */
+ debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
+ dmfc_wr_chan = 0x00000090;
+ dmfc_dp_chan = 0x0000968a;
+ dmfc_size_28 = 128 * 4;
+ dmfc_size_29 = 0;
+ dmfc_size_24 = 0;
+ dmfc_size_27 = 128 * 4;
+ dmfc_size_23 = 256 * 4;
+ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
+ /* 5B - segement 0~3;
+ * 5F - segement 4~7;
+ * 1, 1C, 2C and 6B, 6F unused;
+ */
+ debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
+ dmfc_wr_chan = 0x00000000;
+ dmfc_dp_chan = 0x00008c88;
+ dmfc_size_28 = 0;
+ dmfc_size_29 = 0;
+ dmfc_size_24 = 0;
+ dmfc_size_27 = 256 * 4;
+ dmfc_size_23 = 256 * 4;
+ } else {
+ /* 1 - segment 0, 1;
+ * 5B - segement 4, 5;
+ * 5F - segement 6, 7;
+ * 1C, 2C and 6B, 6F unused;
+ */
+ debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
+ dmfc_wr_chan = 0x00000090;
+ dmfc_dp_chan = 0x00009694;
+ dmfc_size_28 = 128 * 4;
+ dmfc_size_29 = 0;
+ dmfc_size_24 = 0;
+ dmfc_size_27 = 128 * 4;
+ dmfc_size_23 = 128 * 4;
+ }
+ __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
+ __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
+ __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
+ /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
+ __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
+}
+
+void ipu_dmfc_set_wait4eot(int dma_chan, int width)
+{
+ u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
+
+ if (width >= HIGH_RESOLUTION_WIDTH) {
+ if (dma_chan == 23)
+ ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
+ else if (dma_chan == 28)
+ ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
+ }
+
+ if (dma_chan == 23) { /*5B*/
+ if (dmfc_size_23 / width > 3)
+ dmfc_gen1 |= 1UL << 20;
+ else
+ dmfc_gen1 &= ~(1UL << 20);
+ } else if (dma_chan == 24) { /*6B*/
+ if (dmfc_size_24 / width > 1)
+ dmfc_gen1 |= 1UL << 22;
+ else
+ dmfc_gen1 &= ~(1UL << 22);
+ } else if (dma_chan == 27) { /*5F*/
+ if (dmfc_size_27 / width > 2)
+ dmfc_gen1 |= 1UL << 21;
+ else
+ dmfc_gen1 &= ~(1UL << 21);
+ } else if (dma_chan == 28) { /*1*/
+ if (dmfc_size_28 / width > 2)
+ dmfc_gen1 |= 1UL << 16;
+ else
+ dmfc_gen1 &= ~(1UL << 16);
+ } else if (dma_chan == 29) { /*6F*/
+ if (dmfc_size_29 / width > 1)
+ dmfc_gen1 |= 1UL << 23;
+ else
+ dmfc_gen1 &= ~(1UL << 23);
+ }
+
+ __raw_writel(dmfc_gen1, DMFC_GENERAL1);
+}
+
+static void ipu_di_data_wave_config(int di,
+ int wave_gen,
+ int access_size, int component_size)
+{
+ u32 reg;
+ reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
+ (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
+ __raw_writel(reg, DI_DW_GEN(di, wave_gen));
+}
+
+static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
+ int up, int down)
+{
+ u32 reg;
+
+ reg = __raw_readl(DI_DW_GEN(di, wave_gen));
+ reg &= ~(0x3 << (di_pin * 2));
+ reg |= set << (di_pin * 2);
+ __raw_writel(reg, DI_DW_GEN(di, wave_gen));
+
+ __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
+}
+
+static void ipu_di_sync_config(int di, int wave_gen,
+ int run_count, int run_src,
+ int offset_count, int offset_src,
+ int repeat_count, int cnt_clr_src,
+ int cnt_polarity_gen_en,
+ int cnt_polarity_clr_src,
+ int cnt_polarity_trigger_src,
+ int cnt_up, int cnt_down)
+{
+ u32 reg;
+
+ if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
+ (repeat_count >= 0x1000) ||
+ (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
+ printf("DI%d counters out of range.\n", di);
+ return;
+ }
+
+ reg = (run_count << 19) | (++run_src << 16) |
+ (offset_count << 3) | ++offset_src;
+ __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
+ reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
+ (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
+ reg |= (cnt_down << 16) | cnt_up;
+ if (repeat_count == 0) {
+ /* Enable auto reload */
+ reg |= 0x10000000;
+ }
+ __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
+ reg = __raw_readl(DI_STP_REP(di, wave_gen));
+ reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
+ reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
+ __raw_writel(reg, DI_STP_REP(di, wave_gen));
+}
+
+static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
+{
+ int ptr = map * 3 + byte_num;
+ u32 reg;
+
+ reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
+ reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
+ reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
+ __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
+
+ reg = __raw_readl(DC_MAP_CONF_PTR(map));
+ reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
+ reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
+ __raw_writel(reg, DC_MAP_CONF_PTR(map));
+}
+
+static void ipu_dc_map_clear(int map)
+{
+ u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
+ __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
+ DC_MAP_CONF_PTR(map));
+}
+
+static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
+ int wave, int glue, int sync)
+{
+ u32 reg;
+ int stop = 1;
+
+ reg = sync;
+ reg |= (glue << 4);
+ reg |= (++wave << 11);
+ reg |= (++map << 15);
+ reg |= (operand << 20) & 0xFFF00000;
+ __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
+
+ reg = (operand >> 12);
+ reg |= opcode << 4;
+ reg |= (stop << 9);
+ __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
+}
+
+static void ipu_dc_link_event(int chan, int event, int addr, int priority)
+{
+ u32 reg;
+
+ reg = __raw_readl(DC_RL_CH(chan, event));
+ reg &= ~(0xFFFF << (16 * (event & 0x1)));
+ reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
+ __raw_writel(reg, DC_RL_CH(chan, event));
+}
+
+/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
+ * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
+ * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
+ */
+static const int rgb2ycbcr_coeff[5][3] = {
+ {0x4D, 0x96, 0x1D},
+ {0x3D5, 0x3AB, 0x80},
+ {0x80, 0x395, 0x3EB},
+ {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
+ {0x2, 0x2, 0x2}, /* S0, S1, S2 */
+};
+
+/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+ * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+ * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
+ */
+static const int ycbcr2rgb_coeff[5][3] = {
+ {0x095, 0x000, 0x0CC},
+ {0x095, 0x3CE, 0x398},
+ {0x095, 0x0FF, 0x000},
+ {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
+ {0x1, 0x1, 0x1}, /*S0,S1,S2 */
+};
+
+#define mask_a(a) ((u32)(a) & 0x3FF)
+#define mask_b(b) ((u32)(b) & 0x3FFF)
+
+/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
+static int rgb_to_yuv(int n, int red, int green, int blue)
+{
+ int c;
+ c = red * rgb2ycbcr_coeff[n][0];
+ c += green * rgb2ycbcr_coeff[n][1];
+ c += blue * rgb2ycbcr_coeff[n][2];
+ c /= 16;
+ c += rgb2ycbcr_coeff[3][n] * 4;
+ c += 8;
+ c /= 16;
+ if (c < 0)
+ c = 0;
+ if (c > 255)
+ c = 255;
+ return c;
+}
+
+/*
+ * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ */
+static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
+ {
+ {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
+ {0, 0},
+ {0, 0},
+ {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
+ {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
+ },
+ {
+ {0, 0},
+ {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
+ {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
+ {0, 0},
+ {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
+ },
+ {
+ {0, 0},
+ {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
+ {0, 0},
+ {0, 0},
+ {0, 0}
+ },
+ {
+ {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
+ {0, 0},
+ {0, 0},
+ {0, 0},
+ {0, 0}
+ },
+ {
+ {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
+ {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
+ {0, 0},
+ {0, 0},
+ {0, 0}
+ }
+};
+
+static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
+static int color_key_4rgb = 1;
+
+void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
+ unsigned char srm_mode_update)
+{
+ u32 reg;
+ const int (*coeff)[5][3];
+
+ if (dp_csc_param.mode >= 0) {
+ reg = __raw_readl(DP_COM_CONF(dp));
+ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+ reg |= dp_csc_param.mode;
+ __raw_writel(reg, DP_COM_CONF(dp));
+ }
+
+ coeff = dp_csc_param.coeff;
+
+ if (coeff) {
+ __raw_writel(mask_a((*coeff)[0][0]) |
+ (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
+ __raw_writel(mask_a((*coeff)[0][2]) |
+ (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
+ __raw_writel(mask_a((*coeff)[1][1]) |
+ (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
+ __raw_writel(mask_a((*coeff)[2][0]) |
+ (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
+ __raw_writel(mask_a((*coeff)[2][2]) |
+ (mask_b((*coeff)[3][0]) << 16) |
+ ((*coeff)[4][0] << 30), DP_CSC_0(dp));
+ __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
+ (mask_b((*coeff)[3][2]) << 16) |
+ ((*coeff)[4][2] << 30), DP_CSC_1(dp));
+ }
+
+ if (srm_mode_update) {
+ reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+ __raw_writel(reg, IPU_SRM_PRI2);
+ }
+}
+
+int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+ uint32_t out_pixel_fmt)
+{
+ int in_fmt, out_fmt;
+ int dp;
+ int partial = 0;
+ uint32_t reg;
+
+ if (channel == MEM_FG_SYNC) {
+ dp = DP_SYNC;
+ partial = 1;
+ } else if (channel == MEM_BG_SYNC) {
+ dp = DP_SYNC;
+ partial = 0;
+ } else if (channel == MEM_BG_ASYNC0) {
+ dp = DP_ASYNC0;
+ partial = 0;
+ } else {
+ return -EINVAL;
+ }
+
+ in_fmt = format_to_colorspace(in_pixel_fmt);
+ out_fmt = format_to_colorspace(out_pixel_fmt);
+
+ if (partial) {
+ if (in_fmt == RGB) {
+ if (out_fmt == RGB)
+ fg_csc_type = RGB2RGB;
+ else
+ fg_csc_type = RGB2YUV;
+ } else {
+ if (out_fmt == RGB)
+ fg_csc_type = YUV2RGB;
+ else
+ fg_csc_type = YUV2YUV;
+ }
+ } else {
+ if (in_fmt == RGB) {
+ if (out_fmt == RGB)
+ bg_csc_type = RGB2RGB;
+ else
+ bg_csc_type = RGB2YUV;
+ } else {
+ if (out_fmt == RGB)
+ bg_csc_type = YUV2RGB;
+ else
+ bg_csc_type = YUV2YUV;
+ }
+ }
+
+ /* Transform color key from rgb to yuv if CSC is enabled */
+ reg = __raw_readl(DP_COM_CONF(dp));
+ if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
+ (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+ ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+ ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+ ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
+ int red, green, blue;
+ int y, u, v;
+ uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) &
+ 0xFFFFFFL;
+
+ debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
+ color_key);
+
+ red = (color_key >> 16) & 0xFF;
+ green = (color_key >> 8) & 0xFF;
+ blue = color_key & 0xFF;
+
+ y = rgb_to_yuv(0, red, green, blue);
+ u = rgb_to_yuv(1, red, green, blue);
+ v = rgb_to_yuv(2, red, green, blue);
+ color_key = (y << 16) | (u << 8) | v;
+
+ reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
+ __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp));
+ color_key_4rgb = 0;
+
+ debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
+ color_key);
+ }
+
+ ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
+
+ return 0;
+}
+
+void ipu_dp_uninit(ipu_channel_t channel)
+{
+ int dp;
+ int partial = 0;
+
+ if (channel == MEM_FG_SYNC) {
+ dp = DP_SYNC;
+ partial = 1;
+ } else if (channel == MEM_BG_SYNC) {
+ dp = DP_SYNC;
+ partial = 0;
+ } else if (channel == MEM_BG_ASYNC0) {
+ dp = DP_ASYNC0;
+ partial = 0;
+ } else {
+ return;
+ }
+
+ if (partial)
+ fg_csc_type = CSC_NONE;
+ else
+ bg_csc_type = CSC_NONE;
+
+ ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
+}
+
+void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
+{
+ u32 reg = 0;
+
+ if ((dc_chan == 1) || (dc_chan == 5)) {
+ if (interlaced) {
+ ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
+ } else {
+ if (di) {
+ ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
+ 4, 1);
+ } else {
+ ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
+ 7, 1);
+ }
+ }
+ ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+
+ reg = 0x2;
+ reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+ reg |= di << 2;
+ if (interlaced)
+ reg |= DC_WR_CH_CONF_FIELD_MODE;
+ } else if ((dc_chan == 8) || (dc_chan == 9)) {
+ /* async channels */
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
+
+ reg = 0x3;
+ reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+ }
+ __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+ __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
+
+ __raw_writel(0x00000084, DC_GEN);
+}
+
+void ipu_dc_uninit(int dc_chan)
+{
+ if ((dc_chan == 1) || (dc_chan == 5)) {
+ ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+ } else if ((dc_chan == 8) || (dc_chan == 9)) {
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
+ ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
+ }
+}
+
+int ipu_chan_is_interlaced(ipu_channel_t channel)
+{
+ if (channel == MEM_DC_SYNC)
+ return !!(__raw_readl(DC_WR_CH_CONF_1) &
+ DC_WR_CH_CONF_FIELD_MODE);
+ else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
+ return !!(__raw_readl(DC_WR_CH_CONF_5) &
+ DC_WR_CH_CONF_FIELD_MODE);
+ return 0;
+}
+
+void ipu_dp_dc_enable(ipu_channel_t channel)
+{
+ int di;
+ uint32_t reg;
+ uint32_t dc_chan;
+
+ if (channel == MEM_FG_SYNC)
+ dc_chan = 5;
+ if (channel == MEM_DC_SYNC)
+ dc_chan = 1;
+ else if (channel == MEM_BG_SYNC)
+ dc_chan = 5;
+ else
+ return;
+
+ if (channel == MEM_FG_SYNC) {
+ /* Enable FG channel */
+ reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+ __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
+
+ reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+ __raw_writel(reg, IPU_SRM_PRI2);
+ return;
+ }
+
+ di = g_dc_di_assignment[dc_chan];
+
+ /* Make sure other DC sync channel is not assigned same DI */
+ reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
+ if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
+ reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
+ reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
+ __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+ }
+
+ reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+ reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
+ __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+ clk_enable(g_pixel_clk[di]);
+}
+
+static unsigned char dc_swap;
+
+void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
+{
+ uint32_t reg;
+ uint32_t csc;
+ uint32_t dc_chan = 0;
+ int timeout = 50;
+
+ dc_swap = swap;
+
+ if (channel == MEM_DC_SYNC) {
+ dc_chan = 1;
+ } else if (channel == MEM_BG_SYNC) {
+ dc_chan = 5;
+ } else if (channel == MEM_FG_SYNC) {
+ /* Disable FG channel */
+ dc_chan = 5;
+
+ reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+ csc = reg & DP_COM_CONF_CSC_DEF_MASK;
+ if (csc == DP_COM_CONF_CSC_DEF_FG)
+ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+
+ reg &= ~DP_COM_CONF_FG_EN;
+ __raw_writel(reg, DP_COM_CONF(DP_SYNC));
+
+ reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+ __raw_writel(reg, IPU_SRM_PRI2);
+
+ timeout = 50;
+
+ /*
+ * Wait for DC triple buffer to empty,
+ * this check is useful for tv overlay.
+ */
+ if (g_dc_di_assignment[dc_chan] == 0)
+ while ((__raw_readl(DC_STAT) & 0x00000002)
+ != 0x00000002) {
+ udelay(2000);
+ timeout -= 2;
+ if (timeout <= 0)
+ break;
+ }
+ else if (g_dc_di_assignment[dc_chan] == 1)
+ while ((__raw_readl(DC_STAT) & 0x00000020)
+ != 0x00000020) {
+ udelay(2000);
+ timeout -= 2;
+ if (timeout <= 0)
+ break;
+ }
+ return;
+ } else {
+ return;
+ }
+
+ if (dc_swap) {
+ /* Swap DC channel 1 and 5 settings, and disable old dc chan */
+ reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+ __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+ reg ^= DC_WR_CH_CONF_PROG_DI_ID;
+ __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+ } else {
+ timeout = 50;
+
+ /* Wait for DC triple buffer to empty */
+ if (g_dc_di_assignment[dc_chan] == 0)
+ while ((__raw_readl(DC_STAT) & 0x00000002)
+ != 0x00000002) {
+ udelay(2000);
+ timeout -= 2;
+ if (timeout <= 0)
+ break;
+ }
+ else if (g_dc_di_assignment[dc_chan] == 1)
+ while ((__raw_readl(DC_STAT) & 0x00000020)
+ != 0x00000020) {
+ udelay(2000);
+ timeout -= 2;
+ if (timeout <= 0)
+ break;
+ }
+
+ reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+ __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+ reg = __raw_readl(IPU_DISP_GEN);
+ if (g_dc_di_assignment[dc_chan])
+ reg &= ~DI1_COUNTER_RELEASE;
+ else
+ reg &= ~DI0_COUNTER_RELEASE;
+ __raw_writel(reg, IPU_DISP_GEN);
+
+ /* Clock is already off because it must be done quickly, but
+ we need to fix the ref count */
+ clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
+ }
+}
+
+void ipu_init_dc_mappings(void)
+{
+ /* IPU_PIX_FMT_RGB24 */
+ ipu_dc_map_clear(0);
+ ipu_dc_map_config(0, 0, 7, 0xFF);
+ ipu_dc_map_config(0, 1, 15, 0xFF);
+ ipu_dc_map_config(0, 2, 23, 0xFF);
+
+ /* IPU_PIX_FMT_RGB666 */
+ ipu_dc_map_clear(1);
+ ipu_dc_map_config(1, 0, 5, 0xFC);
+ ipu_dc_map_config(1, 1, 11, 0xFC);
+ ipu_dc_map_config(1, 2, 17, 0xFC);
+
+ /* IPU_PIX_FMT_YUV444 */
+ ipu_dc_map_clear(2);
+ ipu_dc_map_config(2, 0, 15, 0xFF);
+ ipu_dc_map_config(2, 1, 23, 0xFF);
+ ipu_dc_map_config(2, 2, 7, 0xFF);
+
+ /* IPU_PIX_FMT_RGB565 */
+ ipu_dc_map_clear(3);
+ ipu_dc_map_config(3, 0, 4, 0xF8);
+ ipu_dc_map_config(3, 1, 10, 0xFC);
+ ipu_dc_map_config(3, 2, 15, 0xF8);
+
+ /* IPU_PIX_FMT_LVDS666 */
+ ipu_dc_map_clear(4);
+ ipu_dc_map_config(4, 0, 5, 0xFC);
+ ipu_dc_map_config(4, 1, 13, 0xFC);
+ ipu_dc_map_config(4, 2, 21, 0xFC);
+}
+
+int ipu_pixfmt_to_map(uint32_t fmt)
+{
+ switch (fmt) {
+ case IPU_PIX_FMT_GENERIC:
+ case IPU_PIX_FMT_RGB24:
+ return 0;
+ case IPU_PIX_FMT_RGB666:
+ return 1;
+ case IPU_PIX_FMT_YUV444:
+ return 2;
+ case IPU_PIX_FMT_RGB565:
+ return 3;
+ case IPU_PIX_FMT_LVDS666:
+ return 4;
+ }
+
+ return -1;
+}
+
+/*
+ * This function is called to adapt synchronous LCD panel to IPU restriction.
+ */
+void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
+ uint16_t width, uint16_t height,
+ uint16_t h_start_width,
+ uint16_t h_end_width,
+ uint16_t v_start_width,
+ uint16_t *v_end_width)
+{
+ if (*v_end_width < 2) {
+ uint16_t total_width = width + h_start_width + h_end_width;
+ uint16_t total_height_old = height + v_start_width +
+ (*v_end_width);
+ uint16_t total_height_new = height + v_start_width + 2;
+ *v_end_width = 2;
+ *pixel_clk = (*pixel_clk) * total_width * total_height_new /
+ (total_width * total_height_old);
+ printf("WARNING: adapt panel end blank lines\n");
+ }
+}
+
+/*
+ * This function is called to initialize a synchronous LCD panel.
+ *
+ * @param disp The DI the panel is attached to.
+ *
+ * @param pixel_clk Desired pixel clock frequency in Hz.
+ *
+ * @param pixel_fmt Input parameter for pixel format of buffer.
+ * Pixel format is a FOURCC ASCII code.
+ *
+ * @param width The width of panel in pixels.
+ *
+ * @param height The height of panel in pixels.
+ *
+ * @param hStartWidth The number of pixel clocks between the HSYNC
+ * signal pulse and the start of valid data.
+ *
+ * @param hSyncWidth The width of the HSYNC signal in units of pixel
+ * clocks.
+ *
+ * @param hEndWidth The number of pixel clocks between the end of
+ * valid data and the HSYNC signal for next line.
+ *
+ * @param vStartWidth The number of lines between the VSYNC
+ * signal pulse and the start of valid data.
+ *
+ * @param vSyncWidth The width of the VSYNC signal in units of lines
+ *
+ * @param vEndWidth The number of lines between the end of valid
+ * data and the VSYNC signal for next frame.
+ *
+ * @param sig Bitfield of signal polarities for LCD interface.
+ *
+ * @return This function returns 0 on success or negative error code on
+ * fail.
+ */
+
+int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
+ uint16_t width, uint16_t height,
+ uint32_t pixel_fmt,
+ uint16_t h_start_width, uint16_t h_sync_width,
+ uint16_t h_end_width, uint16_t v_start_width,
+ uint16_t v_sync_width, uint16_t v_end_width,
+ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+{
+ uint32_t reg;
+ uint32_t di_gen, vsync_cnt;
+ uint32_t div, rounded_pixel_clk;
+ uint32_t h_total, v_total;
+ int map;
+ struct clk *di_parent;
+
+ debug("panel size = %d x %d\n", width, height);
+
+ if ((v_sync_width == 0) || (h_sync_width == 0))
+ return EINVAL;
+
+ adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
+ h_start_width, h_end_width,
+ v_start_width, &v_end_width);
+ h_total = width + h_sync_width + h_start_width + h_end_width;
+ v_total = height + v_sync_width + v_start_width + v_end_width;
+
+ /* Init clocking */
+ debug("pixel clk = %d\n", pixel_clk);
+
+ if (sig.ext_clk) {
+ if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
+ /*
+ * Set the PLL to be an even multiple
+ * of the pixel clock.
+ */
+ if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
+ (clk_get_usecount(g_pixel_clk[1]) == 0)) {
+ di_parent = clk_get_parent(g_di_clk[disp]);
+ rounded_pixel_clk =
+ clk_round_rate(g_pixel_clk[disp],
+ pixel_clk);
+ div = clk_get_rate(di_parent) /
+ rounded_pixel_clk;
+ if (div % 2)
+ div++;
+ if (clk_get_rate(di_parent) != div *
+ rounded_pixel_clk)
+ clk_set_rate(di_parent,
+ div * rounded_pixel_clk);
+ udelay(10000);
+ clk_set_rate(g_di_clk[disp],
+ 2 * rounded_pixel_clk);
+ udelay(10000);
+ }
+ }
+ clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+ } else {
+ if (clk_get_usecount(g_pixel_clk[disp]) != 0)
+ clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
+ }
+ rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
+ clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
+ udelay(5000);
+ /* Get integer portion of divider */
+ div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
+ rounded_pixel_clk;
+
+ ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
+ ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
+
+ map = ipu_pixfmt_to_map(pixel_fmt);
+ if (map < 0) {
+ debug("IPU_DISP: No MAP\n");
+ return -EINVAL;
+ }
+
+ di_gen = __raw_readl(DI_GENERAL(disp));
+
+ if (sig.interlaced) {
+ /* Setup internal HSYNC waveform */
+ ipu_di_sync_config(
+ disp, /* display */
+ 1, /* counter */
+ h_total / 2 - 1,/* run count */
+ DI_SYNC_CLK, /* run_resolution */
+ 0, /* offset */
+ DI_SYNC_NONE, /* offset resolution */
+ 0, /* repeat count */
+ DI_SYNC_NONE, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ /* Field 1 VSYNC waveform */
+ ipu_di_sync_config(
+ disp, /* display */
+ 2, /* counter */
+ h_total - 1, /* run count */
+ DI_SYNC_CLK, /* run_resolution */
+ 0, /* offset */
+ DI_SYNC_NONE, /* offset resolution */
+ 0, /* repeat count */
+ DI_SYNC_NONE, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 4 /* COUNT DOWN */
+ );
+
+ /* Setup internal HSYNC waveform */
+ ipu_di_sync_config(
+ disp, /* display */
+ 3, /* counter */
+ v_total * 2 - 1,/* run count */
+ DI_SYNC_INT_HSYNC, /* run_resolution */
+ 1, /* offset */
+ DI_SYNC_INT_HSYNC, /* offset resolution */
+ 0, /* repeat count */
+ DI_SYNC_NONE, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 4 /* COUNT DOWN */
+ );
+
+ /* Active Field ? */
+ ipu_di_sync_config(
+ disp, /* display */
+ 4, /* counter */
+ v_total / 2 - 1,/* run count */
+ DI_SYNC_HSYNC, /* run_resolution */
+ v_start_width, /* offset */
+ DI_SYNC_HSYNC, /* offset resolution */
+ 2, /* repeat count */
+ DI_SYNC_VSYNC, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ /* Active Line */
+ ipu_di_sync_config(
+ disp, /* display */
+ 5, /* counter */
+ 0, /* run count */
+ DI_SYNC_HSYNC, /* run_resolution */
+ 0, /* offset */
+ DI_SYNC_NONE, /* offset resolution */
+ height / 2, /* repeat count */
+ 4, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ /* Field 0 VSYNC waveform */
+ ipu_di_sync_config(
+ disp, /* display */
+ 6, /* counter */
+ v_total - 1, /* run count */
+ DI_SYNC_HSYNC, /* run_resolution */
+ 0, /* offset */
+ DI_SYNC_NONE, /* offset resolution */
+ 0, /* repeat count */
+ DI_SYNC_NONE, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ /* DC VSYNC waveform */
+ vsync_cnt = 7;
+ ipu_di_sync_config(
+ disp, /* display */
+ 7, /* counter */
+ v_total / 2 - 1,/* run count */
+ DI_SYNC_HSYNC, /* run_resolution */
+ 9, /* offset */
+ DI_SYNC_HSYNC, /* offset resolution */
+ 2, /* repeat count */
+ DI_SYNC_VSYNC, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ /* active pixel waveform */
+ ipu_di_sync_config(
+ disp, /* display */
+ 8, /* counter */
+ 0, /* run count */
+ DI_SYNC_CLK, /* run_resolution */
+ h_start_width, /* offset */
+ DI_SYNC_CLK, /* offset resolution */
+ width, /* repeat count */
+ 5, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 0 /* COUNT DOWN */
+ );
+
+ ipu_di_sync_config(
+ disp, /* display */
+ 9, /* counter */
+ v_total - 1, /* run count */
+ DI_SYNC_INT_HSYNC,/* run_resolution */
+ v_total / 2, /* offset */
+ DI_SYNC_INT_HSYNC,/* offset resolution */
+ 0, /* repeat count */
+ DI_SYNC_HSYNC, /* CNT_CLR_SEL */
+ 0, /* CNT_POLARITY_GEN_EN */
+ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
+ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
+ 0, /* COUNT UP */
+ 4 /* COUNT DOWN */
+ );
+
+ /* set gentime select and tag sel */
+ reg = __raw_readl(DI_SW_GEN1(disp, 9));
+ reg &= 0x1FFFFFFF;
+ reg |= (3 - 1)<<29 | 0x00008000;
+ __raw_writel(reg, DI_SW_GEN1(disp, 9));
+
+ __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
+
+ /* set y_sel = 1 */
+ di_gen |= 0x10000000;
+ di_gen |= DI_GEN_POLARITY_5;
+ di_gen |= DI_GEN_POLARITY_8;
+ } else {
+ /* Setup internal HSYNC waveform */
+ ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
+ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+ 0, DI_SYNC_NONE,
+ DI_SYNC_NONE, 0, 0);
+
+ /* Setup external (delayed) HSYNC waveform */
+ ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
+ DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
+ 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
+ DI_SYNC_CLK, 0, h_sync_width * 2);
+ /* Setup VSYNC waveform */
+ vsync_cnt = DI_SYNC_VSYNC;
+ ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
+ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
+ DI_SYNC_NONE, 1, DI_SYNC_NONE,
+ DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
+ __raw_writel(v_total - 1, DI_SCR_CONF(disp));
+
+ /* Setup active data waveform to sync with DC */
+ ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
+ v_sync_width + v_start_width, DI_SYNC_HSYNC,
+ height,
+ DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
+ DI_SYNC_NONE, 0, 0);
+ ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
+ h_sync_width + h_start_width, DI_SYNC_CLK,
+ width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
+ 0);
+
+ /* reset all unused counters */
+ __raw_writel(0, DI_SW_GEN0(disp, 6));
+ __raw_writel(0, DI_SW_GEN1(disp, 6));
+ __raw_writel(0, DI_SW_GEN0(disp, 7));
+ __raw_writel(0, DI_SW_GEN1(disp, 7));
+ __raw_writel(0, DI_SW_GEN0(disp, 8));
+ __raw_writel(0, DI_SW_GEN1(disp, 8));
+ __raw_writel(0, DI_SW_GEN0(disp, 9));
+ __raw_writel(0, DI_SW_GEN1(disp, 9));
+
+ reg = __raw_readl(DI_STP_REP(disp, 6));
+ reg &= 0x0000FFFF;
+ __raw_writel(reg, DI_STP_REP(disp, 6));
+ __raw_writel(0, DI_STP_REP(disp, 7));
+ __raw_writel(0, DI_STP_REP(disp, 9));
+
+ /* Init template microcode */
+ if (disp) {
+ ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+ ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+ ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+ } else {
+ ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+ ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+ ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+ }
+
+ if (sig.Hsync_pol)
+ di_gen |= DI_GEN_POLARITY_2;
+ if (sig.Vsync_pol)
+ di_gen |= DI_GEN_POLARITY_3;
+
+ if (sig.clk_pol)
+ di_gen |= DI_GEN_POL_CLK;
+
+ }
+
+ __raw_writel(di_gen, DI_GENERAL(disp));
+
+ __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+ 0x00000002, DI_SYNC_AS_GEN(disp));
+
+ reg = __raw_readl(DI_POL(disp));
+ reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
+ if (sig.enable_pol)
+ reg |= DI_POL_DRDY_POLARITY_15;
+ if (sig.data_pol)
+ reg |= DI_POL_DRDY_DATA_POLARITY;
+ __raw_writel(reg, DI_POL(disp));
+
+ __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
+
+ return 0;
+}
+
+/*
+ * This function sets the foreground and background plane global alpha blending
+ * modes. This function also sets the DP graphic plane according to the
+ * parameter of IPUv3 DP channel.
+ *
+ * @param channel IPUv3 DP channel
+ *
+ * @param enable Boolean to enable or disable global alpha
+ * blending. If disabled, local blending is used.
+ *
+ * @param alpha Global alpha value.
+ *
+ * @return Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
+ uint8_t alpha)
+{
+ uint32_t reg;
+ uint32_t flow;
+
+ unsigned char bg_chan;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+ flow = DP_SYNC;
+ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+ flow = DP_ASYNC0;
+ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+ flow = DP_ASYNC1;
+ else
+ return -EINVAL;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
+ channel == MEM_BG_ASYNC1)
+ bg_chan = 1;
+ else
+ bg_chan = 0;
+
+ if (!g_ipu_clk_enabled)
+ clk_enable(g_ipu_clk);
+
+ if (bg_chan) {
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+ } else {
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+ }
+
+ if (enable) {
+ reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+ __raw_writel(reg | ((uint32_t) alpha << 24),
+ DP_GRAPH_WIND_CTRL(flow));
+
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+ } else {
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+ }
+
+ reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+ __raw_writel(reg, IPU_SRM_PRI2);
+
+ if (!g_ipu_clk_enabled)
+ clk_disable(g_ipu_clk);
+
+ return 0;
+}
+
+/*
+ * This function sets the transparent color key for SDC graphic plane.
+ *
+ * @param channel Input parameter for the logical channel ID.
+ *
+ * @param enable Boolean to enable or disable color key
+ *
+ * @param colorKey 24-bit RGB color for transparent color key.
+ *
+ * @return Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
+ uint32_t color_key)
+{
+ uint32_t reg, flow;
+ int y, u, v;
+ int red, green, blue;
+
+ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+ flow = DP_SYNC;
+ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+ flow = DP_ASYNC0;
+ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+ flow = DP_ASYNC1;
+ else
+ return -EINVAL;
+
+ if (!g_ipu_clk_enabled)
+ clk_enable(g_ipu_clk);
+
+ color_key_4rgb = 1;
+ /* Transform color key from rgb to yuv if CSC is enabled */
+ if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+ ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+ ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+ ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
+
+ debug("color key 0x%x need change to yuv fmt\n", color_key);
+
+ red = (color_key >> 16) & 0xFF;
+ green = (color_key >> 8) & 0xFF;
+ blue = color_key & 0xFF;
+
+ y = rgb_to_yuv(0, red, green, blue);
+ u = rgb_to_yuv(1, red, green, blue);
+ v = rgb_to_yuv(2, red, green, blue);
+ color_key = (y << 16) | (u << 8) | v;
+
+ color_key_4rgb = 0;
+
+ debug("color key change to yuv fmt 0x%x\n", color_key);
+ }
+
+ if (enable) {
+ reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
+ __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+ } else {
+ reg = __raw_readl(DP_COM_CONF(flow));
+ __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+ }
+
+ reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+ __raw_writel(reg, IPU_SRM_PRI2);
+
+ if (!g_ipu_clk_enabled)
+ clk_disable(g_ipu_clk);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IPU_REGS_INCLUDED__
+#define __IPU_REGS_INCLUDED__
+
+#define IPU_DISP0_BASE 0x00000000
+#define IPU_MCU_T_DEFAULT 8
+#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
+#define IPU_CM_REG_BASE 0x1E000000
+#define IPU_STAT_REG_BASE 0x1E000200
+#define IPU_IDMAC_REG_BASE 0x1E008000
+#define IPU_ISP_REG_BASE 0x1E010000
+#define IPU_DP_REG_BASE 0x1E018000
+#define IPU_IC_REG_BASE 0x1E020000
+#define IPU_IRT_REG_BASE 0x1E028000
+#define IPU_CSI0_REG_BASE 0x1E030000
+#define IPU_CSI1_REG_BASE 0x1E038000
+#define IPU_DI0_REG_BASE 0x1E040000
+#define IPU_DI1_REG_BASE 0x1E048000
+#define IPU_SMFC_REG_BASE 0x1E050000
+#define IPU_DC_REG_BASE 0x1E058000
+#define IPU_DMFC_REG_BASE 0x1E060000
+#define IPU_CPMEM_REG_BASE 0x1F000000
+#define IPU_LUT_REG_BASE 0x1F020000
+#define IPU_SRM_REG_BASE 0x1F040000
+#define IPU_TPM_REG_BASE 0x1F060000
+#define IPU_DC_TMPL_REG_BASE 0x1F080000
+#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000
+#define IPU_VDI_REG_BASE 0x1E068000
+
+
+extern u32 *ipu_dc_tmpl_reg;
+
+#define DC_EVT_NF 0
+#define DC_EVT_NL 1
+#define DC_EVT_EOF 2
+#define DC_EVT_NFIELD 3
+#define DC_EVT_EOL 4
+#define DC_EVT_EOFIELD 5
+#define DC_EVT_NEW_ADDR 6
+#define DC_EVT_NEW_CHAN 7
+#define DC_EVT_NEW_DATA 8
+
+#define DC_EVT_NEW_ADDR_W_0 0
+#define DC_EVT_NEW_ADDR_W_1 1
+#define DC_EVT_NEW_CHAN_W_0 2
+#define DC_EVT_NEW_CHAN_W_1 3
+#define DC_EVT_NEW_DATA_W_0 4
+#define DC_EVT_NEW_DATA_W_1 5
+#define DC_EVT_NEW_ADDR_R_0 6
+#define DC_EVT_NEW_ADDR_R_1 7
+#define DC_EVT_NEW_CHAN_R_0 8
+#define DC_EVT_NEW_CHAN_R_1 9
+#define DC_EVT_NEW_DATA_R_0 10
+#define DC_EVT_NEW_DATA_R_1 11
+
+/* Software reset for ipu */
+#define SW_IPU_RST 8
+
+enum {
+ IPU_CONF_DP_EN = 0x00000020,
+ IPU_CONF_DI0_EN = 0x00000040,
+ IPU_CONF_DI1_EN = 0x00000080,
+ IPU_CONF_DMFC_EN = 0x00000400,
+ IPU_CONF_DC_EN = 0x00000200,
+
+ DI0_COUNTER_RELEASE = 0x01000000,
+ DI1_COUNTER_RELEASE = 0x02000000,
+
+ DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
+ DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
+
+ DI_GEN_DI_CLK_EXT = 0x100000,
+ DI_GEN_POLARITY_1 = 0x00000001,
+ DI_GEN_POLARITY_2 = 0x00000002,
+ DI_GEN_POLARITY_3 = 0x00000004,
+ DI_GEN_POLARITY_4 = 0x00000008,
+ DI_GEN_POLARITY_5 = 0x00000010,
+ DI_GEN_POLARITY_6 = 0x00000020,
+ DI_GEN_POLARITY_7 = 0x00000040,
+ DI_GEN_POLARITY_8 = 0x00000080,
+ DI_GEN_POL_CLK = 0x20000,
+
+ DI_POL_DRDY_DATA_POLARITY = 0x00000080,
+ DI_POL_DRDY_POLARITY_15 = 0x00000010,
+ DI_VSYNC_SEL_OFFSET = 13,
+
+ DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
+ DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
+ DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
+ DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
+ DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
+ DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
+
+ DP_COM_CONF_FG_EN = 0x00000001,
+ DP_COM_CONF_GWSEL = 0x00000002,
+ DP_COM_CONF_GWAM = 0x00000004,
+ DP_COM_CONF_GWCKE = 0x00000008,
+ DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
+ DP_COM_CONF_CSC_DEF_OFFSET = 8,
+ DP_COM_CONF_CSC_DEF_FG = 0x00000300,
+ DP_COM_CONF_CSC_DEF_BG = 0x00000200,
+ DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
+ DP_COM_CONF_GAMMA_EN = 0x00001000,
+ DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
+};
+
+enum di_pins {
+ DI_PIN11 = 0,
+ DI_PIN12 = 1,
+ DI_PIN13 = 2,
+ DI_PIN14 = 3,
+ DI_PIN15 = 4,
+ DI_PIN16 = 5,
+ DI_PIN17 = 6,
+ DI_PIN_CS = 7,
+
+ DI_PIN_SER_CLK = 0,
+ DI_PIN_SER_RS = 1,
+};
+
+enum di_sync_wave {
+ DI_SYNC_NONE = -1,
+ DI_SYNC_CLK = 0,
+ DI_SYNC_INT_HSYNC = 1,
+ DI_SYNC_HSYNC = 2,
+ DI_SYNC_VSYNC = 3,
+ DI_SYNC_DE = 5,
+};
+
+struct ipu_cm {
+ u32 conf;
+ u32 sisg_ctrl0;
+ u32 sisg_ctrl1;
+ u32 sisg_set[6];
+ u32 sisg_clear[6];
+ u32 int_ctrl[15];
+ u32 sdma_event[10];
+ u32 srm_pri1;
+ u32 srm_pri2;
+ u32 fs_proc_flow[3];
+ u32 fs_disp_flow[2];
+ u32 skip;
+ u32 disp_alt_conf;
+ u32 disp_gen;
+ u32 disp_alt[4];
+ u32 snoop;
+ u32 mem_rst;
+ u32 pm;
+ u32 gpr;
+ u32 reserved0[26];
+ u32 ch_db_mode_sel[2];
+ u32 reserved1[16];
+ u32 alt_ch_db_mode_sel[2];
+ u32 reserved2[2];
+ u32 ch_trb_mode_sel[2];
+};
+
+struct ipu_idmac {
+ u32 conf;
+ u32 ch_en[2];
+ u32 sep_alpha;
+ u32 alt_sep_alpha;
+ u32 ch_pri[2];
+ u32 wm_en[2];
+ u32 lock_en[2];
+ u32 sub_addr[5];
+ u32 bndm_en[2];
+ u32 sc_cord[2];
+ u32 reserved[45];
+ u32 ch_busy[2];
+};
+
+struct ipu_com_async {
+ u32 com_conf_async;
+ u32 graph_wind_ctrl_async;
+ u32 fg_pos_async;
+ u32 cur_pos_async;
+ u32 cur_map_async;
+ u32 gamma_c_async[8];
+ u32 gamma_s_async[4];
+ u32 dp_csca_async[4];
+ u32 dp_csc_async[2];
+};
+
+struct ipu_dp {
+ u32 com_conf_sync;
+ u32 graph_wind_ctrl_sync;
+ u32 fg_pos_sync;
+ u32 cur_pos_sync;
+ u32 cur_map_sync;
+ u32 gamma_c_sync[8];
+ u32 gamma_s_sync[4];
+ u32 csca_sync[4];
+ u32 csc_sync[2];
+ u32 cur_pos_alt;
+ struct ipu_com_async async[2];
+};
+
+struct ipu_di {
+ u32 general;
+ u32 bs_clkgen0;
+ u32 bs_clkgen1;
+ u32 sw_gen0[9];
+ u32 sw_gen1[9];
+ u32 sync_as;
+ u32 dw_gen[12];
+ u32 dw_set[48];
+ u32 stp_rep[4];
+ u32 stp_rep9;
+ u32 ser_conf;
+ u32 ssc;
+ u32 pol;
+ u32 aw0;
+ u32 aw1;
+ u32 scr_conf;
+ u32 stat;
+};
+
+struct ipu_stat {
+ u32 int_stat[15];
+ u32 cur_buf[2];
+ u32 alt_cur_buf_0;
+ u32 alt_cur_buf_1;
+ u32 srm_stat;
+ u32 proc_task_stat;
+ u32 disp_task_stat;
+ u32 triple_cur_buf[4];
+ u32 ch_buf0_rdy[2];
+ u32 ch_buf1_rdy[2];
+ u32 alt_ch_buf0_rdy[2];
+ u32 alt_ch_buf1_rdy[2];
+ u32 ch_buf2_rdy[2];
+};
+
+struct ipu_dc_ch {
+ u32 wr_ch_conf;
+ u32 wr_ch_addr;
+ u32 rl[5];
+};
+
+struct ipu_dc {
+ struct ipu_dc_ch dc_ch0_1_2[3];
+ u32 cmd_ch_conf_3;
+ u32 cmd_ch_conf_4;
+ struct ipu_dc_ch dc_ch5_6[2];
+ struct ipu_dc_ch dc_ch8;
+ u32 rl6_ch_8;
+ struct ipu_dc_ch dc_ch9;
+ u32 rl6_ch_9;
+ u32 gen;
+ u32 disp_conf1[4];
+ u32 disp_conf2[4];
+ u32 di0_conf[2];
+ u32 di1_conf[2];
+ u32 dc_map_ptr[15];
+ u32 dc_map_val[12];
+ u32 udge[16];
+ u32 lla[2];
+ u32 r_lla[2];
+ u32 wr_ch_addr_5_alt;
+ u32 stat;
+};
+
+struct ipu_dmfc {
+ u32 rd_chan;
+ u32 wr_chan;
+ u32 wr_chan_def;
+ u32 dp_chan;
+ u32 dp_chan_def;
+ u32 general[2];
+ u32 ic_ctrl;
+ u32 wr_chan_alt;
+ u32 wr_chan_def_alt;
+ u32 general1_alt;
+ u32 stat;
+};
+
+#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
+ IPU_CM_REG_BASE))
+#define IPU_CONF (&IPU_CM_REG->conf)
+#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
+#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
+#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
+#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
+#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
+#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
+#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
+#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
+#define IPU_GPR (&IPU_CM_REG->gpr)
+#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
+
+#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
+ IPU_STAT_REG_BASE))
+#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
+#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
+#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
+
+#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
+
+#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
+ IPU_IDMAC_REG_BASE))
+#define IDMAC_CONF (&IDMAC_REG->conf)
+#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
+#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
+
+#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
+ ((di == 1) ? IPU_DI1_REG_BASE : \
+ IPU_DI0_REG_BASE)))
+#define DI_GENERAL(di) (&DI_REG(di)->general)
+#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
+#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
+
+#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
+#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
+#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
+#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
+#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
+#define DI_POL(di) (&DI_REG(di)->pol)
+#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
+
+#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
+ IPU_DMFC_REG_BASE))
+#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
+#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
+#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
+#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
+#define DMFC_GENERAL1 (&DMFC_REG->general[0])
+#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
+
+
+#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
+ IPU_DC_REG_BASE))
+#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
+#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
+
+
+static inline struct ipu_dc_ch *dc_ch_offset(int ch)
+{
+ switch (ch) {
+ case 0:
+ case 1:
+ case 2:
+ return &DC_REG->dc_ch0_1_2[ch];
+ case 5:
+ case 6:
+ return &DC_REG->dc_ch5_6[ch - 5];
+ case 8:
+ return &DC_REG->dc_ch8;
+ case 9:
+ return &DC_REG->dc_ch9;
+ default:
+ printf("%s: invalid channel %d\n", __func__, ch);
+ return NULL;
+ }
+
+}
+
+#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
+
+#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
+#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
+
+#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
+#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
+
+#define DC_GEN (&DC_REG->gen)
+#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
+#define DC_STAT (&DC_REG->stat)
+
+#define DP_SYNC 0
+#define DP_ASYNC0 0x60
+#define DP_ASYNC1 0xBC
+
+#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
+ IPU_DP_REG_BASE))
+#define DP_COM_CONF(flow) (&DP_REG->com_conf_sync)
+#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
+#define DP_CSC_A_0(flow) (&DP_REG->csca_sync[0])
+#define DP_CSC_A_1(flow) (&DP_REG->csca_sync[1])
+#define DP_CSC_A_2(flow) (&DP_REG->csca_sync[2])
+#define DP_CSC_A_3(flow) (&DP_REG->csca_sync[3])
+
+#define DP_CSC_0(flow) (&DP_REG->csc_sync[0])
+#define DP_CSC_1(flow) (&DP_REG->csc_sync[1])
+
+/* DC template opcodes */
+#define WROD(lf) (0x18 | (lf << 1))
+
+#endif
#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
-#define IF_CLK_DIV 0x175
+#define IF_CLK_DIV 0x55
#else
#define XRES 240
#define YRES 320
#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
-enum lcd_pin {
- MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
- MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
- MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
- MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
- MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
-
- MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
- MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
- MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
-
- MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
- MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
- MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
- MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
- MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
- MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
- MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
- MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
- MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
- MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
- MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
- MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
- MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
- MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
- MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
- MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
- MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
- MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
-};
-
struct chan_param_mem_planar {
/* Word 0 */
u32 xv:10;
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * MX51 Linux framebuffer:
+ *
+ * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+#include <common.h>
+#include <asm/errno.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <lcd.h>
+#include "videomodes.h"
+#include "ipu.h"
+#include "mxcfb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+vidinfo_t panel_info;
+
+static int mxcfb_map_video_memory(struct fb_info *fbi);
+static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+void fb_videomode_to_var(struct fb_var_screeninfo *var,
+ const struct fb_videomode *mode)
+{
+ var->xres = mode->xres;
+ var->yres = mode->yres;
+ var->xres_virtual = mode->xres;
+ var->yres_virtual = mode->yres;
+ var->xoffset = 0;
+ var->yoffset = 0;
+ var->pixclock = mode->pixclock;
+ var->left_margin = mode->left_margin;
+ var->right_margin = mode->right_margin;
+ var->upper_margin = mode->upper_margin;
+ var->lower_margin = mode->lower_margin;
+ var->hsync_len = mode->hsync_len;
+ var->vsync_len = mode->vsync_len;
+ var->sync = mode->sync;
+ var->vmode = mode->vmode & FB_VMODE_MASK;
+}
+
+/*
+ * Structure containing the MXC specific framebuffer information.
+ */
+struct mxcfb_info {
+ int blank;
+ ipu_channel_t ipu_ch;
+ int ipu_di;
+ u32 ipu_di_pix_fmt;
+ unsigned char overlay;
+ unsigned char alpha_chan_en;
+ dma_addr_t alpha_phy_addr0;
+ dma_addr_t alpha_phy_addr1;
+ void *alpha_virt_addr0;
+ void *alpha_virt_addr1;
+ uint32_t alpha_mem_len;
+ uint32_t cur_ipu_buf;
+ uint32_t cur_ipu_alpha_buf;
+
+ u32 pseudo_palette[16];
+};
+
+enum {
+ BOTH_ON,
+ SRC_ON,
+ TGT_ON,
+ BOTH_OFF
+};
+
+static unsigned long default_bpp = 16;
+static unsigned char g_dp_in_use;
+static struct fb_info *mxcfb_info[3];
+static int ext_clk_used;
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+ uint32_t pixfmt = 0;
+
+ debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);
+
+ if (fbi->var.nonstd)
+ return fbi->var.nonstd;
+
+ switch (fbi->var.bits_per_pixel) {
+ case 24:
+ pixfmt = IPU_PIX_FMT_BGR24;
+ break;
+ case 32:
+ pixfmt = IPU_PIX_FMT_BGR32;
+ break;
+ case 16:
+ pixfmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ return pixfmt;
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param info framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+ struct fb_fix_screeninfo *fix = &info->fix;
+ struct fb_var_screeninfo *var = &info->var;
+
+ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+ fix->type = FB_TYPE_PACKED_PIXELS;
+ fix->accel = FB_ACCEL_NONE;
+ fix->visual = FB_VISUAL_TRUECOLOR;
+ fix->xpanstep = 1;
+ fix->ypanstep = 1;
+
+ return 0;
+}
+
+static int setup_disp_channel1(struct fb_info *fbi)
+{
+ ipu_channel_params_t params;
+ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+ memset(¶ms, 0, sizeof(params));
+ params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
+
+ debug("%s called\n", __func__);
+ /*
+ * Assuming interlaced means yuv output, below setting also
+ * valid for mem_dc_sync. FG should have the same vmode as BG.
+ */
+ if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+ params.mem_dp_bg_sync.interlaced = 1;
+ params.mem_dp_bg_sync.out_pixel_fmt =
+ IPU_PIX_FMT_YUV444;
+ } else {
+ if (mxc_fbi->ipu_di_pix_fmt) {
+ params.mem_dp_bg_sync.out_pixel_fmt =
+ mxc_fbi->ipu_di_pix_fmt;
+ } else {
+ params.mem_dp_bg_sync.out_pixel_fmt =
+ IPU_PIX_FMT_RGB666;
+ }
+ }
+ params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+ if (mxc_fbi->alpha_chan_en)
+ params.mem_dp_bg_sync.alpha_chan_en = 1;
+
+ ipu_init_channel(mxc_fbi->ipu_ch, ¶ms);
+
+ return 0;
+}
+
+static int setup_disp_channel2(struct fb_info *fbi)
+{
+ int retval = 0;
+ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+ mxc_fbi->cur_ipu_buf = 1;
+ if (mxc_fbi->alpha_chan_en)
+ mxc_fbi->cur_ipu_alpha_buf = 1;
+
+ fbi->var.xoffset = fbi->var.yoffset = 0;
+
+ debug("%s: %x %d %d %d %lx %lx\n",
+ __func__,
+ mxc_fbi->ipu_ch,
+ fbi->var.xres,
+ fbi->var.yres,
+ fbi->fix.line_length,
+ fbi->fix.smem_start,
+ fbi->fix.smem_start +
+ (fbi->fix.line_length * fbi->var.yres));
+
+ retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+ bpp_to_pixfmt(fbi),
+ fbi->var.xres, fbi->var.yres,
+ fbi->fix.line_length,
+ fbi->fix.smem_start +
+ (fbi->fix.line_length * fbi->var.yres),
+ fbi->fix.smem_start,
+ 0, 0);
+ if (retval)
+ printf("ipu_init_channel_buffer error %d\n", retval);
+
+ return retval;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param info framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+ int retval = 0;
+ u32 mem_len;
+ ipu_di_signal_cfg_t sig_cfg;
+ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+ uint32_t out_pixel_fmt;
+
+ ipu_disable_channel(mxc_fbi->ipu_ch);
+ ipu_uninit_channel(mxc_fbi->ipu_ch);
+ mxcfb_set_fix(fbi);
+
+ mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+ if (fbi->fix.smem_start)
+ mxcfb_unmap_video_memory(fbi);
+
+ if (mxcfb_map_video_memory(fbi) < 0)
+ return -ENOMEM;
+ }
+
+ setup_disp_channel1(fbi);
+
+ memset(&sig_cfg, 0, sizeof(sig_cfg));
+ if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+ sig_cfg.interlaced = 1;
+ out_pixel_fmt = IPU_PIX_FMT_YUV444;
+ } else {
+ if (mxc_fbi->ipu_di_pix_fmt)
+ out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+ else
+ out_pixel_fmt = IPU_PIX_FMT_RGB666;
+ }
+ if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
+ sig_cfg.odd_field_first = 1;
+ if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)
+ sig_cfg.ext_clk = 1;
+ if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+ sig_cfg.Hsync_pol = 1;
+ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ sig_cfg.Vsync_pol = 1;
+ if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
+ sig_cfg.clk_pol = 1;
+ if (fbi->var.sync & FB_SYNC_DATA_INVERT)
+ sig_cfg.data_pol = 1;
+ if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+ sig_cfg.enable_pol = 1;
+ if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
+ sig_cfg.clkidle_en = 1;
+
+ debug("pixclock = %ul Hz\n",
+ (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+ if (ipu_init_sync_panel(mxc_fbi->ipu_di,
+ (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+ fbi->var.xres, fbi->var.yres,
+ out_pixel_fmt,
+ fbi->var.left_margin,
+ fbi->var.hsync_len,
+ fbi->var.right_margin,
+ fbi->var.upper_margin,
+ fbi->var.vsync_len,
+ fbi->var.lower_margin,
+ 0, sig_cfg) != 0) {
+ puts("mxcfb: Error initializing panel.\n");
+ return -EINVAL;
+ }
+
+ retval = setup_disp_channel2(fbi);
+ if (retval)
+ return retval;
+
+ if (mxc_fbi->blank == FB_BLANK_UNBLANK)
+ ipu_enable_channel(mxc_fbi->ipu_ch);
+
+ return retval;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param var framebuffer variable parameters
+ *
+ * @param info framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ u32 vtotal;
+ u32 htotal;
+
+ if (var->xres_virtual < var->xres)
+ var->xres_virtual = var->xres;
+ if (var->yres_virtual < var->yres)
+ var->yres_virtual = var->yres;
+
+ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+ var->bits_per_pixel = default_bpp;
+
+ switch (var->bits_per_pixel) {
+ case 8:
+ var->red.length = 3;
+ var->red.offset = 5;
+ var->red.msb_right = 0;
+
+ var->green.length = 3;
+ var->green.offset = 2;
+ var->green.msb_right = 0;
+
+ var->blue.length = 2;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 16:
+ var->red.length = 5;
+ var->red.offset = 11;
+ var->red.msb_right = 0;
+
+ var->green.length = 6;
+ var->green.offset = 5;
+ var->green.msb_right = 0;
+
+ var->blue.length = 5;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 24:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 32:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 8;
+ var->transp.offset = 24;
+ var->transp.msb_right = 0;
+ break;
+ }
+
+ if (var->pixclock < 1000) {
+ htotal = var->xres + var->right_margin + var->hsync_len +
+ var->left_margin;
+ vtotal = var->yres + var->lower_margin + var->vsync_len +
+ var->upper_margin;
+ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+ var->pixclock = KHZ2PICOS(var->pixclock);
+ printf("pixclock set for 60Hz refresh = %u ps\n",
+ var->pixclock);
+ }
+
+ var->height = -1;
+ var->width = -1;
+ var->grayscale = 0;
+
+ return 0;
+}
+
+static int mxcfb_map_video_memory(struct fb_info *fbi)
+{
+ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
+ fbi->fix.smem_len = fbi->var.yres_virtual *
+ fbi->fix.line_length;
+ }
+
+ fbi->screen_base = (char *)lcd_base;
+ fbi->fix.smem_start = (unsigned long)lcd_base;
+ if (fbi->screen_base == 0) {
+ puts("Unable to allocate framebuffer memory\n");
+ fbi->fix.smem_len = 0;
+ fbi->fix.smem_start = 0;
+ return -EBUSY;
+ }
+
+ debug("allocated fb @ paddr=0x%08X, size=%d.\n",
+ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+ fbi->screen_size = fbi->fix.smem_len;
+
+ /* Clear the screen */
+ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+ return 0;
+}
+
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+ fbi->screen_base = 0;
+ fbi->fix.smem_start = 0;
+ fbi->fix.smem_len = 0;
+ return 0;
+}
+
+/*
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures. This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(void)
+{
+#define BYTES_PER_LONG 4
+#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
+ struct fb_info *fbi;
+ struct mxcfb_info *mxcfbi;
+ char *p;
+ int size = sizeof(struct mxcfb_info) + PADDING +
+ sizeof(struct fb_info);
+
+ debug("%s: %d %d %d %d\n",
+ __func__,
+ PADDING,
+ size,
+ sizeof(struct mxcfb_info),
+ sizeof(struct fb_info));
+ /*
+ * Allocate sufficient memory for the fb structure
+ */
+
+ p = malloc(size);
+ if (!p)
+ return NULL;
+
+ memset(p, 0, size);
+
+ fbi = (struct fb_info *)p;
+ fbi->par = p + sizeof(struct fb_info) + PADDING;
+
+ mxcfbi = (struct mxcfb_info *)fbi->par;
+ debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
+ (unsigned int)fbi, (unsigned int)mxcfbi);
+
+ fbi->var.activate = FB_ACTIVATE_NOW;
+
+ fbi->flags = FBINFO_FLAG_DEFAULT;
+ fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+ return fbi;
+}
+
+/*
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process. The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(u32 interface_pix_fmt, struct fb_videomode *mode)
+{
+ struct fb_info *fbi;
+ struct mxcfb_info *mxcfbi;
+ int ret = 0;
+
+ /*
+ * Initialize FB structures
+ */
+ fbi = mxcfb_init_fbinfo();
+ if (!fbi) {
+ ret = -ENOMEM;
+ goto err0;
+ }
+ mxcfbi = (struct mxcfb_info *)fbi->par;
+
+ if (!g_dp_in_use) {
+ mxcfbi->ipu_ch = MEM_BG_SYNC;
+ mxcfbi->blank = FB_BLANK_UNBLANK;
+ } else {
+ mxcfbi->ipu_ch = MEM_DC_SYNC;
+ mxcfbi->blank = FB_BLANK_POWERDOWN;
+ }
+
+ mxcfbi->ipu_di = 0;
+
+ ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
+ ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
+ strcpy(fbi->fix.id, "DISP3 BG");
+
+ g_dp_in_use = 1;
+
+ mxcfb_info[mxcfbi->ipu_di] = fbi;
+
+ /* Need dummy values until real panel is configured */
+ fbi->var.xres = 640;
+ fbi->var.yres = 480;
+ fbi->var.bits_per_pixel = 16;
+
+ mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
+ fb_videomode_to_var(&fbi->var, mode);
+
+ mxcfb_check_var(&fbi->var, fbi);
+
+ /* Default Y virtual size is 2x panel size */
+ fbi->var.yres_virtual = fbi->var.yres * 2;
+
+ mxcfb_set_fix(fbi);
+
+ /* alocate fb first */
+ if (mxcfb_map_video_memory(fbi) < 0)
+ return -ENOMEM;
+
+ mxcfb_set_par(fbi);
+
+ /* Setting panel_info for lcd */
+ panel_info.cmap = NULL;
+ panel_info.vl_col = fbi->var.xres;
+ panel_info.vl_row = fbi->var.yres;
+ panel_info.vl_bpix = LCD_BPP;
+
+ lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+
+ debug("MXC IPUV3 configured\n"
+ "XRES = %d YRES = %d BitsXpixel = %d\n",
+ panel_info.vl_col,
+ panel_info.vl_row,
+ panel_info.vl_bpix);
+
+ ipu_dump_registers();
+
+ return 0;
+
+err0:
+ return ret;
+}
+
+int overwrite_console(void)
+{
+ /* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+ return 1;
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ u32 mem_len = panel_info.vl_col *
+ panel_info.vl_row *
+ NBITS(panel_info.vl_bpix) / 8;
+
+ /*
+ * We rely on lcdbase being a physical address, i.e., either MMU off,
+ * or 1-to-1 mapping. Might want to add some virt2phys here.
+ */
+ if (!lcdbase)
+ return;
+
+ memset(lcdbase, 0, mem_len);
+}
+
+int mx51_fb_init(struct fb_videomode *mode)
+{
+ int ret;
+
+ ret = ipu_probe();
+ if (ret)
+ puts("Error initializing IPU\n");
+
+ lcd_base += 56;
+
+ debug("Framebuffer at 0x%x\n", (unsigned int)lcd_base);
+ ret = mxcfb_probe(IPU_PIX_FMT_RGB666, mode);
+
+ return ret;
+}
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXCFB_H__
+#define __ASM_ARCH_MXCFB_H__
+
+#define FB_SYNC_OE_LOW_ACT 0x80000000
+#define FB_SYNC_CLK_LAT_FALL 0x40000000
+#define FB_SYNC_DATA_INVERT 0x20000000
+#define FB_SYNC_CLK_IDLE_EN 0x10000000
+#define FB_SYNC_SHARP_MODE 0x08000000
+#define FB_SYNC_SWAP_RGB 0x04000000
+
+struct mxcfb_gbl_alpha {
+ int enable;
+ int alpha;
+};
+
+struct mxcfb_loc_alpha {
+ int enable;
+ int alpha_in_pixel;
+ unsigned long alpha_phy_addr0;
+ unsigned long alpha_phy_addr1;
+};
+
+struct mxcfb_color_key {
+ int enable;
+ __u32 color_key;
+};
+
+struct mxcfb_pos {
+ __u16 x;
+ __u16 y;
+};
+
+struct mxcfb_gamma {
+ int enable;
+ int constk[16];
+ int slopek[16];
+};
+
+#endif
include $(TOPDIR)/config.mk
-LIB := $(obj)libwatchdog.a
+LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
COBJS := $(ELF:=.o)
-LIB = $(obj)libstubs.a
+LIB = $(obj)libstubs.o
LIBAOBJS-$(ARCH) :=
LIBAOBJS-$(CPU) :=
CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS))
endif
+# We don't want gcc reordering functions if possible. This ensures that an
+# application's entry point will be the first function in the application's
+# source file.
+CFLAGS += $(call cc-option,-fno-toplevel-reorder)
+
all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
#########################################################################
$(LIB): $(obj).depend $(LIBOBJS)
- $(AR) $(ARFLAGS) $@ $(LIBOBJS)
+ $(call cmd_link_o_target, $(LIBOBJS))
$(ELF):
$(obj)%: $(obj)%.o $(LIB)
include $(TOPDIR)/config.mk
-LIB = $(obj)libcramfs.a
+LIB = $(obj)libcramfs.o
AOBJS =
COBJS-$(CONFIG_CMD_CRAMFS) := cramfs.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libext2fs.a
+LIB = $(obj)libext2fs.o
AOBJS =
COBJS-$(CONFIG_CMD_EXT2) := ext2fs.o dev.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
}
-int ext2fs_ls (char *dirname) {
+int ext2fs_ls (const char *dirname) {
ext2fs_node_t dirnode;
int status;
}
-int ext2fs_open (char *filename) {
+int ext2fs_open (const char *filename) {
ext2fs_node_t fdiro = NULL;
int status;
int len;
include $(TOPDIR)/config.mk
-LIB = $(obj)libfat.a
+LIB = $(obj)libfat.o
AOBJS =
COBJS-$(CONFIG_CMD_FAT) := fat.o file.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libfdos.a
+LIB = $(obj)libfdos.o
AOBJS =
COBJS-$(CONFIG_CMD_FDOS) := fat.o vfat.o dev.o fdos.o fs.o subdir.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libjffs2.a
+LIB = $(obj)libjffs2.o
AOBJS =
ifdef CONFIG_CMD_JFFS2
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libreiserfs.a
+LIB = $(obj)libreiserfs.o
AOBJS =
COBJS-$(CONFIG_CMD_REISER) := reiserfs.o dev.o mode_string.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)libubifs.a
+LIB = $(obj)libubifs.o
COBJS-$(CONFIG_CMD_UBIFS) := ubifs.o io.o super.o sb.o master.o lpt.o
COBJS-$(CONFIG_CMD_UBIFS) += lpt_commit.o scan.o lprops.o
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
* through mounting (error path cleanup function). So it has to make sure the
* resource was actually allocated before freeing it.
*/
-static void ubifs_umount(struct ubifs_info *c)
+void ubifs_umount(struct ubifs_info *c)
{
dbg_gen("un-mounting UBI device %d, volume %d", c->vi.ubi_num,
c->vi.vol_id);
*
* Copyright (C) 2006-2008 Nokia Corporation.
*
- * (C) Copyright 2008-2009
+ * (C) Copyright 2008-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or modify it
{
ubifs_compressors[compr->compr_type] = compr;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
ubifs_compressors[compr->compr_type]->name += gd->reloc_off;
ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off;
ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off;
unsigned long root_inum = 1;
unsigned long inum;
int symlink_count = 0; /* Don't allow symlink recursion */
+ char link_name[64];
strcpy(fpath, filename);
ui = ubifs_inode(inode);
if ((inode->i_mode & S_IFMT) == S_IFLNK) {
- char link_name[64];
char buf[128];
/* We have some sort of symlink recursion, bail out */
return -EINVAL;
}
-static int do_readpage(struct ubifs_info *c, struct inode *inode, struct page *page)
+static int do_readpage(struct ubifs_info *c, struct inode *inode,
+ struct page *page, int last_block_size)
{
void *addr;
int err = 0, i;
err = -ENOENT;
memset(addr, 0, UBIFS_BLOCK_SIZE);
} else {
- ret = read_block(inode, addr, block, dn);
- if (ret) {
- err = ret;
- if (err != -ENOENT)
+ /*
+ * Reading last block? Make sure to not write beyond
+ * the requested size in the destination buffer.
+ */
+ if (((block + 1) == beyond) || last_block_size) {
+ void *buff;
+ int dlen;
+
+ /*
+ * We need to buffer the data locally for the
+ * last block. This is to not pad the
+ * destination area to a multiple of
+ * UBIFS_BLOCK_SIZE.
+ */
+ buff = malloc(UBIFS_BLOCK_SIZE);
+ if (!buff) {
+ printf("%s: Error, malloc fails!\n",
+ __func__);
+ err = -ENOMEM;
break;
- } else if (block + 1 == beyond) {
- int dlen = le32_to_cpu(dn->size);
- int ilen = i_size & (UBIFS_BLOCK_SIZE - 1);
-
- if (ilen && ilen < dlen)
- memset(addr + ilen, 0, dlen - ilen);
+ }
+
+ /* Read block-size into temp buffer */
+ ret = read_block(inode, buff, block, dn);
+ if (ret) {
+ err = ret;
+ if (err != -ENOENT) {
+ free(buff);
+ break;
+ }
+ }
+
+ if (last_block_size)
+ dlen = last_block_size;
+ else
+ dlen = le32_to_cpu(dn->size);
+
+ /* Now copy required size back to dest */
+ memcpy(addr, buff, dlen);
+
+ free(buff);
+ } else {
+ ret = read_block(inode, addr, block, dn);
+ if (ret) {
+ err = ret;
+ if (err != -ENOENT)
+ break;
+ }
}
}
if (++i >= UBIFS_BLOCKS_PER_PAGE)
int err = 0;
int i;
int count;
+ int last_block_size = 0;
c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY);
/* ubifs_findfile will resolve symlinks, so we know that we get
page.index = 0;
page.inode = inode;
for (i = 0; i < count; i++) {
- err = do_readpage(c, inode, &page);
+ /*
+ * Make sure to not read beyond the requested size
+ */
+ if (((i + 1) == count) && (size < inode->i_size))
+ last_block_size = size - (i * PAGE_SIZE);
+
+ err = do_readpage(c, inode, &page, last_block_size);
if (err)
break;
#EXTRA_COMPILE_FLAGS = -DYAFFS_IGNORE_TAGS_ECC
include $(TOPDIR)/config.mk
-LIB = $(obj)libyaffs2.a
+LIB = $(obj)libyaffs2.o
COBJS-$(CONFIG_YAFFS2) := \
yaffscfg.o yaffs_ecc.o yaffsfs.o yaffs_guts.o yaffs_packedtags1.o \
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
.PHONY: clean distclean
clean:
--- /dev/null
+#ifndef DO_DEPS_ONLY
+
+#include <generated/generic-asm-offsets.h>
+/* #include <generated/asm-offsets.h> */
+
+#endif
extern int cmd_usage(cmd_tbl_t *cmdtp);
#ifdef CONFIG_AUTO_COMPLETE
-extern void install_auto_complete(void);
+extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
#endif
* void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
*/
-typedef void command_t (cmd_tbl_t *, int, int, char *[]);
-
#if defined(CONFIG_CMD_MEMORY) \
|| defined(CONFIG_CMD_I2C) \
|| defined(CONFIG_CMD_ITEST) \
extern int cmd_get_data_size(char* arg, int default_size);
#endif
+#ifdef CONFIG_CMD_BOOTD
+extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
#endif /* __ASSEMBLY__ */
/*
#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd")))
-#ifdef CONFIG_SYS_LONGHELP
+#ifdef CONFIG_AUTO_COMPLETE
+# define _CMD_COMPLETE(x) x,
+#else
+# define _CMD_COMPLETE(x)
+#endif
+#ifdef CONFIG_SYS_LONGHELP
+# define _CMD_HELP(x) x,
+#else
+# define _CMD_HELP(x)
+#endif
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
+#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
+ {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)}
#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
-{#name, maxargs, rep, cmd, usage, help}
+ U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
-#else /* no long help info */
+#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
+ cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
+ U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
-
-#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
-{#name, maxargs, rep, cmd, usage}
-
-#endif /* CONFIG_SYS_LONGHELP */
+ U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
#endif
#endif /* __COMMAND_H */
typedef volatile unsigned char vu_char;
#include <config.h>
+#include <asm-offsets.h>
#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/string.h>
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */
-int console_assign (int file, char *devname); /* Assign the console */
+int console_assign(int file, const char *devname); /* Assign the console */
int ctrlc (void);
int had_ctrlc (void); /* have we had a Control-C since last clear? */
void clear_ctrlc (void); /* clear the Control-C condition */
/*********************************************************************/
-
-/*** CCM and PCU E ***********************************************/
-
-/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
-
-#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_PCU_E, CONFIG_CCM */
-
/*** ELPT860 *********************************************************/
#ifdef CONFIG_ELPT860
#elif defined(__MACH__)
# include <machine/endian.h>
typedef unsigned long ulong;
-typedef unsigned int uint;
#endif
typedef uint8_t __u8;
#define CONFIG_CMD_PORTIO /* Port I/O */
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_REISER /* Reiserfs support */
+#define CONFIG_CMD_RARP /* rarpboot support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_MPC8245 1
#define CONFIG_A3000 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
* Definitions for initial stack pointer and data area
*/
-/* #define CONFIG_SYS_MONITOR_BASE TEXT_BASE */
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
+/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
/* Processor type */
#define CONFIG_MPC860 1
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MPC860 1
#define CONFIG_AMX860 1
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
#undef CONFIG_8xx_CONS_SMC2
#define CONFIG_8xx_CONS_SCC2 1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
#define CONFIG_SYS_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_AP1000 1 /* ...on an AP1000 board */
+/*
+ * Start at bottom of RAM, but at an aliased address so that it looks
+ * like it's not in RAM. This is a bit of voodoo to allow it to be
+ * run from RAM instead of Flash.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds"
+
#define CONFIG_PCI 1
#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define SPD_EEPROM_ADDRESS 0x50
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_APCG405 1 /* ...on a APC405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* reserve some memory for BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
#endif
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* PCI OHCI controller
*/
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_AR405 1 /* ...on a AR405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_ASH405 1 /* ...on a ASH405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
#define CONFIG_PCI 1 /* enable any pci type devices */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI 1
/* Memory */
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_ADDER /* Analogue&Micro Adder board */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 38400
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MPC8220 1
#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* Serial console configuration
*/
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024 )
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
* (easy to change)
*/
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* these hardware addresses are pretty bogus, please change them to
suit your needs */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_END 0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP /* pci plug-and-play */
#define CONFIG_PCI_HOST PCI_HOST_AUTO
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_L2_BAB7xx
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_TULIP
#define CONFIG_TULIP_SELECT_MEDIA
#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000 boot low (standard configuration with room for
+ * max 64 MByte Flash ROM)
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_MPC8245 1
#define CONFIG_BMW 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CANBT 1 /* ...on a CANBT board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* Definitions for initial stack pointer and data area (in RAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define CONFIG_NO_SERIAL_EEPROM
/*--------------------------------------------------------------------*/
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * configuration options, board specific, for Siemens Card Controller Module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CCM_80MHz /* define for 80 MHz CPU only */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */
-#define CONFIG_CCM 1 /* on a Card Controller Module */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r() */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-/* ENVIRONMENT */
-
-#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
-
-#define CONFIG_IPADDR 192.168.0.42
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 0.0.0.0
-#define CONFIG_SERVERIP 192.168.0.254
-
-#define CONFIG_HOSTNAME CCM
-
-#define CONFIG_LOADADDR 40180000
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND "setenv bootargs " \
- "mem=${mem} " \
- "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
- "wt_8xx=timeout:3600; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_SPI /* enable SPI driver */
-#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */
-
-
-#define CONFIG_MAC_PARTITION /* nod used yet */
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/* Ethernet hardware configuration done using port pins */
-#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */
-#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
-
-/* Ethernet settings:
- * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CONFIG_SYS_ETH_MDDIS_VALUE 0
-#define CONFIG_SYS_ETH_CFG1_VALUE 1
-#define CONFIG_SYS_ETH_CFG2_VALUE 1
-#define CONFIG_SYS_ETH_CFG3_VALUE 1
-
-/* PUMA configuration */
-#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */
-#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
-#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#if 1
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 2048
-#define CONFIG_ENV_SIZE 2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * we must activate GPL5 in the SIUMCR for CAN
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR \
- ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif /* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif /* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3 and OR3 (CAN Controller)
- */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8520
- * - "load" mode (chip select on UPM B):
- * BR4: 0x101004c1 OR4: 0xffff8600
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
-#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
-
-#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- * BR5: 0x10200401 OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- * BR6: 0x10600801 OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-
-/*
- * BR7/OR7: PUMA: external Flash
- * BR7: 0x10a00801 OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
-#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
-#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC8245 1
#define CONFIG_CPC45 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* NS16550 Configuration
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
-
/*----------------------------------------------------------------------*/
/* CPC45 Memory Map */
/*----------------------------------------------------------------------*/
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_SYS_EARLY_PCI_INIT
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#define CONFIG_CPCI405AB 1 /* ...and special AB version */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
#define CONFIG_MV64360_ECC /* enable ECC support */
/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOARD_ASM_INIT 1
#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
*/
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_CPU86 1 /* ...on a CPU86 board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#ifdef CONFIG_BOOT_ROM
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+#endif
+
/*
* select serial console configuration
*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#define CONFIG_ENV_SIZE (2048 - 512)
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_PCI
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#ifdef CONFIG_BOOT_ROM
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+#endif
+
/*
* select serial console configuration
*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#define CONFIG_ENV_SIZE (2048 - 512)
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC405 family */
+
+/*
+ * Note: I make an "image" from U-Boot itself, which prefixes 0x40
+ * bytes of header info, hence start address is thus shifted.
+ */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0040
+
#define CONFIG_SYS_CLK_FREQ 25000000
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#endif
#define EEPROM_WRITE_ADDRESS 0xA0
#define EEPROM_READ_ADDRESS 0xA1
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC8240 1
#define CONFIG_CU824 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* NS16550 Configuration
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_DB64360 1 /* this is an DB64360 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
*/
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOARD_ASM_INIT 1
#endif /* __CONFIG_H */
#define CONFIG_DB64460 1 /* this is an DB64460 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
*/
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define RELOCATE_INTERNAL_RAM_ADDR
#ifdef RELOCATE_INTERNAL_RAM_ADDR
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOARD_ASM_INIT 1
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DP405 1 /* ...on a DP405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#undef CONFIG_WATCHDOG /* watchdog disabled */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_DU405 1 /* ...on a DU405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
*-----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 64
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
-#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
-#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* (easy to change)
*/
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* these hardware addresses are pretty bogus, please change them to
suit your needs */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_END 0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#endif
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_MPC860T 1
#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
+#define CONFIG_SYS_TEXT_BASE 0x02000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *-----------------------------------------------------------------------
- *
- */
-
-/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#endif /* __CONFIG_H */
#define CONFIG_EP88X /* Embedded Planet EP88x board */
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_ERIC 1 /* ...on a ERIC board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#endif
-#if 0
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#endif
-#if 0
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
-#endif /* total size of a X1240 is 2048 bytes */
-
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
-#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#else
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#else
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
- "nfsroot=192.168.1.2:/eric_root_devel " \
- "ip=192.168.1.22:192.168.1.2"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_NET_MULTI
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
-#define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
-/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
-/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
-/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
-/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
-/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
-/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
-/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
-
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 0 (Flash) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS0_AP 0x9B015480
-#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 1 (NVRAM/RTC) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
- /* ----------------------------------------------------------------------- */
- /* Memory Bank 2 (A/D converter) initialization */
- /* ----------------------------------------------------------------------- */
-#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 3 (Ethernet PHY Reset) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 6 (CPU LED0) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/* Memory Bank 7 (CPU LED1) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-
-#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
-#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
-#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
-#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
-#define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
-#define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
-
-
-/* SDRAM CONFIG */
-#define CONFIG_SYS_SDRAM_MANUALLY 1
-#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
-
-#ifdef CONFIG_SYS_SDRAM_MANUALLY
-/*-----------------------------------------------------------------------
- * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#define MB0CF 0x00062001 /* 32MB @ 0 */
-/*-----------------------------------------------------------------------
- * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
-#define MB1CF 0x0 /* 0MB @ 32MB */
-#else
-#define MB1CF 0x02062001 /* 32MB @ 32MB */
-#endif
-/*-----------------------------------------------------------------------
- * Set MB2CF for bank 2. off
- *----------------------------------------------------------------------*/
-#define MB2CF 0x0 /* 0MB */
-/*-----------------------------------------------------------------------
- * Set MB3CF for bank 3. off
- *----------------------------------------------------------------------*/
-#define MB3CF 0x0 /* 0MB */
-
-#define SDTR_100 0x0086400D
-#define RTR_100 0x05F0
-#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
-#define RTR_66 0x03f8
-
-#endif /* CONFIG_SYS_SDRAM_MANUALLY */
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 32
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
-#define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
-/*#define CONFIG_SYS_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128*1024)
-
-#if 0 /* force ENV to be NOT embedded */
-#define CONFIG_ENV_ADDR 0xfffa0000
-#else /* force ENV to be embedded */
-#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
-/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#endif
-
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-/* #define CONFIG_PORT_ADDR 0xF0000500 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MAMR_8COL 0x18803112
#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_ETX094 1 /* ...on a ETX_094 board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+#define CONFIG_SYS_LDSCRIPT "board/evb64260/u-boot.lds"
+
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
#undef CONFIG_ECC /* enable ECC support */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOARD_ASM_INIT 1
#define CONFIG_SYS_FLASH1_SIZE 0x02000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/* Global info and initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CONFIG_SYS_MAMR 0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* values according to the manual */
#define CONFIG_MPC850SAR 1
#define CONFIG_FADS 1
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CONFIG_SYS_MAMR 0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* values according to the manual */
/* processor type */
#define CONFIG_MPC860T 1 /* 860T */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */
#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
#define CONFIG_8xx_CONS_SMC2 1
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
/* pass open firmware flat tree */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_G2000 1 /* ...on a PLU405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC860
#define CONFIG_GEN860T
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/*
* Identify the board
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
)
/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* FEC interrupt assignment
*/
#define FEC_INTERRUPT SIU_LEVEL1
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+
#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
| MAMR_TLFA_4X) /* 0x5d802114 */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_HH405 1 /* ...on a HH405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC8245 1
#define CONFIG_HIDDEN_DRAGON 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#if 0
#define USE_DINK32 1
#else
#define CONFIG_SYS_MONITOR_BASE 0x00090000
#define CONFIG_SYS_RAMBOOT 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
*/
-#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
+/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_HUB405 1 /* ...on a HUB405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_8xx_CONS_SMC1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_MPC860T
/* Interrupt level assignments.
#define CONFIG_ICU862 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_TEXT_BASE 0x40F00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#else
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
/*
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CONFIG_SYS_MAMR 0x13a01114
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
#ifdef CONFIG_MPC860T
#define CPU_ID_STR "MPC8247"
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
* The main FLASH is whichever is connected to *CS0.
*/
#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_IP860 1 /* ...on a IP860 board */
+
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
+#define CONFIG_SYS_TEXT_BASE 0xffb00000
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*-----------------------------------------------------------------------
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
-/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
+
/*-----------------------------------------------------------------------
* Select serial console configuration
*
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_IVML24 1 /* ...on a IVML24 board */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#if defined (CONFIG_IVML24_16M)
# define CONFIG_IDENT_STRING " IVML24"
#elif defined (CONFIG_IVML24_32M)
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#if defined (CONFIG_IVML24_16M)
-# define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#elif defined (CONFIG_IVML24_32M)
-# define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
#elif defined (CONFIG_IVML24_64M)
-# define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#if defined (CONFIG_IVMS8_16M)
# define CONFIG_IDENT_STRING " IVMS8"
#elif defined (CONFIG_IVMS8_32M)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#if defined (CONFIG_IVMS8_16M)
-# define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#elif defined (CONFIG_IVMS8_32M)
-# define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
#elif defined (CONFIG_IVMS8_64M)
-# define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFF000000 boot low for 16 MiB boards
+ * 0xFF800000 boot low for 8 MiB boards
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#endif
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
-#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
#if defined(CONFIG_LITE5200B)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#else
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
/* JSE has a PPC405GPr */
#define CONFIG_405GP 1
/* ... which is a 4xxx series */
-#define CONFIG_4xx 1
+#define CONFIG_4x 1
/* ... with a 33MHz OSC. connected to the SysCLK input */
#define CONFIG_SYS_CLK_FREQ 33333333
/* ... with on-chip memory here (4KBytes) */
/* Do not set up locked dcache as init ram. */
#undef CONFIG_SYS_INIT_DCACHE_CS
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
/* ... place INIT RAM in the OCM address */
# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* ... give it the whole init ram */
-# define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
/* ... Shave a bit off the end for global data */
-# define CONFIG_SYS_GBL_DATA_SIZE 128
-# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* ... and place the stack pointer at the top of what's left. */
# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ }
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define LATCH_ADDR 0x90000200
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR "."
#define CONFIG_SILENT_CONSOLE 1
#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ }
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define LATCH_ADDR 0x90000200
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/*
* Port assignments (CONFIG_LANTEC == 1):
* - SMC1: J11 (MDB) ?
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* JFFS2 partitions
*
*/
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
/*
* Start addresses for the final memory configuration
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
-# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 1000 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
-#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#else
-#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
-# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#ifdef CONFIG_CF_SBF
-# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_MBX 1 /* ...on an MBX module */
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
*/
#define CONFIG_SYS_DER 0
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC860T 1
#define CONFIG_MBX 1
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+
#define CONFIG_8xx_CPUCLOCK 40
#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK)
#define TARGET_SYSTEM_FREQUENCY 40
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#define CONFIG_SYS_MAMR 0x13821000
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* values according to the manual */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
#define CONFIG_MISC_INIT_R 1
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+
#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_DER 0
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_MIP405 1 /* ...on a MIP405 board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/***********************************************************
* Note that it may also be a MIP405T board which is a subset of the
* MIP405
#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/***********************************************************************
* External peripheral base address
***********************************************************************/
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_ML2 1 /* ...on a ML2 board */
+#define CONFIG_SYS_TEXT_BASE 0x18000000
+#define CONFIG_SYS_LDSCRIPT "board/ml2/u-boot.lds"
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_RTC
#undef CONFIG_CMD_PCI
#undef CONFIG_CMD_I2C
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define SPD_EEPROM_ADDRESS 0x50
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_MOUSSE 1
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds"
+
#define CONFIG_SYS_ADDR_MAP_B 1
+
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#if 1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* Localizations */
#if 0
#define CONFIG_ETHADDR 0:0:0:0:1:d
#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
+#endif
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* Figure out if we are booting low via flash HRCW or high via the BCSR.
*/
-#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
+#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
# define CONFIG_SYS_LOWBOOT 1
#endif
#define BCSR_PCI_MODE 0x01000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#ifdef CONFIG_SYS_LOWBOOT
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=400000\0" \
"console=ttyCPM0\0" \
"setbootargs=setenv bootargs " \
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! !!
!! This configuration requires JP3 to be in position 1-2 to work !!
- !! To make it work for the default, the TEXT_BASE define in !!
+ !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !!
!! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
!! 0xfff00000 !!
!! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
#define FETH_RST 0x04000004
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_MISC_INIT_R
/*
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_MPC8313 1
#define CONFIG_MPC8313ERDB 1
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_NAND_U_BOOT */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
#define CONFIG_PCI
#define CONFIG_FSL_ELBC 1
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
"ethprime=TSEC1\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"console=ttyS0\0" \
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_MK_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_NAND_U_BOOT */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/*
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_PCI 1
/*
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"ramdiskaddr=1000000\0" \
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
-#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
-#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
/*
* System Clock Setup
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-#define PCI_66M
-#ifdef PCI_66M
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif /* CONFIG_PCISLAVE */
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#ifndef __CONFIG_H
#define __CONFIG_H
-#if (TEXT_BASE == 0xFE000000)
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
#define CONFIG_SYS_LOWBOOT
#endif
#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8349 /* MPC8349 specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFEF00000
+#endif
+
#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
#define CONFIG_MISC_INIT_F
/*
* U-Boot memory configuration
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#endif
-#define PCI_66M
-#ifdef PCI_66M
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
/*
* CS4 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
+#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
+#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+
/*
* System Clock Setup
*/
#ifdef CONFIG_CLKIN_33MHZ
#define CONFIG_83XX_CLKIN 33333333
#define CONFIG_SYS_CLK_FREQ 33333333
-#define PCI_33M 1
+#define CONFIG_PCI_33M 1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
#else
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
-#define PCI_66M 1
+#define CONFIG_PCI_66M 1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
#endif /* CONFIG_CLKIN_33MHZ */
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
/*
* System Clock Setup
*/
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_PCI 1
#define CONFIG_BOARD_EARLY_INIT_F
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"ramdiskaddr=1000000\0" \
#include "../board/freescale/common/ics307_clk.h"
-#ifdef CONFIG_MK_36BIT
+#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT 1
#endif
-#ifdef CONFIG_MK_NAND
+#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#endif /* CONFIG_NAND_SPL */
#endif
-#ifdef CONFIG_MK_SDCARD
+#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
#endif
-#ifdef CONFIG_MK_SPIFLASH
+#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
- || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+ defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8536ds/ramdisk.uboot\0" \
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8541 1 /* MPC8541 specific */
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds/ramdisk.uboot\0" \
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
#define CONFIG_MPC8555 1 /* MPC8555 specific */
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_MPC8560 1
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_MK_ATM
+#ifdef CONFIG_ATM
#define CONFIG_PQ_MDS_PIB
#define CONFIG_PQ_MDS_PIB_ATM
#endif
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_MK_NAND
+#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#endif
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/*
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
/* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#include "../board/freescale/common/ics307_clk.h"
-#ifdef CONFIG_MK_36BIT
+#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#define CONFIG_MPC8572DS 1
#define CONFIG_MP 1 /* support multiple processors */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_RTL8139
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8572ds/ramdisk.uboot\0" \
#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
/* video */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
/* Map the last 1M of flash where we're running from reset */
#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
#define CONFIG_ADDR_MAP 1 /* Use addr map */
+/*
+ * default CCSRBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define CONFIG_SYS_TEXT_BASE 0xeff00000
+
#ifdef RUN_DIAG
#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
/* Map the last 1M of flash where we're running from reset */
#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
#undef CONFIG_MPC859DSL
#undef CONFIG_MPC852T
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MPC8245 1
#define CONFIG_MUSENKI 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
* Definitions for initial stack pointer and data area
*/
-/* #define CONFIG_SYS_MONITOR_BASE TEXT_BASE */
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
+/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC5xxx 1
#define CONFIG_MPC5200 1
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+#endif
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_SIZE 0x00800000
/*
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_MPC834x 1
#define CONFIG_MPC8343 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
/*
* U-Boot memory configuration
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 3
-#define PCI_66M
+#define CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66666667
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_SCCR_TSEC1CM 1
#define CONFIG_SYS_SCCR_TSEC2CM 1
-#define CONFIG_SYS_SICRH 0x1fff8003
+#define CONFIG_SYS_SICRH 0x1fef0003
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#define MVBLUE_BOARD_BOX 1
#define MVBLUE_BOARD_LYNX 2
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds"
+
#if 0
#define ERR_LED(code) do { if (code) \
*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Low Level Configuration Settings
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC5xxx 1
#define CONFIG_MPC5200 1
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+#endif
+#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_SIZE 0x00800000
/*
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
+++ /dev/null
-/*
- * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC852T 1
-#define CONFIG_NC650 1
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-/*
- * 10 MHz - PLL input clock
- */
-#define CONFIG_8xx_OSCLK 10000000
-
-/*
- * 50 MHz - default CPU clock
- */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-
-/*
- * 15 MHz - CPU minimum clock
- */
-#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000
-
-/*
- * 133 MHz - CPU maximum clock
- */
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-
-#define CONFIG_SYS_MEASURE_CPUCLK
-#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d seconds...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "ids"
-#define CONFIG_BOOT_RETRY_TIME 900
-#define CONFIG_BOOT_RETRY_MIN 30
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_WATCHDOG /* watchdog enabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define FEC_ENET
-#define CONFIG_MII
-#define CONFIG_SYS_DISCOVER_PHY 1
-
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#if defined(CONFIG_IDS852_REV1)
-
-#define SCL 0x1000 /* PA 3 */
-#define SDA 0x2000 /* PA 2 */
-
-#define __I2C_DIR immr->im_ioport.iop_padir
-#define __I2C_DAT immr->im_ioport.iop_padat
-#define __I2C_PAR immr->im_ioport.iop_papar
-
-#elif defined(CONFIG_IDS852_REV2)
-
-#define SCL 0x0002 /* PB 30 */
-#define SDA 0x0001 /* PB 31 */
-
-#define __I2C_PAR immr->im_cpm.cp_pbpar
-#define __I2C_DIR immr->im_cpm.cp_pbdir
-#define __I2C_DAT immr->im_cpm.cp_pbdat
-
-#endif
-
-#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
- __I2C_DIR |= (SDA|SCL); }
-#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
-#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define I2C_DELAY { udelay(5); }
-#define I2C_ACTIVE { __I2C_DIR |= SDA; }
-#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00740000
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*
- * NAND flash support
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
- SCCR_DFLCD000 | SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: Default value of OR0 after reset */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
- OR_SCY_15_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
- * rev2 only uses the chipselect
- */
-#define CONFIG_SYS_NAND_BASE 0x50000000
-#define CONFIG_SYS_NAND_SIZE 0x04000000
-
-#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
-#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
-
-/*
- * BR3 and OR3 (SDRAM)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
- /*
- * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * BR4 and OR4 (CPLD)
- */
-#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */
-#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */
-
-#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_1_CLK)
-
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
-
-/*
- * BR5 and OR5 (SRAM)
- */
-#define CONFIG_SYS_SRAM_BASE 0x60000000
-#define CONFIG_SYS_SRAM_SIZE 0x00080000
-
-#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
-
-#if defined(CONFIG_CP850)
-/*
- * BR6 and OR6 (DPRAM) - only on CP850
- */
-#define CONFIG_SYS_OR6_PRELIM 0xffff8170
-#define CONFIG_SYS_BR6_PRELIM 0xa0000401
-#define DPRAM_BASE_ADDR 0xa0000000
-
-#define CONFIG_MISC_INIT_R 1
-#endif
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 39
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * MBMR settings for NAND flash
- */
-
-#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
-
-#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
- "4m(cramfs1),1m(cramfs2)," \
- "256k(u-boot),128k(env);" \
- "nc650-nand:4m(jffs1),28m(jffs2)"
-
-#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND 0
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_NETTA 1 /* ...on a NetTA board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND 0
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/***********************************************************************************************************
#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_NETVIA 1 /* ...on a NetVia board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND 0
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
#define CONFIG_NSCU 1
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#undef CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/*#define CONFIG_VIDEO 1 */
#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
#define CONFIG_ETHADDR 00:10:20:30:40:50
#define CONFIG_IPADDR 10.77.77.20
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC8240 1
#define CONFIG_OXC 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_IDENT_STRING " [oxc] "
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN 0x00030000
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_PRELIMBASE)
#endif
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_P1022DS
#define CONFIG_MP /* support multiple processors */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
#define CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
-
/* Video */
-/* #define CONFIG_VIDEO */
-#ifdef CONFIG_VIDEO
+#undef CONFIG_FSL_DIU_FB
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
#endif
/*
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
#endif
/* SATA */
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=uramdisk\0" \
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_MK_P1011RDB
+#ifdef CONFIG_P1011RDB
#define CONFIG_P1011
#endif
-#ifdef CONFIG_MK_P1020RDB
+#ifdef CONFIG_P1020RDB
#define CONFIG_P1020
#endif
-#ifdef CONFIG_MK_P2010RDB
+#ifdef CONFIG_P2010RDB
#define CONFIG_P2010
#endif
-#ifdef CONFIG_MK_P2020RDB
+#ifdef CONFIG_P2020RDB
#define CONFIG_P2020
#endif
-#ifdef CONFIG_MK_NAND
+#ifdef CONFIG_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_NAND 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#endif /* CONFIG_NAND_SPL */
#endif
-#ifdef CONFIG_MK_SDCARD
+#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
#endif
-#ifdef CONFIG_MK_SPIFLASH
+#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH 1
-#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
- || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+ defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
- - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_DS1337_NOOSC
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* General PCI
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_ANEG_ENABLE \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
#endif /* CONFIG_TSEC_ENET */
/*
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
#include "../board/freescale/common/ics307_clk.h"
-#ifdef CONFIG_MK_36BIT
+#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#define CONFIG_P2020DS 1
#define CONFIG_MP 1 /* support multiple processors */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x7fffffff
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_MK_DDR2
+#ifdef CONFIG_DDR2
#define CONFIG_FSL_DDR2
#else
#define CONFIG_FSL_DDR3 1
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p2020ds/ramdisk.uboot\0" \
#define CONFIG_P3G4 1 /* this is a P3G4 board */
#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
#undef CONFIG_ECC /* enable ECC support */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_FLASH_BASE 0xff000000
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* areas to map different things with the GT in physical space */
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOARD_ASM_INIT 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
+
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
#define CONFIG_PATI 1 /* ...On a PATI board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
#undef CONFIG_5xx_CONS_SCI2
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
-#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
/*
* Start addresses for the final memory configuration
#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
-/* CONFIG_SYS_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
+/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
/* This adress is given to the linker with -Ttext to */
/* locate the text section at this adress. */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
*/
#define CONFIG_SYS_DER 0x00000000
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10084-001"
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PCI405 1 /* ...on a PCI405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_RAM_LOCK
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_RAM_LOCK
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
RTC m48t59
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PIP405 1 /* ...on a PIP405 board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/***********************************************************
* Clock
***********************************************************/
#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/***********************************************************************
* External peripheral base address
***********************************************************************/
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PLU405 1 /* ...on a PLU405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
/*
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in MHz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_PM520 1 /* ... on PM520 board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_PM826 1 /* ...on a PM8260 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */
+#endif
+
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_PM828 1 /* ...on a PM828 module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */
+#endif
+
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_PM854 1 /* PM854 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_PM856 1 /* PM856 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PMC405 1 /* ...on a PMC405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_BOARD_TYPES 1 /* support board types */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xfe000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/*
/* inside SDRAM */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF90000
+#endif
+
#define CONFIG_SYS_CLK_FREQ 33333400
#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_NAND_QUIET_TEST 1
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8240 1
#define CONFIG_PN62 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#define CONFIG_NO_SERIAL_EEPROM
/*--------------------------------------------------------------------*/
#define CONFIG_QS823 1 /* ...on a QS823 module */
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* Select the target clock speed */
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_BR7_PRELIM 0xF0700000
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#define CONFIG_QS850 1 /* ...on a QS850 module */
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* Select the target clock speed */
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_BR7_PRELIM 0xF0700000
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_QS860T 1 /* ...on a QS860T module */
+/* Start address of 512K Socketed Flash */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
#define CONFIG_MII
#define FEC_INTERRUPT SIU_LEVEL1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/* #define CONFIG_SYS_OR7 0xFF000000 */
/* #define CONFIG_SYS_BR7 0xE8000000 */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* Sanity checks
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_R360MPI 1
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_LCD
#undef CONFIG_EDT32F10
#define CONFIG_SHARP_LQ057Q3DC02
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_RBC823 1 /* ...on a RBC823 module */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#if 0
#define DEBUG 1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* JFFS2 partitions
*
#define CONFIG_MPC860 1
#define CONFIG_RPXCLASSIC 1
+#define CONFIG_SYS_TEXT_BASE 0xff000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/* Configuration variable added by yooth. */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_RPXLITE 1
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/* Configuration variable added by yooth. */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
+#define CONFIG_SYS_TEXT_BASE 0xff000000
+
#ifdef CONFIG_LCD /* with LCD controller ? */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
/* Configuration variable added by yooth. */
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x80F00000
/*****************************************************************************
*
#undef CONFIG_SYS_SBC_BOOT_LOW
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
ORxG_SCY_5_CLK |\
ORxG_TRLX)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_RRVISION 1 /* ...on a RRvision board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_GCLK_FREQ 64000000
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CPU_ID_STR "MPC8250"
#endif /* CONFIG_MPC8248 */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
*/
#endif /* CONFIG_CMD_JFFS2 */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Top level Makefile configuration choices
*/
-#ifdef CONFIG_MK_66
+#ifdef CONFIG_66
#define CONFIG_PCI_66
#endif
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
+#define CONFIG_SYS_TEXT_BASE 0xfffc0000
+
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if 0
/* XXX This doesn't work and I don't want to fix it */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_SCM 1 /* ...on a System Controller Module */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#if (CONFIG_TQM8260 <= 100)
# error "TQM8260 module revison not supported"
#endif
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
* The main FLASH is whichever is connected to *CS0.
*/
#define CONFIG_SYS_FLASH0_BASE 0x40000000
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
#define CONFIG_PCI
#define CONFIG_FSL_ELBC 1
*/
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-
#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
"ethprime=TSEC1\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=ae0000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"console=ttyS0\0" \
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* High Level Configuration Options
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_INITRD_TAG
#define CONFIG_MMC 1
/* we use this ethernet chip */
-#define CONFIG_ENC28J60
+#define CONFIG_ENC28J60_LPC2292
#endif /* __CONFIG_H */
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_MPC860T 1
#define CONFIG_MPC855T 1
+#define CONFIG_SYS_TEXT_BASE 0xF8000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_SCC1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
-/**********************************************************
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_MPC8240 1
#define CONFIG_SANDPOINT 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
+
#if 0
#define USE_DINK32 1
#else
#define CONFIG_SYS_MONITOR_BASE 0x00090000
#define CONFIG_SYS_RAMBOOT 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
*/
-#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
+/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_MPC8245 1
#define CONFIG_SANDPOINT 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
+
#if 0
#define USE_DINK32 1
#else
#define CONFIG_SYS_MONITOR_BASE 0x00090000
#define CONFIG_SYS_RAMBOOT 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
*/
-#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */
+/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000 boot low (standard configuration with room for
+ * max 64 MByte Flash ROM)
+ * 0xFFF00000 boot high (for a backup copy of U-Boot)
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* List of I2C addresses to be verified by POST */
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
#define CONFIG_TK885D 1 /* ...in a TK885D base board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Network configuration
*/
#define CONFIG_FEC_ENET /* enable ethernet on FEC */
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * allowed and functional CONFIG_SYS_TEXT_BASE values:
+ * 0xff000000 low boot at 0x00000100 (default board setting)
+ * 0xfff00000 high boot at 0xfff00100 (board needs modification)
+ * 0x00100000 RAM load and test
+ */
+#define CONFIG_SYS_TEXT_BASE 0xff000000
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* MUST be low boot - HIGHBOOT is not supported anymore
*/
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#else
-# error "TEXT_BASE must be 0xff000000"
+# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
#endif
/*
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_MPC860T 1 /* even better... an FEC! */
#define CONFIG_TOP860 1 /* ...on a TOP860 module */
+
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_IDENT_STRING " EMK TOP860"
* adresses
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
*/
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
* Debug Enable Register
*-----------------------------------------------------------------------
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000 boot low (standard configuration with room for
+ * max 64 MByte Flash ROM)
+ * 0xFFF00000 boot high (for a backup copy of U-Boot)
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
+
/* On a Cameron or on a FO300 board or ... */
-#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
+#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
+ && !defined(CONFIG_FO300)
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
/* switch is open */
#endif /* CONFIG_FO300 */
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_ISO_PARTITION
/* USB */
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_STK52XX)
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_USB_STORAGE
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#endif
-#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#endif
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+ defined(CONFIG_STK52XX)
#define CONFIG_CFG_USB
#define CONFIG_CFG_FAT
#endif
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE != 0xFFF00000)
+#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
# define CONFIG_SYS_LOWBOOT 1 /* Boot low */
#endif
"fdt_addr=FC100000\0" \
"kernel_addr=FC140000\0" \
"ramdisk_addr=FC600000\0"
+#elif defined(CONFIG_CHARON)
+#define ENV_FLASH_LAYOUT \
+ "fdt_addr=FDFC0000\0" \
+ "kernel_addr=FC0A0000\0" \
+ "ramdisk_addr=FC200000\0"
#else /* !CONFIG_TQM5200_B */
#define ENV_FLASH_LAYOUT \
"fdt_addr=FC0A0000\0" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
- "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "flash_self_old=sete console ttyS0; " \
+ "run ramargs addip addcons addmtd; " \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"sete console ttyS0; run nfsargs addip addcons;bootm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addcons; " \
+ "run nfsargs addip addcons addmtd; " \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_HWMON_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_HWMON_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
#endif
/*
/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_FLASH_CFI_MTD /* with MTD support */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#define MTDIDS_DEFAULT "nor0=fc000000.flash"
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_STK52XX)
# if defined(CONFIG_TQM5200_B)
# if defined(CONFIG_SYS_LOWBOOT)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \
"256k(dtb)," \
"2304k(kernel)," \
"2560k(small-fs)," \
"8m(misc)," \
"16m(big-fs)"
# else /* highboot */
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\
"3584k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"1m(firmware)"
# endif /* CONFIG_SYS_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
"128k(dtb)," \
"2304k(kernel)," \
"2m(initrd)," \
"15m(big-fs)"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\
"1792k(kernel)," \
"5632k(rootfs)," \
"24m(home)"
+#elif defined (CONFIG_CHARON)
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "24320k(big-fs)," \
+ "256k(dts)"
#elif defined (CONFIG_FO300)
-# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
* use PSC1: Bits 29-31 (mask: 0x00000007):
* 100 -> UART (on all boards).
*/
+#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
#if defined (CONFIG_MINIFAP)
# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
#elif defined (CONFIG_STK52XX)
#else /* TMQ5200 Inbetriebnahme-Board */
# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
#endif
+#endif
/*
* RTC configuration
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#ifdef CONFIG_LCD /* with LCD controller ? */
#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
#define CONFIG_LCD_INFO 1 /* ... and some board info */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#ifdef CONFIG_LCD /* with LCD controller ? */
/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
#endif
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
* (easy to change)
*/
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
#if 0
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
* The main FLASH is whichever is connected to *CS0.
*/
#define CONFIG_SYS_FLASH0_BASE 0x40000000
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_MPC8272_FAMILY 1
#define CONFIG_TQM8272 1
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
* The main FLASH is whichever is connected to *CS0.
*/
#define CONFIG_SYS_FLASH0_BASE 0x40000000
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_TQM834X 1 /* TQM834X board specific */
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+
/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
/*
* Monitor config
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#if defined(CONFIG_TQM8548_BE)
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xfffc0000
+#endif
+
#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
#define CONFIG_TQM8548
#endif
* NAND flash support (disabled by default)
*
* Warning: NAND support will likely increase the U-Boot image size
- * to more than 256 KB. Please adjust TEXT_BASE if necessary.
+ * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
*/
#ifdef CONFIG_TQM8548_BE
#define CONFIG_NAND
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/*
* Note: when changing the Local Bus clock divider you have to
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
+ 0x04010000) /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */
#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
/* Serial Port */
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCIE1
* Addresses are mapped 1-1.
*/
#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
-#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
#endif /* CONFIG_PCIE1 */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
MK_STR(CONFIG_HOSTNAME)".dtb\0"
#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
- "uboot_addr="MK_STR(TEXT_BASE)"\0"
+ "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_ENV_BOOTFILE \
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_NET_MULTI
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_NET_MULTI
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Network configuration
*/
#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFE000000 boot low
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_CMD_USB
-#if (TEXT_BASE == 0xFE000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
* Size of malloc() pool
*/
/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOH405 1 /* ...on a VOH405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
/* define busmode: 8260 */
#undef CONFIG_BUSMODE_60x
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#ifdef CONFIG_CLKIN_66MHz
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
/* definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
#define CONFIG_SYS_MONITOR_LEN 0x00020000
#define CONFIG_SYS_MALLOC_LEN 0x00020000
-/* boot flags */
-#define BOOTFLAG_COLD 0x01 /* normal power-on */
-#define BOOTFLAG_WARM 0x02 /* software reboot */
-
/* cache configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
* Definitions for initial stack pointer and data area (in RAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
* Definitions for initial stack pointer and data area (in RAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WUH405 1 /* ...on a WUH405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Default speed selection (cpu_plb_opb_ebc) in mhz.
* This value will be set if iic boot eprom is disabled.
*/
#define CONFIG_MPC8220 1
#define CONFIG_YUKON8220 1 /* ... on Yukon board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* Serial console configuration
*/
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CPU_ID_STR "MPC8265"
#define CONFIG_CPM2 1 /* Has a CPM2 */
#define BCSR_PCI_MODE 0x01
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK
*/
#define CONFIG_GT_I2C
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
/*-----------------------------------------------------------------------
* size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*-----------------------------------------------------------------------
* SDRAM controller configuration
--- /dev/null
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
+#define CONFIG_A4M072 1 /* ... on A4M072 board */
+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+/* define to enable silent console */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+#endif
+
+#define CONFIG_SYS_XLB_PIPELINING 1
+
+#undef CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DISPLAY
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
+#define CONFIG_SYS_LOWBOOT 1
+#define CONFIG_SYS_LOWBOOT32 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
+
+#define CONFIG_SYS_AUTOLOAD "n"
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "asdfg"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_PREBOOT "run try_update"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
+ "cf1=diskboot 200000 0:1\0" \
+ "bootcmd_cf1=run bcf1\0" \
+ "bcf=setenv bootargs root=/dev/hda3\0" \
+ "bootcmd_nfs=run bnfs\0" \
+ "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
+ "panic=1\0" \
+ "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \
+ "run norargs addip; run bk\0" \
+ "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \
+ "run nfsargs addip ; run bk\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "try_update=usb start;sleep 2;usb start;sleep 1;" \
+ "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \
+ "source 2F0000\0" \
+ "env_addr=FE060000\0" \
+ "kernel_addr=FE100000\0" \
+ "rootfs_addr=FE200000\0" \
+ "add_mtd=setenv bootargs ${bootargs} mtdparts=" \
+ "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
+ "bcf1=run cf1; run bcf; run addip; run bk\0" \
+ "add_consolespec=setenv bootargs ${bootargs} " \
+ "console=/dev/null quiet\0" \
+ "addip=if test -n ${ethaddr};" \
+ "then if test -n ${ipaddr};" \
+ "then setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:"\
+ "${netmask}:${hostname}:${netdev}:off;" \
+ "fi;" \
+ "else;" \
+ "setenv bootargs ${bootargs} no_ethaddr;" \
+ "fi\0" \
+ "hostname=CPUP0\0" \
+ "ethaddr=00:00:00:00:00:00\0" \
+ "netdev=eth0\0" \
+ "bootcmd=run bootcmd_nor\0" \
+ ""
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_EEPROM_WREN 1
+#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000
+#define CONFIG_SYS_FLASH_SIZE 0x02000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#error "CONFIG_SYS_LOWBOOT not defined?"
+#else /* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT32)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif
+#endif /* CONFIG_SYS_LOWBOOT */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
+#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE}
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xF0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR 0x1f
+#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING 1
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+/* Flash at CSBoot, CS0 */
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+/* External SRAM at CS1 */
+#define CONFIG_SYS_CS1_START 0x62000000
+#define CONFIG_SYS_CS1_SIZE 0x00400000
+#define CONFIG_SYS_CS1_CFG 0x00009930
+#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
+#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
+/* LED display at CS7 */
+#define CONFIG_SYS_CS7_START 0x6a000000
+#define CONFIG_SYS_CS7_SIZE (64*1024)
+#define CONFIG_SYS_CS7_CFG 0x0000bf30
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33333003
+
+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define CONFIG_ATAPI 1
+
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
+/* Support for the 7-segment display */
+#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
+#define CONFIG_SHOW_ACTIVITY /* used for display realization */
+
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_AEVFIFO 1
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000 boot low (standard configuration with room for
+ * max 64 MByte Flash ROM)
+ * 0xFFF00000 boot high (for a backup copy of U-Boot)
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* DDR related
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
/*
* Board NAND Info.
*/
extern unsigned int boot_flash_type;
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
#define __AMCC_COMMON_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#if defined(CONFIG_SYS_RAMBOOT)
-/*
- * Disable NOR FLASH commands on RAM-booting version. One main reason for this
- * RAM-booting version is boards with NAND and without NOR. This image can
- * be used for initial NAND programming.
- */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
/*
* Miscellaneous configurable options
*/
"load=tftp 200000 ${u-boot}\0" \
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}" \
+ "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
"u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \
"nload=tftp 200000 ${u-boot-nand}\0" \
- "nupdate=nand erase 0 100000;nand write 200000 0 100000" \
+ "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
"nupd=run nload nupdate\0"
#endif /* __AMCC_COMMON_H */
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
/* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
-#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
/* video */
#undef CONFIG_VIDEO
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_ASPENITE_H
+#define __CONFIG_ASPENITE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-Aspenite DB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
+#define CONFIG_ARMADA100 1 /* SOC Family Name */
+#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
+#define CONFIG_MACH_ASPENITE /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#define CONFIG_ENV_SIZE 0x20000 /* 64k */
+
+#endif /* __CONFIG_ASPENITE_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
/*
* Hardware drivers
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
#include <config_cmd_default.h>
/*
- * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from
+ * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
* a different bootloader that has already performed RAM setup) or
* started directly from flash, which is the regular case for production
* boards.
*/
-#ifdef CONFIG_MK_RAM
+#ifdef CONFIG_RAM
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_TEXT_BASE 0x40020000
+#define CONFIG_SYS_TEXT_BASE 0x40020000
#define ENABLE_JFFS 0
#else
-#define CONFIG_TEXT_BASE 0x00000000
+#define CONFIG_SYS_TEXT_BASE 0x00000000
#define ENABLE_JFFS 1
#endif
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_FLASH_BASE 0x00000000
#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#else
/* This is mainly used during relocation in start.S */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
/*
+ * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
+ *
+ * based on previous work by
+ *
* Ulf Samuelsson <ulf@atmel.com>
* Rick Bronson <rick@efn.org>
*
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __AT91RM9200EK_CONFIG_H__
+#define __AT91RM9200EK_CONFIG_H__
-#define CONFIG_AT91_LEGACY
+#include <asm/sizes.h>
-/* ARM asynchronous clock */
/*
- * from 18.432 MHz crystal
- * (18432000 / 4 * 39)
+ * set some initial configurations depending on configure target
+ *
+ * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
+ * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
+ * initialisation was done by some preloader
*/
-#define AT91C_MAIN_CLOCK 179712000
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x20100000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+#endif
+
/*
- * peripheral clock
- * (AT91C_MASTER_CLOCK / 3)
+ * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
+ * AT91C_MAIN_CLOCK is the frequency of PLLA output
+ * AT91C_MASTER_CLOCK is the peripherial clock
+ * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
+ * set in arch/arm/cpu/arm920t/at91/timer.c)
+ * CONFIG_SYS_HZ is the tick rate for timer tc0
*/
-#define AT91C_MASTER_CLOCK 59904000
+#define AT91C_XTAL_CLOCK 18432000
+#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_HZ 1000
+
+/* CPU configuration */
+#define CONFIG_ARM920T
+#define CONFIG_AT91RM9200
+#define CONFIG_AT91RM9200EK
+#define CONFIG_CPUAT91
+#define USE_920T_MMU
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define AT91_SLOW_CLOCK 32768 /* slow clock */
+#define CONFIG_AT91FAMILY
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#define USE_920T_MMU 1
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE SZ_32M
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
/*
* LowLevel Init
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
-#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
-
-/*
- * Memory Configuration
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */
-
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
-
/*
* Hardware drivers
*/
-
/*
- * UART Configuration
- *
- * define one of these to choose the DBGU,
- * USART0 or USART1 as console
+ * Choose a USART for serial console
+ * CONFIG_DBGU is DBGU unit on J10
+ * CONFIG_USART1 is USART1 on J14
*/
#define CONFIG_AT91RM9200_USART
#define CONFIG_DBGU
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-/* don't include RTS/CTS flow control support */
-#undef CONFIG_HWFLOW
-/* disable modem initialization stuff */
-#undef CONFIG_MODEM_SUPPORT
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_IMI
+#define CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_LOADS
-
-#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-/* Options for MMC/SD Card */
-#define CONFIG_DOS_PARTITION 1
-#undef CONFIG_MMC
-#define CONFIG_SYS_MMC_BASE 0xFFFB4000
-#define CONFIG_SYS_MMC_BLOCKSIZE 512
/*
* Network Driver Setting
*/
-#define CONFIG_NET_MULTI 1
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#else
-#define CONFIG_DRIVER_ETHER 1
-#endif
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_AT91C_USE_RMII
-
-/*
- * AC Characteristics
- * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
- */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#if defined(CONFIG_HAS_DATAFLASH)
-#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
-#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
-/* Logical adress for CS0 */
-#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
-/* Logical adress for CS3 */
-#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000
-#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1
-#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22
-#endif
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER 16
+#define CONFIG_RMII
+#define CONFIG_MII
/*
* NOR Flash
*/
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define PHYS_FLASH_SIZE 0x800000 /* 8MB */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_SIZE SZ_8M
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_PROTECTION
/*
- * Environment Settings
- */
-#ifdef CONFIG_ENV_IS_IN_DATAFLASH
-/*
- * Datasflash Environment Settings
+ * USB Config
*/
-#define CONFIG_ENV_OFFSET 0x4200
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
-/* 8 * 1056 really , but start.s is not OK with this*/
-#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_USB_ATMEL 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_KEYBOARD 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
-#else
-/*
- * NOR Flash Environment Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
/*
- * between boot.bin and u-boot.bin.gz
+ * Environment Settings
*/
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
-#else
+#define CONFIG_ENV_IS_IN_FLASH
+
/*
* after u-boot.bin
*/
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
+#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN \
- (CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
+#define CONFIG_SYS_MONITOR_LEN SZ_256K
/*
* Boot option
*/
#define CONFIG_BOOTDELAY 3
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-/* boot.bin, env, u-boot.bin.gz */
-#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000)
-#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
-#else
-/* u-boot.bin */
-#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * USB Config
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C
-
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED 0 /* not used */
-#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
-#endif
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
+#define CONFIG_ENV_OVERWRITE
/*
* Shell Settings
*/
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#ifndef __ASSEMBLY__
-/*-----------------------------------------------------------------------
- * Board specific extension for bd_info
- *
- * This structure is embedded in the global bd_info (bd_t) structure
- * and can be used by the board specific code (eg board/...)
- */
-
-struct bd_info_ext {
- /* helper variable for board environment handling
- *
- * env_crc_valid == 0 => uninitialised
- * env_crc_valid > 0 => environment crc in flash is valid
- * env_crc_valid < 0 => environment crc in flash is invalid
- */
- int env_crc_valid;
-};
-#endif
-
-#define CONFIG_SYS_HZ 1000
-/*
- * AT91C_TC0_CMR is implicitly set to
- * AT91C_TC_TIMER_DIV1_CLOCK
- */
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
- , 0x1000)
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
+ SZ_4K)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/
-#endif
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
+ - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE SZ_32K /* regular stack */
+#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
+#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
+#endif /* __AT91RM9200EK_CONFIG_H__ */
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#define CONFIG_ATC 1 /* ...on a ATC board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
/*
* select serial console configuration
*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
#define CONFIG_ENV_SIZE 2048
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
* Cache Configuration
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_DOS_PARTITION 1
-
/*
* Command line configuration.
*/
--- /dev/null
+/*
+ * Balloon3 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_BALLOON3 1 /* Balloon3 board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOOTCOMMAND \
+ "fpga load 0x0 0x50000 0x62638; " \
+ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0xd0000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_STUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FPGA
+#undef CONFIG_LCD
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0xa1000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_ENV_IS_IN_FLASH
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
+#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
+#define CONFIG_SYS_GPSR2_VAL 0x7131c000
+#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
+
+#define CONFIG_SYS_GPCR0_VAL 0x0
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPCR3_VAL 0x0
+
+#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
+#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
+#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
+#define CONFIG_SYS_GPDR3_VAL 0x000201fe
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
+#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
+#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
+#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0xffffffff
+#define CONFIG_SYS_CCCR 0x00000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
+#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
+#define CONFIG_SYS_MSC2_VAL 0x74a42491
+#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
+#define CONFIG_SYS_MDREFR_VAL 0x001d8018
+#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_BALLOON3LCD
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * FPGA
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT 1000
+#define CONFIG_MAX_FPGA_DEVICES 1
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
+++ /dev/null
-/********************************************************************
- *
- * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
- *
- * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
- * $Revision: 1.2 $
- * $Author: mleeman $
- * $Date: 2005/02/21 12:48:58 $
- *
- * Last ChangeLog Entry
- * $Log: barco.h,v $
- * Revision 1.2 2005/02/21 12:48:58 mleeman
- * update of copyright years (feedback wd)
- *
- * Revision 1.1 2005/02/14 09:29:25 mleeman
- * moved barcohydra.h to barco.h
- *
- * Revision 1.4 2005/02/09 12:56:23 mleeman
- * add generic header to track changes in sources
- *
- *
- *******************************************************************/
-
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X 1
-#define CONFIG_MPC8245 1
-#define CONFIG_BARCOBCD_STREAMING 1
-
-#undef USE_DINK32
-
-#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-#define CONFIG_BOOTARGS "mem=32M"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_CMD_NET
-
-
-#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_BOOTCOMMAND "boot_default"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
-
-#define CONFIG_LOGBUFFER
-#ifdef CONFIG_LOGBUFFER
-#define CONFIG_SYS_STDOUT_ADDR 0x1FFC000
-#define CONFIG_SYS_POST_WORD_ADDR \
- (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 4)
-#else
-#define CONFIG_SYS_STDOUT_ADDR 0x2B9000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#define CONFIG_SYS_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFDF00000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00400000
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SOFT_I2C
-#error "Soft I2C is not configured properly. Please review!"
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-#define CONFIG_SYS_DBUS_SIZE2 1
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
- /*
- * NS16550 Configuration (internal DUART)
- */
- /*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_SYS_ROMNAL 0x0F /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 0x1E /*rom/flash access time */
-
-#define CONFIG_SYS_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 0
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END 0x01FFFFFF
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x02000000
-#define CONFIG_SYS_BANK1_END 0x02ffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x03f00000
-#define CONFIG_SYS_BANK2_END 0x03ffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x04000000
-#define CONFIG_SYS_BANK3_END 0x04ffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x05000000
-#define CONFIG_SYS_BANK4_END 0x05FFFFFF
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x06000000
-#define CONFIG_SYS_BANK5_END 0x06FFFFFF
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x07000000
-#define CONFIG_SYS_BANK6_END 0x07FFFFFF
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x08000000
-#define CONFIG_SYS_BANK7_END 0x08FFFFFF
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * U-boot - Configuration file for BF536 brettl2 board
+ */
+
+#ifndef __CONFIG_BCT_BRETTL2_H__
+#define __CONFIG_BCT_BRETTL2_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 16384000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 24
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 3
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+
+/*
+ * SDRAM Settings
+ */
+#define CONFIG_EBIU_SDRRC_VAL 0x07f6
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC 1
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HOSTNAME brettl2
+#define CONFIG_IPADDR 192.168.233.224
+#define CONFIG_GATEWAYIP 192.168.233.1
+#define CONFIG_SERVERIP 192.168.233.53
+#define CONFIG_ROOTPATH /romfs/brettl2
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
+ . = DEFINED(env_offset) ? env_offset : .; \
+ common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_LOADADDR 0x800000
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/* disable unnecessary features */
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BZIP2
+#undef CONFIG_KALLSYMS
+
+#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf526-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
* (can't be used same time as ethernet)
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf527-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
#define CONFIG_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_SPI_MMC
-#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3)
+#define CONFIG_SPI_MMC_DEFAULT_CS (MAX_CTRL_CS + GPIO_PH3)
/*
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Video Settings
*/
-#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
# define CONFIG_LQ035Q1_SPI_BUS 0
# define CONFIG_LQ035Q1_SPI_CS 7
#endif
--- /dev/null
+/*
+ * U-boot - Configuration file for BF527 SDP board
+ */
+
+#ifndef __CONFIG_BF527_SDP_H__
+#define __CONFIG_BF527_SDP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 25
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+#define CONFIG_PLL_LOCKCNT_VAL 0x0200
+#define CONFIG_PLL_CTL_VAL 0x2a00
+#define CONFIG_VR_CTL_VAL 0x7090
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+#define CONFIG_EBIU_SDRRC_VAL 0x00FE
+#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
/*
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
/*
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf538-0.4
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
/*
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
* Misc Settings
*/
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
+#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
#ifndef __ADSPBF542__
/* Don't waste time transferring a logo over the UART */
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
- lib/zlib.o (.text .text.*); \
- board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
# endif
# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
# define CONFIG_CMD_NAND
+# define CONFIG_CMD_NAND_LOCK_UNLOCK
# endif
# ifdef CONFIG_POST
# define CONFIG_CMD_DIAG
/*
* Env Settings
*/
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY -1
-#else
-# define CONFIG_BOOTDELAY 5
+#ifndef CONFIG_BOOTDELAY
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+# else
+# define CONFIG_BOOTDELAY 5
+# endif
#endif
#ifndef CONFIG_BOOTCOMMAND
# define CONFIG_BOOTCOMMAND "run ramboot"
# define UBOOT_ENV_UPDATE \
"eeprom write $(loadaddr) 0x0 $(filesize)"
# else
+# ifndef CONFIG_BFIN_SPI_IMG_SIZE
+# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
+# endif
# define UBOOT_ENV_UPDATE \
"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 0x40000;" \
+ "sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#else
# define NETWORK_ENV_SETTINGS
#endif
+#ifndef BOARD_ENV_SETTINGS
+# define BOARD_ENV_SETTINGS
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
NAND_ENV_SETTINGS \
NETWORK_ENV_SETTINGS \
- FLASHBOOT_ENV_SETTINGS
+ FLASHBOOT_ENV_SETTINGS \
+ BOARD_ENV_SETTINGS
/*
* Network Settings
*/
#ifdef CONFIG_CMD_NET
-# define CONFIG_IPADDR 192.168.0.15
# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_GATEWAYIP 192.168.0.1
-# define CONFIG_SERVERIP 192.168.0.2
-# define CONFIG_ROOTPATH /romfs
+# ifndef CONFIG_IPADDR
+# define CONFIG_IPADDR 192.168.0.15
+# define CONFIG_GATEWAYIP 192.168.0.1
+# define CONFIG_SERVERIP 192.168.0.2
+# endif
+# ifndef CONFIG_ROOTPATH
+# define CONFIG_ROOTPATH /romfs
+# endif
# ifdef CONFIG_CMD_DHCP
# ifndef CONFIG_SYS_AUTOLOAD
# define CONFIG_SYS_AUTOLOAD "no"
#endif
/*
+ * SPI Settings
+ */
+#ifdef CONFIG_SPI_FLASH_ALL
+# define CONFIG_SPI_FLASH_ATMEL
+# define CONFIG_SPI_FLASH_MACRONIX
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
+/*
* I2C Settings
*/
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
/*
* Misc Settings
*/
+#ifndef CONFIG_BOARD_SIZE_LIMIT
+# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
+#endif
#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
/* CPU Options
* Be sure to set the Silicon Revision Correctly
*/
-#define CONFIG_BFIN_CPU bf532-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
--- /dev/null
+/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
+ * The board includes ADSP-BF561 rev. 0.5,
+ * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
+ * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
+ * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
+ * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
+ * Spartan6-LX150 (memory-mapped; both PPIs also connected).
+ * See http://www.skutek.com
+ */
+
+#ifndef __CONFIG_BLACKVME_H__
+#define __CONFIG_BLACKVME_H__
+
+#include <asm/config-pre.h>
+
+/* Debugging: Set these options if you're having problems
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+ * CONFIG_PANIC_HANG means that the board will not auto-reboot
+ */
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options */
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+/*
+ * CLOCK SETTINGS CAVEAT
+ * You CANNOT just change the clock settings, esp. the SCLK.
+ * The SDRAM timing, SPI baud, and the serial UART baud
+ * use SCLK frequency to set their own frequencies. Therefore,
+ * if you change the SCLK_DIV, you may also have to adjust
+ * SDRAM refresh and other timings.
+ * --------------------------------------------------------------
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * 25 * 8 / 1 = 200 MHz
+ * 25 * 16 / 1 = 400 MHz
+ * 25 * 24 / 1 = 600 MHz
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ * 25 * 8 / 2 = 100 MHz
+ * 25 * 24 / 6 = 100 MHz
+ * 25 * 24 / 5 = 120 MHz
+ * 25 * 16 / 3 = 133 MHz
+ * 25 MHz because the oscillator also feeds the ether chip.
+ * CONFIG_CLKIN_HZ is 25 MHz written in Hz
+ * CLKIN_HALF controls the DF bit in PLL_CTL
+ * 0 = CLKIN 1 = CLKIN / 2
+ * PLL_BYPASS controls the BYPASS bit in PLL_CTL
+ * 0 = do not bypass 1 = bypass PLL
+ * VCO_MULT = MSEL (multiplier) in PLL_CTL
+ * Values can range from 0-63 (where 0 means 64)
+ * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
+ * SCLK_DIV = system clock divider, 1 to 15
+ */
+#define CONFIG_CLKIN_HZ 25000000
+#define CONFIG_CLKIN_HALF 0
+#define CONFIG_PLL_BYPASS 0
+#define CONFIG_VCO_MULT 8
+#define CONFIG_CCLK_DIV 1
+#define CONFIG_SCLK_DIV 2
+
+/*
+ * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
+ * Used in 32-bit mode. 16-bit mode not supported.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ */
+/*
+ * Network settings using a dedicated 2nd ether card in PC
+ * Windows will automatically acquire IP of that card
+ * Then use the dedicated card IP + 1 for the board
+ * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
+ */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_DRIVER_AX88180 1
+#define AX88180_BASE 0x2c000000
+#define CONFIG_CMD_MII /* enable probing PHY */
+
+#ifdef CONFIG_NET_MULTI /* also used as the network enabler */
+# define CONFIG_HOSTNAME blackvme /* Bfin board */
+# define CONFIG_IPADDR 169.254.144.145 /* Bfin board */
+# define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */
+# define CONFIG_SERVERIP 169.254.144.144 /* tftp server */
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_ROOTPATH /export/uClinux-dist/romfs /*NFS*/
+# define CFG_AUTOLOAD "no"
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+# define CONFIG_ENV_OVERWRITE 1 /* enable changing MAC at runtime */
+/* Comment out hardcoded MAC to enable MAC storage in EEPROM */
+/* # define CONFIG_ETHADDR ff:ee:dd:cc:bb:aa */
+#endif
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
+/*
+ * SDRAM reference page
+ * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+ * NOTE: BlackVME populates only SDRAM bank 0
+ */
+/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */
+#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */
+
+/* Async memory global settings. (ASRAM, not SDRAM)
+ * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
+ * CLKOUT enabled, all async banks enabled, core has priority
+ * bank 0&1 16 bit (FPGA)
+ * bank 2&3 32 bit (ether and USB chips)
+ */
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */
+
+/* Async mem timing: BF561 HRM page 16-12 and 16-15.
+ * Default values 0xFFC2 FFC2 are the slowest supported.
+ * Example settings of CONFIG_EBIU_AMBCTL1_VAL
+ * 1. EZ-KIT settings: 0xFFC2 7BB0
+ * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
+ * See the following page:
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
+ * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
+ * One extra clock needed because AX88180 is asynchronous to CPU.
+ */
+ /* bank 1 0 */
+#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
+ /* bank 3 2 */
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
+
+/* memory layout */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (384 << 10)
+
+/*
+ * Serial SPI Flash
+ * For the M25P64 SCK should be kept < 15 MHz
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x40000
+
+#define CONFIG_ENV_SPI_MAX_HZ 15000000
+#define CONFIG_SF_DEFAULT_SPEED 15000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Interactive command settings
+ */
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE 1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ELF
+
+/*
+ * Default: boot from SPI flash.
+ * "sfboot" is a composite command defined in extra settings
+ */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "run sfboot"
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_UART_CONSOLE 0
+
+/*
+ * U-Boot environment variables. Use "printenv" to examine.
+ * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
+ */
+#define CONFIG_BOOTARGS \
+ "root=/dev/mtdblock0 rw " \
+ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "earlyprintk=serial,uart0," \
+ MK_STR(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
+
+/* Convenience env variables & commands.
+ * Reserve kernstart = 0x20000 = 128 kB for U-Boot.
+ * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size).
+ * U-Boot image is saved at flash offset=0.
+ * Kernel image is saved at flash offset=$kernstart.
+ * Instructions. Ksave takes about a minute to complete.
+ * 1. Update U-Boot: run uget; run usave
+ * 2. Update kernel: run kget; run ksave
+ * After updating U-Boot also update the kernel per above instructions
+ * to make the saved environment consistent with the flash.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernstart=0x20000\0" \
+ "kernarea=0x500000\0" \
+ "uget=tftp u-boot.ldr\0" \
+ "kget=tftp uImage\0" \
+ "usave=sf probe 2; " \
+ "sf erase 0 $(kernstart); " \
+ "sf write $(fileaddr) 0 $(filesize)\0" \
+ "ksave=sf probe 2; " \
+ "saveenv; " \
+ "echo Now patiently wait for the prompt...; " \
+ "sf erase $(kernstart) $(kernarea); " \
+ "sf write $(fileaddr) $(kernstart) $(filesize)\0" \
+ "sfboot=sf probe 2; " \
+ "sf read $(loadaddr) $(kernstart) $(filesize); " \
+ "run addip; bootm\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):eth0:off\0"
+
+/*
+ * Soft I2C settings (BF561 does not have hard I2C)
+ * PF12,13 on SPI connector 0.
+ */
+#ifdef CONFIG_SOFT_I2C
+# define CONFIG_CMD_I2C
+# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
+# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
+# define CONFIG_SYS_I2C_SPEED 50000
+# define CONFIG_SYS_I2C_SLAVE 0xFE
+#endif
+
+/*
+ * No Parallel Flash on this board
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#endif
--- /dev/null
+/*
+ * bluestone.h - configuration for Bluestone (APM821XX)
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_APM821XX 1 /* APM821XX series */
+#define CONFIG_HOSTNAME bluestone
+
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+#define CONFIG_SYS_CLK_FREQ 50000000
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* EBC stuff */
+/* later mapped to this addr */
+#define CONFIG_SYS_FLASH_BASE 0xFFF00000
+#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
+
+/* EBC Boot Space: 0xFF000000 */
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
+#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
+#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
+#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
+
+#define CONFIG_SYS_SRAM_SIZE (256 << 10)
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 80
+/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
+/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* SDRAM */
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
+#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
+#define CONFIG_DDR_ECC 1 /* with ECC support */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
+#define CONFIG_HAS_ETH0
+/* PHY address, See schematics */
+#define CONFIG_PHY_ADDR 0x1f
+/* reset phy upon startup */
+#define CONFIG_PHY_RESET 1
+/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_GIGE 1
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+/*
+ * External Bus Controller (EBC) Setup
+ **/
+#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
+ EBC_CFG_PTD_ENABLE | \
+ EBC_CFG_RTC_2048PERCLK | \
+ EBC_CFG_ATC_HI | \
+ EBC_CFG_DTC_HI | \
+ EBC_CFG_CTC_HI | \
+ EBC_CFG_OEO_PREVIOUS)
+/* NOR Flash */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(64) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(1) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(2) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(7) | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+/* Peripheral Bank Configuration Register - EBC_BxCR */
+#define CONFIG_SYS_EBC_PB0CR \
+ (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT)
+
+
+#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_C2MON 1 /* ...on a C2MON module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ * configurations.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board info register */
+#define SYS_ID 0x10000000
+#define CONFIG_REVISION_TAG 1
+
+/* High Level Configuration Options */
+#define CONFIG_ARMV7 1
+
+#define CONFIG_SYS_MEMTEST_START 0x60000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_L2_OFF 1
+#define CONFIG_INITRD_TAG 1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+#define SCTL_BASE 0x10001000
+#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
+
+/* SMSC9115 Ethernet from SMSC9118 family */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE 0x4E000000
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX 0
+
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0 0x10009000
+#define CONFIG_SYS_SERIAL1 0x1000A000
+
+/* Command line configuration */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_RUN
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR 0x60008000 /* load address */
+#define LINUX_BOOT_PARAM_ADDR 0x60000200
+#define CONFIG_BOOTDELAY 2
+
+/* Stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 0x60000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
+#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
+
+/* additions for new relocation code */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Basic environment settings */
+#define CONFIG_BOOTCOMMAND "run bootflash;"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80008000\0" \
+ "initrd=0x61000000\0" \
+ "kerneladdr=0x44100000\0" \
+ "initrdaddr=0x44800000\0" \
+ "maxinitrd=0x1800000\0" \
+ "console=ttyAMA0,38400n8\0" \
+ "dram=1024M\0" \
+ "root=/dev/sda1 rw\0" \
+ "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
+ "24M@0x2000000(initrd)\0" \
+ "flashargs=setenv bootargs root=${root} console=${console} " \
+ "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
+ "devtmpfs.mount=0 vmalloc=256M\0" \
+ "bootflash=run flashargs; " \
+ "cp ${initrdaddr} ${initrd} ${maxinitrd}; " \
+ "bootm ${kerneladdr} ${initrd}\0"
+
+/* FLASH and environment organization */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_SIZE 0x04000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BASE0 0x40000000
+#define CONFIG_SYS_FLASH_BASE1 0x44000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
+#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
+
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
+
+/*
+ * Amount of flash used for environment:
+ * We don't know which end has the small erase blocks so we use the penultimate
+ * sector location for the environment
+ */
+#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE
+#define CONFIG_ENV_OVERWRITE 1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
+ (2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
+ CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
+ CONFIG_SYS_FLASH_BASE1 }
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT "VExpress# "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMD_SOURCE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 16 /* max command args */
+
+#endif
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * allowed and functional CONFIG_SYS_TEXT_BASE values:
+ * 0xfe000000 low boot at 0x00000100 (default board setting)
+ * 0x00100000 RAM load and test
+ */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_BOARD_EARLY_INIT_R
/*
* MUST be low boot - HIGHBOOT is not supported anymore
*/
-#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#else
-# error "TEXT_BASE must be 0xFE000000"
+# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
#endif
/*
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
* Initial RAM & stack pointer (placed in OCM)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_CERF250 1 /* on Cerf PXA Board */
#define BOARD_LATE_INIT 1
#define CONFIG_BAUDRATE 38400
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
--- /dev/null
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_CHARON_H
+#define __CONFIG_CHARON_H
+
+#define CONFIG_CHARON
+#define CONFIG_HOSTNAME charon
+
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x81550414
+
+/* include common defines/options for TQM52xx boards */
+#include "TQM5200.h"
+
+/* defines special on charon board */
+#undef CONFIG_RTC_MPC5200
+#undef CONFIG_CMD_DATE
+
+#undef CUSTOM_ENV_SETTINGS
+#define CUSTOM_ENV_SETTINGS \
+ "bootfile=/tftpboot/charon/uImage\0" \
+ "fdt_file=/tftpboot/charon/charon.dtb\0" \
+ "u-boot=/tftpboot/charon/u-boot.bin\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
+
+
+/* additional features on charon board */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_SYS_TFP410_ADDR 0x38
+#define CONFIG_SYS_TFP410_BUS 0
+
+/*
+ * FPGA configuration
+ */
+#define CONFIG_SYS_CS3_START 0xE8000000
+#define CONFIG_SYS_CS3_SIZE 0x80000 /* 512 KByte */
+
+/*
+ * CS3 Config Register Init:
+ * CS3 Enabled
+ * AddrBus: 8bits
+ * DataBus: 4bytes
+ * Multiplexed: Yes
+ * MuxBank: 00
+ */
+#define CONFIG_SYS_CS3_CFG 0x00009310
+
+#endif /* __CONFIG_CHARON_H */
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_CM5200 1 /* ... on CM5200 platform */
+#define CONFIG_SYS_TEXT_BASE 0xfc000000
+
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
+ CONFIG_SYS_I2C_IO, \
+ CONFIG_SYS_I2C_EEPROM}
/* display image timestamps */
#define CONFIG_TIMESTAMP 1
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_BOARD_TYPES 1 /* we use board_type */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
/*
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 9600
#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
#define CONFIG_CMI 1 /* Using the customized cmi board */
+#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */
+
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
#undef CONFIG_5xx_CONS_SCI2
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
+#undef CONFIG_CMD_NFS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADB
* Definitions for initial stack pointer and data area
*/
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
-#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
/*
#define ANYBUS_BASE 0x03010000 /* Anybus Module */
#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
/* This adress is given to the linker with -Ttext to */
/* locate the text section at this adress. */
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
*/
#define CONFIG_SYS_DER 0x00000000
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
*
* Setting #if 0: u-boot will start from flash and relocate itself to RAM
*
- * Please do not forget to modify the setting of TEXT_BASE
+ * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
* in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
*
* ---
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
#define CONFIG_CMD_KGDB
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#else
#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
* (the *_SIZE vars must be a power of 2)
*/
-#define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */
+#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
#if 0
#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
#endif
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2010
* Murray Jensen <Murray.Jensen@cmst.csiro.au>
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#else
#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
* (the *_SIZE vars must be a power of 2)
*/
-#define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */
+#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
#undef BOARD_LATE_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
*/
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_ENV_OVERWRITE /* override default environment */
#define CONFIG_BOOTCOMMAND \
#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
#endif
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
-#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
-#else
-#define CONFIG_SYS_SDRAM_SIZE 4096
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x01031000
-#define CONFIG_SYS_DDR_TIMING_0 0x55440804
-#define CONFIG_SYS_DDR_TIMING_1 0x74713a66
-#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b
-#define CONFIG_SYS_DDR_MODE_1 0x00421850
-#define CONFIG_SYS_DDR_MODE_2 0x00100000
-#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x10400100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03401500
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608
-#define CONFIG_SYS_DDR_CONTROL 0xc7048000
-#define CONFIG_SYS_DDR_CONTROL2 0x24400011
-#define CONFIG_SYS_DDR_CDR1 0x00000000
-#define CONFIG_SYS_DDR_CDR2 0x00000000
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-#define CONFIG_SYS_DDR_DEBUG_18 0x40100400
-
-#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf
-#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff
-#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
-#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG
-#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3
-#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0
-#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1
-#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2
-#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1
-#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2
-#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL
-#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL
-#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT
-#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL
-#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4
-#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5
-#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL
-#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL
-#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL
-#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2
-#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1
-#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2
-#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN
-#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS
-#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE
-#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18
-
-#endif
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_DHCP
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_DATE
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
-#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
*/
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_STACKSIZE (32 * 1024)
#ifdef CONFIG_CPUAT91_RAM
#define CONFIG_SKIP_LOWLEVEL_INIT 1
-#define CONFIG_SKIP_RELOCATE_UBOOT 1
#else
#define CONFIG_BOOTDELAY 1
#endif
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_STACKSIZE (32 * 1024)
#if defined(CONFIG_USE_IRQ)
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
-
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
* Clocks, power control and interrupts
*/
#define CONFIG_SYS_PSSR_VAL 0x00000020
-#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
+#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/* FIXME
*
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
#endif
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
#define LED_IRDA1 2
#define LED_IRDA2 4
#define LED_IRDA3 6
-#define CRADLE_LED_SET_REG GPSR2
-#define CRADLE_LED_CLR_REG GPCR2
/* SuperIO defines */
#define CRADLE_SIO_INDEX 0x2e
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
-
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Hardware drivers
*/
*
*/
#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
# if 0
/* FIXME: switch to _documented_ registers */
/*
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
#define CONFIG_SYS_MDREFR_VAL 0x038ff030
#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* OS Bootstrap configuration
*
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
*
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
-/*
- * Internal Definitions
- *
- * Boot Flags
- *
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* OS Bootstrap configuration
*
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 0x00800000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
*
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
*/
#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
-/*
- * Internal Definitions
- *
- * Boot Flags
- *
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Start */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
-#define DEF_BOOTM ""
#endif
#ifdef CONFIG_USE_NOR
"mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST
#endif
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/*
* Board
*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
/*
* SoC Configuration
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
/*
* I2C Configuration
*/
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 25000
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
/*
* U-Boot general configuration
/*
* Linux Information
*/
-#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS \
"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
#undef CONFIG_CMD_PING
#endif
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#endif
/* additions for new relocation code, must added to all boards */
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
#define DAVINCI_DM355EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_DISPLAY_CPUINFO
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define DAVINCI_DM355LEOPARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_DISPLAY_CPUINFO
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define DAVINCI_DM365EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define DAVINCI_DM6467EVM
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* initial data */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_CMD_NAND
#endif
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/*=======*/
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NOR
+#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
/*====================*/
/* Serial Driver info */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_PREBOOT "usb start"
#endif
#endif
-/*=======================*/
-/* KGDB support (if any) */
-/*=======================*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
-/*=======================*/
-/* KGDB support (if any) */
-/*=======================*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
-/* KGDB support (if any) */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
-/*=======================*/
-/* KGDB support (if any) */
-/*=======================*/
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define CONFIG_FLASH_CFI_DRIVER 1
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* Environments */
/* bootargs */
#define CONFIG_SYS_MONITOR_BASE 0x00090000
#define CONFIG_SYS_RAMBOOT 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END 0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
+++ /dev/null
-/*
- * Configuation settings for the Delta board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
-#define CONFIG_DELTA 1 /* Delta board */
-
-/* #define CONFIG_LCD 1 */
-#ifdef CONFIG_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-#define BOARD_LATE_INIT 1
-
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#undef TURN_ON_ETHERNET
-#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
-# define CONFIG_SMC91111_BASE 0x14000300
-# define CONFIG_SMC91111_EXT_PHY
-# define CONFIG_SMC_USE_32_BIT
-# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
-#endif
-
-#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
-#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
-#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
-#define CONFIG_SYS_I2C_INIT_BOARD 1
-/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
-
-#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
-#define CONFIG_PREBOOT "\0"
-
-#ifdef DELTA_CHECK_KEYBD
-# define KEYBD_DATALEN 4 /* we have four keys */
-# define KEYBD_KP_DKIN0 0x1 /* vol+ */
-# define KEYBD_KP_DKIN1 0x2 /* vol- */
-# define KEYBD_KP_DKIN2 0x3 /* multi */
-# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
-#endif /* DELTA_CHECK_KEYBD */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#ifdef TURN_ON_ETHERNET
-
-#define CONFIG_CMD_PING
-
-#else
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-#endif
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-
-#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 192.168.0.21
-#define CONFIG_SERVERIP 192.168.0.250
-#define CONFIG_BOOTCOMMAND "bootm 80000"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_TIMESTAMP
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-
-#define CONFIG_SYS_HZ 1000
-
-/* Monahans Core Frequency */
-#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
-#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
-
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
-
-#undef CONFIG_SYS_SKIP_DRAM_SCRUB
-
-/*
- * NAND Flash
- */
-#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
-#undef CONFIG_SYS_NAND1_BASE
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-/* nand timeout values */
-#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
-#define CONFIG_SYS_NAND_OTHER_TO 100
-#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
-#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
-
-/* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH 10
-#define NAND_TIMING_tCS 0
-#define NAND_TIMING_tWH 20
-#define NAND_TIMING_tWP 40
-
-#define NAND_TIMING_tRH 20
-#define NAND_TIMING_tRP 40
-
-#define NAND_TIMING_tR 11123
-#define NAND_TIMING_tWHR 100
-#define NAND_TIMING_tAR 10
-
-/* NAND debugging */
-#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
-#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
-#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
-
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 1
-
-#define CONFIG_SYS_NO_FLASH 1
-
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_OFFSET_REDUND 0x44000
-#define CONFIG_ENV_SIZE 0x4000
-
-#endif /* __CONFIG_H */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/* Hardware drivers */
extern unsigned int boot_flash_type;
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFE000000 boot low
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
+#endif
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
-#if (TEXT_BASE == 0xFF000000)
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
#define CONFIG_SYS_LOWBOOT 1
#endif
* Use SRAM until RAM will be available
*/
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 4096
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_DLVISION 1 /* on a Neo board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#define CONFIG_SKIP_LOWLEVEL_INIT 1
-#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* High Level Configuration Options
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
--- /dev/null
+/*
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_DOCKSTAR_H
+#define _CONFIG_DOCKSTAR_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nSeagate FreeAgent DockStar"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_MACH_DOCKSTAR /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT "DockStar> " /* Command Prompt */
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k */
+#define CONFIG_ENV_ADDR 0x60000
+#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount root; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x1100000 ${initrd}; " \
+ "bootm 0x800000 0x1100000"
+
+#define CONFIG_MTDPARTS "mtdparts=orion_nand:1m(uboot),-(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/uImage\0" \
+ "initrd=/boot/uInitrd\0" \
+ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_DOCKSTAR_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_RELOC_FIXUP_WORKS
-
/*
* Stuff still to be dealt with -
*/
#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
#define CONFIG_MPC8245 1
#define CONFIG_EXALION 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#if defined (CONFIG_MPC8240)
/* #warning ---------- eXalion with MPC8240 --------------- */
#elif defined (CONFIG_MPC8245)
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area
#define CONFIG_SYS_INIT_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (8 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "ea20 > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
#define CONFIG_MISC_INIT_R
/*--------------------------------------------------------------------------*/
-
+#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* sdram
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- PHYS_SDRAM_SIZE - 0x00400000 - \
+ CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
/* FLASH organization */
/* NOR-FLASH */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_FLASH_CFI_DRIVER 1
"nandboot=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=nand " \
";bootm $(kerneladdr)\0" \
- "uu=run update_uboot\0" \
- "ur=run update_root;run nk\0" \
- "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
- "boot=local " \
- ";echo $(bootargs)" \
- ";dhcp uImage_cpux9k2;bootm\0" \
- "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
- "boot=nand " \
- ";echo $(bootargs)" \
- ";dhcp uImage_cpux9k2;bootm\0" \
" "
/*--------------------------------------------------------------------------*/
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_MK_edb9301
+#ifdef CONFIG_edb9301
#define CONFIG_EDB9301
-#elif defined(CONFIG_MK_edb9302)
+#elif defined(CONFIG_edb9302)
#define CONFIG_EDB9302
-#elif defined(CONFIG_MK_edb9302a)
+#elif defined(CONFIG_edb9302a)
#define CONFIG_EDB9302A
-#elif defined(CONFIG_MK_edb9307)
+#elif defined(CONFIG_edb9307)
#define CONFIG_EDB9307
-#elif defined(CONFIG_MK_edb9307a)
+#elif defined(CONFIG_edb9307a)
#define CONFIG_EDB9307A
-#elif defined(CONFIG_MK_edb9312)
+#elif defined(CONFIG_edb9312)
#define CONFIG_EDB9312
-#elif defined(CONFIG_MK_edb9315)
+#elif defined(CONFIG_edb9315)
#define CONFIG_EDB9315
-#elif defined(CONFIG_MK_edb9315a)
+#elif defined(CONFIG_edb9315a)
#define CONFIG_EDB9315A
#else
#error "no board defined"
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
/* Run-time memory allocatons */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_STACKSIZE (128 * 1024)
#if defined(CONFIG_USE_IRQ)
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Other required minimal configurations
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
#define CONFIG_SYS_MAXARGS 16
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* _CONFIG_EDMINIV2_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_EP8260_H2 1
/* #undef CONFIG_SYS_EP8260_H2 */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#endif
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* JFFS2 partitions
*
*/
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
/* 256MB SDRAM / 64MB FLASH */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_FLASH_CFI
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFE000000 boot low
+ * 0x00100000 boot from RAM (for testing only) does not work
+ */
+#ifdef CONFIG_galaxy5200_LOWBOOT
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
+#endif
/*
* Serial console configuration
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-#if (TEXT_BASE == 0xFE000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
#define CONFIG_SYS_LOWBOOT 1
#endif
/* RAMBOOT will be defined automatically in memory section */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
/* End of used area in SPRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
/* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
* we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem.
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT 1
/*
* High Level Configuration Options
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
/*
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/*
* Include common defines/options for all AMCC eval boards
*/
*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
- - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
/*
* Ethernet configuration uses on board SMC91C111
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
/*
* Ethernet configuration uses on board SMC91C111, however if a mezzanine
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
/*
* Ethernet configuration
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
/*
* Ethernet configuration
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_SIZE (8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE))
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
/*
* Ethernet configuration
#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_GURUPLUG /* Machine type */
-
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-
-/*
- * CLKs configurations
- */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
-/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
/*
- * NAND configuration
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
*/
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-#endif
+#include "mv-common.h"
/*
* Environment variables configurations
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
+#define CONFIG_ENV_ADDR 0x60000
+#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Default environment variables
"x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-/*
- * Other required configurations
- */
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
-#define CONFIG_SYS_MEMTEST_END 0x1fffffff /*(_512M -1) */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_CMD_MII
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
+ * SATA Driver configuration
*/
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
#define CONFIG_SYS_ALT_MEMTEST
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/* Enable debug prints */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#define CONFIG_SYS_SBC_BOOT_LOW 1
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
ORxG_SCY_11_CLK |\
ORxG_EHTR)
#endif /* CONFIG_SYS_IO_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
#define __INCLUDED_H2_P2_DBH_BOARD_H
-#include <asm/arch/sizes.h>
+#include <asm/sizes.h>
/*
* The Debug board is designed to function with the P2 Sample, H2
--- /dev/null
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_SYS_USE_NAND 1
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_HAWK
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xc1180000
+#endif
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
+#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\
+ GENERATED_GBL_DATA_SIZE)
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Network & Ethernet Configuration
+ */
+#define CONFIG_EMAC_MDIO_PHY_NUM 0x7
+#if !defined(CONFIG_NAND_SPL)
+#define CONFIG_DRIVER_TI_EMAC
+#endif
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+
+/*
+ * Nand Flash
+ */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_CLE_MASK 0x10
+#define CONFIG_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CFG_DAVINCI_STD_NAND_LAYOUT
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
+#define NAND_MAX_CHIPS 1
+/* Block 0--not used by bootcode */
+#define CONFIG_ENV_OFFSET 0x0
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+#endif /* CONFIG_SYS_USE_NAND */
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS \
+ "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
+ "4M ip=static"
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_4xx 1
#define CONFIG_HOSTNAME hcu4
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
+
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* ... with on-chip memory here (4KBytes) */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
CONFIG_SYS_POST_ETHER | \
CONFIG_SYS_POST_SPR)
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
#undef CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_HOSTNAME hcu5
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
+
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#define CONFIG_SYS_BOOT_BASE_ADDR 0xfff00000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
CONFIG_SYS_POST_ETHER | \
CONFIG_SYS_POST_SPR)
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_HMI1001 1 /* HMI1001 board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
/* Display addresses */
/*---------------------------------------------------------------------*/
+#define CONFIG_PDSP188x
#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
#define CONFIG_HYMOD 1 /* ...on a Hymod board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FPGA_BASE 0x80000000
/*
* unfortunately, CONFIG_SYS_MONITOR_LEN must include the
#define FPGA_MAIN_IRQ SIU_INT_IRQ2
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* JFFS2 partitions
*
*/
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
- lib/zlib.o (.text .text.*); \
- board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 8)
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_END - 4)
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR */
+#define CONFIG_OMAP3_NUMONYX_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+ "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR */
+#define CONFIG_OMAP3_NUMONYX_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* nfs */
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+ "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/* malloc() len */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/* memtest start address */
#define CONFIG_SYS_MEMTEST_START 0xA0000000
#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
-/* additions for new relocation code, must added to all boards */
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
+/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#endif /* __IMX27LITE_COMMON_CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#ifdef CONFIG_IMX31_PHYCORE_EET
#define BOARD_LATE_INIT
-#define CONFIG_MX31_GPIO 1
+#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_INKA4X0 1 /* INKA4x0 board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFE00000 boot low
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
+#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-#if (TEXT_BASE == 0xFFE00000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
#ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* for timer/console/ethernet */
+#define CONFIG_SYS_TEXT_BASE 0x0
+
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* JFFS2 partitions
*
*/
#define CONFIG_SYS_PSSR_VAL 0x37
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*
#define CONFIG_SYS_MCIO0_VAL 0x00000000
#define CONFIG_SYS_MCIO1_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
#define CSB226_USER_LED0 0x00000008
#define CSB226_USER_LED1 0x00000010
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* PL010 Configuration
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
* Initial RAM & stack pointer (placed in OCM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_IO 1 /* on a Io board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME io
+#define CONFIG_IDENT_STRING " io 0.04"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
+#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0xa382a880
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB1CR 0x7f318000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_EBC_PB2AP 0x02025080
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
+
+#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
+#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
+#define CONFIG_SYS_EBC_PB3AP 0xa2015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_IOCON 1 /* on a IoCon board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME iocon
+#define CONFIG_IDENT_STRING " iocon 0.03"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(int pin);
+void fpga_gpio_clear(int pin);
+int fpga_gpio_get(int pin);
+#endif
+
+#define I2C_ACTIVE { }
+#define I2C_TRISTATE { }
+#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
+#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
+ else fpga_gpio_clear(0x0040)
+#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
+ else fpga_gpio_clear(0x0020)
+#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0xa382a880
+#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP 0x92015480
+#define CONFIG_SYS_EBC_PB1CR 0xFB858000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_EBC_PB2AP 0x02825080
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
+#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE 0x7f200000
+#define CONFIG_SYS_EBC_PB3AP 0x02025080
+#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET 0xffef
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffff
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+#endif /* __CONFIG_H */
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf532-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#define CONFIG_IPEK01 /* Motherboard is ipek01 */
+#define CONFIG_SYS_TEXT_BASE 0xfc000000
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
/* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
--- /dev/null
+/*
+ * Copyright 2010 (C)
+ * Kristoffer Ericson <kristoffer.ericson@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110 1 /* This is an SA110 CPU */
+#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_SYS_TEXT_BASE 0xC1F00000
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+#undef CONFIG_USE_IRQ
+
+/* Console setting */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SA1100_SERIAL 1
+#define CONFIG_SERIAL3 1 /* we use serial 3 */
+#define CONFIG_BAUDRATE 19200
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
+#define CONFIG_BOOTCOMMAND "run boot_kernel"
+#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
+#define CONFIG_SYS_LOAD_ADDR 0xc0000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "HP Jornada# "
+#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
+#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
+#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_ERASE_TOUT (4096)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (4096)
+#define CONFIG_SYS_FLASH_INCREMENT 0x02000000
+#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 260
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_MONITOR_LEN 0x00040000
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x00040000
+#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_SIZE 0x00040000
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ Monitor - 0x00000000 - 0x00040000 (256kb)
+ Environment - 0x00040000 - 0x00080000 (256kb)
+ Kernel - 0x00080000 - 0x00380000 (3mb)
+ Rootfs - 0x00380000 - 0x........ (rest)
+*/
+
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_INIT_SP_ADDR 0x0
+#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=jornada7xx-0"
+#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
+ "3m(kernel),-(user);"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "flash_kernel=protect off all; " \
+ "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \
+ "flash_uboot=protect off all; " \
+ "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \
+ "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
+#endif /* __CONFIG_H */
#define CONFIG_MPC5200 1 /* especially an MPC5200 */
#define CONFIG_JUPITER 1 /* ... on Jupiter board */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_BOARD_EARLY_INIT_F 1
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-#define CONFIG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
/*
* Enable this board for more than 2GB of SDRAM
*/
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT /* undef this for direct boot from */
- /* NOR flash without preloader */
#define CONFIG_SYS_LONGHELP
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (roundup(CONFIG_ENV_SIZE,4096) + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/*
+ * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x00400000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
+/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */
/*
* How to get access to the slot ID. Put this here to make it easy
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* If the data cache is being used for the primordial stack and global
CONFIG_SYS_POST_UART)
/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_BR3_PRELIM (0x30000401)
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SCC3_ENET
#define CONFIG_ETHPRIME "SCC"
#define CONFIG_HAS_ETH0
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Other required minimal configurations
#undef CONFIG_JFFS2_CMDLINE
#endif
-/* additions for new relocation code, must added to all boards */
+/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \
- CONFIG_SYS_GBL_DATA_SIZE)
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
+/* Do early setups now in board_init_f() */
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* _CONFIG_KM_ARM_H */
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
#define CONFIG_SYS_PIGGY_SIZE 128
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define BOOTFLASH_START F0000000
#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
#define CONFIG_KMSUPX4 1 /* ...on a kmsupx4 board */
#define CONFIG_HOSTNAME kmsupx4
+#define CONFIG_SYS_TEXT_BASE 0xf0000000
+
/* include common defines/options for all Keymile 8xx boards */
#include "km8xx.h"
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333
+#ifdef CONFIG_KORAT_PERMANENT
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xF7F60000
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
#undef CONFIG_SYS_INIT_RAM_DCACHE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*
} \
}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8245 1
#define CONFIG_KVME080 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x7C000000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#ifndef __CONFIG_H
#define __CONFIG_H
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ *
+ * Standard configuration - all models
+ * 0xFFF00000 boot from flash
+ *
+ * Test configuration (boot from RAM using uloader.o)
+ * LinkStation HD-HLAN and KuroBox Standard
+ * 0x03F00000 boot from RAM
+ * LinkStation HD-HGLAN and KuroBox HG
+ * 0x07F00000 boot from RAM
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+
#if 0
#define DEBUG
#endif
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
#define CONFIG_SYS_FLASH_SIZE 0x00400000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
#define CONFIG_SYS_EUMB_ADDR 0x80000000
#endif
/*-----------------------------------------------------------------------
- * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build
+ * Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build
*
* RAM based builds are for testing purposes. A Linux module, uloader.o,
* exists to load U-Boot and pass control to it
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*----------------------------------------------------------------------
* Serial configuration
*/
#define CONFIG_DOS_PARTITION
-/*-----------------------------------------------------------------------
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Logotronic DL board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/logodl.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
- /* for timer/console/ethernet */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 19200
-#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_RUN
-
-
-#define CONFIG_BOOTDELAY 3
-/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
-#define CONFIG_BOOTARGS "console=ttyS0,19200"
-#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.1.56
-#define CONFIG_SERVERIP 192.168.1.2
-#define CONFIG_BOOTCOMMAND "bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG 1
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CONFIG_SYS_MALLOC_LEN (256*1024)
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x08000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0800ffff /* 64 KiB */
-
-#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */
-
-#define CONFIG_SYS_HZ 1000
- /* RS: the oscillator is actually 3680130?? */
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
- /* 0101000001 */
- /* ^^^^^ Memory Speed 99.53 MHz */
- /* ^^ Run Mode Speed = 2x Mem Speed */
- /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * SMSC91C111 Network Card
- */
-#if 0
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
-#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-#undef CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
-#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
-#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-
-/*
- * GPIO settings
- *
- * GP?? == FOOBAR is 0/1
- */
-
-#define _BIT0 0x00000001
-#define _BIT1 0x00000002
-#define _BIT2 0x00000004
-#define _BIT3 0x00000008
-
-#define _BIT4 0x00000010
-#define _BIT5 0x00000020
-#define _BIT6 0x00000040
-#define _BIT7 0x00000080
-
-#define _BIT8 0x00000100
-#define _BIT9 0x00000200
-#define _BIT10 0x00000400
-#define _BIT11 0x00000800
-
-#define _BIT12 0x00001000
-#define _BIT13 0x00002000
-#define _BIT14 0x00004000
-#define _BIT15 0x00008000
-
-#define _BIT16 0x00010000
-#define _BIT17 0x00020000
-#define _BIT18 0x00040000
-#define _BIT19 0x00080000
-
-#define _BIT20 0x00100000
-#define _BIT21 0x00200000
-#define _BIT22 0x00400000
-#define _BIT23 0x00800000
-
-#define _BIT24 0x01000000
-#define _BIT25 0x02000000
-#define _BIT26 0x04000000
-#define _BIT27 0x08000000
-
-#define _BIT28 0x10000000
-#define _BIT29 0x20000000
-#define _BIT30 0x40000000
-#define _BIT31 0x80000000
-
-
-#define CONFIG_SYS_LED_A_BIT (_BIT18)
-#define CONFIG_SYS_LED_A_SR GPSR0
-#define CONFIG_SYS_LED_A_CR GPCR0
-
-#define CONFIG_SYS_LED_B_BIT (_BIT16)
-#define CONFIG_SYS_LED_B_SR GPSR1
-#define CONFIG_SYS_LED_B_CR GPCR1
-
-
-/* LED A: off, LED B: off */
-#define CONFIG_SYS_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
-#define CONFIG_SYS_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CONFIG_SYS_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
-
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-
-#define CONFIG_SYS_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
-#define CONFIG_SYS_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
-#define CONFIG_SYS_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
-
-#define CONFIG_SYS_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
-#define CONFIG_SYS_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
- _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
-#define CONFIG_SYS_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
- _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
-#define CONFIG_SYS_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CONFIG_SYS_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
- _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
-#define CONFIG_SYS_GAFR2_U_VAL (_BIT1)
-
-#define CONFIG_SYS_PSSR_VAL (0x20)
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x123c2980
-#define CONFIG_SYS_MSC1_VAL 0x123c2661
-#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
-
-
-/* no sdram/pcmcia here */
-#define CONFIG_SYS_MDCNFG_VAL 0x00000000
-#define CONFIG_SYS_MDREFR_VAL 0x00000000
-#define CONFIG_SYS_MDREFR_VAL_100 0x00000000
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-
-/* only SRAM */
-#define SXCNFG_SETTINGS 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00004715
-#define CONFIG_SYS_MCIO1_VAL 0x00004715
-
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* FIXME */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-#endif /* __CONFIG_H */
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* High Level Configuration Options
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_INITRD_TAG
#define CONFIG_MMC 1
/* we use this ethernet chip */
-#define CONFIG_ENC28J60
+#define CONFIG_ENC28J60_LPC2292
#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* select serial console configuration
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* select serial console configuration
#define CONFIG_440 1
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END (8 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_MMC
#define BOARD_LATE_INIT 1
#define CONFIG_DOS_PARTITION
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
#define FPGA_REGS_BASE_PHYSICAL 0x08000000
/*
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
#define CONFIG_SYS_MDREFR_VAL 0x00018018
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
#define CONFIG_LWMON 1 /* ...on a LWMON board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/* Default Ethernet MAC address */
#define CONFIG_ETHADDR 00:11:B0:00:00:00
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/* List of I2C addresses to be verified by POST */
#ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ }
#else /* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR+0, \
- CONFIG_SYS_I2C_EEPROM_ADDR+1, \
- CONFIG_SYS_I2C_EEPROM_ADDR+2, \
- CONFIG_SYS_I2C_EEPROM_ADDR+3, \
- CONFIG_SYS_I2C_EEPROM_ADDR+4, \
- CONFIG_SYS_I2C_EEPROM_ADDR+5, \
- CONFIG_SYS_I2C_EEPROM_ADDR+6, \
- CONFIG_SYS_I2C_EEPROM_ADDR+7, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+0, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+1, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+2, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+3, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+4, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+5, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+6, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+7, \
+ }
#endif /* CONFIG_USE_FRAM */
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAR 0x00000088
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* MA 02111-1307 USA
*/
-/************************************************************************
+/*
* lwmon5.h - configuration for lwmon5 board
- ***********************************************************************/
+ */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*-----------------------------------------------------------------------
+/*
+ * Liebherr extra version info
+ */
+#define CONFIG_IDENT_STRING " - v2.0"
+
+/*
* High Level Configuration Options
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#endif
+
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_BOARD_RESET 1 /* Call board_reset */
+#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
+#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
+#define CONFIG_MISC_INIT_R /* Call misc_init_r */
+#define CONFIG_BOARD_RESET /* Call board_reset */
-/*-----------------------------------------------------------------------
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_LIME_BASE_0 0xc0000000
-#define CONFIG_SYS_LIME_BASE_1 0xc1000000
-#define CONFIG_SYS_LIME_BASE_2 0xc2000000
-#define CONFIG_SYS_LIME_BASE_3 0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
+#define CONFIG_SYS_LIME_BASE_0 0xc0000000
+#define CONFIG_SYS_LIME_BASE_1 0xc1000000
+#define CONFIG_SYS_LIME_BASE_2 0xc2000000
+#define CONFIG_SYS_LIME_BASE_3 0xc3000000
+#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
+#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
/*
+ * Initial RAM & stack pointer
+ *
* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
* the POST_WORD from OCM to a 440EPx register that preserves it's
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+/* unused GPT0 COMP reg */
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
- /* unused GPT0 COMP reg */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
#define CONFIG_SYS_OCM_SIZE (16 << 10)
+/* 440EPx errata CHIP 11: don't use last 4kbytes */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
/* Additional registers for watchdog timer post test */
-
#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
-/*-----------------------------------------------------------------------
+/*
* Serial Port
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-/*-----------------------------------------------------------------------
+/*
* Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+ */
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
-/*-----------------------------------------------------------------------
+/*
* FLASH related
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH0 0xFC000000
#define CONFIG_SYS_FLASH1 0xF8000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-/*-----------------------------------------------------------------------
+/*
* DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
+ */
+#define CONFIG_SYS_MBYTES_SDRAM 256
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
-#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
-#define CONFIG_DDR_ECC 1 /* enable ECC */
-#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_DDR_ECC /* enable ECC */
/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC_ON | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_OCM | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_SYSMON | \
- CONFIG_SYS_POST_WATCHDOG | \
- CONFIG_SYS_POST_DSP | \
- CONFIG_SYS_POST_BSPEC1 | \
- CONFIG_SYS_POST_BSPEC2 | \
- CONFIG_SYS_POST_BSPEC3 | \
- CONFIG_SYS_POST_BSPEC4 | \
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ECC | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_FPU | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_OCM | \
+ CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_SPR | \
+ CONFIG_SYS_POST_UART | \
+ CONFIG_SYS_POST_SYSMON | \
+ CONFIG_SYS_POST_WATCHDOG | \
+ CONFIG_SYS_POST_DSP | \
+ CONFIG_SYS_POST_BSPEC1 | \
+ CONFIG_SYS_POST_BSPEC2 | \
+ CONFIG_SYS_POST_BSPEC3 | \
+ CONFIG_SYS_POST_BSPEC4 | \
CONFIG_SYS_POST_BSPEC5)
-#define CONFIG_POST_WATCHDOG {\
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_POST_UART { \
+ "UART test", \
+ "uart", \
+ "This test verifies the UART operation.", \
+ POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
+ &uart_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_UART \
+ }
+
+#define CONFIG_POST_WATCHDOG { \
"Watchdog timer test", \
"watchdog", \
"This test checks the watchdog timer.", \
&lwmon5_watchdog_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_WATCHDOG \
+ CONFIG_SYS_POST_WATCHDOG \
}
-#define CONFIG_POST_BSPEC1 {\
+#define CONFIG_POST_BSPEC1 { \
"dsPIC init test", \
"dspic_init", \
"This test returns result of dsPIC READY test run earlier.", \
&dspic_init_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC1 \
+ CONFIG_SYS_POST_BSPEC1 \
}
-#define CONFIG_POST_BSPEC2 {\
+#define CONFIG_POST_BSPEC2 { \
"dsPIC test", \
"dspic", \
"This test gets result of dsPIC POST and dsPIC version.", \
&dspic_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC2 \
+ CONFIG_SYS_POST_BSPEC2 \
}
-#define CONFIG_POST_BSPEC3 {\
+#define CONFIG_POST_BSPEC3 { \
"FPGA test", \
"fpga", \
"This test checks FPGA registers and memory.", \
- POST_RAM | POST_ALWAYS, \
+ POST_RAM | POST_ALWAYS | POST_MANUAL, \
&fpga_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC3 \
+ CONFIG_SYS_POST_BSPEC3 \
}
-#define CONFIG_POST_BSPEC4 {\
+#define CONFIG_POST_BSPEC4 { \
"GDC test", \
"gdc", \
"This test checks GDC registers and memory.", \
- POST_RAM | POST_ALWAYS, \
+ POST_RAM | POST_ALWAYS | POST_MANUAL,\
&gdc_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC4 \
+ CONFIG_SYS_POST_BSPEC4 \
}
-#define CONFIG_POST_BSPEC5 {\
+#define CONFIG_POST_BSPEC5 { \
"SYSMON1 test", \
"sysmon1", \
"This test checks GPIO_62_EPX pin indicating power failure.", \
&sysmon1_post_test, \
NULL, \
NULL, \
- CONFIG_SYS_POST_BSPEC5 \
+ CONFIG_SYS_POST_BSPEC5 \
}
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-/*-----------------------------------------------------------------------
+/*
* I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
+#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
+#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
+#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
+
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
/* 64 byte page write mode using*/
/* last 6 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
+
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+ CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_2_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR }
-#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
-#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+
+#define CONFIG_FIT /* enable FIT image support */
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
-#if 0
-#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d sec...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
-#endif
#define CONFIG_PREBOOT "setenv bootdelay 15"
"cp.b 200000 FFF80000 80000\0" \
"upd=run load update\0" \
"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
- "source 200000\0" \
+ "autoscr 200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-/* USB */
-#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
+#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
+#define CONFIG_EHCI_DCACHE /* with dcache handling support */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#define CONFIG_USB_STORAGE
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_USB
#endif
-/*-----------------------------------------------------------------------
+/*
* Miscellaneous configurable options
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *----------------------------------------------------------------------*/
+ */
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
#define CONFIG_WD_PERIOD 40000 /* in usec */
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x03050200
+#define CONFIG_SYS_EBC_PB0AP 0x03000280
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
/* Memory Bank 1 (Lime) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x01004380
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000)
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x01004400
#define CONFIG_SYS_EBC_CFG 0xb8400000
-/*-----------------------------------------------------------------------
+/*
* Graphics (Fujitsu Lime)
- *----------------------------------------------------------------------*/
+ */
+/* SDRAM Clock frequency adjustment register */
+#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
+#if 1 /* 133MHz is not tested enough, use 100MHz for now */
/* Lime Clock frequency is to set 100MHz */
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
-#if 0
+#else
/* Lime Clock frequency for 133MHz */
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
#endif
-/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- and pixel flare on display when 133MHz was configured. According to
- SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+/* SDRAM Parameter register */
+#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
+/*
+ * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ * and pixel flare on display when 133MHz was configured. According to
+ * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
+ * Grade
+ */
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
#endif
-/*-----------------------------------------------------------------------
+/*
* GPIO Setup
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_PHY0_RST 22
#define CONFIG_SYS_GPIO_DSPIC_READY 51
+#define CONFIG_SYS_GPIO_CAN_ENABLE 53
+#define CONFIG_SYS_GPIO_LSB_ENABLE 54
#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
#define CONFIG_SYS_GPIO_HIGHSIDE 56
#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_WATCHDOG 63
-/*-----------------------------------------------------------------------
+/*
* PPC440 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
} \
}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* If the data cache is being used for the primordial stack and global
CONFIG_SYS_POST_UART)
/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
* (easy to change)
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_BOARD_EARLY_INIT_R
/* Partitions */
#define CONFIG_CMD_MII
#define CONFIG_CMD_SNTP
+/*
+ * 8-symbol LED display (can be accessed with 'display' command)
+ */
+#define CONFIG_PDSP188x
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
/*
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
"u-boot_addr_r=200000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(TEXT_BASE) " +${filesize};" \
- "erase " xstr(TEXT_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(TEXT_BASE) \
+ "update=protect off " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
+ "erase " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_TEXT_BASE) \
" ${filesize};" \
- "protect on " xstr(TEXT_BASE) " +${filesize}\0" \
+ "protect on " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
230400 }
-#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -\
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MCC200 1 /* ... on MCC200 board */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000 boot low (standard configuration)
+ * 0xFFF00000 boot high
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
#define CONFIG_MISC_INIT_R
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
#define CONFIG_CMD_USB
#undef CONFIG_CMD_NET
-
+#undef CONFIG_CMD_NFS
/*
* Autobooting
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
- "text_base=" MK_STR(TEXT_BASE) "\0" \
+ "text_base=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
"kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#if TEXT_BASE == CONFIG_SYS_FLASH_BASE
+#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LOWBOOT 1
#endif
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_4xx 1
#define CONFIG_HOSTNAME mcu25
+#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
+
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* ... with on-chip memory here (4KBytes) */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
CONFIG_SYS_POST_ETHER | \
CONFIG_SYS_POST_SPR)
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
#undef CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_CMD_ELF
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
-#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
#define CONFIG_ARCH_CPU_INIT
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#define CONFIG_MGCOGE 1
#define CONFIG_HOSTNAME mgcoge
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
/* include common defines/options for all Keymile boards */
CONFIG_SYS_FLASH_BASE_1, \
CONFIG_SYS_FLASH_BASE_2 }
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
#define CONFIG_HOSTNAME mgsuvd
+#define CONFIG_SYS_TEXT_BASE 0xf0000000
+
/* include common defines/options for all Keymile 8xx boards */
#include "km8xx.h"
/*
- * (C) Copyright 2007-2008 Michal Simek
+ * (C) Copyright 2007-2010 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
#include "../board/xilinx/microblaze-generic/xparameters.h"
-#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+/* MicroBlaze CPU */
+#define CONFIG_MICROBLAZE 1
#define MICROBLAZE_V5 1
/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
- #define CONFIG_XILINX_UARTLITE
- #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
- #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
- #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
- #define CONSOLE_ARG "console=console=ttyUL0,115200\0"
+# define CONFIG_XILINX_UARTLITE
+# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
+# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
+# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
+# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
- #define CONFIG_SYS_NS16550 1
- #define CONFIG_SYS_NS16550_SERIAL
- #define CONFIG_SYS_NS16550_REG_SIZE -4
- #define CONFIG_CONS_INDEX 1
- #define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
- #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
- #define CONFIG_BAUDRATE 115200
-
- /* The following table includes the supported baudrates */
- #define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
- #define CONSOLE_ARG "console=console=ttyS0,115200\0"
+# define CONFIG_SYS_NS16550 1
+# define CONFIG_SYS_NS16550_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE -4
+# define CONFIG_CONS_INDEX 1
+# define CONFIG_SYS_NS16550_COM1 \
+ (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
+# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
+# define CONFIG_BAUDRATE 115200
+
+/* The following table includes the supported baudrates */
+# define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+# define CONSOLE_ARG "console=console=ttyS0,115200\0"
#else
- #error Undefined uart
+# error Undefined uart
#endif
/* setting reset address */
-/*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/
+/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
/* ethernet */
#ifdef XILINX_EMACLITE_BASEADDR
- #define CONFIG_XILINX_EMACLITE 1
- #define CONFIG_SYS_ENET
+# define CONFIG_XILINX_EMACLITE 1
+# define CONFIG_SYS_ENET
#elif XILINX_LLTEMAC_BASEADDR
- #define CONFIG_XILINX_LL_TEMAC 1
- #define CONFIG_SYS_ENET
+# define CONFIG_XILINX_LL_TEMAC 1
+# define CONFIG_SYS_ENET
#endif
#undef ET_DEBUG
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
- #define CONFIG_SYS_GPIO_0 1
- #define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+# define CONFIG_SYS_GPIO_0 1
+# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
- #define CONFIG_SYS_INTC_0 1
- #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
- #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
+# define CONFIG_SYS_INTC_0 1
+# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
+# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
#endif
/* timer */
#ifdef XILINX_TIMER_BASEADDR
- #if (XILINX_TIMER_IRQ != -1)
- #define CONFIG_SYS_TIMER_0 1
- #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
- #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
- #define FREQUENCE XILINX_CLOCK_FREQ
- #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
- #endif
+# if (XILINX_TIMER_IRQ != -1)
+# define CONFIG_SYS_TIMER_0 1
+# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
+# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
+# define FREQUENCE XILINX_CLOCK_FREQ
+# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+# endif
#elif XILINX_CLOCK_FREQ
- #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
+# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
#else
- #error BAD CLOCK FREQ
+# error BAD CLOCK FREQ
#endif
/* FSL */
/* #define CONFIG_SYS_FSL_2 */
/*
* memory layout - Example
- * TEXT_BASE = 0x1200_0000;
+ * CONFIG_SYS_TEXT_BASE = 0x1200_0000;
* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
* CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
*
*
* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
* FREE
- * 0x1200_0000 TEXT_BASE
+ * 0x1200_0000 CONFIG_SYS_TEXT_BASE
* U-BOOT code
* 0x1202_0000
* FREE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
/* global pointer */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size of global data */
/* start of global data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
/* monitor code */
-#define SIZE 0x40000
-#define CONFIG_SYS_MONITOR_LEN (SIZE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define SIZE 0x40000
+#define CONFIG_SYS_MONITOR_LEN (SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MONITOR_BASE \
+ (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MONITOR_END \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN SIZE
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_BASE \
+ (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
/* stack */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
#define FLASH
#ifdef FLASH
- #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
- #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
- #define CONFIG_SYS_FLASH_CFI 1
- #define CONFIG_FLASH_CFI_DRIVER 1
- #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */
- #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
- #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
- #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
-
- #ifdef RAMENV
- #define CONFIG_ENV_IS_NOWHERE 1
- #define CONFIG_ENV_SIZE 0x1000
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
-
- #else /* !RAMENV */
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
- #define CONFIG_ENV_SIZE 0x20000
- #endif /* !RAMBOOT */
+# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
+# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
+# define CONFIG_SYS_FLASH_CFI 1
+# define CONFIG_FLASH_CFI_DRIVER 1
+/* ?empty sector */
+# define CONFIG_SYS_FLASH_EMPTY_INFO 1
+/* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* max number of sectors on one chip */
+# define CONFIG_SYS_MAX_FLASH_SECT 512
+/* hardware flash protection */
+# define CONFIG_SYS_FLASH_PROTECTION
+
+# ifdef RAMENV
+# define CONFIG_ENV_IS_NOWHERE 1
+# define CONFIG_ENV_SIZE 0x1000
+# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else /* !RAMENV */
+# define CONFIG_ENV_IS_IN_FLASH 1
+/* 128K(one sector) for env */
+# define CONFIG_ENV_SECT_SIZE 0x20000
+# define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+# define CONFIG_ENV_SIZE 0x20000
+# endif /* !RAMBOOT */
#else /* !FLASH */
- /* ENV in RAM */
- #define CONFIG_SYS_NO_FLASH 1
- #define CONFIG_ENV_IS_NOWHERE 1
- #define CONFIG_ENV_SIZE 0x1000
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
- #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
+/* ENV in RAM */
+# define CONFIG_SYS_NO_FLASH 1
+# define CONFIG_ENV_IS_NOWHERE 1
+# define CONFIG_ENV_SIZE 0x1000
+# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+/* hardware flash protection */
+# define CONFIG_SYS_FLASH_PROTECTION
#endif /* !FLASH */
/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
- #define CONFIG_SYSTEMACE
- /* #define DEBUG_SYSTEMACE */
- #define SYSTEMACE_CONFIG_FPGA
- #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
- #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
- #define CONFIG_DOS_PARTITION
+# define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+# define SYSTEMACE_CONFIG_FPGA
+# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+# define CONFIG_DOS_PARTITION
#endif
#if defined(XILINX_USE_ICACHE)
- #define CONFIG_ICACHE
+# define CONFIG_ICACHE
#else
- #undef CONFIG_ICACHE
+# undef CONFIG_ICACHE
#endif
#if defined(XILINX_USE_DCACHE)
- #define CONFIG_DCACHE
+# define CONFIG_DCACHE
#else
- #undef CONFIG_DCACHE
+# undef CONFIG_DCACHE
#endif
/*
#define CONFIG_CMD_ECHO
#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
- #define CONFIG_CMD_CACHE
+# define CONFIG_CMD_CACHE
#else
- #undef CONFIG_CMD_CACHE
+# undef CONFIG_CMD_CACHE
#endif
#ifndef CONFIG_SYS_ENET
- #undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NET
+# undef CONFIG_NET_MULTI
#else
- #define CONFIG_CMD_PING
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+# define CONFIG_NET_MULTI
#endif
#if defined(CONFIG_SYSTEMACE)
- #define CONFIG_CMD_EXT2
- #define CONFIG_CMD_FAT
+# define CONFIG_CMD_EXT2
+# define CONFIG_CMD_FAT
#endif
#if defined(FLASH)
- #define CONFIG_CMD_ECHO
- #define CONFIG_CMD_FLASH
- #define CONFIG_CMD_IMLS
- #define CONFIG_CMD_JFFS2
-
- #if !defined(RAMENV)
- #define CONFIG_CMD_SAVEENV
- #define CONFIG_CMD_SAVES
- #endif
+# define CONFIG_CMD_ECHO
+# define CONFIG_CMD_FLASH
+# define CONFIG_CMD_IMLS
+# define CONFIG_CMD_JFFS2
+
+# if !defined(RAMENV)
+# define CONFIG_CMD_SAVEENV
+# define CONFIG_CMD_SAVES
+# endif
#else
- #undef CONFIG_CMD_IMLS
- #undef CONFIG_CMD_FLASH
- #undef CONFIG_CMD_JFFS2
+# undef CONFIG_CMD_IMLS
+# undef CONFIG_CMD_FLASH
+# undef CONFIG_CMD_JFFS2
#endif
#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=ml401-0"
+#define MTDIDS_DEFAULT "nor0=flash-0"
/* default mtd partition table */
-#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
+#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
"256k(env),3m(kernel),1m(romfs),"\
"1m(cramfs),-(jffs2)"
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
-#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
+/* size of console buffer */
+#define CONFIG_SYS_CBSIZE 512
+ /* print buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 15
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
- "nor0=ml401-0\0"\
- "mtdparts=mtdparts=ml401-0:"\
+#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
+ "nor0=flash-0\0"\
+ "mtdparts=mtdparts=flash-0:"\
"256k(u-boot),256k(env),3m(kernel),"\
"1m(romfs),1m(cramfs),-(jffs2)\0"
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+# define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#endif /* __CONFIG_H */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_DOS_PARTITION 1
-
/*
* Command line configuration.
*/
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DTT
-
+#define CONFIG_CMD_REGINFO
/*
* Serial console configuration
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
/*
* Ethernet configuration
*/
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
"press \"<Esc><Esc>\" to stop\n", bootdelay
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
#define CONFIG_ETHADDR 00:50:C2:40:10:00
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
/*
* Default environment settings
*/
"serverip=192.168.1.1\0" \
"gatewayip=192.168.1.1\0" \
"console=ttyPSC0,115200\0" \
- "u-boot_addr=100000\0" \
- "kernel_addr=200000\0" \
- "fdt_addr=400000\0" \
- "ramdisk_addr=500000\0" \
+ "u-boot_addr=400000\0" \
+ "kernel_addr=400000\0" \
+ "fdt_addr=700000\0" \
+ "ramdisk_addr=800000\0" \
"multi_image_addr=800000\0" \
- "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
- "u-boot=/tftpboot/motionpro/u-boot.bin\0" \
- "bootfile=/tftpboot/motionpro/uImage\0" \
- "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
- "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "u-boot=motionpro/u-boot.bin\0" \
+ "bootfile=motionpro/uImage\0" \
+ "fdt_file=motionpro/motionpro.dtb\0" \
+ "ramdisk_file=motionpro/uRamdisk\0" \
"multi_image_file=kernel+initrd+dtb.img\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
- "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
+ "update=prot off fff00000 +${filesize};" \
+ "era fff00000 +${filesize}; " \
"cp.b ${u-boot_addr} fff00000 ${filesize};" \
- "prot on fff00000 fff3ffff\0" \
+ "prot on fff00000 +${filesize}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
*/
#define CONFIG_BOARD_EARLY_INIT_R 1
-
/*
* Low level configuration
*/
-
/*
* Clock configuration: SYS_XTALIN = 33MHz
*/
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
-
/*
* Set IPB speed to 100MHz
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
/*
* Memory map
*/
* Setting MBAR to otherwise will cause system hang when using SmartDMA such
* as network commands.
*/
-#define CONFIG_SYS_MBAR 0xf0000000
+#define CONFIG_SYS_MBAR 0xf0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/*
* (e.g., by the BDI). Otherwise we must specify the default boot-up value of
* MBAR, as given in the doccumentation.
*/
-#if TEXT_BASE == 0x00100000
+#if CONFIG_SYS_TEXT_BASE == 0x00100000
#define CONFIG_SYS_DEFAULT_MBAR 0xf0000000
-#else /* TEXT_BASE != 0x00100000 */
+#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
#define CONFIG_SYS_LOWBOOT 1
-#endif /* TEXT_BASE == 0x00100000 */
+#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
-
/*
* Chip selects configuration
*/
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x22222222
-
/*
* SDRAM configuration
*/
#define SDRAM_CONTROL 0x504f0000
#define SDRAM_MODE 0x00cd0000
-
/*
* Flash configuration
*/
#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_DOS_PARTITION
-
/*
* I2C configuration
*/
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
-
/*
* EEPROM configuration
*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
-
/*
* RTC configuration
*/
#define CONFIG_RTC_DS1337 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
/*
* Status LED configuration
*/
extern void __led_set(led_id_t id, int state);
#endif /* __ASSEMBLY__ */
-
/*
* Temperature sensor
*/
#define CONFIG_DTT_LM75 1
#define CONFIG_DTT_SENSORS { 0x49 }
-
/*
* Environment settings
*/
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004
-
/*
* Motion-PRO's CPLD revision control register
*/
#define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06)
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-
/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of area */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of area */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes of initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
/* video */
#undef CONFIG_VIDEO
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
+ * USB Support
+ */
+#define CONFIG_CMD_USB
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_EHCI /* Enable EHCI Support */
+#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
"mpc5121.nand:-(data)"
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
+
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
+
+#define CONFIG_CMD_FAT
+#define CONFIG_SUPPORT_VFAT
+
#endif /* defined(CONFIG_CMD_IDE) */
/*
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_HIGH_BATS /* High BATs supported */
#define CONFIG_ALTIVEC /* undef to disable */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
*/
#undef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */
-#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* u-boot code base */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* Peripheral Device section */
#define L2_INIT 0
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
#endif /* __CONFIG_H */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFC000000
+#endif
+
/*
* On-board devices
*
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 256
/* Memory */
#define CONFIG_SYS_SDRAM_BASE 0x8C000000
#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
/* NOR Flash */
/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER (8)
#define CONFIG_MPC8260 1
#define CONFIG_MUAS3001 1
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#define CONFIG_CPM2 1 /* Has a CPM2 */
/* Do boardspecific init */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_MUCMC52 1 /* MUCMC52 board */
#define CONFIG_HOSTNAME mucmc52
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+
#include "manroland/common.h"
#include "manroland/mpc5200-common.h"
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
#define CONFIG_MUNICES 1 /* ... on MUNICes board */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_ADDR (TEXT_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR_REDUND (TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_ENV_OVERWRITE 1
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file contains Marvell Board Specific common defincations.
+ * This file should be included in board config header file.
+ *
+ * It supports common definations for Kirkwood platform
+ * TBD: support for Orion5X platforms
+ */
+
+#ifndef _MV_COMMON_H
+#define _MV_COMMON_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+
+/* ====> Kirkwood Platform Common Definations */
+#if defined(CONFIG_KIRKWOOD)
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
+#define MV_UART_CONSOLE_BASE KW_UART0_BASE
+#define MV_SATA_BASE KW_SATA_BASE
+#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
+#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
+
+/* ====> ARMADA100 Platform Common Definations */
+#elif defined (CONFIG_ARMADA100)
+
+#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
+#define MV_MFPR_BASE ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
+ represents UART Unit Enable */
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+#else
+#error "Unsupported SoC Platform..."
+#endif
+
+/*
+ * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x00600000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_SPI_FLASH_MACRONIX 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
+/* size in bytes reserved for initial data */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#ifndef CONFIG_ARMADA100 /* will be removed latter */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#endif /* CONFIG_ARMADA100 */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
+#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/*
+ * DRAM Banks configuration, Custom config can be done in <board>.h
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS CONFIG_NR_DRAM_BANKS_MAX
+#else
+#if (CONFIG_NR_DRAM_BANKS > CONFIG_NR_DRAM_BANKS_MAX)
+#error CONFIG_NR_DRAM_BANKS Configurated more than available
+#endif
+#endif /* CONFIG_NR_DRAM_BANKS */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/*
+ * File system
+ */
+#ifndef CONFIG_ARMADA100 /* will be removed latter */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+#endif /* CONFIG_ARMADA100 */
+
+#endif /* _MV_COMMON_H */
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
-
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
- * CLKs configurations
- */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
-/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
-#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
- * Flash configuration
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
*/
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH 1
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
-#endif
+#include "mv-common.h"
+
+/* Unwanted stuffs from mv-common.h */
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_UBI
+#undef CONFIG_CMD_UBIFS
+#undef CONFIG_RBTREE
/*
* Environment variables configurations
"x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
-#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Marvell 88Exxxx Switch configurations
- */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init phy/swtich */
#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
+#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_MV88F6281GTW_GE_H */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
/*
* CS8900 Ethernet drivers
*/
#define CONFIG_BAUDRATE 115200
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ELF
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
#define CONFIG_BOOTFILE "mx1ads"
#undef _CONFIG_UART4 /* internal uart 4 */
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#undef CONFIG_CMD_PING
#undef CONFIG_CMD_SOURCE
-
/*
* Boot options. Setting delay to -1 stops autostart count down.
*/
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
#define CONFIG_STACKSIZE (120<<10) /* stack size */
#ifdef CONFIG_USE_IRQ
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif
/*
*/
#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
/* Bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_SKIP_RELOCATE_UBOOT
-#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
-#define CONFIG_MX51_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define BOARD_LATE_INIT
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
-#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/*
* MMC Configs
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot_addr=0xa0000000\0" \
- "uboot=u-boot.bin\0" \
- "loadaddr=0x90800000\0" \
- "bootargs_base=setenv bootargs console=tty "\
- "console=ttymxc0,${baudrate}\0"\
- "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_nfs; " \
- "tftpboot ${loadaddr} ${kernel}; bootm\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm\0" \
+ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
*/
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_NEO 1 /* on a Neo board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
#define __NETSTAL_COMMON_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/*
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT */
-
/*
* Partitions (mtdparts command line support)
*/
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define BOARD_LATE_INIT /* call board_late_init during start up */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Global data size rsvd */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000)
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
* data */
/*
#define CONFIG_MPC5200
#define CONFIG_O2DNT 1 /* ... on O2DNT board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* boot low for 16 MiB boards */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_CMD_PCI
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
#else
-# error "TEXT_BASE must be 0xFF000000"
+# error "CONFIG_SYS_TEXT_BASE must be 0xFF000000"
#endif
/*
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <asm/arch/sizes.h>
+#include <asm/sizes.h>
/*
There are 2 sets of general I/O -->
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
+#define CONFIG_OF_LIBFDT 1
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ 0x4000
+
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
+#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "Beagle"
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
+ "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
- /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_type;
#endif
-/* additions for new relocation code, must added to all boards */
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
#endif /* __CONFIG_H */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
- /* on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR boot_flash_env_addr
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_type;
#endif
+/*
+ * Support for relocation
+ */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Define the board revision statically
+ */
+/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
+
/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
+#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
/* commands to include */
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
+ "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
- /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
#endif /* (CONFIG_CMD_NET) */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
+ * (C) Copyright 2008-2010
+ * Gražvydas Ignotas <notasas@gmail.com>
*
* Configuration settings for the OMAP3 Pandora.
*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
- /* initial data */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
/*
* Hardware drivers
*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+
/*
* NS16550 Configuration
*/
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_CACHE /* Cache control */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\
+ "1920k(uboot),128k(uboot-env),"\
+ "10m(boot),-(rootfs)"
+#else
+#define MTDPARTS_DEFAULT
+#endif
/* Environment information */
#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0" \
"loadaddr=0x82000000\0" \
- "console=ttyS0,115200n8\0" \
- "videospec=omapfb:vram:2M,vram:4M\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "video=${videospec} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "video=${videospec} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
+ "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
+ "rw rootflags=bulk_read console=ttyS0,115200n8 " \
+ "vram=6272K omapfb.vram=0:3000K\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
+ "if mmc init && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
+ "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
+ "source ${loadaddr}; " \
+ "fi; " \
+ "ubi part boot && ubifsmount boot && ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
#define CONFIG_AUTO_COMPLETE 1
/*
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
- /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
-#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
*/
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*--------------------------------------------------------------------------*/
#define PHYS_FLASH_SIZE (128 << 20)
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
-/* timeout values are in milliseconds */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* SDRAM Memory Map
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
/*
* NAND FLASH usage ... default nCS1:
* - four 128KB sectors for X-Loader
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
- /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* Miscellaneous configurable options
*/
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
- /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
*/
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/* Vector Base */
#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_TWL6030_POWER 1
/* MMC */
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
+#define CONFIG_OMAP_HSMMC 1
#define CONFIG_SYS_MMC_SET_DEV 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "OMAP4 Panda"
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
/* Disabled commands */
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */
/*
- * Enabling relocation of u-boot by default
- * Relocation can be skipped if u-boot is copied to the TEXT_BASE
- */
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
-/*
* Environment setup
*/
#define CONFIG_BOOTDELAY 3
-/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttyS2,115200n8\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
- "mmcdev=1\0" \
+ "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc init ${mmcdev}; then " \
+ "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
*/
#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
/*
* Size of malloc() pool
- * Total Size Environment - 256k
+ * Total Size Environment - 128k
* Malloc - add 256k
*/
-#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/* Vector Base */
#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-
/* I2C */
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
/* TWL6030 */
#define CONFIG_TWL6030_POWER 1
+#define CONFIG_CMD_BAT 1
/* MMC */
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
+#define CONFIG_OMAP_HSMMC 1
#define CONFIG_SYS_MMC_SET_DEV 1
#define CONFIG_DOS_PARTITION 1
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET 0xE0000
+
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "SDP4430"
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_SAVEENV
/* Disabled commands */
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */
/*
- * Enabling relocation of u-boot by default
- * Relocation can be skipped if u-boot is copied to the TEXT_BASE
- */
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
-/*
* Environment setup
*/
#define CONFIG_BOOTDELAY 3
-/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttyS2,115200n8\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
- "mmcdev=1\0" \
+ "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc init ${mmcdev}; then " \
+ "if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
*/
#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#ifndef __INCLUDED_OMAP730_H
#define __INCLUDED_OMAP730_H
-#include <asm/arch/sizes.h>
+#include <asm/sizes.h>
/***************************************************************************
* OMAP730 Configuration Registers
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_OPENRD_BASE /* Machine type */
-
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-
-/*
- * CLKs configurations
- */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
* Commands configuration
*/
#define CONFIG_CMD_IDE
/*
- * NAND configuration
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
*/
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL 1
-#endif
+#include "mv-common.h"
/*
* Environment variables configurations
"mtdparts="MTDPARTS_DEFAULT"\0"
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
-#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
-
-/*
- * IDe Support on SATA port0
- */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_CMD_EXT2
-#define CONFIG_MVSATA_IDE
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT1
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR KW_SATA_BASE
-/* ATA bus 0 is Kirkwood port 0 on openrd */
-#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET
-/* ATA bus 1 is Kirkwood port 1 on openrd */
-#define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET
-#endif /* CONFIG_CMD_IDE */
-
-/*
- * File system
+ * SATA Driver configuration
*/
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_OPENRD_BASE_H */
#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_ARCH_CPU_INIT
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
*----------------------------------------------------------------------*/
#define CONFIG_P3Mx /* used for both board versions */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#if defined (CONFIG_P3M750)
#define CONFIG_750FX /* 750GL/GX/FX */
#define CONFIG_HIGH_BATS /* High BATs supported */
*/
#undef CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*-----------------------------------------------------------------------
#define L2_ENABLE (L2_INIT | L2CR_L2E)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
--- /dev/null
+/*
+ * Palm LifeDrive configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_TEXT_BASE 0x0
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x0x60000; " \
+ "fi; "
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_IDE
+#define CONFIG_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_LQ038J7DH53
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+
+#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SIZE 0x4000
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define __io
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x10
+#define CONFIG_SYS_ATA_REG_OFFSET 0x10
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x10
+
+#define CONFIG_SYS_ATA_STRIDE 1
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012
+#define CONFIG_SYS_GAFR1_L_VAL 0x69988056
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa
+#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x01040001
+#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
+#define CONFIG_SYS_GAFR3_U_VAL 0x00000009
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000000
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xc26b0000
+#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93
+#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff
+#define CONFIG_SYS_GPDR3_VAL 0x006ff38d
+#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee
+#define CONFIG_SYS_GPSR1_VAL 0x03affdae
+#define CONFIG_SYS_GPSR2_VAL 0x07554000
+#define CONFIG_SYS_GPSR3_VAL 0x01bc0785
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x01ffffff
+#define CONFIG_SYS_CCCR 0x02000210
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
+#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
+#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
+#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
+#define CONFIG_SYS_MDREFR_VAL 0x201fa031
+#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000003
+#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
+#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
+#define CONFIG_SYS_MCATT0_VAL 0x0001c391
+#define CONFIG_SYS_MCATT1_VAL 0x0001c391
+#define CONFIG_SYS_MCIO0_VAL 0x00014611
+#define CONFIG_SYS_MCIO1_VAL 0x0001c391
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Palm Tungsten|C configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA250 1 /* Intel PXA255 CPU */
+#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_TEXT_BASE 0x0
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x80000; " \
+ "fi; "
+#define CONFIG_BOOTARGS \
+ "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_ACX517AKN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */
+#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 64
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_ENV_ADDR 0x40000
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x00011004
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
+#define CONFIG_SYS_GAFR1_L_VAL 0x60888050
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
+#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+#define CONFIG_SYS_GPCR0_VAL 0x0
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPDR0_VAL 0xcfff8140
+#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
+#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
+#define CONFIG_SYS_GPSR0_VAL 0x00010f8f
+#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
+#define CONFIG_SYS_GPSR2_VAL 0x03fe0800
+
+#define CONFIG_SYS_PSSR_VAL PSSR_RDH
+
+/* Clock setup:
+ * CKEN[1] - PWM1 ; CKEN[6] - FFUART
+ * CKEN[12] - MMC ; CKEN[16] - LCD
+ */
+#define CONFIG_SYS_CKEN 0x00011042
+#define CONFIG_SYS_CCCR 0x00000161
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x800092c2
+#define CONFIG_SYS_MSC1_VAL 0x80008000
+#define CONFIG_SYS_MSC2_VAL 0x80008000
+#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
+#define CONFIG_SYS_MDREFR_VAL 0x00118018
+#define CONFIG_SYS_MDMRS_VAL 0x00220032
+#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00010504
+#define CONFIG_SYS_MCMEM1_VAL 0x00010504
+#define CONFIG_SYS_MCATT0_VAL 0x00010504
+#define CONFIG_SYS_MCATT1_VAL 0x00010504
+#define CONFIG_SYS_MCIO0_VAL 0x00010e04
+#define CONFIG_SYS_MCIO1_VAL 0x00010e04
+
+#endif /* __CONFIG_H */
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
/* FEC configuration and IDE */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFF000000 boot low
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*-----------------------------------------------------------------------------
Serial console configuration
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
-#if (TEXT_BASE == 0xFF000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
#define CONFIG_SYS_LOWBOOT 1
#endif
/* RAMBOOT will be defined automatically in memory section */
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
/* area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes */
/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
} \
}
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+++ /dev/null
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Workaround for layout bug on prototype board
- */
-#define PCU_E_WITH_SWAPPED_CS 1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
-#define CONFIG_MPC860T 1
-#define CONFIG_PCU_E 1 /* ...on a PCU E board */
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_SPI /* enable SPI driver */
-#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
-
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-/* Ethernet hardware configuration done using port pins */
-#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
-#else /* XXX */
-#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
-#endif /* XXX */
-
-/* Ethernet settings:
- * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CONFIG_SYS_ETH_MDDIS_VALUE 0
-#define CONFIG_SYS_ETH_CFG1_VALUE 1
-#define CONFIG_SYS_ETH_CFG2_VALUE 1
-#define CONFIG_SYS_ETH_CFG3_VALUE 1
-
-/* PUMA configuration */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
-#else /* XXX */
-#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
-#endif /* XXX */
-#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
-#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFE000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* this is an ugly hack needed because of the silly non-constant address map */
-#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
-
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#if 0
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
-#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_ENV_OFFSET 1024
-#define CONFIG_ENV_SIZE 1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
- * running in RAM.
- */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * External Arbitration max. priority (7),
- * Debug pins configuration '11',
- * Asynchronous external master enable.
- */
-/* => 0x70600200 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00004080 */
-#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
-#define CONFIG_SYS_PLPRCR \
- ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
- )
-
-#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD100 | \
- SCCR_DFALCD01)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- *
- * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
- *
- * Don't expect the "date" command to work without a 32kHz clock input!
- */
-/* 0x00C3 => 0x0003 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0x0000
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
-#else /* XXX */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
-#endif /* XXX */
-
-/*
- * used to re-map FLASH: restrict access enough but not too much to
- * meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else /* XXX */
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#endif /* XXX */
-
-/*
- * BR2/OR2: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
-#else /* XXX */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
-#endif /* XXX */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
-#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* XXX */
-#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#endif /* XXX */
-
-/*
- * BR3/OR3: CAN Controller
- * BR3: 0x10000401 OR3: 0xffff818a
- */
-#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
-#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
-#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#else /* XXX */
-#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#endif /* XXX */
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8530
- * - "load" mode (chip select on UPM B):
- * BR4: 0x101008c1 OR4: 0xffff8630
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
-#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
-
-#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
- BR_PS_16 | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
-#else /* XXX */
-#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
-#endif /* XXX */
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- * BR5: 0x10200401 OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#else /* XXX */
-#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- * BR6: 0x10600801 OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#else /* XXX */
-#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR7/OR7: PUMA: external Flash
- * BR7: 0x10a00801 OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
-#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
-#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MPTPR 0x0200
-
-/*
- * MAMR settings for SDRAM
- * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
- * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
- * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
- */
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
-
-#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
- MAMR_AMA_TYPE_1 | \
- MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | \
- MAMR_WLFA_1X | \
- MAMR_TLFA_8X )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+#define CONFIG_SYS_TEXT_BASE 0xF0000000
+
/* Used for silent command in environment */
#define CONFIG_SYS_DEVICE_NULLDEV
#define CONFIG_SILENT_CONSOLE
#define CONFIG_FDT_FIXUP_PARTITIONS
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_PF5200 1 /* ... on PF5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
#define CONFIG_CMD_PCI
-#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#endif
-#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT08 1
#endif
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#undef CONFIG_LCD
#undef CONFIG_MMC
#define BOARD_LATE_INIT 1
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#define CONFIG_BOOTDELAY 3
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
#define CONFIG_SYS_PSSR_VAL 0x20
-#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
+#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/*
* Memory settings
/* bits set in lowlevel_init.S */
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_AT91FAMILY
/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_INITRD_TAG 1
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
*/
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_AT91FAMILY
/* clocks */
#define CONFIG_SYS_MOR_VAL \
#define CONFIG_INITRD_TAG 1
#undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_USER_LOWLEVEL_INIT 1
/*
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0x73f00000
+#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_CMD_NAND 1
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#undef CONFIG_ALTIVEC
#define CONFIG_BUS_CLK 66000000
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
/*
* Monitor configuration
* CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x20000
* copied to top of RAM by the init code.
*
* CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
- * CONFIG_SYS_INIT_RAM_END - Size of Init RAM
- * CONFIG_SYS_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
+ * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
+ * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
*/
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
-#define CONFIG_SYS_INIT_RAM_END 0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
#define CONFIG_SYS_BOARD_ASM_INIT
-
-/*
- * Boot flags
- *
- * BOOTFLAG_COLD - Indicates a power-on boot
- * BOOTFLAG_WARM - Indicates a software reset
- */
-
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
-
-
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+
/*****************************************************************************
*
* These settings must match the way _your_ board is set up
#define CONFIG_SYS_PPMC_BOOT_LOW 1
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
ORxG_TRLX |\
ORxG_EHTR)
#endif /* CONFIG_SYS_LED_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
-#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* define the following to enable debug blinks. A debug blink function
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* PXA250 IDP memory map information
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
#define CONFIG_SYS_MDREFR_VAL 0x0085C017
#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
*/
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
-#define CONFIG_MX31_GPIO
+#define CONFIG_MXC_GPIO
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 100000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* FPGA */
+#define CONFIG_FPGA
#define CONFIG_QONG_FPGA 1
#define CONFIG_FPGA_BASE (CS1_BASE)
+#define CONFIG_FPGA_LATTICE
+#define CONFIG_FPGA_COUNT 1
#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_BMP_16BPP
#define CONFIG_DISPLAY_COM57H5M10XRC
+/* USB */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT 2
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
+#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#endif /* CONFIG_CMD_USB */
+
/*
* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
* initial TFTP transfer, should the user wish one, significantly.
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DATE
-#define BOARD_LATE_INIT
-/*
- * You can compile in a MAC address and your custom net settings by using
- * the following syntax.
- *
- * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx
- * #define CONFIG_SERVERIP <server ip>
- * #define CONFIG_IPADDR <board ip>
- * #define CONFIG_GATEWAYIP <gateway ip>
- * #define CONFIG_NETMASK <your netmask>
- */
+#define BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 5
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"uboot_addr=A0000000\0" \
- "kernel_addr=A00A0000\0" \
+ "kernel_addr=A00C0000\0" \
"ramdisk_addr=A0300000\0" \
"u-boot=qong/u-boot.bin\0" \
"kernel_addr_r=80800000\0" \
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
+ "nand0=gen_nand"
#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \
- "128k(env2),2432k(kernel),13m(ramdisk),-(user)"
+ "mtdparts=physmap-flash.0:" \
+ "512k(U-Boot),128k(env1),128k(env2)," \
+ "2304k(kernel),13m(ramdisk),-(user);" \
+ "gen_nand:" \
+ "128m(nand)"
-/* additions for new relocation code, must added to all boards */
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
+/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_FLASH_BASE 0xFFC00000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
/*
* For booting Linux, the board info and command line data
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
/* the environment is located before u-boot */
-#define CONFIG_ENV_ADDR (TEXT_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/
+#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* BCSRx
*
* Board Status and Control Registers
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
/* Address of u-boot image in Flash */
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
/* Flash board support */
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER (8)
#define CONFIG_RTL8169
*/
/* AX88796L Support(NE2000 base chip) */
-#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
#endif
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_RD6281A /* Machine type */
-
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-
-/*
- * CLKs configurations
- */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
-/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
/*
- * NAND configuration
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
*/
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL 1
-#endif
+#include "mv-common.h"
/*
* Environment variables configurations
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
-#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
#define CONFIG_PHY_BASE_ADR 0x0A
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */
#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
+ * SATA Driver configuration
*/
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_RD6281A_H */
#define CONFIG_460SX 1 /* ... PPC460 family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_SYS_TEXT_BASE 0xfffb0000
+
/*-----------------------------------------------------------------------
* Include common defines/options for all AMCC boards
*----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
#define CONFIG_RMU 1
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#else
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR ((TEXT_BASE) + 0x40000)
+#define CONFIG_ENV_ADDR ((CONFIG_SYS_TEXT_BASE) + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Used size for environment */
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* BCSRx
*
* Board Status and Control Registers
#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
+#define CONFIG_SYS_TEXT_BASE 0xff000000
+#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
+
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
ORxG_ACS_DIV4)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
* 1MB = 0x100000, 0x100000 = 1024 * 1024
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */
/* initial data */
/*
* select serial console configuration
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
+#define CONFIG_CRC16
+#define CONFIG_XYZMODEM
+
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#undef CONFIG_LOGBUFFER /* External logbuffer support */
#define CONFIG_SYS_SBC_BOOT_LOW 1
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
* The main FLASH is whichever is connected to *CS0.
*/
#define CONFIG_SYS_FLASH0_BASE 0x40000000
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
ORxG_EHTR)
#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define SPD_EEPROM_ADDRESS 0x50
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC8240 1
#define CONFIG_WRSBC8240 1
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Size in bytes reserved for initial data
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* NS16550 Configuration
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/* Enable debug prints */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#define CONFIG_SYS_SBC_BOOT_LOW 1
/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
ORxG_TRLX |\
ORxG_EHTR)
#endif /* CONFIG_SYS_LED_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define __CONFIG_H
/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_MK_PCI
-#define CONFIG_PCI
-#endif
-
-#ifdef CONFIG_MK_66
-#define PCI_66M
-#endif
-
-#ifdef CONFIG_MK_33
-#define PCI_33M
-#endif
-
-/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
* physically empty. The board will automatically (i.e w/o jumpers)
* clock down to 33MHz if you insert a 33MHz PCI card.
*/
-#ifdef PCI_33M
+#ifdef CONFIG_PCI_33M
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#else /* 66M */
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_33M
+#ifdef CONFIG_PCI_33M
#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#else /* 66M */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
/*
* Top level Makefile configuration choices
*/
-#ifdef CONFIG_MK_PCI
-#define CONFIG_PCI
+#ifdef CONFIG_PCI
#define CONFIG_PCI1
#endif
-#ifdef CONFIG_MK_66
+#ifdef CONFIG_66
#define CONFIG_SYS_CLK_DIV 1
#endif
-#ifdef CONFIG_MK_33
+#ifdef CONFIG_33
#define CONFIG_SYS_CLK_DIV 2
#endif
-#ifdef CONFIG_MK_PCIE
+#ifdef CONFIG_PCIE
#define CONFIG_PCIE1
#endif
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfffa0000
+#endif
+
#undef CONFIG_RIO
#ifdef CONFIG_PCI
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
- * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
+ * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
* flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
- * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
+ * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
* thing for MONITOR_LEN in both cases.
*/
-#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)
+#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
-#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
+#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
-#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
+#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#else
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=uRamdisk\0" \
/*
* Top level Makefile configuration choices
*/
-#ifdef CONFIG_MK_66
+#ifdef CONFIG_66
#define CONFIG_PCI_66
#endif
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
+#define CONFIG_SYS_TEXT_BASE 0xfffc0000
+
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if 0
/* XXX This doesn't work and I don't want to fix it */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#ifdef RUN_DIAG
#define CONFIG_SYS_DIAG_ADDR 0xff800000
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
#endif
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
/* Map the last 1M of flash where we're running from reset */
#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_4xx 1
#define CONFIG_405GP 1
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
/* Where the internal SRAM starts */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* Where the internal SRAM ends (only offset) */
-#define CONFIG_SYS_INIT_RAM_END 0x0F00
+#define CONFIG_SYS_INIT_RAM_SIZE 0x0F00
/*
| |
| 64 Bytes |
| |
- CONFIG_SYS_INIT_RAM_END ------> ------------ higher address
+ CONFIG_SYS_INIT_RAM_SIZE ------> ------------ higher address
(offset only)
*/
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 64
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Initial value of the stack pointern in internal SRAM */
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* ################################################################################### */
/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
#define CONFIG_SYS_EBC_CFG 0xb84ef000
-#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
+#undef CONFIG_SDRAM_BANK0 /* use private SDRAM initialization */
#undef CONFIG_SPD_EEPROM
/*
* Select serial console configuration
*/
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE
-
/*
* Boot options. Setting delay to -1 stops autostart count down.
* NOTE: Sending parameters to kernel depends on kernel version and
#define CONFIG_INITRD_TAG 1 /* send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
-
/*
* Malloc pool need to host env + 128 Kb reserve for other allocations.
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
#define CONFIG_STACKSIZE (120<<10) /* stack size */
#ifdef CONFIG_USE_IRQ
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
/*
- * Flash Controller settings
- */
-
-/*
- * Hardware drivers
- */
-
-
-/*
* Configuration for FLASH memory for the Synertronixx board
*/
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#endif
+
/*
* Include common defines/options for all AMCC eval boards
*/
/*
* Define this if you want support for video console with radeon 9200 pci card
- * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
+ * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
*/
#undef CONFIG_VIDEO
*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_FLASH_CFI
/* MEMORY */
#if defined(CONFIG_SH_32BIT)
-#define SH7785LCR_SDRAM_PHYS_BASE (0x48000000)
-#define SH7785LCR_SDRAM_BASE (0x88000000)
+/* 0x40000000 - 0x47FFFFFF does not use */
+#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
+#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
+#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
*/
#define CONFIG_INFERNO /* we are using the inferno bootldr */
#define CONFIG_SKIP_LOWLEVEL_INIT 1
-#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* High Level Configuration Options
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
-
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-
-/*
- * CLKs configurations
- */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
-/* auto boot */
-#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
-
-#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
-#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
-
/*
- * NAND configuration
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
*/
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL 1
-#endif
+#include "mv-common.h"
/*
* Environment variables configurations
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
-#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
-#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-
-/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */
/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#endif /* CONFIG_CMD_USB */
-
-/*
* File system
*/
#define CONFIG_CMD_EXT2
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
-#define CONFIG_SKIP_RELOCATE_UBOOT
-
#define CONFIG_PERIPORT_REMAP
#define CONFIG_PERIPORT_BASE 0x70000000
#define CONFIG_PERIPORT_SIZE 0x13
/* input clock of PLL: SMDK6400 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
-#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
/*
* Hardware drivers
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
/* input clock of PLL: SMDKC100 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
* 1MB = 0x100000, 0x100000 = 1024 * 1024
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */
/* initial data */
/*
* select serial console configuration
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
#define CONFIG_IDENT_STRING " for SMDKC100"
-#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
/*
* Ethernet Contoller driver
*/
#define CONFIG_MPC8544 1
#define CONFIG_SOCRATES 1
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC8220 1
#define CONFIG_SORCERY 1 /* Sorcery board */
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/*
* Serial console configuration
*/
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SPC1920 1 /* SPC1920 board */
#define CONFIG_MPC885 1 /* MPC885 CPU */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
#ifdef CONFIG_BZIP2
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
#define CONFIG_SYS_MALLOC_LEN (1024*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "u-boot> "
* High Level Configuration Options
* (easy to change)
*/
-#if defined(CONFIG_MK_spear300)
+#if defined(CONFIG_spear300)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR300 1
-#elif defined(CONFIG_MK_spear310)
+#elif defined(CONFIG_spear310)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR310 1
-#elif defined(CONFIG_MK_spear320)
+#elif defined(CONFIG_spear320)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR320 1
#endif
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_HWMON_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_HWMON_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
#endif
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
#define CONFIG_MPC8560 1
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
+#define CONFIG_SYS_TEXT_BASE 0x40F00000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/* Custom configuration */
/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#define CONFIG_SYS_DOC_BASE 0x80000000
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
#define CONFIG_HOSTNAME t3corp
/*
* Initial RAM & stack pointer (placed in OCM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
+#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
+#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
+ 0xbddf } /* set async read mode */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
"ramdisk_addr=fc200000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
+ "unlock=yes\0" \
""
/*
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
- EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_TAIHU 1 /* on a taihu board */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Processor Settings
*/
-#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
#define CONFIG_TNETV107X
#define CONFIG_TNETV107X_EVM
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_UBOOT_BASE TEXT_BASE
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_DISABLE_TCM
#define CONFIG_PERIPORT_REMAP
#define CONFIG_PERIPORT_BASE 0x2000000
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE
#define PHYS_SDRAM_1_SIZE 0x04000000
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_JFFS2_NAND
#define NAND_MAX_CHIPS 1
#define CONFIG_ENV_OFFSET 0x180000
-#define DEF_BOOTM ""
/*
* davinci_nand is a bit of a misnomer since this particular EMIF block is
#define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
/*
* Hardware drivers
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * top9000 with at91sam9xe256 or at91sam9xe512
+ *
+ * Initial Bootloader is in embedded flash.
+ * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
+ * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
+ * kernel and file system are either in NAND flash or on a micro SD card.
+ * NAND flash is optional.
+ * I2C EEPROM is never optional.
+ * SPI FRAM is optional.
+ * SPI ENC28J60 is optional.
+ * 16 or 32 bit wide SDRAM.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x20000000 /* start of SDRAM */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_ASKENV
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT "TOP9000> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz xtal */
+#define CONFIG_SYS_HZ 1000
+
+/* SoC */
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 based SoC */
+#define CONFIG_AT91SAM9XE
+
+/* Misc CPU related */
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_AT91RESET_EXTRST /* assert external reset */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART3 /* USART 3 is DBGU !!! */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+/* SD/MMC card */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
+#define CONFIG_CMD_MMC
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_SYS_PHY_ID 1
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 20
+
+/* real time clock */
+#define CONFIG_RTC_AT91SAM9_RTT
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_AT91SAM9XE)
+/*
+ * NOR flash - use embedded flash of SAM9XE256/512
+ * U-Boot will not fit into 128K !
+ * 2010.09 will not fit into 256K with all options enabled !
+ *
+ * Layout:
+ * 16kB 1st Bootloader
+ * Rest U-Boot
+ * the first sector (16kB) of EFLASH cannot be unprotected
+ * with u-boot commands
+ */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_FLASH_BASE 0x200000
+# define CONFIG_SYS_MAX_FLASH_SECT 32
+# define CONFIG_SYS_MAX_FLASH_BANKS 1
+# define CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */
+#endif
+
+/* SPI */
+#define CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SPI
+
+/* RAMTRON FRAM */
+#define CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */
+#define FRAM_SPI_BUS 0
+#define FRAM_CS_NUM 0
+#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */
+#define CONFIG_SPI_FRAM_RAMTRON
+#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20"
+
+/* Microchip ENC28J60 (second LAN) */
+#if defined(CONFIG_EVAL9000)
+# define CONFIG_ENC28J60
+# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */
+# define ENC_SPI_BUS 1
+# define ENC_CS_NUM 0
+# define ENC_SPI_CLOCK 1000000
+#endif /* CONFIG_EVAL9000 */
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x21e00000
+#define CONFIG_SYS_LOAD_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x01000000)
+/*
+ * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (0x00300000 + 0x4000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NAND flash: 256 MB (optional)
+ *
+ * Layout:
+ * 640kB: u-boot (includes space for spare sectors, handled by
+ * initial loader)
+ * 2MB: kernel
+ * rest: file system
+ */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CONFIG_CMD_NAND
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* I2C support must always be enabled */
+#define CONFIG_SOFT_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_I2C_MULTI_BUS
+#define I2C0_PORT AT91_PIO_PORTA
+#define SDA0_PIN 23
+#define SCL0_PIN 24
+#define I2C1_PORT AT91_PIO_PORTB
+#define SDA1_PIN 12
+#define SCL1_PIN 13
+#define I2C_SOFT_DECLARATIONS void iic_init(void);\
+ int iic_read(void);\
+ void iic_sda(int);\
+ void iic_scl(int);
+#define I2C_ACTIVE
+#define I2C_TRISTATE
+#define I2C_INIT iic_init()
+#define I2C_READ iic_read()
+#define I2C_SDA(bit) iic_sda(bit)
+#define I2C_SCL(bit) iic_scl(bit)
+#define I2C_DELAY udelay(3)
+/* EEPROM configuration */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */
+/* ENV is always in I2C-EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x1000
+#define CONFIG_ENV_SIZE 0x0f00
+/* VPD settings */
+#define CONFIG_SYS_I2C_FACT_ADDR 0x57
+#define CONFIG_SYS_FACT_OFFSET 0x1F00
+#define CONFIG_SYS_FACT_SIZE 0x0100
+/* later: #define CONFIG_MISC_INIT_R */
+/* define the next only if you want to allow users to enter VPD data */
+#define CONFIG_SYS_FACT_ENTRY
+#ifndef __ASSEMBLY__
+extern void read_factory_r(void);
+#endif
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * add filesystem commands if we have at least 1 storage
+ * media with filesystem
+ */
+#if defined(CONFIG_NAND_ATMEL) \
+ || defined(CONFIG_USB_ATMEL) \
+ || defined(CONFIG_MMC)
+# define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_EXT2
+/* later: #define CONFIG_CMD_JFFS2 */
+#endif
+
+/* add NET commands if we have at least 1 LAN */
+#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_MII
+/* is this really needed ? */
+# define CONFIG_RESET_PHY_R
+/* BOOTP options */
+# define CONFIG_BOOTP_BOOTFILESIZE
+# define CONFIG_BOOTP_BOOTPATH
+# define CONFIG_BOOTP_GATEWAY
+# define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/* linux in NAND flash */
+#define CONFIG_BOOTCOUNT_LIMIT 1
+#define CONFIG_BOOTCOMMAND \
+ "nand read 0x21000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "mtdparts=atmel_nand:" \
+ "640k(uboot)ro," \
+ "2M(linux)," \
+ "16M(root)," \
+ "-(rest) " \
+ "rw "\
+ "rootfstype=jffs2"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_STACKSIZE (32*1024)
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_MMC 1
#define BOARD_LATE_INIT 1
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
/* malloc() len */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Board has 2 32MB banks of DRAM but there is a bug when using
* both so only the first is configured
"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
"upd=run load update\0" \
-/* additions for new relocation code, must added to all boards */
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
+/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
#define CONFIG_UC100 1 /* ...on a UC100 module */
+#define CONFIG_SYS_TEXT_BASE 0x40700000
+
#define MPC8XX_FACT 4 /* Multiply by 4 */
#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define FEC_ENET
#define CONFIG_MII
#define CONFIG_UC101 1 /* UC101 board */
#define CONFIG_HOSTNAME uc101
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
+
#include "manroland/common.h"
#include "manroland/mpc5200-common.h"
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_UTX8245 1
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define DEBUG 1
#define CONFIG_IDENT_STRING " [UTX5] "
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
/* initial data */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_END 0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*--------------------------------------------------------------------
* NS16550 Configuration
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-
#endif /* __CONFIG_H */
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_V37 1 /* ...on a Marel V37 board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_LCD
#define CONFIG_SHARP_LQ084V1DG21
#undef CONFIG_LCD_LOGO
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_V38B 1 /* ...on V38B board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFF000000
+
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_STACKSIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
#define CONFIG_MPC8313 1
#define CONFIG_VE8313 1
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfe000000
+#endif
+
#define CONFIG_PCI 1
#define CONFIG_FSL_ELBC 1
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME ve8313
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Hardware drivers
#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
#define CONFIG_TQM8xxL 1
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
/* Map peripheral control registers on CS4 */
#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_MX51 /* in a mx51 */
+#define CONFIG_L2_OFF
+
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define BOARD_LATE_INIT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (2048 * 1024)
+
+/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX51_UART3
+#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_SPI
+#define CONFIG_HW_WATCHDOG
+
+ /*
+ * SPI Configs
+ * */
+#define CONFIG_FSL_SF
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Use gpio 4 pin 25 as chip select for SPI flash
+ * This corresponds to gpio 121
+ */
+#define CONFIG_SPI_FLASH_CS (1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+
+#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
+#define CONFIG_ENV_SIZE (4 * 1024)
+
+#define CONFIG_FSL_ENV_IN_SF
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* PMIC Controller */
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 0
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 2500000
+#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
+#define CONFIG_RTC_MC13783
+
+/*
+ * MMC Configs
+ */
+#define CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_CMD_DATE
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SPI
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x90800000\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "Vision II U-boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x90000000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > "
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE 0x90000000
+#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000
+
+#define CONFIG_SYS_INIT_RAM_SIZE (64 * 1024)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* 166 MHz DDR RAM */
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Framebuffer and LCD
+ */
+#define CONFIG_PREBOOT
+#define CONFIG_LCD
+#define CONFIG_VIDEO_MX5
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+
+#endif /* __CONFIG_H */
* esd vme8349 U-Boot configuration file
* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* reinhard.arlt@esd-electronics.de
/*
* Top level Makefile configuration choices
*/
-#ifdef CONFIG_MK_caddy2
+#ifdef CONFIG_CADDY2
#define VME_CADDY2
#endif
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000
+
#define CONFIG_MISC_INIT_R
#define CONFIG_PCI
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define PCI_66M
-#ifdef PCI_66M
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
+#ifdef CONFIG_PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
/*
* Size of malloc() pool and stack
*/
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_STACKSIZE (1 * 1024 * 1024)
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
-
-#undef BOARD_LATE_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ
-#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Environment settings
*/
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-#define CONFIG_ENV_OVERWRITE /* override default environment */
-
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
"fi; " \
- "bootm 0x40000;"
+ "if ide reset && fatload ide 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0x60000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_LZMA /* LZMA compression support */
/*
#undef CONFIG_LCD
#define CONFIG_CMD_IDE
-#ifdef CONFIG_ONENAND_U_BOOT
+#ifdef CONFIG_ONENAND
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_ONENAND
#else
#define CONFIG_NET_MULTI 1
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
-#define DM9000_IO (CONFIG_DM9000_BASE)
-#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_PXA_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#endif
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "$ "
#else
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "=> "
#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
-#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
/*
* Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
/*
* DRAM Map
*/
-#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+
+#ifdef CONFIG_RAM_256M
#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#endif
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
+#else
+#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
+#endif
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
+#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
/*
* NOR FLASH
*/
+#define CONFIG_SYS_MONITOR_BASE 0x0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x4000
+
#if defined(CONFIG_CMD_FLASH) /* NOR */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#ifdef CONFIG_RAM_256M
#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+#endif
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+#else
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/*
+ * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
+ * flash consists of 0x20000 bytes big sectors.
+ */
+#if (CONFIG_ENV_ADDR <= 0x18000)
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#else
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ONENAND_BASE 0x00000000
+
#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#endif
-#define CONFIG_SYS_MONITOR_BASE 0x000000
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
/*
* IDE
*/
#define __io
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
-#define CONFIG_SYS_ATA_REG_OFFSET 0x120
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
+#define CONFIG_SYS_ATA_REG_OFFSET 0x120
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
#define CONFIG_SYS_ATA_STRIDE 2
#endif
#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
#define CONFIG_SYS_MSC1_VAL 0x02ccf974
#define CONFIG_SYS_MSC2_VAL 0x00000000
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
+#else
+#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
+#endif
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
* LCD
*/
#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
+#define CONFIG_VOIPAC_LCD
#endif
/*
* USB
*/
-#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
- /* ...and on a SYCAMORE board */
+ /* ...or on a SYCAMORE board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*
* Include common defines/options for all AMCC eval boards
#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
+++ /dev/null
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PXA250 1 /* this is an PXA250 CPU */
-#define CONFIG_WEPEP250 1 /* config for wepep250 board */
-#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP /* undef saves memory */
-#define CONFIG_SYS_PROMPT "WEP> " /* prompt string */
-#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#undef CONFIG_INITRD_TAG /* do not send initrd params */
-#undef CONFIG_VFD /* do not send framebuffer setup */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE (120<<10) /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
-#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */
-#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */
-#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */
-#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */
-#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */
-#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x02000000
-
-/* Uncomment used SDRAM chip */
-#define WEP_SDRAM_K4S281633
-/*#define WEP_SDRAM_K4S561633*/
-
-
-/*
- * Configuration for FLASH memory
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
-#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
-#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
-#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/
-#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */
-#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */
-#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */
-
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
- is not so clear to me. In other words we can provide more informations
- to user, but this expects more complex flash handling we do not provide
- now.*/
-#undef CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE WEP_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x2000
-
-#undef CONFIG_ENV_OVERWRITE /* env is not writable now */
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR 0x40000
-
-#endif /* __CONFIG_H */
*/
#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
#define CONFIG_XAENIAX 1 /* on a xaeniax board */
+#define CONFIG_SYS_TEXT_BASE 0x0
#define BOARD_LATE_INIT 1
* used for the RAM copy of the uboot code
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Miscellaneous configurable options
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
*/
#define CONFIG_SYS_PSSR_VAL 0x00000030
-#define CONFIG_SYS_CKEN_VAL 0x00000080 /* */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CKEN 0x00000080 /* */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
/*
*/
#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
/*Mem Map*/
#define CONFIG_SYS_SDRAM_BASE 0x0
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS
/*Misc*/
#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */
/*Stack*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
- - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
*
*/
#define CONFIG_SYS_MALLOC_LEN (256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
* Clocks, power control and interrupts
*/
#define CONFIG_SYS_PSSR_VAL 0x00000030
-#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
-#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
+#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/* FIXME
*
#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
/* High Level Configuration Options */
#define CONFIG_XPEDITE1000 1
#define CONFIG_SYS_BOARD_NAME "XPedite1000"
+#define CONFIG_SYS_FORM_PMC 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/*
* DDR config
*/
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
* ff000000 - ffbfffff OS Use/Filesystem (12MB)
*/
-#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE)
+#define CONFIG_UBOOT_ENV_ADDR MK_STR(CONFIG_SYS_TEXT_BASE)
#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite1000\0" \
- "fdtfile=/home/user/xpedite1000.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
*/
/*
- * xpedite5170 board configuration file
+ * xpedite517x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
+#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
+#define CONFIG_SYS_TEXT_BASE 0xfff00000
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
+ CONFIG_SYS_I2C_DS4510_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA9553_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_PEX8518_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
{0xf7f00000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
/*
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_END 0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
/*
* PU = pulled high, PD = pulled low
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - PEX8518 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - VPX P1 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
BATL_PP_RW |\
BATL_CACHEINHIBIT |\
BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\
+#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
BATU_BL_1M |\
BATU_VS |\
BATU_VP)
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5170\0" \
- "fdtfile=/home/user/xpedite5170.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
*/
/*
- * xpedite5200 board configuration file
+ * xpedite520x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
+#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_RTC_ADDR}
/*
* Memory map
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xfbf40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/*
* Chip select configuration
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_END 0x4000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
-#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20
#define CONFIG_SYS_PCA953X_MONARCH 0x40
#define CONFIG_SYS_PCA953X_EREADY 0x80
#define CONFIG_SYS_PCA953X_P14_IO6 0x40
#define CONFIG_SYS_PCA953X_P14_IO7 0x80
+/* 12-bit ADC used to measure CPU diode */
+#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
+
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5200\0" \
- "fdtfile=/home/user/xpedite5200.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
*/
/*
- * xpedite5370 board configuration file
+ * xpedite537x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
+#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
+ CONFIG_SYS_I2C_DS4510_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_PEX8518_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/*
* Chip select configuration
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_END 0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5370\0" \
- "fdtfile=/home/user/xpedite5370.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
--- /dev/null
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite550x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_P2020 1
+#define CONFIG_XPEDITE550X 1
+#define CONFIG_SYS_BOARD_NAME "XPedite5500"
+#define CONFIG_SYS_FORM_PMC_XMC 1
+#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x54
+#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM75_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
+ * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
+ * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
+ CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000
+#define CONFIG_SYS_FLASH_BASE2 0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
+ {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_XACS | \
+ OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_8 | \
+ OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
+ OR_FCM_PGS | \
+ OR_FCM_CSCT | \
+ OR_FCM_CST | \
+ OR_FCM_CHT | \
+ OR_FCM_SCY_1 | \
+ OR_FCM_TRLX | \
+ OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CONFIG_FDT_FIXUP_PCI_IRQ 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C DS7505 temperature sensor */
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM75_ADDR 0x48
+
+/* I2C ADT7461 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * GPIO pin definitions, PU = pulled high, PD = pulled low
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
+#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
+#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1 - PEX8112 or XMC, depending on build option */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
+
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_ETHPRIME "eTSEC2"
+
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_PHY_ADDR 3
+#define TSEC3_PHYIDX 0
+#define CONFIG_HAS_ETH2
+
+/*
+ * USB
+ */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff Pri FDT (256KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff Sec FDT (256KB)
+ * f6f00000 - f7efffff Sec OS image (16MB)
+ * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_XSENGINE 1
-#define CONFIG_MMC 1
-#define CONFIG_DOS_PARTITION 1
-#define BOARD_LATE_INIT 1
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=xsengine-0"
-#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
-*/
-
-/* Environment settings */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-/* Hardware drivers */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE 0x04000300
-#define CONFIG_SMC_USE_32_BIT 1
-
-/* select serial console configuration */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.1.50
-#define CONFIG_SERVERIP 192.168.1.2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/* Stack sizes - The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/* GP set register */
-#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */
-#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
-
-/* GP clear register */
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-
-/* GP direction register */
-#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
-#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
-
-/* GP rising edge detect register */
-#define CONFIG_SYS_GRER0_VAL 0x00000000
-#define CONFIG_SYS_GRER1_VAL 0x00000000
-#define CONFIG_SYS_GRER2_VAL 0x00000000
-
-/* GP falling edge detect register */
-#define CONFIG_SYS_GFER0_VAL 0x00000000
-#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
-
-/* GP alternate function register */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */
-#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */
-#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
-
-#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */
-#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
-
-/* Memory settings */
-#define CONFIG_SYS_MSC0_VAL 0x25F425F0
-
-/* MDCNFG: SDRAM Configuration Register */
-#define CONFIG_SYS_MDCNFG_VAL 0x000009C9
-
-/* MDREFR: SDRAM Refresh Control Register */
-#define CONFIG_SYS_MDREFR_VAL 0x00018018
-
-/* MDMRS: Mode Register Set Configuration Register */
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-
-#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/*
* Include common defines/options for all AMCC eval boards
*/
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CONFIG_SYS_INIT_RAM_END (4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define EXTCLK_50 50000000
#define EXTCLK_83 83333333
+#define CONFIG_SYS_TEXT_BASE 0xfffb0000
+
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_SYS_TEMP_STACK_OCM 1
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
/*-----------------------------------------------------------------------
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EP 1 /* Specifc 405EP support*/
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
-#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
#define CONFIG_SYS_TIME_POST 5000
#define CONFIG_SYS_TIME_FACTORY_RESET 10000
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef BOARD_LATE_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
-#define CONFIG_SYS_GBL_DATA_SIZE 512
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_LZMA /* LZMA compression support */
/*
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
+
/*
* NOR FLASH
*/
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff
+#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL 0x06080400
#define CONFIG_SYS_GPSR1_VAL 0x007f0000
* (easy to change)
*/
#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_CPU_PXA320
#define CONFIG_ZYLONITE 1 /* Zylonite board */
/* #define CONFIG_LCD 1 */
#undef CONFIG_MMC
#define BOARD_LATE_INIT 1
-#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
/*
* NAND Flash
unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
+#ifndef DO_DEPS_ONLY
+
+#include <search.h>
+
+extern struct hsearch_data env_htab;
+
/* Function that returns a character from the environment */
unsigned char env_get_char (int);
/* Import from binary representation into hash table */
int env_import(const char *buf, int check);
+#endif
+
#endif /* _ENVIRONMENT_H_ */
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
-void do_reset (void);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
char *getenv (char *name);
int setenv (char *varname, char *varvalue);
extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
-extern int ext2fs_ls (char *dirname);
-extern int ext2fs_open (char *filename);
+extern int ext2fs_ls (const char *dirname);
+extern int ext2fs_open (const char *filename);
extern int ext2fs_read (char *buf, unsigned len);
extern int ext2fs_mount (unsigned part_length);
extern int ext2fs_close(void);
void do_fixup_by_compat_u32(void *fdt, const char *compat,
const char *prop, u32 val, int create);
int fdt_fixup_memory(void *blob, u64 start, u64 size);
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
void fdt_fixup_ethernet(void *fdt);
int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
const void *val, int len, int create);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
fpga_min_type, /* range check value */
fpga_xilinx, /* Xilinx Family) */
fpga_altera, /* unimplemented */
+ fpga_lattice, /* Lattice family */
fpga_undefined /* invalid range check value */
} fpga_type; /* end, typedef fpga_type */
extern char *fsl_fb_open(struct fb_info **info);
int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix);
+int platform_diu_init(unsigned int *xres, unsigned int *yres);
* entry that matches the given short name. If a matching entry is
* found, it's id is returned to the caller.
*/
-int get_table_entry_id (table_entry_t *table,
+int get_table_entry_id(const table_entry_t *table,
const char *table_name, const char *name);
/*
* get_table_entry_name() scans the translation table trying to find
* an entry that matches the given id. If a matching entry is found,
* its long name is returned to the caller.
*/
-char *get_table_entry_name (table_entry_t *table, char *msg, int id);
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
const char *genimg_get_os_name (uint8_t os);
const char *genimg_get_arch_name (uint8_t arch);
char **of_flat_tree, ulong *of_size);
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
-
+#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end,
ulong bootmap_base);
+#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
+#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base);
-#endif /* CONFIG_PPC || CONFIG_M68K */
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
#endif /* !USE_HOSTCC */
/*******************************************************************/
int iomux_doenv(const int, const char *);
void iomux_printdevs(const int);
-struct stdio_dev *search_device(int, char *);
+struct stdio_dev *search_device(int, const char *);
#endif /* _IO_MUX_H */
--- /dev/null
+/*
+ * Porting to U-Boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
+ *
+ * Lattice Semiconductor Corp. Copyright 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _VME_OPCODE_H
+#define _VME_OPCODE_H
+
+#define VME_VERSION_NUMBER "12.1"
+
+/* Maximum declarations. */
+
+#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */
+#define SCANMAX 64000L /* The maximum SDR/SIR burst. */
+
+/*
+ *
+ * Supported JTAG state transitions.
+ *
+ */
+
+#define RESET 0x00
+#define IDLE 0x01
+#define IRPAUSE 0x02
+#define DRPAUSE 0x03
+#define SHIFTIR 0x04
+#define SHIFTDR 0x05
+/* 11/15/05 Nguyen changed to support DRCAPTURE*/
+#define DRCAPTURE 0x06
+
+/*
+ * Flow control register bit definitions. A set bit indicates
+ * that the register currently exhibits the corresponding mode.
+ */
+
+#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */
+#define CASCADE 0x0002 /* Currently splitting large SDR. */
+#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */
+#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */
+#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */
+#define VERIFYUES 0x0200 /* Continue if fail is in effect. */
+
+/*
+ * DataType register bit definitions. A set bit indicates
+ * that the register currently holds the corresponding type of data.
+ */
+
+#define EXPRESS 0x0001 /* Simultaneous program and verify. */
+#define SIR_DATA 0x0002 /* SIR is the active SVF command. */
+#define SDR_DATA 0x0004 /* SDR is the active SVF command. */
+#define COMPRESS 0x0008 /* Data is compressed. */
+#define TDI_DATA 0x0010 /* TDI data is present. */
+#define TDO_DATA 0x0020 /* TDO data is present. */
+#define MASK_DATA 0x0040 /* MASK data is present. */
+#define HEAP_IN 0x0080 /* Data is from the heap. */
+#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */
+#define VARIABLE 0x0400 /* Data is from a declared variable. */
+#define CRC_DATA 0x0800 /* CRC data is pressent. */
+#define CMASK_DATA 0x1000 /* CMASK data is pressent. */
+#define RMASK_DATA 0x2000 /* RMASK data is pressent. */
+#define READ_DATA 0x4000 /* READ data is pressent. */
+#define DMASK_DATA 0x8000 /* DMASK data is pressent. */
+
+/*
+ *
+ * Pin opcodes.
+ *
+ */
+
+#define signalENABLE 0x1C /* ispENABLE pin. */
+#define signalTMS 0x1D /* TMS pin. */
+#define signalTCK 0x1E /* TCK pin. */
+#define signalTDI 0x1F /* TDI pin. */
+#define signalTRST 0x20 /* TRST pin. */
+
+/*
+ *
+ * Supported vendors.
+ *
+ */
+
+#define VENDOR 0x56
+#define LATTICE 0x01
+#define ALTERA 0x02
+#define XILINX 0x03
+
+/*
+ * Opcode definitions.
+ *
+ * Note: opcodes must be unique.
+ */
+
+#define ENDDATA 0x00 /* The end of the current SDR data stream. */
+#define RUNTEST 0x01 /* The duration to stay at the stable state. */
+#define ENDDR 0x02 /* The stable state after SDR. */
+#define ENDIR 0x03 /* The stable state after SIR. */
+#define ENDSTATE 0x04 /* The stable state after RUNTEST. */
+#define TRST 0x05 /* Assert the TRST pin. */
+#define HIR 0x06 /*
+ * The sum of the IR bits of the
+ * leading devices.
+ */
+#define TIR 0x07 /*
+ * The sum of the IR bits of the trailing
+ * devices.
+ */
+#define HDR 0x08 /* The number of leading devices. */
+#define TDR 0x09 /* The number of trailing devices. */
+#define ispEN 0x0A /* Assert the ispEN pin. */
+#define FREQUENCY 0x0B /*
+ * The maximum clock rate to run the JTAG state
+ * machine.
+ */
+#define STATE 0x10 /* Move to the next stable state. */
+#define SIR 0x11 /* The instruction stream follows. */
+#define SDR 0x12 /* The data stream follows. */
+#define TDI 0x13 /* The following data stream feeds into
+ the device. */
+#define TDO 0x14 /*
+ * The following data stream is compared against
+ * the device.
+ */
+#define MASK 0x15 /* The following data stream is used as mask. */
+#define XSDR 0x16 /*
+ * The following data stream is for simultaneous
+ * program and verify.
+ */
+#define XTDI 0x17 /* The following data stream is for shift in
+ * only. It must be stored for the next
+ * XSDR.
+ */
+#define XTDO 0x18 /*
+ * There is not data stream. The data stream
+ * was stored from the previous XTDI.
+ */
+#define MEM 0x19 /*
+ * The maximum memory needed to allocate in
+ * order hold one row of data.
+ */
+#define WAIT 0x1A /* The duration of delay to observe. */
+#define TCK 0x1B /* The number of TCK pulses. */
+#define SHR 0x23 /*
+ * Set the flow control register for
+ * right shift
+ */
+#define SHL 0x24 /*
+ * Set the flow control register for left shift.
+ */
+#define HEAP 0x32 /* The memory size needed to hold one loop. */
+#define REPEAT 0x33 /* The beginning of the loop. */
+#define LEFTPAREN 0x35 /* The beginning of data following the loop. */
+#define VAR 0x55 /* Plac holder for loop data. */
+#define SEC 0x1C /*
+ * The delay time in seconds that must be
+ * observed.
+ */
+#define SMASK 0x1D /* The mask for TDI data. */
+#define MAX_WAIT 0x1E /* The absolute maximum wait time. */
+#define ON 0x1F /* Assert the targeted pin. */
+#define OFF 0x20 /* Dis-assert the targeted pin. */
+#define SETFLOW 0x30 /* Change the flow control register. */
+#define RESETFLOW 0x31 /* Clear the flow control register. */
+
+#define CRC 0x47 /*
+ * The following data stream is used for CRC
+ * calculation.
+ */
+#define CMASK 0x48 /*
+ * The following data stream is used as mask
+ * for CRC calculation.
+ */
+#define RMASK 0x49 /*
+ * The following data stream is used as mask
+ * for read and save.
+ */
+#define READ 0x50 /*
+ * The following data stream is used for read
+ * and save.
+ */
+#define ENDLOOP 0x59 /* The end of the repeat loop. */
+#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */
+#define VUES 0x61 /* Support continue if fail. */
+#define DMASK 0x62 /*
+ * The following data stream is used for dynamic
+ * I/O.
+ */
+#define COMMENT 0x63 /* Support SVF comments in the VME file. */
+#define HEADER 0x64 /* Support header in VME file. */
+#define FILE_CRC 0x65 /* Support crc-protected VME file. */
+#define LCOUNT 0x66 /* Support intelligent programming. */
+#define LDELAY 0x67 /* Support intelligent programming. */
+#define LSDR 0x68 /* Support intelligent programming. */
+#define LHEAP 0x69 /*
+ * Memory needed to hold intelligent data
+ * buffer
+ */
+#define CONTINUE 0x70 /* Allow continuation. */
+#define LVDS 0x71 /* Support LVDS. */
+#define ENDVME 0x7F /* End of the VME file. */
+#define ENDFILE 0xFF /* End of file. */
+
+/*
+ *
+ * ispVM Embedded Return Codes.
+ *
+ */
+
+#define VME_VERIFICATION_FAILURE -1
+#define VME_FILE_READ_FAILURE -2
+#define VME_VERSION_FAILURE -3
+#define VME_INVALID_FILE -4
+#define VME_ARGUMENT_FAILURE -5
+#define VME_CRC_FAILURE -6
+
+#define g_ucPinTDI 0x01
+#define g_ucPinTCK 0x02
+#define g_ucPinTMS 0x04
+#define g_ucPinENABLE 0x08
+#define g_ucPinTRST 0x10
+
+/*
+ *
+ * Type definitions.
+ *
+ */
+
+/* Support LVDS */
+typedef struct {
+ unsigned short usPositiveIndex;
+ unsigned short usNegativeIndex;
+ unsigned char ucUpdate;
+} LVDSPair;
+
+typedef enum {
+ min_lattice_iface_type, /* insert all new types after this */
+ lattice_jtag_mode, /* jtag/tap */
+ max_lattice_iface_type /* insert all new types before this */
+} Lattice_iface;
+
+typedef enum {
+ min_lattice_type,
+ Lattice_XP2, /* Lattice XP2 Family */
+ max_lattice_type /* insert all new types before this */
+} Lattice_Family;
+
+typedef struct {
+ Lattice_Family family; /* part type */
+ Lattice_iface iface; /* interface type */
+ size_t size; /* bytes of data part can accept */
+ void *iface_fns; /* interface function table */
+ void *base; /* base interface address */
+ int cookie; /* implementation specific cookie */
+ char *desc; /* description string */
+} Lattice_desc; /* end, typedef Altera_desc */
+
+/* Lattice Model Type */
+#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1)
+
+/* Board specific implementation specific function types */
+typedef void (*Lattice_jtag_init)(void);
+typedef void (*Lattice_jtag_set_tdi)(int v);
+typedef void (*Lattice_jtag_set_tms)(int v);
+typedef void (*Lattice_jtag_set_tck)(int v);
+typedef int (*Lattice_jtag_get_tdo)(void);
+
+typedef struct {
+ Lattice_jtag_init jtag_init;
+ Lattice_jtag_set_tdi jtag_set_tdi;
+ Lattice_jtag_set_tms jtag_set_tms;
+ Lattice_jtag_set_tck jtag_set_tck;
+ Lattice_jtag_get_tdo jtag_get_tdo;
+} lattice_board_specific_func;
+
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void calibration(void);
+
+int lattice_load(Lattice_desc *desc, void *buf, size_t bsize);
+int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize);
+int lattice_info(Lattice_desc *desc);
+
+void ispVMStart(void);
+void ispVMEnd(void);
+extern void ispVMFreeMem(void);
+signed char ispVMCode(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void ispVMCalculateCRC32(unsigned char a_ucData);
+unsigned char GetByte(void);
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+#endif
u_long vl_sync; /* Horizontal / vertical sync */
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_long vl_tft; /* 0 = passive, 1 = TFT */
+ u_long vl_cont_pol_low; /* contrast polarity is low */
/* Horizontal control register. */
u_long vl_hsync_len; /* Length of horizontal sync */
/*
- * Voipac PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * (C) Copyright 2005-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#ifndef _led_display_h_
+#define _led_display_h_
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- pxa_gpio_setup
- pxa_wait_ticks 0x8000
- pxa_mem_setup
- pxa_wakeup
- pxa_intr_setup
- pxa_clock_setup
+/* Display Commands */
+#define DISPLAY_CLEAR 0x1 /* Clear the display */
+#define DISPLAY_HOME 0x2 /* Set cursor at home position */
- mov pc, lr
+void display_set(int cmd);
+int display_putc(char c);
+#endif
#define _X 0x40 /* hex digit */
#define _SP 0x80 /* hard space (0x20) */
-extern unsigned char _ctype[];
+extern const unsigned char _ctype[];
#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
--- /dev/null
+#ifndef _LINUX_FB_H
+#define _LINUX_FB_H
+
+#include <linux/types.h>
+
+/* Definitions of frame buffers */
+
+#define FB_MAX 32 /* sufficient for now */
+
+#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
+
+#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR 2 /* True color */
+#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
+
+#define FB_ACCEL_NONE 0 /* no hardware accelerator */
+
+struct fb_fix_screeninfo {
+ char id[16]; /* identification string eg "TT Builtin" */
+ unsigned long smem_start; /* Start of frame buffer mem */
+ /* (physical address) */
+ __u32 smem_len; /* Length of frame buffer mem */
+ __u32 type; /* see FB_TYPE_* */
+ __u32 type_aux; /* Interleave for interleaved Planes */
+ __u32 visual; /* see FB_VISUAL_* */
+ __u16 xpanstep; /* zero if no hardware panning */
+ __u16 ypanstep; /* zero if no hardware panning */
+ __u16 ywrapstep; /* zero if no hardware ywrap */
+ __u32 line_length; /* length of a line in bytes */
+ unsigned long mmio_start; /* Start of Memory Mapped I/O */
+ /* (physical address) */
+ __u32 mmio_len; /* Length of Memory Mapped I/O */
+ __u32 accel; /* Indicate to driver which */
+ /* specific chip/card we have */
+ __u16 reserved[3]; /* Reserved for future compatibility */
+};
+
+/*
+ * Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified.
+ *
+ * For pseudocolor: offset and length should be the same for all color
+ * components. Offset specifies the position of the least significant bit
+ * of the pallette index in a pixel value. Length indicates the number
+ * of available palette entries (i.e. # of entries = 1 << length).
+ */
+struct fb_bitfield {
+ __u32 offset; /* beginning of bitfield */
+ __u32 length; /* length of bitfield */
+ __u32 msb_right;
+
+};
+
+#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
+#define FB_NONSTD_REV_PIX_IN_B 2 /* order of pixels in each byte is reversed */
+
+#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
+#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
+#define FB_ACTIVATE_MASK 15
+ /* values */
+#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
+#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
+#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
+#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
+
+#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
+#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
+#define FB_SYNC_EXT 4 /* external sync */
+#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
+#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
+ /* vtotal = 144d/288n/576i => PAL */
+ /* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN 32 /* sync on green */
+
+#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+#define FB_VMODE_INTERLACED 1 /* interlaced */
+#define FB_VMODE_DOUBLE 2 /* double scan */
+#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
+#define FB_VMODE_MASK 255
+
+#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
+#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
+
+/*
+ * Display rotation support
+ */
+#define FB_ROTATE_UR 0
+#define FB_ROTATE_CW 1
+#define FB_ROTATE_UD 2
+#define FB_ROTATE_CCW 3
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+ __u32 xres; /* visible resolution */
+ __u32 yres;
+ __u32 xres_virtual; /* virtual resolution */
+ __u32 yres_virtual;
+ __u32 xoffset; /* offset from virtual to visible */
+ __u32 yoffset; /* resolution */
+
+ __u32 bits_per_pixel; /* guess what */
+ __u32 grayscale; /* != 0 Graylevels instead of colors */
+
+ struct fb_bitfield red; /* bitfield in fb mem if true color, */
+ struct fb_bitfield green; /* else only length is significant */
+ struct fb_bitfield blue;
+ struct fb_bitfield transp; /* transparency */
+
+ __u32 nonstd; /* != 0 Non standard pixel format */
+
+ __u32 activate; /* see FB_ACTIVATE_* */
+
+ __u32 height; /* height of picture in mm */
+ __u32 width; /* width of picture in mm */
+
+ __u32 accel_flags; /* (OBSOLETE) see fb_info.flags */
+
+ /* Timing: All values in pixclocks, except pixclock (of course) */
+ __u32 pixclock; /* pixel clock in ps (pico seconds) */
+ __u32 left_margin; /* time from sync to picture */
+ __u32 right_margin; /* time from picture to sync */
+ __u32 upper_margin; /* time from sync to picture */
+ __u32 lower_margin;
+ __u32 hsync_len; /* length of horizontal sync */
+ __u32 vsync_len; /* length of vertical sync */
+ __u32 sync; /* see FB_SYNC_* */
+ __u32 vmode; /* see FB_VMODE_* */
+ __u32 rotate; /* angle we rotate counter clockwise */
+ __u32 reserved[5]; /* Reserved for future compatibility */
+};
+
+struct fb_cmap {
+ __u32 start; /* First entry */
+ __u32 len; /* Number of entries */
+ __u16 *red; /* Red values */
+ __u16 *green;
+ __u16 *blue;
+ __u16 *transp; /* transparency, can be NULL */
+};
+
+struct fb_con2fbmap {
+ __u32 console;
+ __u32 framebuffer;
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING 0
+#define VESA_VSYNC_SUSPEND 1
+#define VESA_HSYNC_SUSPEND 2
+#define VESA_POWERDOWN 3
+
+
+enum {
+ /* screen: unblanked, hsync: on, vsync: on */
+ FB_BLANK_UNBLANK = VESA_NO_BLANKING,
+
+ /* screen: blanked, hsync: on, vsync: on */
+ FB_BLANK_NORMAL = VESA_NO_BLANKING + 1,
+
+ /* screen: blanked, hsync: on, vsync: off */
+ FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+
+ /* screen: blanked, hsync: off, vsync: on */
+ FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+
+ /* screen: blanked, hsync: off, vsync: off */
+ FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */
+#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
+
+struct fb_vblank {
+ __u32 flags; /* FB_VBLANK flags */
+ __u32 count; /* counter of retraces since boot */
+ __u32 vcount; /* current scanline position */
+ __u32 hcount; /* current scandot position */
+ __u32 reserved[4]; /* reserved for future compatibility */
+};
+
+/* Internal HW accel */
+#define ROP_COPY 0
+#define ROP_XOR 1
+
+struct fb_copyarea {
+ __u32 dx;
+ __u32 dy;
+ __u32 width;
+ __u32 height;
+ __u32 sx;
+ __u32 sy;
+};
+
+struct fb_fillrect {
+ __u32 dx; /* screen-relative */
+ __u32 dy;
+ __u32 width;
+ __u32 height;
+ __u32 color;
+ __u32 rop;
+};
+
+struct fb_image {
+ __u32 dx; /* Where to place image */
+ __u32 dy;
+ __u32 width; /* Size of image */
+ __u32 height;
+ __u32 fg_color; /* Only used when a mono bitmap */
+ __u32 bg_color;
+ __u8 depth; /* Depth of the image */
+ const char *data; /* Pointer to image data */
+ struct fb_cmap cmap; /* color map info */
+};
+
+/*
+ * hardware cursor control
+ */
+
+#define FB_CUR_SETIMAGE 0x01
+#define FB_CUR_SETPOS 0x02
+#define FB_CUR_SETHOT 0x04
+#define FB_CUR_SETCMAP 0x08
+#define FB_CUR_SETSHAPE 0x10
+#define FB_CUR_SETSIZE 0x20
+#define FB_CUR_SETALL 0xFF
+
+struct fbcurpos {
+ __u16 x, y;
+};
+
+struct fb_cursor {
+ __u16 set; /* what to set */
+ __u16 enable; /* cursor on/off */
+ __u16 rop; /* bitop operation */
+ const char *mask; /* cursor mask bits */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fb_image image; /* Cursor image */
+};
+
+#ifdef CONFIG_FB_BACKLIGHT
+/* Settings for the generic backlight code */
+#define FB_BACKLIGHT_LEVELS 128
+#define FB_BACKLIGHT_MAX 0xFF
+#endif
+
+#ifdef __KERNEL__
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF 1
+#define FB_DPMS_SUSPEND 2
+#define FB_DPMS_STANDBY 4
+
+#define FB_DISP_DDI 1
+#define FB_DISP_ANA_700_300 2
+#define FB_DISP_ANA_714_286 4
+#define FB_DISP_ANA_1000_400 8
+#define FB_DISP_ANA_700_000 16
+
+#define FB_DISP_MONO 32
+#define FB_DISP_RGB 64
+#define FB_DISP_MULTI 128
+#define FB_DISP_UNKNOWN 256
+
+#define FB_SIGNAL_NONE 0
+#define FB_SIGNAL_BLANK_BLANK 1
+#define FB_SIGNAL_SEPARATE 2
+#define FB_SIGNAL_COMPOSITE 4
+#define FB_SIGNAL_SYNC_ON_GREEN 8
+#define FB_SIGNAL_SERRATION_ON 16
+
+#define FB_MISC_PRIM_COLOR 1
+#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */
+struct fb_chroma {
+ __u32 redx; /* in fraction of 1024 */
+ __u32 greenx;
+ __u32 bluex;
+ __u32 whitex;
+ __u32 redy;
+ __u32 greeny;
+ __u32 bluey;
+ __u32 whitey;
+};
+
+struct fb_monspecs {
+ struct fb_chroma chroma;
+ struct fb_videomode *modedb; /* mode database */
+ __u8 manufacturer[4]; /* Manufacturer */
+ __u8 monitor[14]; /* Monitor String */
+ __u8 serial_no[14]; /* Serial Number */
+ __u8 ascii[14]; /* ? */
+ __u32 modedb_len; /* mode database length */
+ __u32 model; /* Monitor Model */
+ __u32 serial; /* Serial Number - Integer */
+ __u32 year; /* Year manufactured */
+ __u32 week; /* Week Manufactured */
+ __u32 hfmin; /* hfreq lower limit (Hz) */
+ __u32 hfmax; /* hfreq upper limit (Hz) */
+ __u32 dclkmin; /* pixelclock lower limit (Hz) */
+ __u32 dclkmax; /* pixelclock upper limit (Hz) */
+ __u16 input; /* display type - see FB_DISP_* */
+ __u16 dpms; /* DPMS support - see FB_DPMS_ */
+ __u16 signal; /* Signal Type - see FB_SIGNAL_* */
+ __u16 vfmin; /* vfreq lower limit (Hz) */
+ __u16 vfmax; /* vfreq upper limit (Hz) */
+ __u16 gamma; /* Gamma - in fractions of 100 */
+ __u16 gtf : 1; /* supports GTF */
+ __u16 misc; /* Misc flags - see FB_MISC_* */
+ __u8 version; /* EDID version... */
+ __u8 revision; /* ...and revision */
+ __u8 max_x; /* Maximum horizontal size (cm) */
+ __u8 max_y; /* Maximum vertical size (cm) */
+};
+
+struct fb_cmap_user {
+ __u32 start; /* First entry */
+ __u32 len; /* Number of entries */
+ __u16 *red; /* Red values */
+ __u16 *green;
+ __u16 *blue;
+ __u16 *transp; /* transparency, can be NULL */
+};
+
+struct fb_image_user {
+ __u32 dx; /* Where to place image */
+ __u32 dy;
+ __u32 width; /* Size of image */
+ __u32 height;
+ __u32 fg_color; /* Only used when a mono bitmap */
+ __u32 bg_color;
+ __u8 depth; /* Depth of the image */
+ const char *data; /* Pointer to image data */
+ struct fb_cmap_user cmap; /* color map info */
+};
+
+struct fb_cursor_user {
+ __u16 set; /* what to set */
+ __u16 enable; /* cursor on/off */
+ __u16 rop; /* bitop operation */
+ const char *mask; /* cursor mask bits */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fb_image_user image; /* Cursor image */
+};
+
+/*
+ * Register/unregister for framebuffer events
+ */
+
+/* The resolution of the passed in fb_info about to change */
+#define FB_EVENT_MODE_CHANGE 0x01
+/* The display on this fb_info is beeing suspended, no access to the
+ * framebuffer is allowed any more after that call returns
+ */
+#define FB_EVENT_SUSPEND 0x02
+/* The display on this fb_info was resumed, you can restore the display
+ * if you own it
+ */
+#define FB_EVENT_RESUME 0x03
+/* An entry from the modelist was removed */
+#define FB_EVENT_MODE_DELETE 0x04
+/* A driver registered itself */
+#define FB_EVENT_FB_REGISTERED 0x05
+/* A driver unregistered itself */
+#define FB_EVENT_FB_UNREGISTERED 0x06
+/* CONSOLE-SPECIFIC: get console to framebuffer mapping */
+#define FB_EVENT_GET_CONSOLE_MAP 0x07
+/* CONSOLE-SPECIFIC: set console to framebuffer mapping */
+#define FB_EVENT_SET_CONSOLE_MAP 0x08
+/* A hardware display blank change occured */
+#define FB_EVENT_BLANK 0x09
+/* Private modelist is to be replaced */
+#define FB_EVENT_NEW_MODELIST 0x0A
+/* The resolution of the passed in fb_info about to change and
+ all vc's should be changed */
+#define FB_EVENT_MODE_CHANGE_ALL 0x0B
+/* A software display blank change occured */
+#define FB_EVENT_CONBLANK 0x0C
+/* Get drawing requirements */
+#define FB_EVENT_GET_REQ 0x0D
+/* Unbind from the console if possible */
+#define FB_EVENT_FB_UNBIND 0x0E
+
+struct fb_event {
+ struct fb_info *info;
+ void *data;
+};
+
+struct fb_blit_caps {
+ u32 x;
+ u32 y;
+ u32 len;
+ u32 flags;
+};
+
+/*
+ * Pixmap structure definition
+ *
+ * The purpose of this structure is to translate data
+ * from the hardware independent format of fbdev to what
+ * format the hardware needs.
+ */
+
+#define FB_PIXMAP_DEFAULT 1 /* used internally by fbcon */
+#define FB_PIXMAP_SYSTEM 2 /* memory is in system RAM */
+#define FB_PIXMAP_IO 4 /* memory is iomapped */
+#define FB_PIXMAP_SYNC 256 /* set if GPU can DMA */
+
+struct fb_pixmap {
+ u8 *addr; /* pointer to memory */
+ u32 size; /* size of buffer in bytes */
+ u32 offset; /* current offset to buffer */
+ u32 buf_align; /* byte alignment of each bitmap */
+ u32 scan_align; /* alignment per scanline */
+ u32 access_align; /* alignment per read/write (bits) */
+ u32 flags; /* see FB_PIXMAP_* */
+ u32 blit_x; /* supported bit block dimensions (1-32)*/
+ u32 blit_y; /* Format: blit_x = 1 << (width - 1) */
+ /* blit_y = 1 << (height - 1) */
+ /* if 0, will be set to 0xffffffff (all)*/
+ /* access methods */
+ void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size);
+ void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size);
+};
+
+#ifdef CONFIG_FB_DEFERRED_IO
+struct fb_deferred_io {
+ /* delay between mkwrite and deferred handler */
+ unsigned long delay;
+ struct mutex lock; /* mutex that protects the page list */
+ struct list_head pagelist; /* list of touched pages */
+ /* callback */
+ void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
+};
+#endif
+
+/* FBINFO_* = fb_info.flags bit flags */
+#define FBINFO_MODULE 0x0001 /* Low-level driver is a module */
+#define FBINFO_HWACCEL_DISABLED 0x0002
+ /* When FBINFO_HWACCEL_DISABLED is set:
+ * Hardware acceleration is turned off. Software implementations
+ * of required functions (copyarea(), fillrect(), and imageblit())
+ * takes over; acceleration engine should be in a quiescent state */
+
+/* hints */
+#define FBINFO_PARTIAL_PAN_OK 0x0040 /* otw use pan only for double-buffering */
+#define FBINFO_READS_FAST 0x0080 /* soft-copy faster than rendering */
+
+/*
+ * A driver may set this flag to indicate that it does want a set_par to be
+ * called every time when fbcon_switch is executed. The advantage is that with
+ * this flag set you can really be sure that set_par is always called before
+ * any of the functions dependant on the correct hardware state or altering
+ * that state, even if you are using some broken X releases. The disadvantage
+ * is that it introduces unwanted delays to every console switch if set_par
+ * is slow. It is a good idea to try this flag in the drivers initialization
+ * code whenever there is a bug report related to switching between X and the
+ * framebuffer console.
+ */
+#define FBINFO_MISC_ALWAYS_SETPAR 0x40000
+
+/*
+ * Host and GPU endianness differ.
+ */
+#define FBINFO_FOREIGN_ENDIAN 0x100000
+/*
+ * Big endian math. This is the same flags as above, but with different
+ * meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag
+ * and host endianness. Drivers should not use this flag.
+ */
+#define FBINFO_BE_MATH 0x100000
+
+struct fb_info {
+ int node;
+ int flags;
+ struct fb_var_screeninfo var; /* Current var */
+ struct fb_fix_screeninfo fix; /* Current fix */
+ struct fb_monspecs monspecs; /* Current Monitor specs */
+ struct fb_pixmap pixmap; /* Image hardware mapper */
+ struct fb_pixmap sprite; /* Cursor hardware mapper */
+ struct fb_cmap cmap; /* Current cmap */
+ struct list_head modelist; /* mode list */
+ struct fb_videomode *mode; /* current mode */
+
+ char *screen_base; /* Virtual address */
+ unsigned long screen_size; /* Amount of ioremapped VRAM or 0 */
+ void *pseudo_palette; /* Fake palette of 16 colors */
+#define FBINFO_STATE_RUNNING 0
+#define FBINFO_STATE_SUSPENDED 1
+ u32 state; /* Hardware state i.e suspend */
+ void *fbcon_par; /* fbcon use-only private area */
+ /* From here on everything is device dependent */
+ void *par;
+};
+
+#define FBINFO_DEFAULT 0
+
+#define FBINFO_FLAG_MODULE FBINFO_MODULE
+#define FBINFO_FLAG_DEFAULT FBINFO_DEFAULT
+
+/* This will go away */
+#if defined(__sparc__)
+
+/* We map all of our framebuffers such that big-endian accesses
+ * are what we want, so the following is sufficient.
+ */
+
+/* This will go away */
+#define fb_readb sbus_readb
+#define fb_readw sbus_readw
+#define fb_readl sbus_readl
+#define fb_readq sbus_readq
+#define fb_writeb sbus_writeb
+#define fb_writew sbus_writew
+#define fb_writel sbus_writel
+#define fb_writeq sbus_writeq
+#define fb_memset sbus_memset_io
+
+#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__) || defined(__bfin__)
+
+#define fb_readb __raw_readb
+#define fb_readw __raw_readw
+#define fb_readl __raw_readl
+#define fb_readq __raw_readq
+#define fb_writeb __raw_writeb
+#define fb_writew __raw_writew
+#define fb_writel __raw_writel
+#define fb_writeq __raw_writeq
+#define fb_memset memset_io
+
+#else
+
+#define fb_readb(addr) (*(volatile u8 *) (addr))
+#define fb_readw(addr) (*(volatile u16 *) (addr))
+#define fb_readl(addr) (*(volatile u32 *) (addr))
+#define fb_readq(addr) (*(volatile u64 *) (addr))
+#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
+#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
+#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
+#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
+#define fb_memset memset
+
+#endif
+
+#define FB_LEFT_POS(p, bpp) (fb_be_math(p) ? (32 - (bpp)) : 0)
+#define FB_SHIFT_HIGH(p, val, bits) (fb_be_math(p) ? (val) >> (bits) : \
+ (val) << (bits))
+#define FB_SHIFT_LOW(p, val, bits) (fb_be_math(p) ? (val) << (bits) : \
+ (val) >> (bits))
+/* drivers/video/fbmon.c */
+#define FB_MAXTIMINGS 0
+#define FB_VSYNCTIMINGS 1
+#define FB_HSYNCTIMINGS 2
+#define FB_DCLKTIMINGS 3
+#define FB_IGNOREMON 0x100
+
+#define FB_MODE_IS_UNKNOWN 0
+#define FB_MODE_IS_DETAILED 1
+#define FB_MODE_IS_STANDARD 2
+#define FB_MODE_IS_VESA 4
+#define FB_MODE_IS_CALCULATED 8
+#define FB_MODE_IS_FIRST 16
+#define FB_MODE_IS_FROM_VAR 32
+
+
+/* drivers/video/fbcmap.c */
+
+extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
+extern void fb_dealloc_cmap(struct fb_cmap *cmap);
+extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
+extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
+extern int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *fb_info);
+extern int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *fb_info);
+extern const struct fb_cmap *fb_default_cmap(int len);
+extern void fb_invert_cmaps(void);
+
+struct fb_videomode {
+ const char *name; /* optional */
+ u32 refresh; /* optional */
+ u32 xres;
+ u32 yres;
+ u32 pixclock;
+ u32 left_margin;
+ u32 right_margin;
+ u32 upper_margin;
+ u32 lower_margin;
+ u32 hsync_len;
+ u32 vsync_len;
+ u32 sync;
+ u32 vmode;
+ u32 flag;
+};
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_FB_H */
--- /dev/null
+/*
+ * Copied from Linux:
+ * commit 37487a56523d402e25650da16c337acf4cecd13d
+ * Author: Christoph Lameter <clameter@sgi.com>
+ */
+#ifndef __LINUX_KBUILD_H
+#define __LINUX_KBUILD_H
+
+#define DEFINE(sym, val) \
+ asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+
+#define BLANK() asm volatile("\n->" : : )
+
+#define OFFSET(sym, str, mem) \
+ DEFINE(sym, offsetof(struct str, mem))
+
+#define COMMENT(x) \
+ asm volatile("\n->#" x)
+
+#endif
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
-#define BMSR_RESV 0x07c0 /* Unused... */
+#define BMSR_RESV 0x00c0 /* Unused... */
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
+#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
-#define ADVERTISE_RESV 0x1c00 /* Unused... */
+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
+#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
-#define LPA_RESV 0x1c00 /* Unused... */
+#define LPA_PAUSE_CAP 0x0400 /* Can pause */
+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
+#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
+#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
+
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX 0x01
+#define FLOW_CTRL_RX 0x02
/**
* mii_nway_result
*
* The one exception to IEEE 802.3u is that 100baseT4 is placed
* between 100T-full and 100T-half. If your phy does not support
- * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
* priority order, you will need to roll your own function.
*/
static inline unsigned int mii_nway_result (unsigned int negotiated)
return 0;
}
-
#endif /* __LINUX_MII_H__ */
int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
- /* Power Management functions */
- int (*suspend) (struct mtd_info *mtd);
- void (*resume) (struct mtd_info *mtd);
-
/* Bad block management functions */
int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
extern struct mtd_info *get_mtd_device_nm(const char *name);
extern void put_mtd_device(struct mtd_info *mtd);
-
+extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+ const uint64_t length, uint64_t *len_incl_bad,
+ int *truncated);
/* XXX U-BOOT XXX */
#if 0
struct mtd_notifier {
#define NAND_CMD_SEQIN 0x80
#define NAND_CMD_RNDIN 0x85
#define NAND_CMD_READID 0x90
+#define NAND_CMD_PARAM 0xec
#define NAND_CMD_ERASE2 0xd0
#define NAND_CMD_RESET 0xff
char * name;
};
-extern struct nand_flash_dev nand_flash_ids[];
-extern struct nand_manufacturers nand_manuf_ids[];
+extern const struct nand_flash_dev nand_flash_ids[];
+extern const struct nand_manufacturers nand_manuf_ids[];
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
/*
* OneNAND Flash Manufacturer ID Codes
*/
+#define ONENAND_MFR_NUMONYX 0x20
#define ONENAND_MFR_SAMSUNG 0xec
/**
* Remy Bohmer <linux@bohmer.net>
*/
+<<<<<<< HEAD
#ifndef _UBOOT_RNDIS_H
#define _UBOOT_RNDIS_H
+=======
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_WHCM 0x08
#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3)
#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */
-
/*-------------------------------------------------------------------------*/
/*
__le16 wIndex;
__le16 wLength;
} __attribute__ ((packed));
+<<<<<<< HEAD
#endif
+=======
+>>>>>>> cdc51c294ad33879c4e57edf4c9d2155381b1d59
/* REG_CHARGE */
-#define VCHRG0 0
+#define VCHRG0 (1 << 0)
#define VCHRG1 (1 << 1)
#define VCHRG2 (1 << 2)
#define ICHRG0 (1 << 3)
#define ICHRG1 (1 << 4)
#define ICHRG2 (1 << 5)
#define ICHRG3 (1 << 6)
-#define ICHRGTR0 (1 << 7)
-#define ICHRGTR1 (1 << 8)
-#define ICHRGTR2 (1 << 9)
+#define TREN (1 << 7)
+#define ACKLPB (1 << 8)
+#define THCHKB (1 << 9)
#define FETOVRD (1 << 10)
#define FETCTRL (1 << 11)
#define RVRSMODE (1 << 13)
-#define OVCTRL0 (1 << 15)
-#define OVCTRL1 (1 << 16)
-#define UCHEN (1 << 17)
+#define PLIM0 (1 << 15)
+#define PLIM1 (1 << 16)
+#define PLIMDIS (1 << 17)
#define CHRGLEDEN (1 << 18)
-#define CHRGRAWPDEN (1 << 19)
+#define CHGTMRRST (1 << 19)
#define CHGRESTART (1 << 20)
#define CHGAUTOB (1 << 21)
#define CYCLB (1 << 22)
#define VSDSTBY (1 << 19)
#define VSDMODE (1 << 20)
+/* Reg Power Control 2*/
+#define WDIRESET (1 << 12)
+
#endif
/*
- * Copyright 2008, Freescale Semiconductor, Inc
+ * Copyright 2008,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based (loosely) on the Linux code
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
-/* GPIO pins */
+/* GPIO pins, for Rev.B chip */
#define GPIO_WKUP_7 0x80000000UL
#define GPIO_PSC6_0 0x10000000UL
#define GPIO_PSC3_9 0x04000000UL
#define GPIO_PSC1_4 0x01000000UL
+#define GPIO_PSC2_4 0x02000000UL
#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_SETUP 0x60
+#define FLASH_CMD_SET_CR_CONFIRM 0x03
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVMFP_H
+#define __MVMFP_H
+
+/*
+ * Header file for MultiFunctionPin (MFP) Configururation framework
+ *
+ * Processors Supported:
+ * 1. Marvell ARMADA100 Processors
+ *
+ * processor to be supported should be added here
+ */
+
+/*
+ * MFP configuration is represented by a 32-bit unsigned integer
+ */
+#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
+ /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
+ /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
+ /* bit 12 - Unused */ \
+ /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \
+ /* bit 09 - Pull State flag */ (((_pF) & 0x1) << 9) | \
+ /* bit 08 - Drv-strength flag */ (((_dF) & 0x1) << 8) | \
+ /* bit 07 - Edge-det flag */ (((_eF) & 0x1) << 7) | \
+ /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
+ /* bits 03..00 - Alt-fun flag */ (((_aF) & 0x1) << 3) | \
+ /* bits Alternate-fun select */ ((_afn) & 0x7))
+
+/*
+ * to facilitate the definition, the following macros are provided
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+#define MFP_OFFSET_MASK MFP(0xffff, 0,0, 0,0, 0,0, 0,0)
+#define MFP_REG(x) MFP(x, 0,0, 0,0, 0,0, 0,0)
+#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16)
+
+#define MFP_AF_FLAG MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
+#define MFP_DRIVE_FLAG MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
+#define MFP_EDGE_FLAG MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
+#define MFP_PULL_FLAG MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
+
+#define MFP_AF0 MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
+#define MFP_AF1 MFP(0x0000, 0,0, 0,0, 0,0, 1,1)
+#define MFP_AF2 MFP(0x0000, 0,0, 0,0, 0,0, 2,1)
+#define MFP_AF3 MFP(0x0000, 0,0, 0,0, 0,0, 3,1)
+#define MFP_AF4 MFP(0x0000, 0,0, 0,0, 0,0, 4,1)
+#define MFP_AF5 MFP(0x0000, 0,0, 0,0, 0,0, 5,1)
+#define MFP_AF6 MFP(0x0000, 0,0, 0,0, 0,0, 6,1)
+#define MFP_AF7 MFP(0x0000, 0,0, 0,0, 0,0, 7,1)
+#define MFP_AF_MASK MFP(0x0000, 0,0, 0,0, 0,0, 7,0)
+
+#define MFP_LPM_EDGE_NONE MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
+#define MFP_LPM_EDGE_RISE MFP(0x0000, 0,0, 0,0, 1,1, 0,0)
+#define MFP_LPM_EDGE_FALL MFP(0x0000, 0,0, 0,0, 2,1, 0,0)
+#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0,0, 0,0, 3,1, 0,0)
+#define MFP_LPM_EDGE_MASK MFP(0x0000, 0,0, 0,0, 3,0, 0,0)
+
+#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
+#define MFP_DRIVE_SLOW MFP(0x0000, 0,0, 1,1, 0,0, 0,0)
+#define MFP_DRIVE_MEDIUM MFP(0x0000, 0,0, 2,1, 0,0, 0,0)
+#define MFP_DRIVE_FAST MFP(0x0000, 0,0, 3,1, 0,0, 0,0)
+#define MFP_DRIVE_MASK MFP(0x0000, 0,0, 3,0, 0,0, 0,0)
+
+#define MFP_PULL_NONE MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_LOW MFP(0x0000, 1,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_HIGH MFP(0x0000, 2,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_BOTH MFP(0x0000, 3,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_FLOAT MFP(0x0000, 4,1, 0,0, 0,0, 0,0)
+#define MFP_PULL_MASK MFP(0x0000, 7,0, 0,0, 0,0, 0,0)
+
+#define MFP_EOC 0xffffffff /* indicates end-of-conf */
+
+/* Functions */
+void mfp_config(u32 *mfp_cfgs);
+
+#endif /* __MVMFP_H */
--- /dev/null
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MXC_GPIO_H
+#define __MXC_GPIO_H
+
+enum mxc_gpio_direction {
+ MXC_GPIO_DIRECTION_IN,
+ MXC_GPIO_DIRECTION_OUT,
+};
+
+#ifdef CONFIG_MXC_GPIO
+extern int mxc_gpio_direction(unsigned int gpio,
+ enum mxc_gpio_direction direction);
+extern void mxc_gpio_set(unsigned int gpio, unsigned int value);
+extern int mxc_gpio_get(unsigned int gpio);
+#else
+static inline int mxc_gpio_direction(unsigned int gpio,
+ enum mxc_gpio_direction direction)
+{
+ return 1;
+}
+static inline int mxc_gpio_get(unsigned int gpio)
+{
+ return 1;
+}
+static inline void mxc_gpio_set(unsigned int gpio, unsigned int value)
+{
+}
+#endif
+
+#endif
typedef struct nand_read_options nand_read_options_t;
struct nand_erase_options {
- ulong length; /* number of bytes to erase */
- ulong offset; /* first address in NAND to erase */
+ loff_t length; /* number of bytes to erase */
+ loff_t offset; /* first address in NAND to erase */
int quiet; /* don't display progress messages */
int jffs2; /* if true: format for jffs2 usage
* (write appropriate cleanmarker blocks) */
int scrub; /* if true, really clean NAND by erasing
* bad blocks (UNSAFE) */
+
+ /* Don't include skipped bad blocks in size to be erased */
+ int spread;
};
typedef struct nand_erase_options nand_erase_options_t;
extern void ip_to_string (IPaddr_t x, char *s);
/* Convert a string to ip address */
-extern IPaddr_t string_to_ip(char *s);
+extern IPaddr_t string_to_ip(const char *s);
/* Convert a VLAN id to a string */
extern void VLAN_to_string (ushort x, char *s);
/* Convert a string to a vlan id */
-extern ushort string_to_VLAN(char *s);
+extern ushort string_to_VLAN(const char *s);
/* read a VLAN id from an environment variable */
extern ushort getenv_VLAN(char *);
/* copy a filename (allow for "..." notation, limit length) */
-extern void copy_filename (char *dst, char *src, int size);
+extern void copy_filename (char *dst, const char *src, int size);
/* get a random source port */
extern unsigned int random_port(void);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode);
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int ethoc_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
int smc911x_initialize(u8 dev_num, int base_addr);
int smc91111_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
-int uec_initialize(int index);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
+int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
int sh_eth_initialize(bd_t *bis);
int dm9000_initialize(bd_t *bis);
pci_addr_t mem,
unsigned long command);
+const char * pci_class_str(u8 class);
int pci_last_busno(void);
#ifdef CONFIG_MPC824X
#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103
#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
#define PCI_DEVICE_ID_PLX_R753 0x1152
+#define PCI_DEVICE_ID_PLX_9030 0x9030
#define PCI_DEVICE_ID_PLX_9050 0x9050
#define PCI_DEVICE_ID_PLX_9060 0x9060
#define PCI_DEVICE_ID_PLX_9060ES 0x906E
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined (CONFIG_MPC85xx)
-#include <asm/cpm_85xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
+#include <asm/immap_85xx.h>
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+ offsetof(ccsr_pic_t, tfrr))
+
+#elif defined (CONFIG_MPC86xx)
+#include <asm/immap_86xx.h>
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
+ offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_4xx)
#define _POST_WORD_ADDR \
int post_run (char *name, int flags);
int post_info (char *name);
int post_log (char *format, ...);
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void post_reloc (void);
#endif
unsigned long post_time_ms (unsigned long base);
#define __set_errno(val) do { errno = val; } while (0)
-/*
- * Prototype structure for a linked-list data structure.
- * This is the type used by the `insque' and `remque' functions.
- */
-
-/* For use with hsearch(3). */
-typedef int (*__compar_fn_t) (__const void *, __const void *);
-typedef __compar_fn_t comparison_fn_t;
-
/* Action which shall be performed in the call the hsearch. */
typedef enum {
FIND,
};
/* Create a new hashing table which will at most contain NEL elements. */
-extern int hcreate(size_t __nel);
extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
/* Destroy current internal hashing table. */
-extern void hdestroy(void);
extern void hdestroy_r(struct hsearch_data *__htab);
/*
* NULL. If ACTION is `ENTER' replace existing data (if any) with
* ITEM.data.
* */
-extern ENTRY *hsearch(ENTRY __item, ACTION __action);
extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
struct hsearch_data *__htab);
/* Search and delete entry matching ITEM.key in internal hash table. */
-extern int hdelete(const char *__key);
extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
-extern ssize_t hexport(const char __sep, char **__resp, size_t __size);
extern ssize_t hexport_r(struct hsearch_data *__htab,
const char __sep, char **__resp, size_t __size);
-extern int himport(const char *__env, size_t __size, const char __sep,
- int __flag);
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
int __flag);
-/* Flags for himport() / himport_r() */
+/* Flags for himport_r() */
#define H_NOCLEAR 1 /* do not clear hash table before importing */
#endif /* search.h */
Xilinx_wr_fn wr;
Xilinx_post_fn post;
Xilinx_bwr_fn bwr; /* block write function */
+ Xilinx_abort_fn abort;
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** PCU E and CCM ************************************************/
-#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** KUP4K, KUP4X ****************************************************/
-#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
+#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
int stdio_init (void);
void stdio_print_current_devices(void);
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(char *devname);
+int stdio_deregister(const char *devname);
#endif
struct list_head* stdio_get_list(void);
-struct stdio_dev* stdio_get_by_name(char* name);
+struct stdio_dev* stdio_get_by_name(const char* name);
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
#ifdef CONFIG_ARM_DCC_MULTI
#define TWL6030_CHIP_CHARGER 0x49
#define TWL6030_CHIP_PWM 0x49
+/* Slave Address 0x48 */
+#define VUSB_CFG_STATE 0xA2
+
+#define MISC1 0xE4
+#define VAC_MEAS (1 << 2)
+#define VBAT_MEAS (1 << 1)
+#define BB_MEAS (1 << 0)
+
+#define MISC2 0xE5
+
+/* Slave Address 0x49 */
+
/* Battery CHARGER REGISTERS */
#define CONTROLLER_INT_MASK 0xE0
#define CONTROLLER_CTRL1 0xE1
#define CHARGERUSB_VOREG_4P0 0x19
#define CHARGERUSB_VOREG_4P2 0x23
#define CHARGERUSB_VOREG_4P76 0x3F
+/* CHARGERUSB_CTRL1 */
+#define SUSPEND_BOOT (1 << 7)
+#define OPA_MODE (1 << 6)
+#define HZ_MODE (1 << 5)
+#define TERM (1 << 4)
/* CHARGERUSB_CTRL2 */
#define CHARGERUSB_CTRL2_VITERM_50 (0 << 5)
#define CHARGERUSB_CTRL2_VITERM_100 (1 << 5)
#define CHARGERUSB_CTRL2_VITERM_150 (2 << 5)
+#define CHARGERUSB_CTRL2_VITERM_400 (7 << 5)
/* CONTROLLER_CTRL1 */
#define CONTROLLER_CTRL1_EN_CHARGER (1 << 4)
#define CONTROLLER_CTRL1_SEL_CHARGER (1 << 3)
+/* CONTROLLER_STAT1 */
+#define CHRG_EXTCHRG_STATZ (1 << 7)
+#define CHRG_DET_N (1 << 5)
+#define VAC_DET (1 << 3)
+#define VBUS_DET (1 << 2)
-#define VUSB_CFG_STATE 0xA2
-#define MISC2 0xE5
+#define FG_REG_10 0xCA
+#define FG_REG_11 0xCB
+
+#define TOGGLE1 0x90
+#define FGS (1 << 5)
+#define FGR (1 << 4)
+#define GPADCS (1 << 1)
+#define GPADCR (1 << 0)
+
+#define CTRL_P2 0x34
+#define CTRL_P2_SP2 (1 << 2)
+#define CTRL_P2_EOCP2 (1 << 1)
+#define CTRL_P2_BUSY (1 << 0)
+
+#define GPCH0_LSB 0x57
+#define GPCH0_MSB 0x58
void twl6030_init_battery_charging(void);
void twl6030_usb_device_settings(void);
+void twl6030_start_usb_charging(void);
+void twl6030_stop_usb_charging(void);
+int twl6030_get_battery_voltage(void);
+int twl6030_get_battery_current(void);
#define PORT_PTS_ULPI (2 << 30)
#define PORT_PTS_SERIAL (3 << 30)
#define PORT_PTS_PTW (1 << 28)
+#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
+#define PORT_PTS_PHCD (1 << 23)
+#define PORT_PP (1 << 12)
+#define PORT_PR (1 << 8)
/* USBMODE Register bits */
#define CM_IDLE (0 << 0)
#define CM_RESERVED (1 << 0)
#define CM_DEVICE (2 << 0)
#define CM_HOST (3 << 0)
+#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
#define USBMODE_RESERVED_2 (0 << 2)
#define SLOM (1 << 3)
#define SDIS (1 << 4)
#define PHY_CLK_VALID (1 << 17)
#define FSL_SOC_USB_PORTSC2 0x188
+
+/* OTG Status Control Register bits */
+#define FSL_SOC_USB_OTGSC 0x1a4
+#define CTRL_VBUS_DISCHARGE (0x1<<0)
+#define CTRL_VBUS_CHARGE (0x1<<1)
+#define CTRL_OTG_TERMINATION (0x1<<3)
+#define CTRL_DATA_PULSING (0x1<<4)
+#define CTRL_ID_PULL_EN (0x1<<5)
+#define HA_DATA_PULSE (0x1<<6)
+#define HA_BA (0x1<<7)
+#define STS_USB_ID (0x1<<8)
+#define STS_A_VBUS_VALID (0x1<<9)
+#define STS_A_SESSION_VALID (0x1<<10)
+#define STS_B_SESSION_VALID (0x1<<11)
+#define STS_B_SESSION_END (0x1<<12)
+#define STS_1MS_TOGGLE (0x1<<13)
+#define STS_DATA_PULSING (0x1<<14)
+#define INTSTS_USB_ID (0x1<<16)
+#define INTSTS_A_VBUS_VALID (0x1<<17)
+#define INTSTS_A_SESSION_VALID (0x1<<18)
+#define INTSTS_B_SESSION_VALID (0x1<<19)
+#define INTSTS_B_SESSION_END (0x1<<20)
+#define INTSTS_1MS (0x1<<21)
+#define INTSTS_DATA_PULSING (0x1<<22)
+#define INTR_USB_ID_EN (0x1<<24)
+#define INTR_A_VBUS_VALID_EN (0x1<<25)
+#define INTR_A_SESSION_VALID_EN (0x1<<26)
+#define INTR_B_SESSION_VALID_EN (0x1<<27)
+#define INTR_B_SESSION_END_EN (0x1<<28)
+#define INTR_1MS_TIMER_EN (0x1<<29)
+#define INTR_DATA_PULSING_EN (0x1<<30)
+#define INTSTS_MASK (0x00ff0000)
+
+/* USBCMD Bits of interest */
+#define EHCI_FSL_USBCMD_RST (1 << 1)
+#define EHCI_FSL_USBCMD_RS (1 << 0)
+
+#define INTERRUPT_ENABLE_BITS_MASK \
+ (INTR_USB_ID_EN | \
+ INTR_1MS_TIMER_EN | \
+ INTR_A_VBUS_VALID_EN | \
+ INTR_A_SESSION_VALID_EN | \
+ INTR_B_SESSION_VALID_EN | \
+ INTR_B_SESSION_END_EN | \
+ INTR_DATA_PULSING_EN)
+
+#define INTERRUPT_STATUS_BITS_MASK \
+ (INTSTS_USB_ID | \
+ INTR_1MS_TIMER_EN | \
+ INTSTS_A_VBUS_VALID | \
+ INTSTS_A_SESSION_VALID | \
+ INTSTS_B_SESSION_VALID | \
+ INTSTS_B_SESSION_END | \
+ INTSTS_DATA_PULSING)
+
#define FSL_SOC_USB_USBMODE 0x1a8
+
+#define USBGENCTRL 0x200 /* NOTE: big endian */
+#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
+#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
+#define GC_PPP (1 << 3) /* Port Power Polarity */
+#define GC_PFP (1 << 2) /* Power Fault Polarity */
+#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
+#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
+
+#define ISIPHYCTRL 0x204 /* NOTE: big endian */
+#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
+#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
+#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
+#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
+#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
+
#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
#elif defined(CONFIG_MPC85xx)
-#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
+#elif defined(CONFIG_MPC512X)
+#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
#endif
/*
* USB Registers
*/
struct usb_ehci {
- u8 res1[0x100];
+ u32 id; /* 0x000 - Identification register */
+ u32 hwgeneral; /* 0x004 - General hardware parameters */
+ u32 hwhost; /* 0x008 - Host hardware parameters */
+ u32 hwdevice; /* 0x00C - Device hardware parameters */
+ u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
+ u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
+ u8 res1[0x68];
+ u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
+ u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
+ u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
+ u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
+ u32 sbuscfg; /* 0x090 - System Bus Interface Control */
+ u8 res2[0x6C];
u16 caplength; /* 0x100 - Capability Register Length */
u16 hciversion; /* 0x102 - Host Interface Version */
u32 hcsparams; /* 0x104 - Host Structural Parameters */
u32 hccparams; /* 0x108 - Host Capability Parameters */
- u8 res2[0x14];
+ u8 res3[0x14];
u32 dciversion; /* 0x120 - Device Interface Version */
u32 dciparams; /* 0x124 - Device Controller Params */
- u8 res3[0x18];
+ u8 res4[0x18];
u32 usbcmd; /* 0x140 - USB Command */
u32 usbsts; /* 0x144 - USB Status */
u32 usbintr; /* 0x148 - USB Interrupt Enable */
u32 frindex; /* 0x14C - USB Frame Index */
- u8 res4[0x4];
+ u8 res5[0x4];
u32 perlistbase; /* 0x154 - Periodic List Base
- USB Device Address */
u32 ep_list_addr; /* 0x158 - Next Asynchronous List
- - Endpoint Address */
- u8 res5[0x4];
+ - End Point Address */
+ u8 res6[0x4];
u32 burstsize; /* 0x160 - Programmable Burst Size */
+#define FSL_EHCI_TXPBURST(X) ((X) << 8)
+#define FSL_EHCI_RXPBURST(X) (X)
u32 txfilltuning; /* 0x164 - Host TT Transmit
pre-buffer packet tuning */
- u8 res6[0x8];
+ u8 res7[0x8];
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
- u8 res7[0xc];
+ u8 res8[0xc];
u32 config_flag; /* 0x180 - Configured Flag Register */
u32 portsc; /* 0x184 - Port status/control */
- u8 res8[0x20];
+ u8 res9[0x1C];
+ u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
u32 usbmode; /* 0x1a8 - USB Device Mode */
- u32 epsetupstat; /* 0x1ac - Endpoint Setup Status */
- u32 epprime; /* 0x1b0 - Endpoint Init Status */
- u32 epflush; /* 0x1b4 - Endpoint De-initlialize */
- u32 epstatus; /* 0x1b8 - Endpoint Status */
- u32 epcomplete; /* 0x1bc - Endpoint Complete */
- u32 epctrl0; /* 0x1c0 - Endpoint Control 0 */
- u32 epctrl1; /* 0x1c4 - Endpoint Control 1 */
- u32 epctrl2; /* 0x1c8 - Endpoint Control 2 */
- u32 epctrl3; /* 0x1cc - Endpoint Control 3 */
- u32 epctrl4; /* 0x1d0 - Endpoint Control 4 */
- u32 epctrl5; /* 0x1d4 - Endpoint Control 5 */
- u8 res9[0x228];
+ u32 epsetupstat; /* 0x1ac - End Point Setup Status */
+ u32 epprime; /* 0x1b0 - End Point Init Status */
+ u32 epflush; /* 0x1b4 - End Point De-initlialize */
+ u32 epstatus; /* 0x1b8 - End Point Status */
+ u32 epcomplete; /* 0x1bc - End Point Complete */
+ u32 epctrl0; /* 0x1c0 - End Point Control 0 */
+ u32 epctrl1; /* 0x1c4 - End Point Control 1 */
+ u32 epctrl2; /* 0x1c8 - End Point Control 2 */
+ u32 epctrl3; /* 0x1cc - End Point Control 3 */
+ u32 epctrl4; /* 0x1d0 - End Point Control 4 */
+ u32 epctrl5; /* 0x1d4 - End Point Control 5 */
+ u8 res10[0x28];
+ u32 usbgenctrl; /* 0x200 - USB General Control */
+ u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
+ u8 res11[0x1F8];
u32 snoop1; /* 0x400 - Snoop 1 */
u32 snoop2; /* 0x404 - Snoop 2 */
u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
u32 prictrl; /* 0x40c - Priority Control */
u32 sictrl; /* 0x410 - System Interface Control */
- u8 res10[0xEC];
+ u8 res12[0xEC];
u32 control; /* 0x500 - Control */
- u8 res11[0xafc];
+ u8 res13[0xafc];
};
#endif /* _EHCI_FSL_H */
include $(TOPDIR)/config.mk
-LIB = $(obj)libgeneric.a
+LIB = $(obj)libgeneric.o
COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
COBJS-$(CONFIG_BZIP2) += bzlib.o
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
--- /dev/null
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(GENERATED_GBL_DATA_SIZE,
+ (sizeof(struct global_data)+15) & ~15);
+
+ return 0;
+}
#include <linux/ctype.h>
-unsigned char _ctype[] = {
+const unsigned char _ctype[] = {
_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
s.zalloc = zalloc;
s.zfree = zfree;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- s.outcb = (cb_func)WATCHDOG_RESET;
-#else
- s.outcb = Z_NULL;
-#endif /* CONFIG_HW_WATCHDOG */
r = inflateInit2(&s, -MAX_WBITS);
if (r != Z_OK) {
# include <linux/string.h>
#endif
+#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */
+#define CONFIG_ENV_MIN_ENTRIES 64
+#endif
#ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */
#define CONFIG_ENV_MAX_ENTRIES 512
#endif
/*
* [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986
- * [Knuth] The Art of Computer Programming, part 3 (6.4)
- */
-
-/*
- * The non-reentrant version use a global space for storing the hash table.
+ * [Knuth] The Art of Computer Programming, part 3 (6.4)
*/
-static struct hsearch_data htab;
/*
* The reentrant version has no static variables to maintain the state.
return number % div != 0;
}
-int hcreate(size_t nel)
-{
- return hcreate_r(nel, &htab);
-}
-
/*
* Before using the hash table we must allocate memory for it.
* Test for an existing table are done. We allocate one element
* The contents of the table is zeroed, especially the field used
* becomes zero.
*/
+
int hcreate_r(size_t nel, struct hsearch_data *htab)
{
/* Test for correct arguments. */
/*
* hdestroy()
*/
-void hdestroy(void)
-{
- hdestroy_r(&htab);
-}
/*
* After using the hash table it has to be destroyed. The used memory can
* be freed and the local static variable can be marked as not used.
*/
+
void hdestroy_r(struct hsearch_data *htab)
{
int i;
* example for functions like hdelete().
*/
-ENTRY *hsearch(ENTRY item, ACTION action)
-{
- ENTRY *result;
-
- (void) hsearch_r(item, action, &result, &htab);
-
- return result;
-}
-
int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
struct hsearch_data *htab)
{
if (htab->table[idx].used) {
/*
- * Further action might be required according to the
+ * Further action might be required according to the
* action value.
*/
unsigned hval2;
do {
/*
- * Because SIZE is prime this guarantees to
- * step through all available indices.
+ * Because SIZE is prime this guarantees to
+ * step through all available indices.
*/
if (idx <= hval2)
idx = htab->size + idx - hval2;
/* An empty bucket has been found. */
if (action == ENTER) {
/*
- * If table is full and another entry should be
- * entered return with error.
+ * If table is full and another entry should be
+ * entered return with error.
*/
if (htab->filled == htab->size) {
__set_errno(ENOMEM);
* do that.
*/
-int hdelete(const char *key)
-{
- return hdelete_r(key, &htab);
-}
-
int hdelete_r(const char *key, struct hsearch_data *htab)
{
ENTRY e, *ep;
* bytes in the string will be '\0'-padded.
*/
-ssize_t hexport(const char sep, char **resp, size_t size)
-{
- return hexport_r(&htab, sep, resp, size);
-}
-
static int cmpkey(const void *p1, const void *p2)
{
ENTRY *e1 = *(ENTRY **) p1;
* '\0' and '\n' have really been tested.
*/
-int himport(const char *env, size_t size, const char sep, int flag)
-{
- return himport_r(&htab, env, size, sep, flag);
-}
-
int himport_r(struct hsearch_data *htab,
const char *env, size_t size, const char sep, int flag)
{
* (CONFIG_ENV_SIZE). This heuristics will result in
* unreasonably large numbers (and thus memory footprint) for
* big flash environments (>8,000 entries for 64 KB
- * envrionment size), so we clip it to a reasonable value
- * (which can be overwritten in the board config file if
- * needed).
+ * envrionment size), so we clip it to a reasonable value.
+ * On the other hand we need to add some more entries for free
+ * space when importing very small buffers. Both boundaries can
+ * be overwritten in the board config file if needed.
*/
if (!htab->table) {
- int nent = size / 8;
+ int nent = CONFIG_ENV_MIN_ENTRIES + size / 8;
if (nent > CONFIG_ENV_MAX_ENTRIES)
nent = CONFIG_ENV_MAX_ENTRIES;
include $(TOPDIR)/config.mk
-LIB = $(obj)libfdt.a
+LIB = $(obj)libfdt.o
SOBJS =
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)liblzma.a
+LIB = $(obj)liblzma.o
SOBJS =
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(TOPDIR)/config.mk
-LIB = $(obj)liblzo.a
+LIB = $(obj)liblzo.o
SOBJS =
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h>
-IPaddr_t string_to_ip(char *s)
+IPaddr_t string_to_ip(const char *s)
{
IPaddr_t addr;
char *e;
#endif
void qsort(void *base,
- size_t nel,
- size_t width,
- int (*comp)(const void *, const void *))
+ size_t nel,
+ size_t width,
+ int (*comp)(const void *, const void *))
{
size_t wgap, i, j, k;
char tmp;
#include <common.h>
#if !defined (CONFIG_PANIC_HANG)
#include <command.h>
-/*cmd_boot.c*/
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
#include <div64.h>
#include <common.h>
#include <compiler.h>
#include <asm/unaligned.h>
+#include <watchdog.h>
#include "u-boot/zlib.h"
#undef OFF /* avoid conflicts */
state->hold = 0;
state->bits = 0;
state->lencode = state->distcode = state->next = state->codes;
- if (strm->outcb != Z_NULL)
- (*strm->outcb)(Z_NULL, 0);
+ WATCHDOG_RESET();
Tracev((stderr, "inflate: reset\n"));
return Z_OK;
}
strm->adler = state->check = adler32(0L, Z_NULL, 0);
state->mode = TYPE;
case TYPE:
+ WATCHDOG_RESET();
if (flush == Z_BLOCK) goto inf_leave;
case TYPEDO:
if (state->last) {
Tracev((stderr, "inflate: codes ok\n"));
state->mode = LEN;
case LEN:
- if (strm->outcb != Z_NULL) /* for watchdog (U-Boot) */
- (*strm->outcb)(Z_NULL, 0);
+ WATCHDOG_RESET();
if (have >= 6 && left >= 258) {
RESTORE();
inflate_fast(strm, out);
return Z_STREAM_ERROR;
state = (struct inflate_state FAR *)strm->state;
if (state->window != Z_NULL) {
- if (strm->outcb != Z_NULL)
- (*strm->outcb)(Z_NULL, 0);
+ WATCHDOG_RESET();
ZFREE(strm, state->window);
}
ZFREE(strm, strm->state);
#
# Parameters: Target Architecture CPU Board [VENDOR] [SOC]
#
-# (C) 2002-2006 DENX Software Engineering, Wolfgang Denk <wd@denx.de>
+# (C) 2002-2010 DENX Software Engineering, Wolfgang Denk <wd@denx.de>
#
APPEND=no # Default: Create new config file
board=""
vendor=""
soc=""
+options=""
if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then
# Automatic mode
done
[ $# -lt 4 ] && exit 1
-[ $# -gt 6 ] && exit 1
+[ $# -gt 7 ] && exit 1
+# Strip all options and/or _config suffixes
CONFIG_NAME="${1%_config}"
-[ "${BOARD_NAME}" ] || BOARD_NAME="${CONFIG_NAME}"
+[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
arch="$2"
cpu="$3"
fi
[ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
[ $# -gt 5 ] && [ "$6" != "-" ] && soc="$6"
+[ $# -gt 6 ] && [ "$7" != "-" ] && {
+ # check if we have a board config name in the options field
+ # the options field mave have a board config name and a list
+ # of options, both separated by a colon (':'); the options are
+ # separated by commas (',').
+ #
+ # Check for board name
+ tmp="${7%:*}"
+ if [ "$tmp" ] ; then
+ CONFIG_NAME="$tmp"
+ fi
+ # Check if we only have a colon...
+ if [ "${tmp}" != "$7" ] ; then
+ options=${7#*:}
+ TARGETS="`echo ${options} | sed 's:,: :g'` ${TARGETS}"
+ fi
+}
if [ "${ARCH}" -a "${ARCH}" != "${arch}" ]; then
echo "Failed: \$ARCH=${ARCH}, should be '${arch}' for ${BOARD_NAME}" 1>&2
exit 1
fi
-echo "Configuring for ${BOARD_NAME} board..."
+if [ "$options" ] ; then
+ echo "Configuring for ${BOARD_NAME} - Board: ${CONFIG_NAME}, Options: ${options}"
+else
+ echo "Configuring for ${BOARD_NAME} board..."
+fi
#
# Create link to architecture specific headers
echo "/* Automatically generated - do not edit */" >>config.h
for i in ${TARGETS} ; do
- echo "#define CONFIG_MK_${i} 1" >>config.h ;
+ i="`echo ${i} | sed '/=/ {s/=/\t/;q } ; { s/$/\t1/ }'`"
+ echo "#define CONFIG_${i}" >>config.h ;
done
cat << EOF >> config.h
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
#
#
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
-# TEXT_BASE to starting address in internal SRAM here.
+# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
-TEXT_BASE = 0xf8004000
+CONFIG_SYS_TEXT_BASE = 0xf8004000
# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x4000
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xf8008000
ifeq ($(debug),1)
{
.resetvec 0xf8004ffc :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
.text :
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
#
#
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into instruction-cache in start.S. So we set
-# TEXT_BASE to starting address in i-cache here.
+# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
#
-TEXT_BASE = 0x00800000
+CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x4000
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
{
.resetvec 0x00800FFC :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
.text :
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
#
#
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
-# TEXT_BASE to starting address in internal SRAM here.
+# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
-TEXT_BASE = 0xE3003000
+CONFIG_SYS_TEXT_BASE = 0xE3003000
# PAD_TO used to generate a 128kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x20000
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
PAD_TO = 0xE3023000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
{
.resetvec 0xE3003FFC :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
.text :
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
#
#
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into SDRAM since we can't access the NAND
# controller at CS0 while running from this location. So we set
-# TEXT_BASE to starting address in SDRAM here.
+# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
#
-TEXT_BASE = 0x00800000
+CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x4000
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
ifeq ($(debug),1)
{
.resetvec 0x00800FFC :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
.text :
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
#
#
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
-# TEXT_BASE to starting address in internal SRAM here.
+# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
-TEXT_BASE = 0xE0013000
+CONFIG_SYS_TEXT_BASE = 0xE0013000
# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 0x4000
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xE0017000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
{
.resetvec 0xE0013FFC :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} = 0xffff
.text :
--- /dev/null
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_NAND_SPL = y
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+
+SOBJS = start.o _udivsi3.o _divsi3.o
+COBJS = cpu.o davinci_nand.o ns16550.o div0.o davinci_pinmux.o psc.o \
+ misc.o hawkboard_nand_spl.o nand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin \
+ $(nandobj)u-boot-spl-16k.bin
+
+all: $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+$(nandobj)u-boot.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links for common files
+
+# from board directory
+$(obj)davinci_pinmux.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/board/davinci/common/davinci_pinmux.c $@
+
+# from drivers/mtd/nand directory
+$(obj)davinci_nand.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/drivers/mtd/nand/davinci_nand.c $@
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
+
+# from drivers/serial directory
+$(obj)ns16550.c:
+ @rm -f $@
+ @ln -sf $(TOPDIR)/drivers/serial/ns16550.c $@
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/start.S $@
+
+# from lib directory
+$(obj)_udivsi3.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/_udivsi3.S $@
+
+# from lib directory
+$(obj)_divsi3.S:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/_divsi3.S $@
+
+# from lib directory
+$(obj)div0.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/lib/div0.c $@
+
+# from SoC directory
+$(obj)cpu.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/cpu.c $@
+
+# from board directory
+$(obj)hawkboard_nand_spl.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/board/davinci/da8xxevm/hawkboard_nand_spl.c $@
+
+# from board directory
+$(obj)misc.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/board/davinci/common/misc.c $@
+
+$(obj)psc.c:
+ @rm -f $@
+ ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/psc.c $@
+
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
* (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0xc1080000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/armv7/start.o
+ start.o (.text)
+ cpu.o (.text)
+ nand_boot.o (.text)
+
*(.text)
}
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ __rel_dyn_end = .;
+ __dynsym_start = .;
+
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
- __got_end = .;
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ __got_end = .;
. = ALIGN(4);
__bss_start = .;
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
PAD_TO := 0xfff04000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds \
+ -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
.text : {
*(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
*(.data*)
*(.sdata*)
_GOT2_TABLE_ = .;
- *(.got2)
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
- .bss (NOLOAD) : { *(.*bss) }
+ .bss (NOLOAD) : {
+ *(.*bss)
+ }
_end = .;
}
ENTRY(_start)
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
PAD_TO := 0xfff04000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds \
+ -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
.text : {
*(.text*)
. = ALIGN(16);
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
*(.data*)
*(.sdata*)
_GOT2_TABLE_ = .;
- *(.got2)
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
- .bss (NOLOAD) : { *(.*bss) }
+ .bss (NOLOAD) : {
+ *(.*bss)
+ }
_end = .;
}
ENTRY(_start)
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
+CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
+CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
+CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
PAD_TO := 0xfff01000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
-
- __got_end = .;
- . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ _end = .;
+ }
+
+ /DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o cpu_init.o lowlevel_init.o
-COBJS = nand_boot.o nand_ecc.o s3c64xx.o
+COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@rm -f $@
@ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
+$(obj)smdk6400_nand_spl.c:
+ @rm -f $@
+ @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
+
#########################################################################
$(obj)%.o: $(obj)%.S
#
# Samsung S3C64xx Reference Platform (smdk6400) board
-# TEXT_BASE for SPL:
+# CONFIG_SYS_TEXT_BASE for SPL:
#
# On S3C64xx platforms the SPL is located in SRAM at 0.
#
-# TEXT_BASE = 0
+# CONFIG_SYS_TEXT_BASE = 0
include $(TOPDIR)/board/$(BOARDDIR)/config.mk
# PAD_TO used to generate a 4kByte binary needed for the combined image
-# -> PAD_TO = TEXT_BASE + 4096
-PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096])
+# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096
+PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
#
NAND_SPL := y
-TEXT_BASE := 0xfff00000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds \
+ -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
*(.sdata*)
_GOT2_TABLE_ = .;
*(.got2)
- __got2_entries = (. - _GOT2_TABLE_) >> 2;
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
. = ALIGN(8);
__bss_start = .;
return 0;
}
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-void board_init_f (ulong bootflag)
-{
- relocate_code (TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE);
-}
-#endif
-
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
/*
* Init board specific nand support
*/
+ nand_chip.select_chip = NULL;
nand_info.priv = &nand_chip;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
nand_chip.dev_ready = NULL; /* preset to NULL */
return 0;
}
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#if defined(CONFIG_ARM)
void board_init_f (ulong bootflag)
{
- relocate_code (TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE);
+ relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
}
#endif
# CFLAGS += -DDEBUG
-LIB = $(obj)libnet.a
+LIB = $(obj)libnet.o
COBJS-$(CONFIG_CMD_NET) += bootp.o
COBJS-$(CONFIG_CMD_DNS) += dns.o
COBJS-$(CONFIG_CMD_NET) += eth.o
COBJS-$(CONFIG_CMD_NET) += net.o
COBJS-$(CONFIG_CMD_NFS) += nfs.o
-COBJS-$(CONFIG_CMD_NET) += rarp.o
+COBJS-$(CONFIG_CMD_RARP) += rarp.o
COBJS-$(CONFIG_CMD_SNTP) += sntp.o
COBJS-$(CONFIG_CMD_NET) += tftp.o
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
*e++ = 42;
*cnt += 1;
#endif
+ /* no options, so back up to avoid sending an empty request list */
+ if (*cnt == 0)
+ e -= 2;
+
*e++ = 255; /* End of the list */
/* Pad to minimal length */
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_init();
#endif
- /* Try board-specific initialization first. If it fails or isn't
- * present, try the cpu-specific initialization */
- if (board_eth_init(bis) < 0)
- cpu_eth_init(bis);
+ /*
+ * If board-specific initialization exists, call it.
+ * If not, call a CPU-specific one
+ */
+ if (board_eth_init != __def_eth_init) {
+ if (board_eth_init(bis) < 0)
+ printf("Board Net Initialization Failed\n");
+ } else if (cpu_eth_init != __def_eth_init) {
+ if (cpu_eth_init(bis) < 0)
+ printf("CPU Net Initialization Failed\n");
+ } else
+ printf("Net Initialization Skipped\n");
#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750)
mv6436x_eth_initialize(bis);
dev = dev->next;
} while(dev != eth_devices);
-#ifdef CONFIG_NET_MULTI
/* update current ethernet name */
if (eth_current) {
char *act = getenv("ethact");
setenv("ethact", eth_current->name);
} else
setenv("ethact", NULL);
-#endif
putc ('\n');
}
void eth_try_another(int first_restart)
{
static struct eth_device *first_failed = NULL;
- char *ethrotate;
+ char *ethrotate, *act;
/*
* Do not rotate between network interfaces when
eth_current = eth_current->next;
-#ifdef CONFIG_NET_MULTI
/* update current ethernet name */
- {
- char *act = getenv("ethact");
- if (act == NULL || strcmp(act, eth_current->name) != 0)
- setenv("ethact", eth_current->name);
- }
-#endif
+ act = getenv("ethact");
+ if (act == NULL || strcmp(act, eth_current->name) != 0)
+ setenv("ethact", eth_current->name);
if (first_failed == eth_current) {
NetRestartWrap = 1;
}
}
-#ifdef CONFIG_NET_MULTI
void eth_set_current(void)
{
static char *act = NULL;
setenv("ethact", eth_current->name);
}
-#endif
char *eth_get_name (void)
{
#include <net.h>
#include "bootp.h"
#include "tftp.h"
+#ifdef CONFIG_CMD_RARP
#include "rarp.h"
+#endif
#include "nfs.h"
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
BootpRequest ();
break;
+#if defined(CONFIG_CMD_RARP)
case RARP:
RarpTry = 0;
NetOurIP = 0;
RarpRequest ();
break;
+#endif
#if defined(CONFIG_CMD_PING)
case PING:
PingStart();
}
break;
+#ifdef CONFIG_CMD_RARP
case PROT_RARP:
debug("Got RARP\n");
arp = (ARP_t *)ip;
(*packetHandler)(0,0,0,0);
}
break;
-
+#endif
case PROT_IP:
debug("Got IP\n");
/* Before we start poking the header, make sure it is there */
}
/* Fall through */
- case DHCP:
+#ifdef CONFIG_CMD_RARP
case RARP:
+#endif
case BOOTP:
case CDP:
+ case DHCP:
if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
#ifdef CONFIG_NET_MULTI
extern int eth_get_dev_index (void);
ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
}
-void copy_filename (char *dst, char *src, int size)
+void copy_filename (char *dst, const char *src, int size)
{
if (*src && (*src == '"')) {
++src;
sprintf(s, "%d", x & VLAN_IDMASK);
}
-ushort string_to_VLAN(char *s)
+ushort string_to_VLAN(const char *s)
{
ushort id;
include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
-LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
-TEXT_BASE = 0x00000000
+CONFIG_SYS_TEXT_BASE = 0x00000000
#endif
_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
-IPL =onenand_ipl
+
include $(TOPDIR)/config.mk
+include $(TOPDIR)/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
-LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
-SOBJS := lowlevel_init.o
SOBJS += start.o
COBJS := vpac270.o
COBJS += onenand_read.o
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x0800 -O binary $< $@
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(obj)vpac270.c:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
-
-$(obj)lowlevel_init.S:
- @rm -f $@
- ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
endif
#########################################################################
-TEXT_BASE = 0x5c03fc00
+CONFIG_SYS_TEXT_BASE = 0x5c03fc00
include $(TOPDIR)/config.mk
include $(OBJTREE)/include/autoconf.mk
-LIB = libpost.a
-GPLIB-$(CONFIG_HAS_POST) += libgenpost.a
+LIB = libpost.o
+GPLIB-$(CONFIG_HAS_POST) += libgenpost.o
COBJS-$(CONFIG_HAS_POST) += post.o
COBJS-$(CONFIG_POST_STD_LIST) += tests.o
-SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.a
+SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.o
SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH) ]; then echo \
- "lib_$(ARCH)/libpost$(ARCH).a"; fi)
+ "lib_$(ARCH)/libpost$(ARCH).o"; fi)
SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \
- "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
+ "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.o"; fi)
SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \
- "cpu/$(CPU)/libpost$(CPU).a"; fi)
+ "cpu/$(CPU)/libpost$(CPU).o"; fi)
SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d board/$(BOARD) ]; then echo \
- "board/$(BOARD)/libpost$(BOARD).a"; fi)
+ "board/$(BOARD)/libpost$(BOARD).o"; fi)
GPLIB := $(addprefix $(obj),$(GPLIB-y))
SPLIB := $(addprefix $(obj),$(SPLIB-y))
# generic POST library
$(GPLIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
# specific POST libraries
$(SPLIB): $(obj).depend postdeps
# the POST lib archive
$(LIB): $(GPLIB) $(SPLIB)
- (echo create $(LIB); for lib in $(GPLIB) $(SPLIB) ; \
- do echo addlib $$lib; done; echo save) \
- | $(AR) -M
+ $(call cmd_link_o_target, $^)
#########################################################################
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostlwmon.a
+LIB = libpostlwmon.o
COBJS-$(CONFIG_HAS_POST) += sysmon.o
# MA 02111-1307 USA
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostlwmon5.a
+LIB = libpostlwmon5.o
COBJS-$(CONFIG_HAS_POST) += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
DECLARE_GLOBAL_DATA_PTR;
-#define DSP_STATUS_REG 0xC4000008
+#define DSP_STATUS_REG 0xC4000008
+#define FPGA_STATUS_REG 0xC400000C
int dsp_post_test(int flags)
{
+ uint old_value;
uint read_value;
int ret;
+ /* momorize fpga status */
+ old_value = in_be32((void *)FPGA_STATUS_REG);
+ /* enable outputs */
+ out_be32((void *)FPGA_STATUS_REG, 0x30);
+
+ /* generate sync signal */
+ out_be32((void *)DSP_STATUS_REG, 0x300);
+ udelay(5);
+ out_be32((void *)DSP_STATUS_REG, 0);
+ udelay(500);
+
+ /* read status */
ret = 0;
read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
- if (read_value != 0x3) {
+ if (read_value != 0x03) {
post_log("\nDSP status read %08X\n", read_value);
ret = 1;
}
+ /* restore fpga status */
+ out_be32((void *)FPGA_STATUS_REG, old_value);
+
return ret;
}
#define DSPIC_POST_ERROR_REG 0x800
#define DSPIC_SYS_ERROR_REG 0x802
-#define DSPIC_VERSION_REG 0x804
+#define DSPIC_SYS_VERSION_REG 0x804
+#define DSPIC_FW_VERSION_REG 0x808
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
/* Verify that dsPIC ready test done early at hw init passed ok */
int dspic_init_post_test(int flags)
{
- if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & CONFIG_SYS_DSPIC_TEST_MASK) {
+ if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) &
+ CONFIG_SYS_DSPIC_TEST_MASK) {
post_log("dsPIC init test failed\n");
return 1;
}
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
/* Read a register from the dsPIC. */
-int dspic_read(ushort reg)
+int dspic_read(ushort reg, ushort *data)
{
- uchar buf[2];
+ uchar buf[sizeof(*data)];
+ int rval;
if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2))
return -1;
+ rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
+ buf, sizeof(*data));
+ *data = (buf[0] << 8) | buf[1];
- return (uint)((buf[0] << 8) | buf[1]);
+ return rval;
}
/* Verify error codes regs, display version */
int dspic_post_test(int flags)
{
- int data;
+ ushort data;
int ret = 0;
post_log("\n");
- data = dspic_read(DSPIC_VERSION_REG);
- if (data == -1) {
- post_log("dsPIC : failed read version\n");
+
+ /* read dspic FW-Version */
+ if (dspic_read(DSPIC_FW_VERSION_REG, &data)) {
+ post_log("dsPIC: failed read FW-Version\n");
+ ret = 1;
+ } else {
+ post_log("dsPIC FW-Version: %u.%u\n",
+ (data >> 8) & 0xFF, data & 0xFF);
+ }
+
+ /* read dspic SYS-Version */
+ if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) {
+ post_log("dsPIC: failed read version\n");
ret = 1;
} else {
- post_log("dsPIC version: %u.%u\n",
- (data >> 8) & 0xFF, data & 0xFF);
+ post_log("dsPIC SYS-Version: %u.%u\n",
+ (data >> 8) & 0xFF, data & 0xFF);
}
- data = dspic_read(DSPIC_POST_ERROR_REG);
- if (data != 0) ret = 1;
- if (data == -1) {
- post_log("dsPIC : failed read POST code\n");
+ /* read dspic POST error code */
+ if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
+ post_log("dsPIC: failed read POST code\n");
+ ret = 1;
} else {
- post_log("dsPIC POST code 0x%04X\n", data);
+ post_log("dsPIC POST-ERROR code: 0x%04X\n", data);
}
- data = dspic_read(DSPIC_SYS_ERROR_REG);
- if (data == -1) {
- post_log("dsPIC : failed read system error\n");
+ /* read dspic SYS error code */
+ if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) {
+ post_log("dsPIC: failed read system error\n");
ret = 1;
} else {
- post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
+ post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
}
return ret;
*/
#include <post.h>
-
+#include <watchdog.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define FPGA_RAM_START 0xC4200000
#define FPGA_RAM_END 0xC4203FFF
#define FPGA_STAT 0xC400000C
+#define FPGA_BUFFER 0x00800000
+#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
-/* Testpattern for fpga memorytest */
-static uint pattern[] = {
+const static unsigned long pattern[] = {
+ 0xffffffff,
+ 0xaaaaaaaa,
+ 0xcccccccc,
+ 0xf0f0f0f0,
+ 0xff00ff00,
+ 0xffff0000,
+ 0x0000ffff,
+ 0x00ff00ff,
+ 0x0f0f0f0f,
+ 0x33333333,
0x55555555,
- 0xAAAAAAAA,
- 0xAA5555AA,
- 0x55AAAA55,
- 0x0
+ 0x00000000,
};
+const static unsigned long otherpattern = 0x01234567;
+
static int one_scratch_test(uint value)
{
uint read_value;
read_value = in_be32((void *)FPGA_SCRATCH_REG);
if (read_value != value) {
post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
- value, read_value);
- ret = 1;
+ value, read_value);
+ ret = -1;
+ }
+
+ return ret;
+}
+
+static int fpga_post_test1(ulong *start, ulong size, ulong val)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = val;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != val) {
+ post_log("FPGA Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, val, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+ return ret;
+}
+
+static int fpga_post_test2(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = 1 << (i % 32);
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != 1 << (i % 32)) {
+ post_log("FPGA Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, 1 << (i % 32), readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+static int fpga_post_test3(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = i;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != i) {
+ post_log("FPGA Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, i, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+static int fpga_post_test4(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = ~i;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != ~i) {
+ post_log("FPGA Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, ~i, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
}
return ret;
}
/* FPGA Memory-pattern-test */
-static int fpga_mem_test(void * address)
+static int fpga_mem_test(void)
{
- int ret = 1;
- uint read_value;
- uint old_value;
- uint i = 0;
- /* save content */
- old_value = in_be32(address);
-
- while (pattern[i] != 0) {
- out_be32(address, pattern[i]);
- /* read other location (protect against data lines capacity) */
- ret = in_be16((void *)FPGA_VERSION_REG);
- /* verify test pattern */
- read_value = in_be32(address);
-
- if (read_value != pattern[i]) {
- post_log("FPGA Memory test failed.");
- post_log(" write %08X, read %08X at address %08X\n",
- pattern[i], read_value, address);
+ int ret = 0;
+ ulong* start = (ulong *)FPGA_RAM_START;
+ ulong size = FPGA_RAM_SIZE;
+
+ if (ret == 0)
+ ret = fpga_post_test1(start, size, 0x00000000);
+
+ if (ret == 0)
+ ret = fpga_post_test1(start, size, 0xffffffff);
+
+ if (ret == 0)
+ ret = fpga_post_test1(start, size, 0x55555555);
+
+ if (ret == 0)
+ ret = fpga_post_test1(start, size, 0xaaaaaaaa);
+
+ WATCHDOG_RESET();
+
+ if (ret == 0)
+ ret = fpga_post_test2(start, size);
+
+ if (ret == 0)
+ ret = fpga_post_test3(start, size);
+
+ if (ret == 0)
+ ret = fpga_post_test4(start, size);
+
+ return ret;
+}
+
+/* Verify FPGA addresslines */
+static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
+{
+ unsigned long *target;
+ unsigned long *end;
+ unsigned long readback;
+ unsigned long xor;
+ int ret = 0;
+
+ end = (ulong *)((ulong)base + size);
+ xor = 0;
+
+ for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
+ target = (ulong*)((ulong)address ^ xor);
+ if ((target >= base) && (target < end)) {
+ *address = ~*target;
+ readback = *target;
+
+ if (readback == *address) {
+ post_log("Memory (address line) error at %08x"
+ "XOR value %08x !\n",
+ address, target, xor);
+ ret = -1;
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/* Verify FPGA addresslines */
+static int fpga_post_dataline(ulong *address)
+{
+ unsigned long temp32 = 0;
+ int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(pattern); i++) {
+ *address = pattern[i];
+ /*
+ * Put a different pattern on the data lines: otherwise they
+ * may float long enough to read back what we wrote.
+ */
+ *(address + 1) = otherpattern;
+ temp32 = *address;
+
+ if (temp32 != pattern[i]){
+ post_log("Memory (date line) error at %08x, "
+ "wrote %08x, read %08x !\n",
+ address, pattern[i], temp32);
ret = 1;
- goto out;
}
- i++;
}
- ret = 0;
-out:
- out_be32(address, old_value);
return ret;
}
+
/* Verify FPGA, get version & memory size */
int fpga_post_test(int flags)
{
- uint address;
uint old_value;
- ushort version;
+ uint version;
uint read_value;
int ret = 0;
out_be32((void *)FPGA_SCRATCH_REG, old_value);
- version = in_be16((void *)FPGA_VERSION_REG);
- post_log("FPGA : version %u.%u\n",
- (version >> 8) & 0xFF, version & 0xFF);
+ version = in_be32((void *)FPGA_VERSION_REG);
+ post_log("FPGA version %u.%u\n",
+ (version >> 8) & 0xFF, version & 0xFF);
/* Enable write to FPGA RAM */
out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
- read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
- post_log("FPGA RAM size: %d bytes\n", read_value);
+ /* get RAM size */
+ read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
+ post_log("FPGA RAM size %d bytes\n", read_value);
+ WATCHDOG_RESET();
- for (address = 0; address < 0x1000; address++) {
- if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
- ret = 1;
- goto out;
- }
+ /* copy fpga memory to DDR2 RAM*/
+ memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
+ WATCHDOG_RESET();
+
+ /* Test datalines */
+ if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+
+ /* Test addresslines */
+ if (fpga_post_addrline((ulong *)FPGA_RAM_START,
+ (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
+ ret = 1;
+ goto out;
}
+ WATCHDOG_RESET();
+ if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
+ (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+
+ /* Memory Pattern Test */
+ if (fpga_mem_test()) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+
+ /* restore memory */
+ memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
+ WATCHDOG_RESET();
out:
+ /* Disable write to RAM */
+ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
return ret;
}
*/
#include <post.h>
-
+#include <watchdog.h>
#include <asm/io.h>
+#include <video.h>
DECLARE_GLOBAL_DATA_PTR;
-#define GDC_SCRATCH_REG 0xC1FF8044
-#define GDC_VERSION_REG 0xC1FF8084
-#define GDC_RAM_START 0xC0000000
-#define GDC_RAM_END 0xC2000000
+#define GDC_SCRATCH_REG 0xC1FF8044
+#define GDC_VERSION_REG 0xC1FF8084
+#define GDC_HOST_BASE 0xC1FC0000
+#define GDC_RAM_START 0xC0000000
+#define GDC_RAM_END (GDC_HOST_BASE - 1)
+#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START)
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
+const static unsigned long pattern[] = {
+ 0xffffffff,
+ 0xaaaaaaaa,
+ 0xcccccccc,
+ 0xf0f0f0f0,
+ 0xff00ff00,
+ 0xffff0000,
+ 0x0000ffff,
+ 0x00ff00ff,
+ 0x0f0f0f0f,
+ 0x33333333,
+ 0x55555555,
+ 0x00000000
+};
+
+const static unsigned long otherpattern = 0x01234567;
+
+/* test write/read og a given LIME Register */
static int gdc_test_reg_one(uint value)
{
int ret;
read_value = in_be32((void *)GDC_SCRATCH_REG);
if (read_value != value) {
post_log("GDC SCRATCH test failed write %08X, read %08X\n",
- value, read_value);
+ value, read_value);
}
return (read_value != value);
}
-/* Verify GDC, get memory size */
+/* test with a given static 32 bit pattern in a given memory addressrange */
+static int gdc_post_test1(ulong *start, ulong size, ulong val)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = val;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != val) {
+ post_log("GDC Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, val, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+/* test with dynamic 32 bit pattern in a given memory addressrange */
+static int gdc_post_test2(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = 1 << (i % 32);
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != 1 << (i % 32)) {
+ post_log("GDC Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, 1 << (i % 32), readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+/* test with dynamic 32 bit pattern in a given memory addressrange */
+static int gdc_post_test3(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = i;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != i) {
+ post_log("GDC Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, i, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+/* test with dynamic 32 bit pattern in a given memory addressrange */
+static int gdc_post_test4(ulong *start, ulong size)
+{
+ int ret = 0;
+ ulong i = 0;
+ ulong *mem = start;
+ ulong readback;
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ mem[i] = ~i;
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ for (i = 0; i < size / sizeof(ulong); i++) {
+ readback = mem[i];
+ if (readback != ~i) {
+ post_log("GDC Memory error at %08x, "
+ "wrote %08x, read %08x !\n",
+ mem + i, ~i, readback);
+ ret = -1;
+ break;
+ }
+ if (i % 1024 == 0)
+ WATCHDOG_RESET();
+ }
+
+ return ret;
+}
+
+/* do some patterntests in a given addressrange */
+int gdc_mem_test(ulong *start, ulong size)
+{
+ int ret = 0;
+
+ /*
+ * check addressrange and do different static and dynamic
+ * pattern tests with it.
+ */
+ if (((void *)start) + size <= (void *)GDC_RAM_END) {
+ if (ret == 0)
+ ret = gdc_post_test1(start, size, 0x00000000);
+
+ if (ret == 0)
+ ret = gdc_post_test1(start, size, 0xffffffff);
+
+ if (ret == 0)
+ ret = gdc_post_test1(start, size, 0x55555555);
+
+ if (ret == 0)
+ ret = gdc_post_test1(start, size, 0xaaaaaaaa);
+
+ if (ret == 0)
+ ret = gdc_post_test2(start, size);
+
+ if (ret == 0)
+ ret = gdc_post_test3(start, size);
+
+ if (ret == 0)
+ ret = gdc_post_test4(start, size);
+ }
+
+ return ret;
+}
+
+/* test function of gdc memory addresslines*/
+static int gdc_post_addrline(ulong *address, ulong *base, ulong size)
+{
+ ulong *target;
+ ulong *end;
+ ulong readback = 0;
+ ulong xor = 0;
+ int ret = 0;
+
+ end = (ulong *)((ulong)base + size);
+
+ for (xor = sizeof(long); xor > 0; xor <<= 1) {
+ target = (ulong *)((ulong)address ^ xor);
+ if ((target >= base) && (target < end)) {
+ *address = ~*target;
+ readback = *target;
+ }
+
+ if (readback == *address) {
+ post_log("GDC Memory (address line) error at %08x"
+ "XOR value %08x !\n",
+ address, target , xor);
+ ret = -1;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int gdc_post_dataline(ulong *address)
+{
+ unsigned long temp32 = 0;
+ int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(pattern); i++) {
+ *address = pattern[i];
+ /*
+ * Put a different pattern on the data lines: otherwise they
+ * may float long enough to read back what we wrote.
+ */
+ *(address + 1) = otherpattern;
+ temp32 = *address;
+
+ if (temp32 != pattern[i]){
+ post_log("GDC Memory (date line) error at %08x, "
+ "wrote %08x, read %08x !\n",
+ address, pattern[i], temp32);
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+/* Verify GDC, get memory size, verify GDC memory */
int gdc_post_test(int flags)
{
- uint old_value;
- int ret = 0;
+ uint old_value;
+ int i = 0;
+ int ret = 0;
post_log("\n");
old_value = in_be32((void *)GDC_SCRATCH_REG);
old_value = in_be32((void *)GDC_VERSION_REG);
post_log("GDC chip version %u.%u, year %04X\n",
- (old_value >> 8) & 0xFF, old_value & 0xFF,
- (old_value >> 16) & 0xFFFF);
+ (old_value >> 8) & 0xFF, old_value & 0xFF,
+ (old_value >> 16) & 0xFFFF);
old_value = get_ram_size((void *)GDC_RAM_START,
- GDC_RAM_END - GDC_RAM_START);
+ 0x02000000);
+
+ debug("GDC RAM size (ist): %d bytes\n", old_value);
+ debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE);
post_log("GDC RAM size: %d bytes\n", old_value);
+ /* Test SDRAM datalines */
+ if (gdc_post_dataline((ulong *)GDC_RAM_START)) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+
+ /* Test SDRAM adresslines */
+ if (gdc_post_addrline((ulong *)GDC_RAM_START,
+ (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+ if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long),
+ (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+ WATCHDOG_RESET();
+
+ /* memory pattern test */
+ debug("GDC Memory test (flags %8x:%8x)\n", flags,
+ POST_SLOWTEST | POST_MANUAL);
+
+ if (flags & POST_MANUAL) {
+ debug("Full memory test\n");
+ if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
+ ret = 1;
+ goto out;
+ }
+ /* load splashscreen again */
+ } else {
+ debug("smart memory test\n");
+ for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) {
+ if (ret == 0)
+ ret = gdc_mem_test((ulong *)(GDC_RAM_START +
+ (i << 20)),
+ 0x800);
+ if (ret == 0)
+ ret = gdc_mem_test((ulong *)(GDC_RAM_START +
+ (i << 20) + 0xff800),
+ 0x800);
+ }
+ }
+ WATCHDOG_RESET();
+
+out:
return ret;
}
#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
DECLARE_GLOBAL_DATA_PTR;
/* from dspic.c */
-extern int dspic_read(ushort reg);
+extern int dspic_read(ushort reg, ushort *data);
#define REG_TEMPERATURE 0x12BC
#define REG_VOLTAGE_5V 0x12CA
typedef struct sysmon_s sysmon_t;
typedef struct sysmon_table_s sysmon_table_t;
-static void sysmon_dspic_init (sysmon_t * this);
-static int sysmon_dspic_read (sysmon_t * this, uint addr);
-static void sysmon_backlight_disable (sysmon_table_t * this);
+static void sysmon_dspic_init(sysmon_t *this);
+static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val);
+static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val);
+static void sysmon_backlight_disable(sysmon_table_t *this);
-struct sysmon_s
-{
+struct sysmon_s {
uchar chip;
void (*init)(sysmon_t *);
- int (*read)(sysmon_t *, uint);
+ int (*read)(sysmon_t *, uint, int *);
};
-static sysmon_t sysmon_dspic =
- {CONFIG_SYS_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read};
+static sysmon_t sysmon_dspic = {
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR,
+ sysmon_dspic_init,
+ sysmon_dspic_read
+};
-static sysmon_t * sysmon_list[] =
-{
+static sysmon_t sysmon_dspic_sgn = {
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR,
+ sysmon_dspic_init,
+ sysmon_dspic_read_sgn
+};
+
+static sysmon_t *sysmon_list[] = {
&sysmon_dspic,
NULL
};
-struct sysmon_table_s
-{
- char * name;
- char * unit_name;
- sysmon_t * sysmon;
+struct sysmon_table_s {
+ char *name;
+ char *unit_name;
+ sysmon_t *sysmon;
void (*exec_before)(sysmon_table_t *);
void (*exec_after)(sysmon_table_t *);
uint addr;
};
-static sysmon_table_t sysmon_table[] =
-{
+static sysmon_table_t sysmon_table[] = {
{
- "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
- 1, 1, -32768, 32767, 0xFFFF,
- 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
- 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
- REG_TEMPERATURE,
+ "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
+ 1, 1, -32768, 32767, 0xFFFF,
+ 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
+ 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
+ REG_TEMPERATURE,
},
{
- "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
- 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
- 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
- REG_VOLTAGE_5V,
+ "+ 5 V", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+ 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
+ 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
+ REG_VOLTAGE_5V,
},
{
- "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
- 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
- 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
- 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
- REG_VOLTAGE_5V_STANDBY,
+ "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
+ 100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+ 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
+ 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
+ REG_VOLTAGE_5V_STANDBY,
+ },
+
+ {
+ "Temperature", "°C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
+ 1, 1, -32768, 32767, 0xFFFF,
+ 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
+ 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
+ REG_TEMPERATURE,
},
};
-static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
-int sysmon_init_f (void)
+int sysmon_init_f(void)
{
- sysmon_t ** l;
+ sysmon_t **l;
for (l = sysmon_list; *l; l++)
(*l)->init(*l);
return 0;
}
-void sysmon_reloc (void)
+void sysmon_reloc(void)
{
/* Do nothing for now, sysmon_reloc() is required by the sysmon post */
}
-static char *sysmon_unit_value (sysmon_table_t *s, uint val)
+static char *sysmon_unit_value(sysmon_table_t *s, uint val)
{
static char buf[32];
char *p, sign;
if (unit_val < 0) {
sign = '-';
unit_val = -unit_val;
- } else
+ } else {
sign = '+';
+ }
p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
-
frac = unit_val % s->unit_div;
-
frac /= (s->unit_div / s->unit_precision);
decimal = s->unit_precision;
return buf;
}
-static void sysmon_dspic_init (sysmon_t * this)
+static void sysmon_dspic_init(sysmon_t *this)
{
}
-static int sysmon_dspic_read (sysmon_t * this, uint addr)
+static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val)
{
- int res = dspic_read(addr);
+ ushort data;
+
+ if (dspic_read(addr, &data) == 0){
+ /* To fit into the table range we should add 0x8000 */
+ *val = data + 0x8000;
+ return 0;
+ }
- /* To fit into the table range we should add 0x8000 */
- return (res == -1) ? -1 : (res + 0x8000);
+ return -1;
}
-static void sysmon_backlight_disable (sysmon_table_t * this)
+static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val)
+{
+ ushort data;
+
+ if (dspic_read(addr, &data) == 0){
+ /* To fit into the table range we should add 0x8000 */
+ *val = (signed short)data + 0x8000;
+ return 0;
+ }
+
+ return -1;
+}
+
+static void sysmon_backlight_disable(sysmon_table_t *this)
{
#if defined(CONFIG_VIDEO)
board_backlight_switch(this->val_valid_alt);
#endif
}
-int sysmon_post_test (int flags)
+int sysmon_post_test(int flags)
{
int res = 0;
sysmon_table_t * t;
int val;
- for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) {
+ for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) {
+ t->val_valid = 1;
if (t->exec_before)
t->exec_before(t);
- val = t->sysmon->read(t->sysmon, t->addr);
- if (val != -1) {
- t->val_valid = val >= t->val_min && val <= t->val_max;
- t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
- } else {
+ if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) {
t->val_valid = 0;
t->val_valid_alt = 0;
+ post_log(": read failed\n");
+ res = 1;
+ break;
+ }
+
+ if (t->val_valid != 0) {
+ t->val_valid = val >= t->val_min && val <= t->val_max;
+ t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
}
if (t->exec_after)
t->exec_after(t);
- if ((!t->val_valid) || (flags & POST_MANUAL)) {
- printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
- printf("allowed range");
- printf(" %-8s ..", sysmon_unit_value(t, t->val_min));
- printf(" %-8s", sysmon_unit_value(t, t->val_max));
- printf(" %s\n", t->val_valid ? "OK" : "FAIL");
+ if ((!t->val_valid) || (flags)) {
+ post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
+ post_log("allowed range");
+ post_log(" %-8s ..", sysmon_unit_value(t, t->val_min));
+ post_log(" %-8s", sysmon_unit_value(t, t->val_max));
+ post_log(" %s", t->val_valid ? "OK" : "FAIL");
}
- if (!t->val_valid)
+ if (!t->val_valid) {
res = 1;
+ break;
+ }
}
+ post_log("\n");
return res;
}
* 3.1. GPIO62 is low
* Assuming system voltage failure.
*/
- post_log("Abnormal voltage detected (GPIO62)\n");
+ post_log("sysmon1 Abnormal voltage detected (GPIO62)\n");
+ post_log("POST sysmon1 FAILED\n");
return 1;
+ } else {
+ post_log("sysmon1 PASSED\n");
}
return 0;
ulong time;
/* 3.3.1. So, the test succeed, save measured time to syslog. */
time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR);
- post_log("hw watchdog time : %u ms, passed ", time);
- /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
- watchdog_magic_write(0);
- return 0;
+ if (time > 90 ) { /* ms*/
+ post_log("hw watchdog time : %u ms, passed ", time);
+ /* 3.3.2. Set scratch register 1 to 0x0000xxxx */
+ watchdog_magic_write(0);
+ return 0;
+ } else {
+ /*test minimum watchdogtime */
+ post_log("hw watchdog time : %u ms, failed ", time);
+ return 2;
+ }
}
return -1;
}
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostnetta.a
+LIB = libpostnetta.o
COBJS-$(CONFIG_HAS_POST) += codec.o dsp.o
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostpdm360ng.a
+LIB = libpostpdm360ng.o
COBJS-$(CONFIG_HAS_POST) += coproc_com.o
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostmpc83xx.a
+LIB = libpostmpc83xx.o
AOBJS-$(CONFIG_HAS_POST) +=
COBJS-$(CONFIG_HAS_POST) += ecc.o
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostmpc8xx.a
+LIB = libpostmpc8xx.o
AOBJS-$(CONFIG_HAS_POST) += cache_8xx.o
COBJS-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o
#
include $(OBJTREE)/include/autoconf.mk
-LIB = libpostppc4xx.a
+LIB = libpostppc4xx.o
AOBJS-$(CONFIG_HAS_POST) += cache_4xx.o
COBJS-$(CONFIG_HAS_POST) += cache.o
clear_and_enable_ecc();
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
/* Verify no ECC error reading back */
value = in_be32(ecc_mem);
/* Test for correctable error by creating a one-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Test for uncorrectable error by creating a two-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Remove error from SDRAM and enable ECC. */
out_be32(ecc_mem, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
return ret;
* are transmitted. The configurable test parameters are:
* MIN_PACKET_LENGTH - minimum size of packet to transmit
* MAX_PACKET_LENGTH - maximum size of packet to transmit
- * TEST_NUM - number of tests
+ * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
+ * is tested with a different frame length. Starting with
+ * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
+ * Defaults to 10 and can be overriden in the board config header.
*/
#include <post.h>
#endif
#define MIN_PACKET_LENGTH 64
-#define MAX_PACKET_LENGTH 256
-#define TEST_NUM 1
+#define MAX_PACKET_LENGTH 1514
+#ifndef CONFIG_SYS_POST_ETH_LOOPS
+#define CONFIG_SYS_POST_ETH_LOOPS 10
+#endif
+#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
+ CONFIG_SYS_POST_ETH_LOOPS)
static volatile mal_desc_t tx __cacheline_aligned;
static volatile mal_desc_t rx __cacheline_aligned;
return 0;
}
+ char packet_send[MAX_PACKET_LENGTH];
+ char packet_recv[MAX_PACKET_LENGTH];
static int test_ctlr (int devnum, int hw_addr)
{
int res = -1;
- char packet_send[MAX_PACKET_LENGTH];
- char packet_recv[MAX_PACKET_LENGTH];
int length;
- int i;
int l;
ether_post_init (devnum, hw_addr);
- for (i = 0; i < TEST_NUM; i++) {
- for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
- packet_fill (packet_send, l);
+ for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
+ l -= PACKET_INCR) {
+ packet_fill (packet_send, l);
- ether_post_send (devnum, hw_addr, packet_send, l);
+ ether_post_send (devnum, hw_addr, packet_send, l);
- length = ether_post_recv (devnum, hw_addr, packet_recv,
- sizeof (packet_recv));
+ length = ether_post_recv (devnum, hw_addr, packet_recv,
+ sizeof (packet_recv));
- if (length != l || packet_check (packet_recv, length) < 0) {
- goto Done;
- }
+ if (length != l || packet_check (packet_recv, length) < 0) {
+ goto Done;
}
}
*/
#include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
#include <ns16550.h>
#include <asm/io.h>
+#include <serial.h>
/*
* UART test
* be overridden in the board config file
*/
#ifndef CONFIG_SYS_POST_UART_TABLE
-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
-#endif
-
-#include <asm/processor.h>
-#include <serial.h>
-
-#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300
-#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000400
-#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000500
-#define UART3_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600
-#else
-#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000200
-#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600
-#endif
-
-#if defined(CONFIG_440GP)
-#define CR0_MASK 0x3fff0000
-#define CR0_EXTCLK_ENA 0x00600000
-#define CR0_UDIV_POS 16
-#define UDIV_SUBTRACT 1
-#define UART0_SDR CPC0_CR0
-#define MFREG(a, d) d = mfdcr(a)
-#define MTREG(a, d) mtdcr(a, d)
-#else /* #if defined(CONFIG_440GP) */
-/* all other 440 PPC's access clock divider via sdr register */
-#define CR0_MASK 0xdfffffff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#define UDIV_SUBTRACT 0
-#define UART0_SDR SDR0_UART0
-#define UART1_SDR SDR0_UART1
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_SDR SDR0_UART2
-#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
- defined(CONFIG_440GR) || defined(CONFIG_440GRX)
-#define UART3_SDR SDR0_UART3
-#endif
-#define MFREG(a, d) mfsdr(a, d)
-#define MTREG(a, d) mtsdr(a, d)
-#endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define UCR0_MASK 0x0000007f
-#define UCR1_MASK 0x00007f00
-#define UCR0_UDIV_POS 0
-#define UCR1_UDIV_POS 8
-#define UDIV_MAX 127
-#elif defined(CONFIG_405EX)
-#define UART0_BASE 0xef600200
-#define UART1_BASE 0xef600300
-#define CR0_MASK 0x000000ff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#define UDIV_SUBTRACT 0
-#define UART0_SDR SDR0_UART0
-#define UART1_SDR SDR0_UART1
-#define MFREG(a, d) mfsdr(a, d)
-#define MTREG(a, d) mtsdr(a, d)
-#else /* CONFIG_405GP || CONFIG_405CR */
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define CR0_MASK 0x00001fff
-#define CR0_EXTCLK_ENA 0x000000c0
-#define CR0_UDIV_POS 1
-#define UDIV_MAX 32
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2, CONFIG_SYS_NS16550_COM3, \
+ CONFIG_SYS_NS16550_COM4 }
#endif
DECLARE_GLOBAL_DATA_PTR;
-static void uart_post_init_common(struct NS16550 *com_port, unsigned short bdiv)
-{
- volatile char val;
-
- out_8(&com_port->lcr, 0x80); /* set DLAB bit */
- out_8(&com_port->dll, bdiv); /* set baudrate divisor */
- out_8(&com_port->dlm, bdiv >> 8); /* set baudrate divisor */
- out_8(&com_port->lcr, 0x03); /* clear DLAB; set 8 bits, no parity */
- out_8(&com_port->fcr, 0x00); /* disable FIFO */
- out_8(&com_port->mcr, 0x10); /* enable loopback mode */
- val = in_8(&com_port->lsr); /* clear line status */
- val = in_8(&com_port->rbr); /* read receive buffer */
- out_8(&com_port->scr, 0x00); /* set scratchpad */
- out_8(&com_port->ier, 0x00); /* set interrupt enable reg */
-}
-
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
-static void serial_divs (int baudrate, unsigned long *pudiv,
- unsigned short *pbdiv)
-{
- sys_info_t sysinfo;
- unsigned long div; /* total divisor udiv * bdiv */
- unsigned long umin; /* minimum udiv */
- unsigned short diff; /* smallest diff */
- unsigned long udiv; /* best udiv */
- unsigned short idiff; /* current diff */
- unsigned short ibdiv; /* current bdiv */
- unsigned long i;
- unsigned long est; /* current estimate */
-
- get_sys_info(&sysinfo);
-
- udiv = 32; /* Assume lowest possible serial clk */
- div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
- umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
- diff = 32; /* highest possible */
-
- /* i is the test udiv value -- start with the largest
- * possible (32) to minimize serial clock and constrain
- * search to umin.
- */
- for (i = 32; i > umin; i--) {
- ibdiv = div / i;
- est = i * ibdiv;
- idiff = (est > div) ? (est-div) : (div-est);
- if (idiff == 0) {
- udiv = i;
- break; /* can't do better */
- } else if (idiff < diff) {
- udiv = i; /* best so far */
- diff = idiff; /* update lowest diff*/
- }
- }
-
- *pudiv = udiv;
- *pbdiv = div / udiv;
-}
-#endif
-
-static int uart_post_init (struct NS16550 *com_port)
+static int test_ctlr (struct NS16550 *com_port, int index)
{
- unsigned long reg = 0;
- unsigned long udiv;
- unsigned short bdiv;
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- unsigned long tmp;
-#endif
+ int res = -1;
+ char test_str[] = "*** UART Test String ***\r\n";
int i;
+ int divisor;
- for (i = 0; i < 3500; i++) {
- if (in_8(&com_port->lsr) & UART_LSR_THRE)
- break;
- udelay (100);
- }
- MFREG(UART0_SDR, reg);
- reg &= ~CR0_MASK;
-
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- reg |= CR0_EXTCLK_ENA;
- udiv = 1;
- tmp = gd->baudrate * 16;
- bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
-#else
- /* For 440, the cpu clock is on divider chain A, UART on divider
- * chain B ... so cpu clock is irrelevant. Get the "optimized"
- * values that are subject to the 1/2 opb clock constraint
- */
- serial_divs (gd->baudrate, &udiv, &bdiv);
-#endif
-
- reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
+ divisor = (get_serial_clock() + (gd->baudrate * (16 / 2))) /
+ (16 * gd->baudrate);
+ NS16550_init(com_port, divisor);
/*
- * Configure input clock to baudrate generator for all
- * available serial ports here
+ * Set internal loopback mode in UART
*/
- MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
- MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
- MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
- MTREG(UART3_SDR, reg);
-#endif
-
- uart_post_init_common(com_port, bdiv);
-
- return 0;
-}
-
-#else /* CONFIG_440 */
-
-static int uart_post_init (struct NS16550 *com_port)
-{
- unsigned long reg;
- unsigned long tmp;
- unsigned long clk;
- unsigned long udiv;
- unsigned short bdiv;
- int i;
-
- for (i = 0; i < 3500; i++) {
- if (in_8(&com_port->lsr) & UART_LSR_THRE)
- break;
- udelay (100);
- }
-
-#if defined(CONFIG_405EZ)
- serial_divs(gd->baudrate, &udiv, &bdiv);
- clk = tmp = reg = 0;
-#else
-#ifdef CONFIG_405EP
- reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
- clk = gd->cpu_clk;
- tmp = CONFIG_SYS_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
- reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
- reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
- mtdcr (CPC0_UCR, reg);
-#else /* CONFIG_405EP */
- reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
- udiv = 1;
- reg |= CR0_EXTCLK_ENA;
-#else
- clk = gd->cpu_clk;
-#ifdef CONFIG_SYS_405_UART_ERRATA_59
- udiv = 31; /* Errata 59: stuck at 31 */
-#else
- tmp = CONFIG_SYS_BASE_BAUD * 16;
- udiv = (clk + tmp / 2) / tmp;
- if (udiv > UDIV_MAX) /* max. n bits for udiv */
- udiv = UDIV_MAX;
-#endif
-#endif
- reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (CPC0_CR0, reg);
-#endif /* CONFIG_405EP */
- tmp = gd->baudrate * udiv * 16;
- bdiv = (clk + tmp / 2) / tmp;
-#endif /* CONFIG_405EZ */
-
- uart_post_init_common(com_port, bdiv);
+ out_8(&com_port->mcr, in_8(&com_port->mcr) | UART_MCR_LOOP);
- return 0;
-}
-#endif /* CONFIG_440 */
-
-static void uart_post_putc (struct NS16550 *com_port, char c)
-{
- int i;
-
- out_8(&com_port->thr, c); /* put character out */
-
- /* Wait for transfer completion */
- for (i = 0; i < 3500; i++) {
- if (in_8(&com_port->lsr) & UART_LSR_THRE)
- break;
- udelay (100);
- }
-}
-
-static int uart_post_getc (struct NS16550 *com_port)
-{
- int i;
-
- /* Wait for character available */
- for (i = 0; i < 3500; i++) {
- if (in_8(&com_port->lsr) & UART_LSR_DR)
- break;
- udelay (100);
- }
-
- return 0xff & in_8(&com_port->rbr);
-}
-
-static int test_ctlr (struct NS16550 *com_port, int index)
-{
- int res = -1;
- char test_str[] = "*** UART Test String ***\r\n";
- int i;
+ /* Reset FIFOs */
+ out_8(&com_port->fcr, UART_FCR_RXSR | UART_FCR_TXSR);
+ udelay(100);
- uart_post_init (com_port);
+ /* Flush RX-FIFO */
+ while (NS16550_tstc(com_port))
+ NS16550_getc(com_port);
for (i = 0; i < sizeof (test_str) - 1; i++) {
- uart_post_putc (com_port, test_str[i]);
- if (uart_post_getc (com_port) != test_str[i])
+ NS16550_putc(com_port, test_str[i]);
+ if (NS16550_getc(com_port) != test_str[i])
goto done;
}
res = 0;
#
include $(TOPDIR)/config.mk
-LIB = libpostdrivers.a
+LIB = libpostdrivers.o
COBJS-$(CONFIG_HAS_POST) += i2c.o memory.o rtc.o
* MA 02111-1307 USA
*/
-#include <common.h>
-
/*
* I2C test
*
* For verifying the I2C bus, a full I2C bus scanning is performed.
*
- * #ifdef I2C_ADDR_LIST
- * The test is considered as passed if all the devices and
- * only the devices in the list are found.
- * #else [ ! I2C_ADDR_LIST ]
+ * #ifdef CONFIG_SYS_POST_I2C_ADDRS
+ * The test is considered as passed if all the devices and only the devices
+ * in the list are found.
+ * #ifdef CONFIG_SYS_POST_I2C_IGNORES
+ * Ignore devices listed in CONFIG_SYS_POST_I2C_IGNORES. These devices
+ * are optional or not vital to board functionality.
+ * #endif
+ * #else [ ! CONFIG_SYS_POST_I2C_ADDRS ]
* The test is considered as passed if any I2C device is found.
* #endif
*/
+#include <common.h>
#include <post.h>
#include <i2c.h>
#if CONFIG_POST & CONFIG_SYS_POST_I2C
+static int i2c_ignore_device(unsigned int chip)
+{
+#ifdef CONFIG_SYS_POST_I2C_IGNORES
+ const unsigned char i2c_ignore_list[] = CONFIG_SYS_POST_I2C_IGNORES;
+ int i;
+
+ for (i = 0; i < sizeof(i2c_ignore_list); i++)
+ if (i2c_ignore_list[i] == chip)
+ return 1;
+#endif
+
+ return 0;
+}
+
int i2c_post_test (int flags)
{
unsigned int i;
- unsigned int good = 0;
-#ifdef I2C_ADDR_LIST
- unsigned int bad = 0;
+#ifndef CONFIG_SYS_POST_I2C_ADDRS
+ /* Start at address 1, address 0 is the general call address */
+ for (i = 1; i < 128; i++) {
+ if (i2c_ignore_device(i))
+ continue;
+ if (i2c_probe (i) == 0)
+ return 0;
+ }
+
+ /* No devices found */
+ return -1;
+#else
+ unsigned int ret = 0;
int j;
- unsigned char i2c_addr_list[] = I2C_ADDR_LIST;
- unsigned char i2c_miss_list[] = I2C_ADDR_LIST;
-#endif
+ unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS;
- for (i = 0; i < 128; i++) {
- if (i2c_probe (i) == 0) {
-#ifndef I2C_ADDR_LIST
- good++;
-#else /* I2C_ADDR_LIST */
- for (j=0; j<sizeof(i2c_addr_list); ++j) {
- if (i == i2c_addr_list[j]) {
- good++;
- i2c_miss_list[j] = 0xFF;
- break;
- }
- }
- if (j == sizeof(i2c_addr_list)) {
- bad++;
- post_log ("I2C: addr %02X not expected\n",
- i);
+ /* Start at address 1, address 0 is the general call address */
+ for (i = 1; i < 128; i++) {
+ if (i2c_ignore_device(i))
+ continue;
+ if (i2c_probe(i) != 0)
+ continue;
+
+ for (j = 0; j < sizeof(i2c_addr_list); ++j) {
+ if (i == i2c_addr_list[j]) {
+ i2c_addr_list[j] = 0xff;
+ break;
}
-#endif /* I2C_ADDR_LIST */
}
- }
-#ifndef I2C_ADDR_LIST
- return good > 0 ? 0 : -1;
-#else /* I2C_ADDR_LIST */
- if (good != sizeof(i2c_addr_list)) {
- for (j=0; j<sizeof(i2c_miss_list); ++j) {
- if (i2c_miss_list[j] != 0xFF) {
- post_log ("I2C: addr %02X did not respond\n",
- i2c_miss_list[j]);
- }
+ if (j == sizeof(i2c_addr_list)) {
+ ret = -1;
+ post_log("I2C: addr %02x not expected\n", i);
}
}
- return ((good == sizeof(i2c_addr_list)) && (bad == 0)) ? 0 : -1;
+
+ for (i = 0; i < sizeof(i2c_addr_list); ++i) {
+ if (i2c_addr_list[i] == 0xff)
+ continue;
+ post_log("I2C: addr %02x did not respond\n", i2c_addr_list[i]);
+ ret = -1;
+ }
+
+ return ret;
#endif
}
return ret;
}
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
- int ret = 0;
bd_t *bd = gd->bd;
- unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = (bd->bi_memsize >= 256 << 20 ?
+ 256 << 20 : bd->bi_memsize) - (1 << 20);
/* Limit area to be tested with the board info struct */
- if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
- memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+ if ((*vstart) + (*size) > (ulong)bd)
+ *size = (ulong)bd - *vstart;
+
+ return 0;
+}
- if (flags & POST_SLOWTEST) {
- ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
- } else { /* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 1;
+}
- unsigned long i;
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 0;
+}
- for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = memory_post_tests (i << 20, 0x800);
- if (ret == 0)
- ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+ return;
+}
+
+int memory_post_test(int flags)
+{
+ int ret = 0;
+ phys_addr_t phys_offset = 0;
+ u32 memsize, vstart;
+
+ arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+ do {
+ if (flags & POST_SLOWTEST) {
+ ret = memory_post_tests(vstart, memsize);
+ } else { /* POST_NORMAL */
+ unsigned long i;
+ for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+ if (ret == 0)
+ ret = memory_post_tests(i << 20, 0x800);
+ if (ret == 0)
+ ret = memory_post_tests(
+ (i << 20) + 0xff800, 0x800);
+ }
}
- }
+ } while (!ret &&
+ !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+ arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+ if (ret)
+ arch_memory_failure_handle();
return ret;
}
#
include $(TOPDIR)/config.mk
-LIB = libpost$(ARCH).a
+LIB = libpost$(ARCH).o
AOBJS-$(CONFIG_HAS_POST) += asm.o
COBJS-$(CONFIG_HAS_POST) += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
#
include $(TOPDIR)/config.mk
-LIB = libpost$(ARCH)fpu.a
+LIB = libpost$(ARCH)fpu.o
COBJS-$(CONFIG_HAS_POST) += fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
COBJS-$(CONFIG_HAS_POST) += acc1.o compare-fp-1.o mul-subnormal-single-1.o
return 0;
}
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
void post_reloc (void)
{
unsigned int i;
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
},
#endif
#if CONFIG_POST & CONFIG_SYS_POST_UART
+#if defined(CONFIG_POST_UART)
+ CONFIG_POST_UART,
+#else
{
"UART test",
"uart",
NULL,
CONFIG_SYS_POST_UART
},
+#endif /* CONFIG_POST_UART */
#endif
#if CONFIG_POST & CONFIG_SYS_POST_ETHER
{
$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS)
@rm -f $@
+ @touch $@
@for f in $(SRCS); do \
g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
$(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
TOOLSUBDIRS =
#
+# Include this after HOSTOS HOSTARCH check
+# so that we can act intelligently.
+#
+include $(TOPDIR)/config.mk
+
+#
# toolchains targeting win32 generate .exe files
#
ifneq (,$(findstring WIN32 ,$(shell $(HOSTCC) -E -dM -xc /dev/null)))
SFX =
endif
-#
-# Include this after HOSTOS HOSTARCH check
-# so that we can act intelligently.
-#
-include $(TOPDIR)/config.mk
-
# Enable all the config-independent tools
ifneq ($(HOST_TOOLS_ALL),)
CONFIG_LCD_LOGO = y
-idirafter $(OBJTREE)/include \
-I $(SRCTREE)/lib/libfdt \
-I $(SRCTREE)/tools \
- -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC \
+ -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
+ -DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-SRCS := $(obj)crc32.c fw_env.c fw_env_main.c
+HOSTSRCS := $(obj)crc32.c fw_env.c fw_env_main.c
HEADERS := fw_env.h
-HOSTCFLAGS += -Wall -DUSE_HOSTCC -I$(SRCTREE)/include
+# Compile for a hosted environment on the target
+HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
+ -idirafter $(OBJTREE)/include2 \
+ -idirafter $(OBJTREE)/include \
+ -DUSE_HOSTCC
ifeq ($(MTD_VERSION),old)
-HOSTCFLAGS += -DMTD_OLD
+HOSTCPPFLAGS += -DMTD_OLD
endif
all: $(obj)fw_printenv
-$(obj)fw_printenv: $(SRCS) $(HEADERS)
- $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $(SRCS)
+# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
+$(obj)fw_printenv: $(HOSTSRCS) $(HEADERS)
+ $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS)
clean:
rm -f $(obj)fw_printenv $(obj)crc32.c
$(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(STRIP) $@
-# Some files complain if compiled with -pedantic, use FIT_CFLAGS
+# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
$(obj)image.o: $(SRCTREE)/common/image.c
$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
s/="\(.*\)"$/=\1/;
# Concatenate string values
s/" *"//g;
- # Wrap non-numeral values with quotes
- s/=\(.*\?[^0-9].*\)$/=\"\1\"/;
+ # Assume strings as default - add quotes around values
+ s/=\(..*\)/="\1"/;
+ # but remove again from decimal numbers
+ s/="\([0-9][0-9]*\)"/=\1/;
+ # ... and from hex numbers
+ s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
# Change '1' and empty values to "y" (not perfect, but
# supports conditional compilation in the makefiles
s/=$/=y/;
--- /dev/null
+#!/bin/sh
+
+# Adapted from Linux kernel's "Kbuild":
+# commit 1cdf25d704f7951d02a04064c97db547d6021872
+# Author: Christoph Lameter <clameter@sgi.com>
+
+mkdir -p $(dirname $2)
+
+# Default sed regexp - multiline due to syntax constraints
+SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \
+ s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \
+ s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+ s:->::; p;}"
+
+(set -e
+ echo "#ifndef __ASM_OFFSETS_H__"
+ echo "#define __ASM_OFFSETS_H__"
+ echo "/*"
+ echo " * DO NOT MODIFY."
+ echo " *"
+ echo " * This file was generated by $(basename $0)"
+ echo " *"
+ echo " */"
+ echo ""
+ sed -ne "${SED_CMD}" $1
+ echo ""
+ echo "#endif" ) > $2
projects / kernel / u-boot.git / commitdiff