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drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 9 Oct 2020 19:44:40 +0000 (12:44 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Sat, 10 Oct 2020 01:51:27 +0000 (18:51 -0700)
The power well that we've been referring to as the 'blitter' well is
actually more of a general GT power well which contains a lot of things
other than the blitter engine registers.  The FORCEWAKE_BLITTER name in
the code was used for historic reasons, but no longer matches how the
bspec describes this power well and just causes confusion for people not
familiar with this area of the code.  Let's rename it to FORCEWAKE_GT to
more accurately describe the role of the power well and match how the
modern bspec refers to it.

v2:
 - Add a comment noting that the GT power well includes the blitter
   engine. (Jose)

Bspec: 66696, 66534, 67609
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201009194442.3668677-2-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
drivers/gpu/drm/i915/gt/uc/intel_guc.c patch | blob | history
drivers/gpu/drm/i915/gvt/handlers.c patch | blob | history
drivers/gpu/drm/i915/gvt/reg.h patch | blob | history
drivers/gpu/drm/i915/i915_reg.h patch | blob | history
drivers/gpu/drm/i915/intel_uncore.c patch | blob | history
drivers/gpu/drm/i915/intel_uncore.h patch | blob | history

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 942c7c187adbaaf1d4c5601411f09567b62620d9..e4aaa5f2979630f4da416286bfd43f41842485a9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -312,18 +312,18 @@ void intel_guc_write_params(struct intel_guc *guc)
        int i;
 
        /*
-        * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
+        * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
         * they are power context saved so it's ok to release forcewake
         * when we are done here and take it again at xfer time.
         */
-       intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER);
+       intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
 
        intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
 
        for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
                intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
 
-       intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER);
+       intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
 }
 
 int intel_guc_init(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3be37e6fe33da016b66123b6077996621899e262..e0edc9d1f3577c3a7e37572b0c26ad861c96a7d3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -290,8 +290,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
                case FORCEWAKE_RENDER_GEN9_REG:
                        ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
                        break;
-               case FORCEWAKE_BLITTER_GEN9_REG:
-                       ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
+               case FORCEWAKE_GT_GEN9_REG:
+                       ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
                        break;
                case FORCEWAKE_MEDIA_GEN9_REG:
                        ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
@@ -2901,8 +2901,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 
        MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
        MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
-       MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
-       MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
+       MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+       MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
        MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
        MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
 
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index b88e033cbed4395f6a43922d568325e54fb2446d..b58860dee970be01986f462edde7d4a9ff556ab3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -101,8 +101,8 @@
 
 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
-#define FORCEWAKE_BLITTER_GEN9_REG 0xa188
-#define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044
+#define FORCEWAKE_GT_GEN9_REG 0xa188
+#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044
 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
 #define FORCEWAKE_ACK_HSW_REG 0x130044
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ad9ee4243a01a7d4617b9d7da5c41e0421e542b..04c966a524cedfd0def5eb65fb666d3b90f1ede3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8958,12 +8958,12 @@ enum {
 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)                _MMIO(0xa540 + (n) * 4)
 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)                _MMIO(0xa560 + (n) * 4)
 #define  FORCEWAKE_RENDER_GEN9                 _MMIO(0xa278)
-#define  FORCEWAKE_BLITTER_GEN9                        _MMIO(0xa188)
+#define  FORCEWAKE_GT_GEN9                     _MMIO(0xa188)
 #define  FORCEWAKE_ACK_MEDIA_GEN9              _MMIO(0x0D88)
 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)    _MMIO(0x0D50 + (n) * 4)
 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)    _MMIO(0x0D70 + (n) * 4)
 #define  FORCEWAKE_ACK_RENDER_GEN9             _MMIO(0x0D84)
-#define  FORCEWAKE_ACK_BLITTER_GEN9            _MMIO(0x130044)
+#define  FORCEWAKE_ACK_GT_GEN9                 _MMIO(0x130044)
 #define   FORCEWAKE_KERNEL                     BIT(0)
 #define   FORCEWAKE_USER                       BIT(1)
 #define   FORCEWAKE_KERNEL_FALLBACK            BIT(15)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 54e201fdeba4b8c595fd38e3cd98dc2d8658232c..ede3a5393d517073ce70ad04152b514aa8116484 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1051,37 +1051,37 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
-       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
-       GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 };
 
@@ -1089,33 +1089,33 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
        GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8800, 0x8bff, 0),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
        GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
        GEN_FW_RANGE(0x9560, 0x95ff, 0),
-       GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24000, 0x2407f, 0),
-       GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x40000, 0x1bffff, 0),
        GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
        GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
@@ -1126,39 +1126,39 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
-       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
        GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
-       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_GT),
        GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-       GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x40000, 0x1bffff, 0),
        GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
        GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
        GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
-       GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
+       GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_GT),
        GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
        GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
        GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
@@ -1469,7 +1469,7 @@ static int __fw_domain_init(struct intel_uncore *uncore,
        d->id = domain_id;
 
        BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
-       BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
+       BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
        BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
        BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
        BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
@@ -1538,9 +1538,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
                fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
                               FORCEWAKE_RENDER_GEN9,
                               FORCEWAKE_ACK_RENDER_GEN9);
-               fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-                              FORCEWAKE_BLITTER_GEN9,
-                              FORCEWAKE_ACK_BLITTER_GEN9);
+               fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+                              FORCEWAKE_GT_GEN9,
+                              FORCEWAKE_ACK_GT_GEN9);
 
                for (i = 0; i < I915_MAX_VCS; i++) {
                        if (!__HAS_ENGINE(emask, _VCS(i)))
@@ -1564,9 +1564,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
                fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
                               FORCEWAKE_RENDER_GEN9,
                               FORCEWAKE_ACK_RENDER_GEN9);
-               fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-                              FORCEWAKE_BLITTER_GEN9,
-                              FORCEWAKE_ACK_BLITTER_GEN9);
+               fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+                              FORCEWAKE_GT_GEN9,
+                              FORCEWAKE_ACK_GT_GEN9);
                fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
                               FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
        } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index c4b22d9d0b45108aab6a3d0dee5f5f7cea8efac4..bd2467284295c95140ceb0a09720375f05953c11 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -46,7 +46,7 @@ struct intel_uncore_mmio_debug {
 
 enum forcewake_domain_id {
        FW_DOMAIN_ID_RENDER = 0,
-       FW_DOMAIN_ID_BLITTER,
+       FW_DOMAIN_ID_GT,        /* also includes blitter engine */
        FW_DOMAIN_ID_MEDIA,
        FW_DOMAIN_ID_MEDIA_VDBOX0,
        FW_DOMAIN_ID_MEDIA_VDBOX1,
@@ -60,7 +60,7 @@ enum forcewake_domain_id {
 
 enum forcewake_domains {
        FORCEWAKE_RENDER        = BIT(FW_DOMAIN_ID_RENDER),
-       FORCEWAKE_BLITTER       = BIT(FW_DOMAIN_ID_BLITTER),
+       FORCEWAKE_GT            = BIT(FW_DOMAIN_ID_GT),
        FORCEWAKE_MEDIA         = BIT(FW_DOMAIN_ID_MEDIA),
        FORCEWAKE_MEDIA_VDBOX0  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
        FORCEWAKE_MEDIA_VDBOX1  = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
Domain: System / Kernel;