platform: mellanox: Add field upgrade capability register

Add new register to indicate the method of FPGA/CPLD field upgrade
supported on the specific system.
Currently two masks are available:
b00 - field upgrade through LPC gateway (new method introduced to
      accelerate field upgrade process).
b11 - field upgrade through CPU GPIO pins (old method).

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael Shych <michaelsh@nvidia.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20230822113451.13785-3-vadimp@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index 26748c2..647a102 100644 (file)
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -62,6 +62,7 @@
 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET        0x37
 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET       0x3a
 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET  0x3b
+#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET     0x3c
 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET     0x40
 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET        0x41
 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET     0x42
@@ -236,6 +237,7 @@
 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK  GENMASK(5, 4)
 #define MLXPLAT_CPLD_GWP_MASK          GENMASK(0, 0)
 #define MLXPLAT_CPLD_EROT_MASK         GENMASK(1, 0)
+#define MLXPLAT_CPLD_FU_CAP_MASK       GENMASK(1, 0)
 #define MLXPLAT_CPLD_PWR_BUTTON_MASK   BIT(0)
 #define MLXPLAT_CPLD_LATCH_RST_MASK    BIT(6)
 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
@@ -3681,6 +3683,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
                .mode = 0200,
        },
        {
+               .label = "jtag_cap",
+               .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
+               .mask = MLXPLAT_CPLD_FU_CAP_MASK,
+               .bit = 1,
+               .mode = 0444,
+       },
+       {
                .label = "jtag_enable",
                .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
                .mask = GENMASK(7, 0) & ~BIT(4),
@@ -4935,6 +4944,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
        case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
@@ -5046,6 +5056,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
@@ -5203,6 +5214,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
        case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
+       case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
        case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: