[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.

The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
	pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
	pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
	pmscr_el2.
	(aarch64_sys_reg_supported_p): Add architecture feature tests for
	the new registers.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
	system registers.
	* gas/aarch64/sysreg-2.d: Enable the statistical profiling
	extension and update the expected output.

Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 4027a7c..dafa360 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
+       system registers.
+       * gas/aarch64/sysreg-2.d: Enable the statistical profiling
+       extension and update the expected output.
+
 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 
        * gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index f73412f..ba5fb52 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -1,5 +1,5 @@
 #objdump: -dr
-#as: -march=armv8.2-a
+#as: -march=armv8.2-a+profile
 
 .*:     file .*
 
@@ -32,3 +32,29 @@ Disassembly of section .text:
   [0-9a-f]+:   d50b7c22        dc      cvap, x2
   [0-9a-f]+:   d5087900        at      s1e1rp, x0
   [0-9a-f]+:   d5087921        at      s1e1wp, x1
+  [0-9a-f]+:   d5189a07        msr     pmblimitr_el1, x7
+  [0-9a-f]+:   d5389a07        mrs     x7, pmblimitr_el1
+  [0-9a-f]+:   d5189a27        msr     pmbptr_el1, x7
+  [0-9a-f]+:   d5389a27        mrs     x7, pmbptr_el1
+  [0-9a-f]+:   d5189a67        msr     pmbsr_el1, x7
+  [0-9a-f]+:   d5389a67        mrs     x7, pmbsr_el1
+  [0-9a-f]+:   d5189ae7        msr     pmbidr_el1, x7
+  [0-9a-f]+:   d5389ae7        mrs     x7, pmbidr_el1
+  [0-9a-f]+:   d5189907        msr     pmscr_el1, x7
+  [0-9a-f]+:   d5389907        mrs     x7, pmscr_el1
+  [0-9a-f]+:   d5189947        msr     pmsicr_el1, x7
+  [0-9a-f]+:   d5389947        mrs     x7, pmsicr_el1
+  [0-9a-f]+:   d5189967        msr     pmsirr_el1, x7
+  [0-9a-f]+:   d5389967        mrs     x7, pmsirr_el1
+  [0-9a-f]+:   d5189987        msr     pmsfcr_el1, x7
+  [0-9a-f]+:   d5389987        mrs     x7, pmsfcr_el1
+  [0-9a-f]+:   d51899a7        msr     pmsevfr_el1, x7
+  [0-9a-f]+:   d53899a7        mrs     x7, pmsevfr_el1
+  [0-9a-f]+:   d51899c7        msr     pmslatfr_el1, x7
+  [0-9a-f]+:   d53899c7        mrs     x7, pmslatfr_el1
+  [0-9a-f]+:   d51c9907        msr     pmscr_el2, x7
+  [0-9a-f]+:   d53c9907        mrs     x7, pmscr_el2
+  [0-9a-f]+:   d51d9907        msr     pmscr_el12, x7
+  [0-9a-f]+:   d53d9907        mrs     x7, pmscr_el12
+  [0-9a-f]+:   d5389ae7        mrs     x7, pmbidr_el1
+  [0-9a-f]+:   d53899e7        mrs     x7, pmsidr_el1

diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index f89d057..2f6ea70 100644 (file)
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -41,3 +41,21 @@
 
        at s1e1rp, x0
        at s1e1wp, x1
+
+       /* Statistical profiling.  */
+
+       .irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1 pmbidr_el1
+       rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
+       .endr
+
+       .irp reg, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1
+       rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
+       .endr
+
+       .irp reg, pmsevfr_el1, pmslatfr_el1, pmscr_el2, pmscr_el12
+       rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
+       .endr
+
+       .irp reg, pmbidr_el1, pmsidr_el1
+       rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=0
+       .endr

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index aec423b..35cdbcf 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
+       pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
+       pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
+       pmscr_el2.
+       (aarch64_sys_reg_supported_p): Add architecture feature tests for
+       the new registers.
+
 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b2f772e..a75c415 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3039,7 +3039,19 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "dbgclaimset_el1",   CPENC(2,0,C7, C8, 6), 0 },
   { "dbgclaimclr_el1",   CPENC(2,0,C7, C9, 6), 0 },
   { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), 0 },  /* r */
-
+  { "pmblimitr_el1",    CPENC (3, 0, C9, C10, 0), F_ARCHEXT },  /* rw */
+  { "pmbptr_el1",       CPENC (3, 0, C9, C10, 1), F_ARCHEXT },  /* rw */
+  { "pmbsr_el1",        CPENC (3, 0, C9, C10, 3), F_ARCHEXT },  /* rw */
+  { "pmbidr_el1",       CPENC (3, 0, C9, C10, 7), F_ARCHEXT },  /* ro */
+  { "pmscr_el1",        CPENC (3, 0, C9, C9, 0),  F_ARCHEXT },  /* rw */
+  { "pmsicr_el1",       CPENC (3, 0, C9, C9, 2),  F_ARCHEXT },  /* rw */
+  { "pmsirr_el1",       CPENC (3, 0, C9, C9, 3),  F_ARCHEXT },  /* rw */
+  { "pmsfcr_el1",       CPENC (3, 0, C9, C9, 4),  F_ARCHEXT },  /* rw */
+  { "pmsevfr_el1",      CPENC (3, 0, C9, C9, 5),  F_ARCHEXT },  /* rw */
+  { "pmslatfr_el1",     CPENC (3, 0, C9, C9, 6),  F_ARCHEXT },  /* rw */
+  { "pmsidr_el1",       CPENC (3, 0, C9, C9, 7),  F_ARCHEXT },  /* ro */
+  { "pmscr_el2",        CPENC (3, 4, C9, C9, 0),  F_ARCHEXT },  /* rw */
+  { "pmscr_el12",       CPENC (3, 5, C9, C9, 0),  F_ARCHEXT },  /* rw */
   { "pmcr_el0",          CPENC(3,3,C9,C12, 0), 0 },
   { "pmcntenset_el0",    CPENC(3,3,C9,C12, 1), 0 },
   { "pmcntenclr_el0",    CPENC(3,3,C9,C12, 2), 0 },
@@ -3215,6 +3227,23 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
     return FALSE;
 
+  /* Statistical Profiling extension.  */
+  if ((reg->value == CPENC (3, 0, C9, C10, 0)
+       || reg->value == CPENC (3, 0, C9, C10, 1)
+       || reg->value == CPENC (3, 0, C9, C10, 3)
+       || reg->value == CPENC (3, 0, C9, C10, 7)
+       || reg->value == CPENC (3, 0, C9, C9, 0)
+       || reg->value == CPENC (3, 0, C9, C9, 2)
+       || reg->value == CPENC (3, 0, C9, C9, 3)
+       || reg->value == CPENC (3, 0, C9, C9, 4)
+       || reg->value == CPENC (3, 0, C9, C9, 5)
+       || reg->value == CPENC (3, 0, C9, C9, 6)
+       || reg->value == CPENC (3, 0, C9, C9, 7)
+       || reg->value == CPENC (3, 4, C9, C9, 0)
+       || reg->value == CPENC (3, 5, C9, C9, 0))
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
+    return FALSE;
+
   return TRUE;
 }