drm/amd/display: determine dp link encoding format from link settings
authorWenjing Liu <wenjing.liu@amd.com>
Mon, 3 May 2021 18:51:27 +0000 (14:51 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 20 May 2021 02:39:04 +0000 (22:39 -0400)
[how]
Implement a function that determines link encoding format
based on the link settings passed in.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

index 74c62cb..b3b9b73 100644 (file)
@@ -4852,4 +4852,11 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
        return false;
 }
 
+enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
+{
+       if ((link_settings->link_rate >= LINK_RATE_LOW) &&
+                       (link_settings->link_rate <= LINK_RATE_HIGH3))
+               return DP_8b_10b_ENCODING;
+       return DP_UNKNOWN_ENCODING;
+}
 
index fcfde2e..1948cd9 100644 (file)
@@ -98,6 +98,11 @@ enum dc_dp_training_pattern {
        DP_TRAINING_PATTERN_VIDEOIDLE,
 };
 
+enum dp_link_encoding {
+       DP_UNKNOWN_ENCODING = 0,
+       DP_8b_10b_ENCODING = 1,
+};
+
 struct dc_link_settings {
        enum dc_lane_count lane_count;
        enum dc_link_rate link_rate;
index 4288425..ffc3f2c 100644 (file)
@@ -105,4 +105,5 @@ enum link_training_result dp_check_link_loss_status(
                struct dc_link *link,
                const struct link_training_settings *link_training_setting);
 
+enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
 #endif /* __DC_LINK_DP_H__ */