* config/tc-m32r.c (allow_m32rx): Must compile with K&R C.

	(m32rx support): only include #ifdef HAVE_CPU_M32RX.

diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index 2d26084..b428532 100644 (file)
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -103,7 +103,8 @@ static struct m32r_hi_fixup * m32r_hi_fixup_list;
 \f
 /* start-sanitize-m32rx */
 static void
-allow_m32rx (int on)
+allow_m32rx (on)
+     int on;
 {
   enable_m32rx = on;
 
@@ -381,6 +382,8 @@ md_begin ()
 /* end-sanitize-m32rx */
 }
 
+#ifdef HAVE_CPU_M32RX
+
 /* Returns non zero if the given instruction writes to a destination register.  */
 static int
 writes_to_dest_reg (insn)
@@ -676,6 +679,9 @@ assemble_parallel_insn (str, str2)
 
   return;
 }
+
+#endif /* HAVE_CPU_M32RX */
+
 /* end-sanitize-m32rx */
 
 
@@ -691,12 +697,14 @@ md_assemble (str)
   cgen_asm_init_parse ();
 
 /* start-sanitize-m32rx */
+#ifdef HAVE_CPU_M32RX
   /* Look for a parallel instruction seperator.  */
   if ((str2 = strstr (str, "||")) != NULL)
     {
       assemble_parallel_insn (str, str2);
       return;
     }
+#endif
 /* end-sanitize-m32rx */
   
   insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
@@ -707,11 +715,13 @@ md_assemble (str)
     }
 
 /* start-sanitize-m32rx */
+#ifdef HAVE_CPU_M32RX
   if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
     {
       as_bad ("instruction '%s' is for the M32RX only", str);
       return;
     }
+#endif
 /* end-sanitize-m32rx */
   
   if (CGEN_INSN_BITSIZE (insn.insn) == 32)
@@ -744,6 +754,7 @@ md_assemble (str)
        {
 /* start-sanitize-m32rx */
 /* start-sanitize-phase2-m32rx */
+#ifdef HAVE_CPU_M32RX
          /* Look to see if this instruction can be combined with the
             previous instruction to make one, parallel, 32 bit instruction.
             If the previous instruction (potentially) changed the flow of
@@ -762,6 +773,7 @@ md_assemble (str)
              else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
                swap = true;
            }
+#endif
 /* end-sanitize-phase2-m32rx */
 /* end-sanitize-m32rx */
          
@@ -779,6 +791,7 @@ md_assemble (str)
 
 /* start-sanitize-m32rx */
 /* start-sanitize-phase2-m32rx */
+#ifdef HAVE_CPU_M32RX
       if (swap)
        {
          int     tmp;
@@ -806,6 +819,7 @@ md_assemble (str)
       /* Record where this instruction was assembled.  */
       prev_insn.addr = insn.addr;
       prev_insn.frag = insn.frag;
+#endif
 /* end-sanitize-m32rx */
       
       /* If the insn needs the following one to be on a 32 bit boundary